Photovoltaic cell and preparation method thereof

Abstract

The invention relates to a photovoltaic cell and a preparation method thereof, the photovoltaic cell comprises a silicon wafer, at least one surface of the silicon wafer is provided with a plurality of pyramid structures and a plurality of pits, and the side wall of each pyramid structure is provided with a groove of an arc-shaped structure; the pits are located between every two adjacent pyramid structures, and the pits are connected with the grooves in the pyramid structures adjacent to the pits. According to the application, the grooves of the arc-shaped structures are formed in the side walls of the pyramid structures, the pits are formed in the surface of the silicon wafer, and the pits are connected with the grooves in the pyramid structures adjacent to the pits, so that the reflected light rays at the tops of the pyramid structures can be incident into the pits and the grooves again; and the light rays entering the pits and the grooves can be reflected for multiple times in the pits and the grooves, so that the light ray utilization rate of the photovoltaic cell can be improved, and the short-circuit current and the efficiency of the photovoltaic cell can be more effectively improved.

Description

Technical Field

[0001] The present application relates to the technical field of photovoltaic cells, and in particular to a photovoltaic cell and a method for preparing the photovoltaic cell. Background Art

[0002] With the continuous consumption of traditional energy and its negative impact on the environment, the development and utilization of solar energy as a pollution-free, renewable energy has developed rapidly, especially photovoltaic cells with high conversion efficiency have become the focus of current research.

[0003] In the related art, a pyramid velvet structure is generally prepared on the surface of a photovoltaic cell through a velvet process to reduce the reflection of sunlight on the surface of the photovoltaic cell, so that the photovoltaic cell can absorb more sunlight, thereby improving the short-circuit current and efficiency of the cell.

[0004] However, for the velvet structure of the pyramid, although the velvet structure can reduce the reflectivity of the battery surface to about 11%, the surface of the velvet structure of the pyramid still does not fully utilize the secondary reflected and refracted light, and still causes a large optical loss. Summary of the invention

[0005] Based on this, it is necessary to provide a photovoltaic cell and a method for preparing the photovoltaic cell, which can improve the utilization rate of light by the photovoltaic cell and can more effectively improve the short-circuit current and efficiency of the photovoltaic cell.

[0006] A photovoltaic cell comprises a silicon wafer, wherein at least one surface of the silicon wafer has a plurality of pyramid structures and a plurality of pits.

[0007] A groove of an arc structure is arranged on the side wall of the pyramid structure; the pit is located between two adjacent pyramid structures, and the pit is connected to the groove on the adjacent pyramid structure.

[0008] In one embodiment, the pit is an arc-shaped structure.

[0009] In one embodiment, a bearing surface is provided between the top of the pyramid structure and the groove, and a protective layer is provided on the bearing surface.

[0010] In one embodiment, the thickness of the protection layer gradually decreases from the top of the pyramid structure to the groove.

[0011] In one of the embodiments, the distance between the bottom of the groove and the opening of the groove is 20 μm to 300 μm.

[0012] In one of the embodiments, the distance between the end of the opening of the groove away from the surface of the silicon wafer and the surface of the silicon wafer is 80 μm to 1200 μm.

[0013] In one embodiment, the distance between the bottom of the pit and the opening of the pit is 30 μm to 400 μm.

[0014] In one embodiment, the length of the opening of the pit is 10 μm to 1600 μm.

[0015] The present application also provides a method for preparing the photovoltaic cell as described above, comprising:

[0016] Using an alkaline solution to perform a first texturing on the surface of the silicon wafer to form the pyramid structure on the surface of the silicon wafer;

[0017] depositing a protective layer on the surface of the pyramid structure;

[0018] The surface of the silicon wafer is textured for the second time using an acidic solution to form pits on the surface of the silicon wafer and grooves on the side walls of the pyramid structure.

[0019] In one embodiment, the protective layer comprises SiO X N X layer or BSG layer.

[0020] In the above scheme, by arranging a groove of an arc structure on the side wall of the pyramid structure, and arranging a pit on the surface of the silicon wafer, and the pit is connected to the groove on the adjacent pyramid structure, the reflected light from the top of the pyramid structure can be incident on the pit and the groove again, and the light incident on the pit and the groove can be reflected multiple times in the pit and the groove, which can improve the utilization rate of light by the photovoltaic cell and can more effectively improve the short-circuit current and efficiency of the photovoltaic cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application.

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] FIG. 1 is a schematic structural diagram of a photovoltaic cell shown in the related art.

[0024] FIG. 2 is a schematic structural diagram of a photovoltaic cell in an embodiment of the present application in which a protective layer is omitted.

[0025] FIG. 3 is a schematic diagram of the structure of a photovoltaic cell after depositing a protective layer according to an embodiment of the present application.

[0026] FIG. 4 is a schematic diagram of the structure of a photovoltaic cell shown in an embodiment of the present application.

[0027] FIG. 5 is a surface SEM photograph of a silicon wafer after a protective layer is deposited according to an embodiment of the present application.

[0028] FIG. 6 is a surface SEM photograph of a silicon wafer after secondary texturing as shown in an embodiment of the present application.

[0029] Reference numerals:

[0030] 10. Photovoltaic cell; 100. Silicon wafer; 200. Pyramid structure; 210. Groove; 200. Pit; 400. Protective layer; 500. Velvet structure. DETAILED DESCRIPTION

[0031] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0032] In the description of the present application, it should be understood that if the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. appear, the orientation or position relationship indicated by these terms is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0033] In addition, if the terms "first" or "second" appear, these terms are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, if the term "plurality" appears, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0034] In this application, unless otherwise clearly specified and limited, if the terms "installed", "connected", "connected", "fixed" and the like appear, these terms should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integrated connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0035] In the present application, unless otherwise clearly specified and limited, if there is a description that a first feature is "above" or "below" a second feature, etc., or similar descriptions appear, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature being "above", "above" and "above" the second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. The first feature being "below", "below" and "below" the second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0036] It should be noted that if an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be a central element. If an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. If any, the terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used in this application are for illustrative purposes only and do not represent the only implementation method.

[0037] Please refer to FIG. 1 . In the related art, a pyramid velvet structure 500 is generally prepared on the surface of a photovoltaic cell through a velvet process to reduce the reflection of sunlight on the surface of the photovoltaic cell, so that the photovoltaic cell can absorb more sunlight, thereby improving the short-circuit current and efficiency of the cell.

[0038] However, for the pyramid's velvet structure 500, although the velvet structure 500 can reduce the reflectivity of the battery surface to about 11%, the surface of the pyramid's velvet structure 500 still does not fully utilize the secondary reflected and refracted light, and still causes a large optical loss.

[0039] In order to solve the above problems, referring to Figures 2, 3 and 4, the embodiment of the present application relates to a photovoltaic cell 10, including a silicon wafer 100, at least one surface of which has a plurality of pyramid structures 200 and a plurality of pits 200. It should be noted that the silicon wafer 100 can be made of single crystal silicon or polycrystalline silicon, which can be set according to the needs.

[0040] In one embodiment, a plurality of pyramid structures 200 and a plurality of pits 200 are disposed on the light-receiving surface of the silicon wafer 100. In another embodiment, a plurality of pyramid structures 200 and a plurality of pits 200 are disposed on both the light-receiving surface and the backlight surface of the silicon wafer 100.

[0041] Referring to Fig. 2, Fig. 3 and Fig. 4, a groove 210 of an arc structure is provided on the side wall of the pyramid structure 200. The pit 200 is located between two adjacent pyramid structures 200, and the pit 200 is connected to the groove 210 on the adjacent pyramid structure 200. Specifically, the pyramid structure 200 is protrudingly arranged on the surface of the silicon wafer 100. The pit 200 is connected to the inside of the groove 210 on the adjacent pyramid structure 200.

[0042] Specifically, a plurality of pyramid structures 200 are randomly arranged on the surface of the silicon wafer 100, and the pit 200 is located between two adjacent pyramid structures 200. It should be noted that: if a plurality of pyramid structures 200 are arranged circumferentially along one of the pyramid structures 200, the pit 200 is located between one of the pyramid structures 200 and the plurality of pyramid structures 200.

[0043] By providing an arc-shaped groove 210 on the side wall of the pyramid structure 200, and providing a pit 200 on the surface of the silicon wafer 100, and the pit 200 is connected to the groove 210 on the adjacent pyramid structure 200, the reflected light from the top of the pyramid structure 200 can be incident on the pit 200 and the groove 210 again, and the light incident on the pit 200 and the groove 210 can be reflected multiple times in the pit 200 and the groove 210, which can improve the utilization rate of the photovoltaic cell 10 for light, and can more effectively improve the short-circuit current and efficiency of the photovoltaic cell 10. Compared with the velvet structure 500 with pyramid protrusions, the reflectivity can be further reduced and the absorption of light can be improved.

[0044] The types of cells to which the present application is applicable include, but are not limited to, Passivated Emitter Rear Cell (PERC), Tunnel Oxide Passivated Contact (TOPCon), Heterojunction with Intrinsic Thin-film (HJT), Interdigitated Back Contact (IBC), Perovskite Cell, etc. Exemplarily, a plurality of pyramid structures 200 and a plurality of pits 200 are disposed on the light-receiving surface of the silicon wafer 100 of the Passivated Emitter Rear Cell, the Tunnel Oxide Passivated Contact, the Intrinsic Thin-film Heterojunction Cell, the Interdigitated Back Contact Cell, and the Perovskite Cell.

[0045] For PERC cells, along the thickness direction, PERC cells include the front surface metal silver electrode, the front surface silicon nitride passivation layer, the phosphorus layer emitter, the P-type base silicon layer, the local aluminum back field, the metal aluminum back electrode, and the back passivation layer (Al2O3 / SiNx). PERC cells use a passivation film to passivate the back, replacing the full aluminum back field, enhancing the internal back reflection of light in the silicon base, reducing the recombination rate on the back, and increasing the efficiency of the cell by 0.5%-1%.

[0046] For TOPCon cells, along the thickness direction, TOPCon cells include metal silver electrodes, front surface silicon nitride passivation layers, boron-doped emitters, N-type base silicon layers, diffused doping layers, ultra-thin silicon oxide, doped polysilicon, silicon nitride, and metal silver electrodes. The back of the cell is composed of an ultra-thin silicon oxide layer (1nm~2nm) and a phosphorus-doped microcrystalline amorphous mixed Si film, which together form a passivation contact structure. This structure can block the recombination of minority carrier holes and increase the open circuit voltage and short circuit current of the cell. The ultra-thin oxide layer allows majority electrons to tunnel into the polysilicon layer while blocking the recombination of minority carrier holes. The good passivation effect of ultra-thin silicon oxide and heavily doped silicon film causes the energy band on the silicon wafer surface to bend, thereby forming a field passivation effect, greatly increasing the probability of electron tunneling, and reducing the contact resistance, which increases the open circuit voltage and short circuit current of the cell, thereby improving the cell conversion efficiency.

[0047] For HJT cells, along the thickness direction, the HJT cells include a front low-temperature silver electrode, a front conductive film, an N-type amorphous silicon film, an intrinsic amorphous silicon film, an N-type base silicon layer, an intrinsic amorphous silicon film, a P-type amorphous silicon film, a back conductive film, and a back low-temperature silver electrode.

[0048] For IBC cells, along the thickness direction, IBC cells include silicon nitride anti-layer, N+ front surface field, N-type base silicon layer, P+ emitter, N+ back field, aluminum oxide passivation layer, silicon nitride anti-reflection layer, and metal silver electrode. IBC cells use ion implantation technology to obtain P and N regions with good uniformity and precisely controllable junction depth. There is no grid line blocking on the front of the cell, which can eliminate the shading current loss of the metal electrode and achieve the maximum utilization of incident photons. The short-circuit current can be increased by about 7% compared with conventional solar cells; due to the back contact structure, there is no need to consider the grid line blocking problem, and the grid line ratio can be appropriately widened, thereby reducing the series resistance and having a high fill factor; the surface passivation and surface light trapping structure can be optimized to obtain a lower front surface recombination rate and surface reflection.

[0049] For perovskite cells, along the thickness direction, the perovskite cell includes substrate material, conductive film, electron transport layer (titanium dioxide), perovskite absorption layer (hole transport layer), and metal cathode. Perovskite materials have a high light absorption coefficient and a long carrier diffusion distance. After the photons absorbed by the perovskite material are converted into electrons, they are easily collected by the electrode with low loss, so they can generate higher photoelectric voltage and current, making perovskite show higher photoelectric conversion efficiency.

[0050] Please refer to Figures 2, 3, 4 and 6. According to some embodiments of the present application, optionally, the pit 200 has an arc-shaped structure. Specifically, the pit 200 has an arc-shaped structure as a whole at a macroscopic angle. At a microscopic angle, the pit 200 has a continuous wave-shaped structure, wherein there are a plurality of continuous depressions. Correspondingly, the groove 210 has an arc-shaped structure as a whole at a macroscopic angle. At a microscopic angle, the groove 210 has a continuous wave-shaped structure, wherein there are a plurality of continuous depressions.

[0051] Referring to Figures 2, 3, 4 and 5, according to some embodiments of the present application, optionally, there is a bearing surface between the top of the pyramid structure 200 and the groove 210, and a protective layer 400 is provided on the bearing surface. The protective layer 400 can protect the bearing surface and prevent the acidic solution from etching part of the bearing surface.

[0052] Please refer to Figures 2, 3 and 4. According to some embodiments of the present application, optionally, the thickness of the protective layer 400 gradually decreases from the top of the pyramid structure 200 to the groove 210. The thicker protective layer 400 can protect the bearing surface, while the protective layer 400 at the bottom of the pyramid structure 200 is thinner and easily etched by an acidic solution, so that the groove 210 is formed on the side wall of the pyramid structure 200 near the bottom, and a pit 200 is formed on the surface of the silicon wafer 100 located between two adjacent pyramid structures 200.

[0053] Referring to FIG. 2 , FIG. 3 and FIG. 4 , according to some embodiments of the present application, optionally, the spacing between the bottom of the groove 210 and the opening of the groove 210 is 20 μm to 300 μm, that is, the groove depth of the groove 210 is 20 μm to 300 μm. By properly setting the groove depth of the groove 210, it is possible to avoid the groove depth of the groove 210 being too shallow, which may lead to a weakening of the reflectivity reduction effect, and it is also possible to avoid the groove depth being too deep, which may lead to an excessive reduction in reflectivity, and it is also possible to avoid the groove depth being too deep, which may lead to a reduction in the strength of the pyramid structure 200, thereby causing the pyramid structure 200 to break.

[0054] Exemplarily, the spacing between the bottom of the groove 210 and the opening of the groove 210 can be 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 150μm, 200μm or 250μm. The present application does not specifically limit the spacing between the bottom of the groove 210 and the opening of the groove 210. The spacing between the bottom of the groove 210 and the opening of the groove 210 can be selected between 20μm and 300μm.

[0055] Please refer to Figures 2, 3 and 4. According to some embodiments of the present application, optionally, the spacing between one end of the opening of the groove 210 away from the surface of the silicon wafer 100 and the surface of the silicon wafer 100 is 80μm to 1200μm, that is, the groove width of the opening of the groove 210 is 80μm to 1200μm.

[0056] By reasonably setting the groove width of the groove 210, it is possible to avoid the groove width of the groove 210 being too narrow, resulting in less light entering the groove 210, which reduces the utilization rate of light by the photovoltaic cell 10. It is also possible to avoid the groove depth being too large, resulting in a reduction in the strength of the pyramid structure 200, thereby causing the pyramid structure 200 to break.

[0057] Exemplarily, the spacing between the end of the opening of the groove 210 away from the surface of the silicon wafer 100 and the surface of the silicon wafer 100 can be 90μm, 100μm, 200μm, 300μm, 400μm, 500μm, 600μm, 700μm, 800μm, 900μm, 1000μm or 1200μm. The present application does not specifically limit the spacing between the end of the opening of the groove 210 away from the surface of the silicon wafer 100 and the surface of the silicon wafer 100. The spacing between the end of the opening of the groove 210 away from the surface of the silicon wafer 100 and the surface of the silicon wafer 100 can be selected between 80μm and 1200μm.

[0058] Please refer to FIG. 2 , FIG. 3 and FIG. 4 . According to some embodiments of the present application, optionally, the distance between the bottom of the pit 200 and the opening of the pit 200 is 30 μm to 400 μm, that is, the depth of the pit 200 is 30 μm to 400 μm.

[0059] By reasonably setting the depth of the pit 200, it is possible to avoid the pit 200 being too shallow, thereby weakening the reflectivity reduction effect, or being too deep, thereby reducing the reflectivity too much. It is also possible to avoid the pit 200 being too deep, thereby reducing the strength of the silicon wafer 100 and causing the silicon wafer 100 to break.

[0060] Exemplarily, the spacing between the bottom of the pit 200 and the opening of the pit 200 can be 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 200μm, 300μm or 400μm. The present application does not specifically limit the spacing between the bottom of the pit 200 and the opening of the pit 200. The spacing between the bottom of the pit 200 and the opening of the pit 200 can be selected between 30μm and 400μm.

[0061] Please refer to FIG. 2 , FIG. 3 and FIG. 4 . According to some embodiments of the present application, optionally, the length of the opening of the pit 200 is 10 μm to 1600 μm, that is, the groove width of the opening of the pit 200 is 10 μm to 1600 μm.

[0062] By reasonably setting the groove width of the pit 200, it is possible to avoid the groove width of the pit 200 being too narrow, resulting in less light entering the groove 210, which reduces the utilization rate of light by the photovoltaic cell 10. It is also possible to avoid the groove depth being too large, resulting in a reduction in the strength of the silicon wafer 100, thereby causing the silicon wafer 100 to break.

[0063] Exemplarily, the length of the opening of the pit 200 can be 10μm, 50μm, 100μm, 200μm, 300μm, 400μm, 500μm, 600μm, 700μm, 800μm, 900μm, 1000μm, 1200μm, 1400μm or 1600μm. The present application does not specifically limit the length of the opening of the pit 200, and the length of the opening of the pit 200 can be selected between 10μm and 1600μm.

[0064] Example 1

[0065] The present application also provides a method for preparing a photovoltaic cell 10, comprising the following steps:

[0066] S1. Clean the surface of the silicon wafer 100 to ensure the subsequent texturing effect.

[0067] S2. Use an alkaline solution to perform a first texturing on the surface of the silicon wafer 100 to form a pyramid structure 200 on the surface of the silicon wafer 100. The alkaline solution is a sodium hydroxide solution, and a texturing additive may also be added to the sodium hydroxide solution to enhance the first texturing effect. Specifically, the temperature of the alkaline texturing is 80° C., and the temperature of the alkaline texturing is 400 seconds.

[0068] S3. Deposit a protective layer 400 on the surface of the pyramid structure 200. Specifically, oxidize the surface of the pyramid structure 200 to form a BSG layer (Boro-silicate Glass) on the surface of the pyramid structure 200. More specifically, the silicon wafer 100 formed with the pyramid structure 200 can be placed in a deposition chamber, firstly introduce nitrogen to create a vacuum, then introduce oxygen, and raise the temperature to above 800° C., and keep it for 1 hour for oxidation, so as to form a BSG layer on the surface of the pyramid structure 200.

[0069] S4, using an acidic solution to perform a second texturing on the surface of the silicon wafer 100, so as to form a pit 200 on the surface of the silicon wafer 100, and a groove 210 on the side wall of the pyramid structure 200. The acidic solution is a nitric acid solution. Specifically, the temperature of the acid texturing is 8°C, and the temperature of the acid texturing is 60s.

[0070] Example 2

[0071] The present application also provides a method for preparing a photovoltaic cell 10, comprising the following steps:

[0072] S1. Clean the surface of the silicon wafer 100 to ensure the subsequent texturing effect.

[0073] S2. Use an alkaline solution to perform a first texturing on the surface of the silicon wafer 100 to form a pyramid structure 200 on the surface of the silicon wafer 100. The alkaline solution is a sodium hydroxide solution, and a texturing additive may also be added to the sodium hydroxide solution to enhance the first texturing effect. Specifically, the temperature of the alkaline texturing is 80° C., and the temperature of the alkaline texturing is 400 seconds.

[0074] S3, depositing a protective layer 400 on the surface of the pyramid structure 200. Specifically, the silicon wafer 100 formed with the pyramid structure 200 is placed in a boron diffusion furnace for BSG deposition and slight advancement, and then the surface of the pyramid structure 200 diffused with boron is oxidized to form a BSG layer on the surface of the pyramid structure 200.

[0075] More specifically, the silicon wafer 100 diffused with boron element is placed in a deposition chamber, nitrogen is introduced to create a vacuum, oxygen is introduced, and the temperature is raised to above 800° C. and maintained for 1 hour for oxidation to form a BSG layer on the surface of the pyramid structure 200 .

[0076] S4, using an acidic solution to perform a second texturing on the surface of the silicon wafer 100, so as to form a pit 200 on the surface of the silicon wafer 100, and a groove 210 on the side wall of the pyramid structure 200. The acidic solution is a sulfuric acid solution. Specifically, the temperature of the acid texturing is 8°C, and the temperature of the acid texturing is 60s.

[0077] Example 3

[0078] The present application also provides a method for preparing a photovoltaic cell 10, comprising the following steps:

[0079] S1. Clean the surface of the silicon wafer 100 to ensure the subsequent texturing effect.

[0080] S2. Use an alkaline solution to perform a first texturing on the surface of the silicon wafer 100 to form a pyramid structure 200 on the surface of the silicon wafer 100. The alkaline solution is a sodium hydroxide solution, and a texturing additive may also be added to the sodium hydroxide solution to enhance the first texturing effect. Specifically, the temperature of the alkaline texturing is 80° C., and the temperature of the alkaline texturing is 400 seconds.

[0081] S3, depositing a protective layer 400 on the surface of the pyramid structure 200. Specifically, the surface of the pyramid structure 200 is subjected to SiN X / SiO X Deposition to form SiO on the surface of the pyramid structure 200 X N X layer.

[0082] S4, using an acidic solution to perform a second texturing on the surface of the silicon wafer 100, so as to form a pit 200 on the surface of the silicon wafer 100, and a groove 210 on the sidewall of the pyramid structure 200. The acidic solution is hydrogen fluoride. Specifically, the temperature of the acid texturing is 8°C, and the temperature of the acid texturing is 60s.

[0083] The comparative example comprises the following steps:

[0084] S1. Clean the surface of the silicon wafer 100 to ensure the subsequent texturing effect.

[0085] S2. Use an alkaline solution to texturize the surface of the silicon wafer 100 to form a pyramid structure 200 on the surface of the silicon wafer 100. The alkaline solution is a sodium hydroxide solution, and a texturizing additive can also be added to the sodium hydroxide solution to improve the texturizing effect. Specifically, the temperature of the alkaline texturizing is 80° C. and the temperature of the alkaline texturizing is 400 seconds.

[0086] The photovoltaic cells 10 after texturing in Examples 1-3 and the comparative example were tested respectively, and the conclusions drawn were: the surface reflectivity of the silicon wafer 100 in Examples 1-3 was 6%, and the surface reflectivity of the silicon wafer 100 in the comparative example was 11%. After the surface of the silicon wafer 100 was texturized for the first time, the protective layer 400 was deposited, and the second texturization was performed, the light reflectivity of the photovoltaic cell 10 can be effectively reduced, and the photoelectric conversion efficiency can be improved.

[0087] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0088] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A photovoltaic cell, characterized in that: The invention comprises a silicon wafer, wherein at least one surface of the silicon wafer has a plurality of pyramid structures and a plurality of pits. A groove of an arc structure is arranged on the side wall of the pyramid structure; the pit is located between two adjacent pyramid structures, and the pit is connected to the groove on the adjacent pyramid structure.

2. The photovoltaic cell according to claim 1, characterized in that: The pit is in an arc-shaped structure.

3. The photovoltaic cell according to claim 1, characterized in that: A bearing surface is provided between the top of the pyramid structure and the groove, and a protective layer is provided on the bearing surface.

4. The photovoltaic cell according to claim 3, characterized in that: The thickness of the protection layer gradually decreases from the top of the pyramid structure to the groove.

5. The photovoltaic cell according to claim 1, characterized in that: The distance between the bottom of the groove and the opening of the groove is 20 μm to 300 μm.

6. The photovoltaic cell according to claim 1, characterized in that: The distance between the end of the opening of the groove away from the surface of the silicon wafer and the surface of the silicon wafer is 80 μm to 1200 μm.

7. The photovoltaic cell according to claim 1, characterized in that: The distance between the bottom of the pit and the opening of the pit is 30 μm to 400 μm.

8. The photovoltaic cell according to claim 1, characterized in that: The opening of the pit has a length of 10 μm to 1600 μm.

9. A method for preparing a photovoltaic cell according to any one of claims 1 to 8, characterized in that: include: Using an alkaline solution to perform a first texturing on the surface of the silicon wafer to form the pyramid structure on the surface of the silicon wafer; depositing a protective layer on the surface of the pyramid structure; The surface of the silicon wafer is textured for the second time using an acidic solution to form pits on the surface of the silicon wafer and grooves on the side walls of the pyramid structure.

10. The method for preparing a photovoltaic cell according to claim 9, characterized in that: The protective layer includes SiO X N X layer or BSG layer.

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