Method of manufacturing display panel

Abstract

The method of manufacturing a display panel includes: forming a light emitting element on a base substrate; the light emitting element is first transferred to the first film; fixing a first film on which the light emitting element is arranged; elongating the first film by pressurizing the first film with a gas; and secondarily transferring the light emitting elements rearranged by stretching the first film to a second film fixed to the stage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0102949 filed in the Korean Intellectual Property Office on August 7, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] One or more embodiments described herein relate to a method of manufacturing a display panel. Background Art

[0004] As information technology develops, the importance of display devices as a connection medium between users and information has been emphasized. Due to the importance of display devices, the use of various display devices such as liquid crystal display devices and organic light emitting display devices has increased.

[0005] A display panel such as a light-emitting display panel or a liquid crystal display panel can be used as a device for displaying an image on a display device. In the above example, the light-emitting display panel may include a plurality of light-emitting elements. For example, the light-emitting element may include an organic light-emitting element using an organic material as a fluorescent material or an inorganic light-emitting element using an inorganic material as a fluorescent material.

[0006] In manufacturing a display panel using an inorganic light emitting element as a light emitting element, micro LEDs need to be precisely arranged on a substrate of the display panel. Summary of the invention

[0007] Various embodiments of the present disclosure are directed to a method of manufacturing a display panel on which a plurality of light emitting elements are substantially uniformly and accurately arranged.

[0008] One or more embodiments of the present disclosure may provide a method for manufacturing a display panel, the method comprising: forming a light-emitting element on a base substrate; first transferring the light-emitting element to a first film; fixing the first film on which the light-emitting element is arranged; stretching the first film by pressurizing the first film with a gas; and secondarily transferring the light-emitting element rearranged by stretching the first film to a second film fixed to a stage.

[0009] Elongating the first film may include elongating the first film into a spherical shape.

[0010] The gas may include air.

[0011] The distance between the light emitting elements may be increased by elongating the first film.

[0012] Elongating the first film may include elongating the first film to a second film spaced apart from the first film.

[0013] Secondarily transferring the light emitting element may include pressurizing a portion of the first film on which the rearranged light emitting element is positioned with a gas so that the portion is parallel to the second film.

[0014] The method may further include positioning a second film on a cell mask that is above the display substrate and defines a cell opening; pressurizing a portion of the second film with a gas; and irradiating the portion of the second film with a laser.

[0015] The portion of the second film may overlap with one of the cell openings.

[0016] When the portion of the second film is pressurized, the light emitting element rearranged and positioned on the portion of the second film may contact the display substrate.

[0017] While illuminating the portion, the light emitting element rearranged and positioned on the portion of the second film may be bonded to the display substrate.

[0018] Pressurizing the portion of the second film and irradiating the portion may be performed based on the cell opening.

[0019] When the light emitting element is secondarily transferred, the stage may be moved downward toward the first film.

[0020] When the light emitting element is secondarily transferred, the stage may be moved downward toward the first film while being tilted.

[0021] When the light-emitting element is transferred secondarily, the first film may be moved upward toward the second film.

[0022] When the light-emitting element is secondarily transferred, the first film may be moved upward toward the second film while being tilted. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a plan view of a display device according to one or more embodiments of the present disclosure.

[0024] Figure 2 is a plan view schematically illustrating an emission area of ​​each pixel according to one or more embodiments.

[0025] Figure 3 is a plan view schematically illustrating an emission area of ​​each pixel according to one or more embodiments.

[0026] Figure 4 is an equivalent circuit diagram of each pixel according to one or more embodiments.

[0027] Figure 5 is an equivalent circuit diagram of each pixel according to one or more embodiments.

[0028] Figure 6 is a schematic diagram showing a method of Figure 2 A cross-sectional view of a section taken along line AA'.

[0029] Figure 7 It is schematically shown Figure 6 A magnified view of the first emission area.

[0030] Figure 8 It is shown in detail Figure 7 A cross-sectional view of a light-emitting element.

[0031] Fig. 9 is a schematic diagram showing a method of Figure 2 A cross-sectional view of a section taken along line AA'.

[0032] Fig.10 is a schematic diagram showing a method of Figure 2 A cross-sectional view of a section taken along line AA'.

[0033] Fig.11 is a flowchart for describing a method of manufacturing a display panel according to one or more embodiments.

[0034] Figures 12 to 30 is a diagram schematically illustrating a process of manufacturing a display panel according to one or more embodiments. DETAILED DESCRIPTION

[0035] Aspects of some embodiments of the present disclosure and methods for realizing them can be more easily understood by referring to the detailed description and drawings of the embodiments. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and aspects of the present disclosure will be fully conveyed to those skilled in the art. Therefore, redundant processes, elements and techniques that are irrelevant or unrelated to the description of the embodiments or that are unnecessary for those of ordinary skill in the art to fully understand the various aspects of the present disclosure can be omitted. Unless otherwise stated, in the entire drawings and written descriptions, the same reference numerals, characters or combinations thereof represent the same elements, and therefore, repeated descriptions thereof can be omitted.

[0036] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments shown herein. The use of "can", "may" or "may not" when describing an embodiment corresponds to one or more embodiments of the present disclosure. The present disclosure encompasses all modifications, equivalents and substitutions within the scope of the ideas and techniques of the present disclosure. In addition, each of the features of the various embodiments of the present disclosure may be combined with each other in part or in its entirety, and may be technically interlocked and driven in various ways. Each embodiment may be implemented independently of one another, or may be implemented together in association.

[0037] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In addition, the use of cross-hatching and / or shading in the drawings is generally provided to clarify boundaries between adjacent elements. Therefore, unless specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements.

[0038] Various embodiments are described herein with reference to cross-sectional views as schematic illustrations of embodiments and / or intermediate structures. Therefore, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances should be expected. In addition, the specific structural or functional descriptions disclosed herein are merely exemplary for the purpose of describing embodiments according to the concepts of the present disclosure. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the shapes of the elements, layers, or regions shown, but should include deviations in shapes due to, for example, manufacturing.

[0039] For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs.

[0040] For ease of explanation, spatial relative terms such as "below", "below", "lower", "lower side", "below", "above", "upper side", etc. may be used herein to describe the relationship between an element or feature and another (some) element or feature as shown in the drawings. It will be understood that, in addition to the orientation depicted in the drawings, spatial relative terms are intended to include different orientations of the device in use or in operation. For example, if the device in the drawings is turned over, the elements described as being "below", "below" or "below" other elements or features will be oriented "above" other elements or features. Therefore, the exemplary terms "below" and "below" can include both upper and lower orientations. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. Similarly, when a first portion is described as being arranged "on" a second portion, this means that the first portion is arranged at the upper or lower side of the second portion (not limited to the upper side of the second portion based on the direction of gravity).

[0041] In addition, the phrase "in a plan view" means when the object portion is observed from above, and the phrase "in a schematic cross-sectional view" means when the schematic cross-section taken by vertically cutting the object portion is observed from the side. The term "overlap" or "overlapped" means that the first object can be above or below the second object, or on one side of the second object, and conversely, the second object can be above or below the first object, or on one side of the first object. In addition, the term "overlap" can include stacking, facing or facing, extending throughout..., covering or partially covering or any other suitable term as will be appreciated and understood by a person of ordinary skill in the art. The expression "non-overlapping" can include meanings such as "spaced apart from..." or "separated from..." or "offset from..." and any other suitable equivalents as will be appreciated and understood by a person of ordinary skill in the art. The terms "facing" and "facing" can mean that the first object can be directly or indirectly opposite to the second object. In the case where a third object is between the first object and the second object, the first object and the second object can be understood to be indirectly opposite to each other, but still facing each other.

[0042] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, it may be formed directly on, directly on, directly connected to, or directly coupled to another element, layer, region, or component, or indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to another element, layer, region, or component such that one or more intervening elements, layers, regions, or components may be present. Furthermore, this may collectively mean directly or indirectly coupled or connected, as well as integrally or non-integrally coupled or connected. For example, when an element, layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another element, layer, region, or component, it may be directly electrically connected or directly electrically coupled to another element, layer, region, and / or component, or there may be one or more intervening elements, layers, regions, or components. One or more intervening components may include switches, resistors, capacitors, etc. When describing an embodiment, unless explicitly described as being directly connected, a connected statement indicates an electrical connection, and "directly connected / directly coupled" or "directly on..." means that one component is directly connected or directly coupled to another component, or directly on another component, without an intermediate component.

[0043] In addition, in this specification, when the part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upper direction, but includes forming the part on the side surface or in the lower direction. On the contrary, when the part of a layer, film, region, plate, etc. is formed "under" another part, this not only includes the situation that the part is "directly below" another part, but also includes the situation that there is another part between the part and the other part. At the same time, other expressions such as "between...", "directly between..." or "adjacent to..." and "directly adjacent to..." describing the relationship between components can be similarly interpreted. It will be understood that when an element or layer is referred to as "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0044] For the purposes of this disclosure, when expressions such as "at least one of" or "any one of" or "one or more of" are located after a list of elements, they modify the entire list of elements and do not modify the individual elements in the list. For example, "at least one of X, Y, and Z", and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z (such as, for example, XYZ, XYY, YZ, and ZZ), or any variation thereof. Similarly, expressions such as "at least one of A and B" may include A, B, or A and B. As used herein, "or" generally means "and / or", and the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, expressions such as "A and / or B" may include A, B, or A and B.

[0045] It will be understood that although the terms "first", "second", "third", etc. can be used in this article to describe various elements, components, areas, layers and / or sections, these elements, components, areas, layers and / or sections should not be limited by these terms. These terms do not correspond to a specific order, position or priority, and are only used to distinguish an element, member, component, area, region, layer, section or part from another element, member, component, area, region, layer, section or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, first component, first area, first layer or first section described below can be referred to as the second element, second component, second area, second layer or second section. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first", "second", etc. may also be used herein to distinguish elements of different categories or groups. For the sake of simplicity, the terms "first", "second", etc. may respectively represent "first category (or first group)", "second category (or second group)", etc.

[0046] In the example, the x-axis, y-axis and / or z-axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction and / or the third direction.

[0047] The terms used herein are only for the purpose of describing the embodiments, and are not intended to limit the present disclosure. As used herein, the singular forms "one" and "a kind of" are intended to also include plural forms, and the plural forms are also intended to include singular forms, unless the context clearly indicates otherwise. It will also be understood that when used in this specification, the terms "include", "include", "have", "have", "contain" and "contain" specify the existence of stated features, wholes, steps, operations, elements and / or components, but do not exclude the existence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups.

[0048] When one or more embodiments can be implemented differently, a specific process order can be performed differently from the described order. For example, two processes described in succession can be performed substantially simultaneously, or in the reverse order of the described order.

[0049] As used herein, the terms "substantially", "about", "approximately" and similar terms are used as approximate terms and not as terms of degree, and are intended to explain the inherent deviations of measured or calculated values ​​that will be recognized by those of ordinary skill in the art. For example, "substantially" may include a range of + / -5% of the corresponding value. In view of the measurement discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), as used herein, "about" or "approximately" includes the stated value and means within an acceptable deviation range of a particular value determined by those of ordinary skill in the art. For example, "about" may mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5% of the stated value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure".

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0051] Figure 1 is a plan view of a display device 10 according to one or more embodiments of the present disclosure.

[0052] refer to Figure 1The display device 10 can be applied to smart phones, mobile phones, tablet PCs, personal digital assistants (PDAs), portable multimedia players (PMPs), televisions, game consoles, watch-type electronic devices, head-mounted displays, monitors for personal computers, laptop computers, car navigation systems, car dashboards, digital cameras, video cameras, outdoor billboards, electronic scoreboards, medical devices, inspection devices, home appliances such as refrigerators and washing machines, or Internet of Things (IoT) devices.

[0053] The display device 10 can be divided into various categories based on the display scheme. For example, the display device 10 can be divided into an organic light emitting diode (OLED) display device, an inorganic light emitting (inorganic EL) display device, a quantum dot light emitting diode (QED) display device, a micron LED (micron-LED) display device, a nano LED display device, a plasma display panel (PDP), a field emission display (FED) device, a cathode ray tube (CRT) display device, a liquid crystal display (LCD) device, an electrophoretic display (EPD) device, etc. In the following, a micron LED display device will be described as an example of the display device 10, and unless otherwise specifically mentioned, the micron LED display device applied in the embodiment will be simply referred to as the display device 10. However, the embodiment is not limited to the micron LED display device, and other display devices listed above or known in the art within the scope of the present technical concept may also be applied.

[0054] In addition, in the following drawings, the first direction DR1 refers to the horizontal direction of the display device 10, the second direction DR2 refers to the vertical direction of the display device 10, and the third direction DR3 refers to the thickness direction of the display device 10. In this case, "left", "right", "upper", and "lower" refer to directions of the display device 10 in a plan view. For example, "right side" refers to one side of the first direction DR1, "left side" refers to the other side of the first direction DR1, "upper side" may refer to one side of the second direction DR2, and "lower side" may refer to the other side of the second direction DR2. In addition, "upper part" may refer to one side of the third direction DR3, and "lower part" may refer to the other side of the third direction DR3.

[0055] In a plan view, the display device 10 may have a circular shape, an oval shape, or a square shape, and for example, has a square shape. In addition, in the case where the display device 10 is a television, the display device 10 may have a rectangular shape in which the long sides are aligned in the horizontal direction. However, the present disclosure is not limited thereto, and the long sides may be aligned in the vertical direction, or the display device 10 may be rotatably mounted so that the long sides can be variably aligned in the horizontal direction or the vertical direction.

[0056] The display device 10 may include a display area DPA and a non-display area NDA. The display area DPA may be an effective area in which an image is displayed. The display area DPA may have a square shape in a plan view in a manner similar to the overall shape of the display device 10, but is not limited thereto. For example, the display area DPA may have a circular shape or an elliptical shape.

[0057] The display area DPA may include a plurality of pixels PX. The plurality of pixels PX may be arranged in a matrix form. In a plan view, the shape of each pixel PX has a rectangular shape or a square shape, but is not limited thereto, and may have a diamond shape in which each side is inclined relative to one side of the display device 10. The plurality of pixels PX may include pixels PX of various colors. For example, the plurality of pixels PX may include, but are not limited to, a first color pixel PX of red, a second color pixel PX of green, and a third color pixel PX of blue. The individual color pixels PX may be alternately arranged in stripes or Type Configuration( is a registered trademark of Samsung Display Co., Ltd. of South Korea).

[0058] The non-display area NDA may be located around the display area DPA. The non-display area NDA may surround the entirety or a portion of the display area DPA. The display area DPA may have various shapes such as a circular shape and a square shape. The non-display area NDA may be formed in a shape surrounding the periphery of the display area DPA. The non-display area NDA may be configured as a frame of the display device 10.

[0059] A driving circuit or a driving element configured to drive the display area DPA may be located in the non-display area NDA. Figure 1 In the non-display area NDA located adjacent to the second side (or the lower side) of the display device 10, the pad assembly may be provided on the display substrate of the display device 10, and the external device EXD may be mounted on the pad electrode of the pad assembly. Examples of the external device EXD may include a connection film, a printed circuit board, a driving chip DIC, a connector, a line connection film, etc. Figure 1 In the non-display area NDA adjacent to the left side of the display device 10, a scan driving component SDR directly formed on the display substrate of the display device 10 may be positioned.

[0060] Figure 2 is a plan view schematically illustrating an emission region of each pixel PX according to one or more embodiments.

[0061] refer to Figure 2, the plurality of pixels PX may be arranged in a matrix form. The plurality of pixels PX may be divided into a first color pixel PX of red, a second color pixel PX of green, and a third color pixel PX of blue. In addition, a fourth color pixel PX of white may also be included.

[0062] The pixel electrode of the first color pixel PX may be positioned in the first emission area EA1, and at least a portion thereof may extend to the non-emission area NEA. The pixel electrode of the second color pixel PX may be positioned in the second emission area EA2, and at least a portion thereof may extend to the non-emission area NEA. The pixel electrode of the third color pixel PX may be positioned in the third emission area EA3, and at least a portion thereof may extend to the non-emission area NEA. The pixel electrode of each of the pixels PX may be connected to any one of the switching elements included in the corresponding pixel circuit through a contact hole passing through at least one insulating layer.

[0063] A plurality of light emitting elements LE are located on the pixel electrodes of the first emission area EA1, the pixel electrodes of the second emission area EA2, and the pixel electrodes of the third emission area EA3. In other words, the light emitting element LE is located in each of the first emission area EA1, the second emission area EA2, and the third emission area EA3. A red first color filter, a green second color filter, and a blue third color filter may be located in the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively, in which the plurality of light emitting elements LE are located. The first organic layer FOL may be located in the non-emission area NEA.

[0064] Figure 3 is a plan view schematically illustrating an emission region of each pixel PX according to one or more embodiments.

[0065] refer to Figure 3 In a plan view, the shape of each of the pixels PX is not limited to a rectangular shape or a square shape, and may have a rhombus shape with each side thereof inclined relative to one side of the display device 10, thereby forming Structure. In each of the pixels PX of the structure, the first emission area EA1 of the first color pixel PX, the second emission area EA2 of the second color pixel PX, the third emission area EA3 of the third color pixel PX, and the fourth emission area EA4 of the pixel PX of any one color from the first color to the third color can each have a diamond shape.

[0066] The size or plane surface area of ​​each of the first to fourth emission areas EA1 to EA4 of each pixel PX may be the same or different. Likewise, the number of light emitting elements LE formed in the first to fourth emission areas EA1 to EA4 may be the same or different.

[0067] The surface area of ​​the first emission area EA1, the surface area of ​​the second emission area EA2, the surface area of ​​the third emission area EA3, and the surface area of ​​the fourth emission area EA4 may be the same or similar, but are not limited thereto, and may be different from each other. The distance between the first emission area EA1 and the second emission area EA2 adjacent to each other, the distance between the second emission area EA2 and the third emission area EA3 adjacent to each other, the distance between the first emission area EA1 and the third emission area EA3 adjacent to each other, and the distance between the third emission area EA3 and the fourth emission area EA4 adjacent to each other may be the same or similar to each other, or may be different from each other. The embodiments of the present disclosure are not limited to the above examples.

[0068] In addition, the first emission area EA1 may emit the first light, the second emission area EA2 may emit the second light, and the third emission area EA3 and the fourth emission area EA4 may emit the third light, but the embodiments of the present disclosure are not limited thereto. For example, the first emission area EA1 may emit the second light, the second emission area EA2 may emit the first light, and the third emission area EA3 and the fourth emission area EA4 may emit the third light. Alternatively, the first emission area EA1 may emit the third light, the second emission area EA2 may emit the second light, and the third emission area EA3 and the fourth emission area EA4 may emit the first light. As another alternative, at least one emission area of ​​the first emission area EA1 to the fourth emission area EA4 may emit the fourth light. The fourth light may be light in the yellow wavelength band. In other words, the main peak wavelength of the fourth light may be in the range of about 550nm to about 600nm, but the embodiments of the present disclosure are not limited thereto.

[0069] Figure 4 is an equivalent circuit diagram of each pixel PX according to one or more embodiments.

[0070] refer to Figure 4 , each pixel PX may include three transistors DTR, STR1 and STR2 and a storage capacitor CST to drive the light emitting element LE. The driving transistor DTR may adjust the current flowing from the first power line ELVDL to which the first power voltage is applied to any one of the light emitting elements LE in response to the voltage difference between the gate electrode and the source electrode. The gate electrode of the driving transistor DTR may be connected to the first electrode of the first transistor STR1. The source electrode of the driving transistor DTR may be connected to the first electrode of any one of the light emitting elements LE. The drain electrode of the driving transistor DTR may be connected to the first power line ELVDL to which the first power voltage is applied.

[0071] The first transistor STR1 may be turned on by a scan signal from a scan line SCL, thereby connecting the data line DTL to the gate electrode of the drive transistor DTR. The gate electrode of the first transistor STR1 may be connected to the scan line SCL. The first electrode of the first transistor STR1 may be connected to the gate electrode of the drive transistor DTR. The second electrode of the first transistor STR1 may be connected to the data line DTL.

[0072] The second transistor STR2 can be turned on by the sensing signal from the sensing signal line SSL, thereby connecting the initialization voltage line VIL to the source electrode of the driving transistor DTR. The gate electrode of the second transistor STR2 can be connected to the sensing signal line SSL. The first electrode of the second transistor STR2 can be connected to the initialization voltage line VIL. The second electrode of the second transistor STR2 can be connected to the source electrode of the driving transistor DTR.

[0073] In one or more embodiments, a first electrode of each of the first transistor STR1 and the second transistor STR2 may be a source electrode, and a second electrode thereof may be a drain electrode, but the present disclosure is not limited thereto and a reverse configuration is also possible.

[0074] The storage capacitor CST may be formed between the gate electrode and the source electrode of the driving transistor DTR. The storage capacitor CST may store a voltage corresponding to a voltage difference between the gate electrode and the source electrode of the driving transistor DTR.

[0075] The driving transistor DTR and the first transistor STR1 and the second transistor STR2 may each be formed of a thin film transistor. Figure 4 , it has been described that the driving transistor DTR and the first transistor STR1 and the second transistor STR2 are each formed by an n-type metal oxide semiconductor field effect transistor (MOSFET), but the present disclosure is not limited thereto. In other words, the driving transistor DTR and the first transistor STR1 and the second transistor STR2 may each be formed by a p-type MOSFET, or one or more may be formed by an n-type MOSFET, and one or more other transistors may be formed by a p-type MOSFET.

[0076] Figure 5 is an equivalent circuit diagram of each pixel PX according to one or more embodiments.

[0077] refer to Figure 5 Each pixel PX may include a driving transistor DTR, a switching element and a storage capacitor CST to drive the light emitting element LE. The switching element may include a first transistor STR1, a second transistor STR2, a third transistor STR3, a fourth transistor STR4, a fifth transistor STR5 and a sixth transistor STR6.

[0078] The driving transistor DTR may include a gate electrode, a first electrode, and a second electrode. The driving transistor DTR may control a drain-source current (hereinafter referred to as a "driving current") flowing between the first electrode and the second electrode in response to a data voltage applied to the gate electrode.

[0079] The capacitor Cel may be formed between the second electrode of the driving transistor DTR and the second power line ELVSL. One electrode of the capacitor Cel may be connected to the second electrode of the driving transistor DTR, and the other electrode of the capacitor Cel may be connected to the second power line ELVSL.

[0080] In the case where the first electrode of each of the first transistor STR1, the second transistor STR2, the third transistor STR3, the fourth transistor STR4, the fifth transistor STR5, the sixth transistor STR6, and the driving transistor DTR is a source electrode, the second electrode thereof may be a drain electrode. Alternatively, in the case where the first electrode of each of the first transistor STR1, the second transistor STR2, the third transistor STR3, the fourth transistor STR4, the fifth transistor STR5, the sixth transistor STR6, and the driving transistor DTR is a drain electrode, the second electrode thereof may be a source electrode.

[0081] The driving transistor DTR, the second transistor STR2, the fourth transistor STR4, the fifth transistor STR5 and the sixth transistor STR6 may each be formed by a p-type MOSFET, and the first transistor STR1 and the third transistor STR3 may each be formed by an n-type MOSFET. Alternatively, the first transistor STR1, the second transistor STR2, the third transistor STR3, the fourth transistor STR4, the fifth transistor STR5 and the sixth transistor STR6 and the driving transistor DTR may each be formed by a p-type MOSFET. The first transistor STR1 may be turned on in response to a scan signal received through the scan line GCL, and therefore, the gate electrode and the second electrode of the driving transistor DTR may be connected to each other, or in other words, the driving transistor DT may be diode-connected. The second transistor STR2 may be turned on in response to a scan signal received through the scan line GWL, and may transmit a data signal transmitted from the data line DTL to the gate electrode of the driving transistor DTR. The third transistor STR3 may be turned on in response to a scan signal transmitted through the scan line GIL, so that the initialization voltage transmitted through the initialization voltage line VIL is transmitted to the gate electrode of the driving transistor DTR. The fourth transistor STR4 is turned on in response to the scan signal received through the scan line GWL to electrically connect the anode of the light emitting element LE and the initialization voltage line VIL. The fifth transistor STR5 and the sixth transistor STR6 can be turned on in parallel with each other (e.g., simultaneously or substantially simultaneously) in response to the emission control signal ELk transmitted through the emission line. In this way, the first power voltage transmitted through the first power line ELVDL can be compensated by the diode-connected drive transistor DTR so that the first power voltage is provided to the light emitting element LE.

[0082] It should be noted that the equivalent circuit diagram of the pixel PX according to the aforementioned embodiment of the present specification is not limited to Figure 4 and Figure 5 The equivalent circuit diagram shown in Figure 4 and Figure 5 In addition to the embodiment shown in , the equivalent circuit diagram of the pixel PX according to the embodiment of this specification can also be formed into other circuit structures known and adopted by those skilled in the art.

[0083] Figure 6 is a schematic diagram showing a method of Figure 2 A cross-sectional view of a section taken along line AA'. Figure 7 It is schematically shown Figure 6 An enlarged view of the first emission area EA1. Figure 8 It is shown in detail Figure 7 A cross-sectional view of a light emitting element LE.

[0084] refer to Figures 6 to 8The display panel of the display device 10 may include a display substrate 100 and a wavelength conversion component 200 located on the display substrate 100 .

[0085] The barrier layer BR may be located on the first substrate 110 of the display substrate 100. The first substrate 110 may be formed of an insulating material such as a polymer resin. For example, the first substrate 110 may be formed of polyimide. The first substrate 110 may be a flexible substrate that can be bent, folded, rolled, etc.

[0086] The barrier layer BR may be a layer provided to protect the thin film transistors T1, T2, and T3 and the light emitting element assembly LEP from moisture that may penetrate through the first substrate 110 susceptible to moisture penetration. The barrier layer BR may be formed of a plurality of inorganic layers stacked alternately. For example, the barrier layer BR may be formed as a multilayer structure provided by alternately stacking one or more inorganic layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0087] The thin film transistors T1, T2, and T3 may be located on the barrier layer BR. Each of the thin film transistors T1, T2, and T3 may include an active layer ACT1 / ACT2 / ACT3, a gate electrode G1 / G2 / G3, a source electrode S1 / S2 / S3, and a drain electrode D1 / D2 / D3.

[0088] The active layer ACT1 / ACT2 / ACT3, the source electrode S1 / S2 / S3 and the drain electrode D1 / D2 / D3 of the thin film transistors T1, T2 and T3 may be located on the barrier layer BR. The active layer ACT1 / ACT2 / ACT3 of each of the thin film transistors T1, T2 and T3 may include polycrystalline silicon, single crystal silicon, low temperature polycrystalline silicon, amorphous silicon or an oxide semiconductor. The active layer ACT1 / ACT2 / ACT3 overlapping with the gate electrode G1 / G2 / G3 in the third direction DR3 (which is the thickness direction of the first substrate 110) may be defined as a channel region. Each of the source electrode S1 / S2 / S3 and the drain electrode D1 / D2 / D3 is a region that does not overlap with the gate electrode G1 / G2 / G3 in the third direction DR3, and may have conductivity by doping the silicon semiconductor or the oxide semiconductor with ions or impurities.

[0089] The gate insulating layer 130 may be located on the active layers ACT1 / ACT2 / ACT3, the source electrodes S1 / S2 / S3, and the drain electrodes D1 / D2 / D3 of the thin film transistors T1, T2, and T3. The gate insulating layer 130 may be formed of an inorganic layer (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer).

[0090] The gate electrodes G1 / G2 / G3 of the thin film transistors T1, T2, and T3 may be located on the gate insulating layer 130. The gate electrodes G1 / G2 / G3 may overlap the active layer ACT1 / ACT2 / ACT3 in the third direction DR3. The gate electrodes G1 / G2 / G3 may have a single-layer or multi-layer structure formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof.

[0091] The first interlayer insulating layer 141 included in the interlayer insulating layer 140 may be located on the gate electrodes G1 / G2 / G3 of the thin film transistors T1, T2, and T3. The first interlayer insulating layer 141 may be formed of an inorganic layer (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer). The first interlayer insulating layer 141 may be formed of a plurality of inorganic layers.

[0092] The capacitor electrode CAE may be located on the first interlayer insulating layer 141. The capacitor electrode CAE may overlap the gate electrodes G1 / G2 / G3 of the thin film transistors T1, T2, and T3 in the third direction DR3. Since the first interlayer insulating layer 141 has a certain dielectric constant, a capacitor may be formed by the capacitor electrode CAE, the gate electrodes G1 / G2 / G3, and the first interlayer insulating layer 141 therebetween. The capacitor electrode CAE may have a single-layer or multi-layer structure formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof.

[0093] The second interlayer insulating layer 142 included in the interlayer insulating layer 140 may be located on the capacitor electrode CAE. The second interlayer insulating layer 142 may be formed of an inorganic layer (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer). The second interlayer insulating layer 142 may be formed of a plurality of inorganic layers.

[0094] The first anode connection electrode ADNE1 may be located on the second interlayer insulating layer 142. The first anode connection electrode ADNE1 may be connected to the drain electrode D1 / D2 / D3 of the thin film transistor T1 / T2 / T3 through the first connection contact hole ANCT1 passing through the gate insulating layer 130, the first interlayer insulating layer 141, and the second interlayer insulating layer 142. The first anode connection electrode ADNE1 may have a single-layer or multi-layer structure formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof.

[0095] The first planarization layer 160 may be located on the first anode connection electrode ADNE1 to planarize a stepped portion formed by the thin film transistors T1, T2, and T3. The first planarization layer 160 may be formed of an organic layer made of, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or the like.

[0096] The second anode connection electrode ADNE2 may be located on the first planarization layer 160. The second anode connection electrode ADNE2 may be connected to the first anode connection electrode ADNE1 through a second connection contact hole ANCT2 passing through the first planarization layer 160. The second anode connection electrode ADNE2 may have a single-layer or multi-layer structure formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof.

[0097] The second planarization layer 180 may be located on the second anode connection electrode ADNE2. The second planarization layer 180 may be formed of an organic layer made of, for example, acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or the like.

[0098] The light emitting element assembly LEP may be formed on the second planarization layer 180. The light emitting element assembly LEP may include a plurality of pixel electrodes PE1, PE2, and PE3, a plurality of light emitting elements LE, and a common electrode CE.

[0099] The plurality of pixel electrodes may include a first pixel electrode PE1, a second pixel electrode PE2, and a third pixel electrode PE3. The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be used as a first electrode of the light emitting element LE, and may be an anode electrode or a cathode electrode. The first pixel electrode PE1 may be positioned in the first emission area EA1, and at least a portion thereof may extend to the non-emission area NEA. The second pixel electrode PE2 may be positioned in the second emission area EA2, and at least a portion thereof may extend to the non-emission area NEA. The third pixel electrode PE3 may be positioned in the third emission area EA3, and at least a portion thereof may extend to the non-emission area NEA. The first pixel electrode PE1 may pass through the second planarization layer 180, and may be connected to the thin film transistor T1 through the corresponding first anode connection electrode ADNE1 and the second anode connection electrode ADNE2. The second pixel electrode PE2 may pass through the second planarization layer 180, and may be connected to the thin film transistor T2 through the corresponding first anode connection electrode ADNE1 and the second anode connection electrode ADNE2. The third pixel electrode PE3 may pass through the second planarization layer 180, and may be connected to the thin film transistor T3 through the corresponding first anode connection electrode ADNE1 and the second anode connection electrode ADNE2. However, the present disclosure is not limited thereto, and in another embodiment not shown, the first anode connection electrode ADNE1 and the second anode connection electrode ADNE2 may be omitted, and thus, the first pixel electrode PE1 may be connected to the thin film transistor T1 by passing through the gate insulating layer 130, the second pixel electrode PE2 may be connected to the thin film transistor T2 by passing through the gate insulating layer 130, and the third pixel electrode PE3 may be connected to the thin film transistor T3 by passing through the gate insulating layer 130.

[0100] Each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be a reflective electrode. Each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be formed of titanium (Ti), copper (Cu), or an alloy of titanium (Ti) and / or copper (Cu). In addition, each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may have a stacked layer structure including titanium (Ti) and copper (Cu). In addition, each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may have a stacked layer structure including titanium (Ti) and copper (Cu). 2), indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO) or magnesium oxide (MgO) The high work function material layer formed by the material and the stacked layer structure formed by the reflective material layer formed by silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), titanium (Ti), copper (Cu) or a compound thereof. The high work function material layer can be positioned above the reflective material layer and can therefore be closer to the light emitting element LE. Each of the first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 can have a multilayer structure including ITO / Mg, ITO / MgF, ITO / Ag or ITO / Ag / ITO, but is not limited thereto.

[0101] The bank BNL may be positioned on the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. The bank BNL may include an opening exposing the first pixel electrode PE1, an opening exposing the second pixel electrode PE2, and an opening exposing the third pixel electrode PE3, and may define the first emission area EA1, the second emission area EA2, the third emission area EA3, and the non-emission area NEA. In other words, the area of ​​the first pixel electrode PE1 that is not covered by the bank BNL and is exposed may correspond to the first emission area EA1. The area of ​​the second pixel electrode PE2 that is not covered by the bank BNL and is exposed may correspond to the second emission area EA2. The area of ​​the third pixel electrode PE3 that is not covered by the bank BNL and is exposed may correspond to the third emission area EA3. The remaining area where the bank BNL is positioned may correspond to the non-emission area NEA.

[0102] The bank BNL may include an organic insulating material such as a polyacrylate-based resin, an epoxy resin, a phenolic resin, a polyamide-based resin, a polyimide-based resin, an unsaturated polyester resin, a polyphenylene ether-based resin, a polyphenylene sulfide-based resin, or benzocyclobutene (BCB).

[0103] The bank BNL may overlap the color filters CF1, CF2, and CF3 and the light blocking component BK of the wavelength conversion component 200. For example, the bank BNL may completely overlap the light blocking component BK. In addition, the color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3.

[0104] A plurality of light emitting elements LE may be located on the first pixel electrode PE1 , the second pixel electrode PE2 , and the third pixel electrode PE3 .

[0105] like Figure 7 and Figure 8As shown in , the light emitting element LE may be located in each of the first emission area EA1, the second emission area EA2, and the third emission area EA3. Each light emitting element LE may be a vertical light emitting diode element extending longitudinally in the third direction DR3. In other words, the length of the light emitting element LE in the third direction DR3 may be greater than its length in the horizontal direction. The length in the horizontal direction refers to the length in the first direction DR1 or the length in the second direction DR2. For example, the length of the light emitting element LE in the third direction DR3 may be in the range of about 1 μm to about 5 μm.

[0106] The light emitting element LE may be a micron light emitting diode element. In the thickness direction of the display substrate 100 (in the third direction DR3), the light emitting element LE may include a connection electrode 125, a first semiconductor layer SEM1, an electron blocking layer EBL, an active layer MQW, a superlattice layer SLT, a second semiconductor layer SEM2, and a third semiconductor layer SEM3. The connection electrode 125, the first semiconductor layer SEM1, the electron blocking layer EBL, the active layer MQW, the superlattice layer SLT, the second semiconductor layer SEM2, and the third semiconductor layer SEM3 may be stacked in sequence in the third direction DR3.

[0107] The light emitting element LE may have a cylindrical, disk-shaped or rod-shaped structure having a width greater than a height. However, the shape of the light emitting element LE is not limited to the above examples, and may have various shapes, for example, a shape such as a rod, a wire or a tube, a polyhedron such as a regular hexahedron, a rectangular parallelepiped or a hexagonal cylinder, or an elongated shape having a partially inclined outer surface.

[0108] The connection electrode 125 may be located on each of the plurality of pixel electrodes PE1, PE2, and PE3. Hereinafter, the light emitting element LE located on the first pixel electrode PE1 may be described by way of example.

[0109] The connection electrode 125 may be adhered to the first pixel electrode PE1, thereby playing a role in applying an emission signal to the light emitting element LE. The connection electrode 125 may be an ohmic connection electrode. However, the present disclosure is not limited thereto, and the connection electrode 125 may be a Schottky connection electrode. The light emitting element LE may include at least one connection electrode 125. Although Figure 7 and Figure 8 1 shows that the light emitting element LE includes one connecting electrode 125, but the present disclosure is not limited thereto. In some cases, the light emitting element LE may include a greater number of connecting electrodes 125, or the connecting electrode 125 may be omitted. Even if the number of connecting electrodes 125 is changed or other structures are included, the following description of the light emitting element LE may also be applied in the same manner.

[0110] The connection electrode 125 can reduce the resistance between the light emitting element LE and the first pixel electrode PE1 when the light emitting element LE in the display device 10 is electrically connected to the first pixel electrode PE1, and can enhance the adhesion between them. The connection electrode 125 may include a conductive metal oxide. For example, the connection electrode 125 may be formed of indium tin oxide (ITO). The connection electrode 125 may be in direct contact with the first pixel electrode PE1 of the lower layer and connected to the first pixel electrode PE1 of the lower layer, and therefore may be made of the same material as the first pixel electrode PE1. In addition, the connection electrode 125 may also optionally include a reflective electrode made of a metal such as aluminum (Al) having a high reflectivity, or include an anti-diffusion layer containing nickel (Ni). Therefore, the adhesion between the connection electrode 125 and the first pixel electrode PE1 can be enhanced, thereby producing improved contact characteristics.

[0111] refer to Figure 8 , the first pixel electrode PE1 may include a lower electrode layer P1, a reflective layer P2, and an upper electrode layer P3. The lower electrode layer P1 may be located at the lowermost portion of the first pixel electrode PE1, and thus may be electrically connected to a corresponding switching element. The lower electrode layer P1 may include a metal oxide, such as titanium dioxide (TiO 2 ), indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO) or magnesium oxide (MgO).

[0112] The reflective layer P2 may be located on the lower electrode layer P1 so as to reflect light emitted from the light emitting element LE upward. The reflective layer P2 may include a metal having a high reflectivity, such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or an alloy thereof.

[0113] The upper electrode layer P3 may be located on the reflective layer P2 so as to directly contact the light emitting element LE. The upper electrode layer P3 may be located between the reflective layer P2 and the connecting electrode 125 of the light emitting element LE so as to directly contact the connecting electrode 125. As described above, the connecting electrode 125 may be formed of a metal oxide. The upper electrode layer P3 may also be formed of a metal oxide in the same manner as the connecting electrode 125.

[0114] The upper electrode layer P3 may be formed of titanium (Ti), copper (Cu), or an alloy of titanium (Ti) and / or copper (Cu). In addition, the upper electrode layer P3 may have a stacked layer structure including titanium (Ti) and copper (Cu). The upper electrode layer P3 may include titanium dioxide (TiO 2), indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO) or magnesium oxide (MgO). In one or more embodiments, when the connection electrode 125 is formed of ITO, the first pixel electrode PE1 may have a multi-layer structure of ITO / Ag / ITO.

[0115] The first semiconductor layer SEM1 may be located on the connection electrode 125. The first semiconductor layer SEM1 may be a p-type semiconductor and may include a material having a chemical formula of Al x Ga y In 1-x-y N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) semiconductor material. For example, the semiconductor material may include any one or more of p-type doped AlGaInN, GaN, AlGaN, InGaN, AlN and InN. The first semiconductor layer SEM1 may be doped with a p-type dopant. The p-type dopant may be Mg, Zn, Ca, Ba, etc. For example, the first semiconductor layer SEM1 may include p-GaN doped with p-type Mg. The thickness of the first semiconductor layer SEM1 may have a range of about 30 nm to about 200 nm, but is not limited thereto.

[0116] The electron blocking layer EBL may be located on the first semiconductor layer SEM1. The electron blocking layer EBL may be a layer configured to mitigate or prevent excessive electrons from flowing into the active layer MQW. For example, the electron blocking layer EBL may include p-AlGaN doped with p-type Mg. The thickness of the electron blocking layer EBL may have a range of about 10 nm to about 50 nm, but is not limited thereto. In addition, the electron blocking layer EBL may be omitted.

[0117] The active layer MQW may be positioned on the electron blocking layer EBL. The active layer MQW may emit light by recombination of electron-hole pairs in response to an electrical signal applied through the first and second semiconductor layers SEM1 and SEM2.

[0118] The active layer MQW may include a material having a single quantum well structure or a multi-quantum well structure. In the case where the active layer MQW includes a material having a multi-quantum well structure, the active layer MQW may have a structure formed by alternately stacking a plurality of well layers and a plurality of barrier layers. Here, although the well layer may be formed of InGaN and the barrier layer may be formed of GaN or AlGaN, the present disclosure is not limited thereto. The thickness of the well layer may be about 1 nm to about 4 nm. The thickness of the barrier layer may be about 3 nm to about 10 nm.

[0119] Alternatively, the active layer MQW may have a structure formed by alternately stacking a semiconductor material having a large energy band gap and a semiconductor material having a small energy band gap, and may include a group III semiconductor material to a group V semiconductor material according to the wavelength band of light to be emitted. The light emitted from the active layer MQW is not limited to the first light, and the second light (light in the green wavelength band) or the third light (light in the blue wavelength band) may be emitted according to circumstances.

[0120] In detail, the color of light to be emitted from the active layer MQW may vary according to the content of indium (In). For example, as the content of indium (In) decreases, the wavelength band of light emitted from the active layer MQW may shift toward the red wavelength band. As the content of indium (In) increases, the wavelength band of light emitted from the active layer MQW may shift toward the blue wavelength band. For example, if the content of indium (In) is about 15% or less, the active layer MQW may emit a first light in a red wavelength band having a main peak wavelength of about 600nm to about 750nm. On the other hand, if the content of indium (In) is about 25%, the active layer MQW may emit a second light in a green wavelength band having a main peak wavelength of about 480nm to about 560nm. In addition, if the content of indium (In) is about 35% or more, the active layer MQW may emit a third light in a blue wavelength band having a main peak wavelength of about 370nm to about 460nm. Reference Figure 6 , an example in which the active layer MQW emits light in a blue wavelength band having a main peak wavelength of about 370 nm to about 460 nm will be described.

[0121] The superlattice layer SLT may be located on the active layer MQW. The superlattice layer SLT may be a layer configured to relieve stress between the second semiconductor layer SEM2 and the active layer MQW. For example, the superlattice layer SLT may be formed of InGaN or GaN. The thickness of the superlattice layer SLT may be about 50 nm to about 200 nm. The superlattice layer SLT may be omitted.

[0122] The second semiconductor layer SEM2 may be located on the superlattice layer SLT. The second semiconductor layer SEM2 may be formed of an n-type semiconductor. The second semiconductor layer SEM2 may include a semiconductor having a chemical formula of Al x Ga y In 1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1) semiconductor material. For example, the second semiconductor layer SEM2 may include any one or more of n-type doped AlGaInN, GaN, AlGaN, InGaN, AlN and InN. The second semiconductor layer SEM2 may be doped with an n-type dopant. The n-type dopant may be Si, Ge, Sn, Se, etc. For example, the second semiconductor layer SEM2 may be n-GaN doped with n-type Si. The thickness of the second semiconductor layer SEM2 may range from about 2 μm to about 4 μm, but is not limited thereto.

[0123] The third semiconductor layer SEM3 may be located on the second semiconductor layer SEM2. The third semiconductor layer SEM3 may be located between the second semiconductor layer SEM2 and the common electrode CE. The third semiconductor layer SEM3 may be formed of an undoped semiconductor. The third semiconductor layer SEM3 may be formed of a material including the same material as the second semiconductor layer SEM2 and not doped with an n-type or p-type dopant. In one or more embodiments, the third semiconductor layer SEM3 may include at least one of undoped AlGaInN, GaN, AlGaN, InGaN, AlN, and InN, but is not limited thereto.

[0124] The planarization layer PLL may be located on the bank BNL and the pixel electrodes PE1, PE2, and PE3. The planarization layer PLL may planarize the stepped portion of the lower layer to facilitate the formation of the common electrode CE as described below. The planarization layer PLL may be formed to have a certain height to allow at least a portion (e.g., an upper portion thereof) of each of the plurality of light emitting elements LE to protrude upward from the upper surface of the planarization layer PLL. In other words, the height of the planarization layer PLL may be less than the height of the light emitting element LE relative to the upper surface of the first pixel electrode PE1.

[0125] The planarization layer PLL may include an organic material to planarize the stepped portion of the lower layer. For example, the planarization layer PLL may include a polyacrylate-based resin, an epoxy resin, a phenolic resin, a polyamide-based resin, a polyimide-based resin, an unsaturated polyester-based resin, a polyphenylene ether-based resin, a polyphenylene sulfide-based resin, benzocyclobutene (BCB), etc.

[0126] The common electrode CE may be located on the planarization layer PLL and the plurality of light emitting elements LE. In detail, the common electrode CE may be located on one surface of the first substrate 110 on which the light emitting elements LE are formed, and may be located on the entire surface of the display area DPA and the non-display area NDA. The common electrode CE may be located to overlap each of the emission areas EA1, EA2, and EA3 in the display area DPA, and have a relatively small thickness to allow light emission.

[0127] The common electrode CE may be directly located on the upper surface and the side surface of the plurality of light emitting elements LE. The common electrode CE may directly contact the second semiconductor layer SEM2 and the third semiconductor layer SEM3 on the side surface of the light emitting element LE. Figure 6 As shown in , the common electrode CE may cover a plurality of light emitting elements LE and may be a common layer positioned to commonly connect the plurality of light emitting elements LE. A second semiconductor layer SEM2 having conductivity is patterned in each of the light emitting elements LE so that the common electrode CE may directly contact a side surface of the second semiconductor layer SEM2 of each light emitting element LE, thereby allowing a common voltage to be applied to each light emitting element LE.

[0128] The common electrode CE is located on the entire surface of the first substrate 110 to allow a common voltage to be applied thereto. Therefore, the common electrode CE may include a low resistance material. In addition, the common electrode CE may be formed with a relatively small thickness to facilitate transmission of light. For example, the common electrode CE may include a low resistance material such as aluminum (Al), silver (Ag), copper (Cu), etc. The thickness of the common electrode CE may be about 1000 Å. to about But it is not limited to this.

[0129] Each of the light emitting elements LE may be supplied with a pixel voltage or an anode voltage from a pixel electrode through the connection electrode 125 and may be supplied with a common voltage through the common electrode CE. The light emitting element LE may emit light with a certain brightness in response to a voltage difference between the pixel voltage and the common voltage.

[0130] A plurality of light emitting elements LE (eg, inorganic light emitting diodes) are disposed on the pixel electrodes PE1, PE2, and PE3, thereby reducing or eliminating defects associated with organic light emitting diodes such as susceptibility to moisture or oxygen, thereby resulting in improved lifespan and reliability.

[0131] The first organic layer FOL may be disposed on the bank BNL located in the non-emission area NEA.

[0132] The first organic layer FOL may be positioned to overlap the non-emission area NEA and may not overlap the emission areas EA1, EA2, and EA3. The first organic layer FOL may be directly located on the bank BNL and may be positioned to be spaced apart from the plurality of pixel electrodes PE1, PE2, and PE3 adjacent thereto. The first organic layer FOL may be positioned on the entire first substrate 110 and may be positioned to surround the plurality of emission areas EA1, EA2, and EA3. The first organic layer FOL may be arranged in an overall lattice shape.

[0133] The first organic layer FOL can play a role in separating the plurality of light emitting elements LE contacting the upper surface of the first organic layer FOL corresponding to the non-emission area NEA. When the laser is irradiated on the first organic layer FOL, the first organic layer FOL can absorb energy and instantly increase the temperature, thereby causing ablation. Therefore, the plurality of light emitting elements LE contacting the upper surface of the first organic layer FOL can be separated from the upper surface of the first organic layer FOL.

[0134] The first organic layer FOL may include a polyimide-based compound. The polyimide-based compound of the first organic layer FOL may include a cyano group to absorb light having a wavelength of about 308 nm, such as laser light. In one or more embodiments, each of the first organic layer FOL and the dam BNL may include a polyimide-based compound, or may include different polyimide-based compounds. For example, the dam BNL may be made of a polyimide-based compound that does not include a cyano group, and the first organic layer FOL may be made of a polyimide-based compound that includes a cyano group. For a laser having a wavelength of about 308 nm, the transmittance of the first organic layer FOL may be less than the transmittance of the dam BNL, wherein the transmittance of the dam BNL is about 60% or more, and the transmittance of the first organic layer FOL may be about 0%. The absorptivity of the first organic layer FOL to the laser having a wavelength of about 308 nm may be about 100%. The first organic layer FOL may have a transmittance of about 100%. If the thickness of the first organic layer FOL is about If the thickness of the first organic layer FOL is about 10 μm or less, the step difference between the first organic layer FOL and the pixel electrode PE1 / PE2 / PE3 can be reduced or prevented from increasing, so that the light emitting element LE can be properly adhered to the pixel electrode PE1 / PE2 / PE3 during subsequent processes.

[0135] The wavelength conversion component 200 may be located on the light emitting element component LEP. The wavelength conversion component 200 may include a partition wall PW, a wavelength conversion layer, color filters CF1, CF2, and CF3, a light blocking component BK, and a protective layer PTL.

[0136] The partition wall PW may be located on the common electrode CE in the display area DPA, and together with the bank BNL, may separate the plurality of emission areas EA1, EA2, and EA3 from each other. The partition wall PW may be positioned to extend in the first direction DR1 and the second direction DR2, and may form a lattice pattern in the entire display area DPA. In addition, the partition wall PW may not overlap with the plurality of emission areas EA1, EA2, and EA3, and may overlap with the non-emission area NEA.

[0137] The partition wall PW may include or define a plurality of openings OP1, OP2, and OP3 exposing the common electrode CE of the lower layer. The plurality of openings OP1, OP2, and OP3 may include a first opening OP1 overlapping the first emission area EA1, a second opening OP2 overlapping the second emission area EA2, and a third opening OP3 overlapping the third emission area EA3. Here, the plurality of openings OP1, OP2, and OP3 may correspond to the plurality of emission areas EA1, EA2, and EA3. In other words, the first opening OP1 may correspond to the first emission area EA1, the second opening OP2 may correspond to the second emission area EA2, and the third opening OP3 may correspond to the third emission area EA3.

[0138] The partition wall PW may function to provide a space for forming the first wavelength conversion layer QDL1 and the second wavelength conversion layer QDL2 (see, for example, Figure 6 ) space. In order to achieve the above purpose, the partition wall PW may have a certain thickness. For example, the thickness of the partition wall PW may be about 1 μm to about 10 μm. The partition wall PW may include an organic insulating material having a certain thickness. The organic insulating material may include, for example, an epoxy-based resin, an acrylic-based resin, a cardo-based resin, or an imide-based resin.

[0139] The first wavelength conversion layer QDL1 may be located in each first opening OP1. The first wavelength conversion layer QDL1 may be formed into an island pattern having a shape in which points are spaced apart from each other. The first wavelength conversion layer QDL1 may include a first base resin BRS1 and first wavelength conversion particles WCP1. The first base resin BRS1 may include a transparent organic material. For example, the first base resin BRS1 may include an epoxy-based resin, an acrylic-based resin, a cardo-based resin, an imide-based resin, and the like. The first wavelength conversion particles WCP1 may be quantum dots (QDs), quantum rods, fluorescent materials, or phosphorescent materials. For example, quantum dots may be granular materials that emit light having a corresponding color when electrons transition from a conduction band to a valence band.

[0140] Quantum dots can be semiconductor nanocrystal materials. Quantum dots can have corresponding band gaps according to their composition and size, and can therefore absorb light, and can then emit light with an intrinsic wavelength. Examples of semiconductor nanocrystals for quantum dots can include IV group nanocrystals, II-VI group compound nanocrystals, III-V group compound nanocrystals, IV-VI group nanocrystals, and combinations thereof.

[0141] The first wavelength conversion layer QDL1 may be formed in the first opening OP1 in the first emission area EA1. The first wavelength conversion layer QDL1 may convert or shift the peak wavelength of the incident light into light of a different corresponding peak wavelength, and may then emit the converted or shifted light. The first wavelength conversion layer QDL1 may convert a portion of the blue light emitted from the light emitting element LE into light similar to red light as the first light. The first wavelength conversion layer QDL1 emits light similar to red light, thereby enabling the light to be converted into red light as the first light through the first color filter CF1.

[0142] The second wavelength conversion layer QDL2 may be located in each second opening OP2 (eg, see Figure 6 ). The second wavelength conversion layer QDL2 may be formed into an island pattern having a shape in which points thereof are spaced apart from each other. For example, the second wavelength conversion layer QDL2 may be positioned to overlap with the second emission area EA2. The second wavelength conversion layer QDL2 may include a second base resin BRS2 and second wavelength conversion particles WCP2. The second base resin BRS2 may include a transparent organic material. The second wavelength conversion layer QDL2 may convert or shift the peak wavelength of the incident light into light of a different corresponding peak wavelength, and may then emit the converted or shifted light. The second wavelength conversion layer QDL2 may convert some of the blue light emitted from the light emitting element LE into light similar to green light as the second light. The second wavelength conversion layer QDL2 emits light similar to green light, thereby enabling the light to be converted into green light as the second light through the second color filter CF2.

[0143] In the third emission area EA3, only the transparent organic material is formed in the third opening OP3, thereby allowing the blue light emitted from the light emitting element LE to be directly emitted through the third color filter CF3 (see, for example, Figure 6 ).

[0144] A plurality of color filters CF1, CF2, and CF3 may be located on the partition wall PW and the first and second wavelength conversion layers QDL1 and QDL2. The plurality of color filters CF1, CF2, and CF3 may be located to overlap with the plurality of openings OP1, OP2, and OP3 and the first and second wavelength conversion layers QDL1 and QDL2. The plurality of color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3.

[0145] The first color filter CF1 may be positioned to overlap with the first emission area EA1. In addition, the first color filter CF1 may be positioned throughout the first opening OP1 of the partition wall PW to overlap with the first opening OP1. The first color filter CF1 allows the first light to pass therethrough, and may absorb or block the second light and the third light. For example, the first color filter CF1 allows light in a red wavelength band to pass therethrough, and may absorb or block light in other wavelength bands such as green and blue.

[0146] The second color filter CF2 may be positioned to overlap with the second emission area EA2. In addition, the second color filter CF2 may be positioned throughout the second opening OP2 of the partition wall PW to overlap with the second opening OP2. The second color filter CF2 allows the second light to pass therethrough, and may absorb or block the first light and the third light. For example, the second color filter CF2 allows light in a green wavelength band to pass therethrough, and may absorb or block light in other wavelength bands such as blue and red.

[0147] The third color filter CF3 may be positioned to overlap with the third emission area EA3. In addition, the third color filter CF3 may be positioned throughout the third opening OP3 of the partition wall PW to overlap with the third opening OP3. The third color filter CF3 allows the third light to pass therethrough, and may absorb or block the first light and the second light. For example, the third color filter CF3 allows light in a blue wavelength band to pass therethrough, and may absorb or block light in other wavelength bands such as red and green.

[0148] The planar surface area of ​​each of the color filters CF1, CF2, and CF3 may be greater than the planar surface area of ​​each of the emission areas EA1, EA2, and EA3. For example, the planar surface area of ​​the first color filter CF1 may be greater than the planar surface area of ​​the first emission area EA1. The planar surface area of ​​the second color filter CF2 may be greater than the planar surface area of ​​the second emission area EA2. The planar surface area of ​​the third color filter CF3 may be greater than the planar surface area of ​​the third emission area EA3. However, the present disclosure is not limited to the above examples, and the planar surface area of ​​each of the color filters CF1, CF2, and CF3 may be equal to the planar surface area of ​​each of the emission areas EA1, EA2, and EA3.

[0149] refer to Figure 6 , the light blocking component BK may be located on the partition wall PW. The light blocking component BK may overlap the non-emission area NEA, thereby blocking the transmission of light. The light blocking component BK may be positioned in an approximately lattice shape in a plan view in a manner similar to the bank BNL or the partition wall PW. The light blocking component BK may be positioned to overlap the bank BNL, the first organic layer FOL, and the partition wall PW, and may not overlap the emission areas EA1, EA2, and EA3.

[0150] In one or more embodiments, the light blocking component BK may include an organic light blocking material and may be formed by processes such as coating and exposure of the organic light blocking material. The light blocking component BK may contain a light blocking dye or pigment and may be a black matrix. At least a portion of the light blocking component BK may overlap with the color filters CF1, CF2, and CF3 adjacent thereto. The color filters CF1, CF2, and CF3 may be located on at least a portion of the light blocking component BK.

[0151] The protective layer PTL may be located on the plurality of color filters CF1, CF2, and CF3 and the light blocking member BK. The protective layer PTL may be located at the uppermost portion of the display device 10, thereby protecting the color filters CF1, CF2, and CF3 and the light blocking member BK of the lower layer. One surface (e.g., the lower surface) of the protective layer PTL may contact the upper surface of each of the color filters CF1, CF2, and CF3 and the light blocking member BK.

[0152] The protective layer PTL may include an inorganic insulating material to protect the color filters CF1, CF2, and CF3 and the light blocking member BK. For example, the protective layer PTL may include an inorganic insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al x O y ), aluminum nitride (AlN), etc., but is not limited thereto. The protection layer PTL may have a certain thickness, for example, about 0.01 μm to about 1 μm. However, the present disclosure is not limited thereto.

[0153] Fig. 9 is a schematic diagram showing a method of Figure 2 A cross-sectional view of a section taken along line AA'.

[0154] refer to Fig. 9 , the third wavelength conversion layer QDL3 may be located in each of the first opening OP1 and the second opening OP2 .

[0155] The third wavelength conversion layer QDL3 may convert or shift the peak wavelength of the incident light into light of a different corresponding peak wavelength, and may then emit the converted or shifted light. The third wavelength conversion layer QDL3 may convert some of the blue light emitted from the light emitting element LE into yellow light as the fourth light. In the third wavelength conversion layer QDL3, the blue light and the fourth light are mixed with each other to emit white light as the fifth light. The fifth light may be converted into the first light by the first color filter CF1, and may be converted into the second light by the second color filter CF2.

[0156] The third wavelength conversion layer QDL3 may be located in each of the first opening OP1 and the second opening OP2 that are spaced apart from each other. In other words, the third wavelength conversion layer QDL3 may be formed into an island pattern having a shape whose midpoints are spaced apart from each other. For example, the third wavelength conversion layer QDL3 may be located only in each of the first opening OP1 and the second opening OP2, and may correspond to each of the first opening OP1 and the second opening OP2 on a one-to-one basis. In addition, the third wavelength conversion layer QDL3 may be positioned to overlap with each of the first emission area EA1 and the second emission area EA2. In one or more embodiments, the third wavelength conversion layer QDL3 may completely overlap with each of the first emission area EA1 and the second emission area EA2.

[0157] The third wavelength conversion layer QDL3 may include a third base resin BRS3 and third wavelength conversion particles WCP3. The third base resin BRS3 may include a transparent organic material. For example, the third base resin BRS3 may include an epoxy-based resin, an acrylic-based resin, a cardo-based resin, an imide-based resin, etc.

[0158] The third wavelength conversion particle WCP3 can convert the blue light emitted from the light emitting element LE into a fourth light. For example, the third wavelength conversion particle WCP3 can convert the light in the blue wavelength band into the light in the yellow wavelength band. The third wavelength conversion particle WCP3 can be a quantum dot (QD), a quantum rod, a fluorescent material, or a phosphorescent material. For example, a quantum dot can be a particle material that emits light of a corresponding color when an electron transitions from a conduction band to a valence band.

[0159] As the thickness of the third wavelength conversion layer QDL3 in the third direction DR3 increases, the content of the third wavelength conversion particles WCP3 included in the third wavelength conversion layer QDL3 may increase, thereby enhancing the light conversion efficiency of the third wavelength conversion layer QDL3. Therefore, for example, the thickness of the third wavelength conversion layer QDL3 may be set in consideration of the light conversion efficiency of the third wavelength conversion layer QDL3.

[0160] In the third wavelength conversion layer QDL3, some of the blue light emitted from the light emitting element LE may be converted into a fourth light. The third wavelength conversion layer QDL3 may mix the blue light and the fourth light with each other to emit white light as the fifth light. As described below, the fifth light emitted from the third wavelength conversion layer QDL3 may pass through the first color filter CF1 to transmit only the first light, and pass through the second color filter CF2 to transmit only the second light. Therefore, in the first emission area EA1 and the second emission area EA2, the light emitted from the wavelength conversion component 200 may be red light and green light as the first light and the second light. In the third emission area EA3, only a transparent organic material is formed in the third opening OP3, thereby allowing the blue light emitted from the light emitting element LE to be directly emitted through the third color filter CF3. In this way, full color can be achieved.

[0161] Fig.10 is a schematic diagram showing a method of Figure 2 A cross-sectional view of a section taken along line AA'.

[0162] As described above, the color of light emitted from the active layer MQW of each light emitting element LE may vary according to the content of indium (In). As the content of indium (In) decreases, the wavelength band of light emitted from the active layer MQW may shift toward the red wavelength band. As the content of indium (In) increases, the wavelength band of light emitted from the active layer MQW may shift toward the blue wavelength band. Therefore, in each light emitting element LE formed in the first emission area EA1, the active layer MQW having an indium (In) content of about 15% or less may emit a first light in a red wavelength band having a main peak wavelength of about 600nm to about 750nm.

[0163] In each light emitting element LE formed in the second emission area EA2 , the active layer MQW having an indium (In) content of about 25% may emit second light in a green wavelength band having a main peak wavelength of about 480 nm to about 560 nm.

[0164] In each light emitting element LE formed in the third emission area EA3 , the active layer MQW having an indium (In) content of about 35% or more may emit third light in a blue wavelength band having a main peak wavelength of about 370 nm to about 460 nm.

[0165] Each light emitting element LE formed in the first emission area EA1 may emit a first light in a red wavelength band. Each light emitting element LE formed in the second emission area EA2 may emit a second light in a green wavelength band. Each light emitting element LE formed in the third emission area EA3 may emit a third light in a blue wavelength band. In this case, it is not necessary to form color filters CF1, CF2, and CF3.

[0166] Fig.11 is a flowchart for describing a method of manufacturing a display panel according to one or more embodiments. Figures 12 to 30 is a diagram schematically illustrating a process of manufacturing a display panel according to one or more embodiments.

[0167] refer to Figures 11 to 13 , a light emitting element LE may be formed on the base substrate BSUB (at operation S100). First, a sapphire substrate (Al 2 O 3 ), a silicon wafer including silicon, etc. as a base substrate BSUB. A plurality of semiconductor material layers including a third semiconductor material layer SEM3L, a second semiconductor material layer SEM2L, a superlattice material layer SLTL, an active material layer MQWL, an electron blocking material layer EBLL, and a first semiconductor material layer SEM1L are formed on the base substrate BSUB. A plurality of semiconductor material layers grown by an epitaxial method can be formed by growing seed crystals. In one or more embodiments, the method for forming the semiconductor material layer may include an electron beam deposition method, a physical vapor deposition (PVD) method, a chemical vapor deposition (CVD) method, a plasma laser deposition (PLD) method, a dual-type thermal evaporation method, a sputtering method, a metal organic chemical vapor deposition (MOCVD) method, etc. It is desirable to form the semiconductor material layer by an MOCVD method. However, the present disclosure is not limited thereto.

[0168] The precursor material for forming the semiconductor material layer is not particularly limited as long as it can be generally selected within the range of forming the target material. For example, the precursor material may be a metal precursor including an alkyl group such as a methyl group or an ethyl group. For example, the precursor material may include a precursor such as trimethylgallium (Ga(CH3) 3 ), trimethylaluminum (Al(CH 3 ) 3 ) and triethyl phosphate ((C 2 H 5 ) 3 PO 4 ) compounds, but are not limited thereto.

[0169] In detail, a third semiconductor material layer SEM3L is formed on the base substrate BSUB. Although an example in which one third semiconductor layer SEM3 is stacked is shown in the drawings, the present disclosure is not limited thereto, and a plurality of layers may be formed. The third semiconductor material layer SEM3L may be positioned to reduce the lattice constant difference between the second semiconductor material layer SEM2L and the base substrate BSUB. For example, the third semiconductor material layer SEM3L may include an undoped semiconductor, and may be a material that is not doped with an n-type or p-type dopant. In one or more embodiments, the third semiconductor material layer SEM3L may include at least one of undoped AlGaInN, GaN, AlGaN, InGaN, AlN, and InN, but is not limited thereto.

[0170] Using the above method, a second semiconductor material layer SEM2L, a superlattice material layer SLTL, an active material layer MQWL, an electron blocking material layer EBLL and a first semiconductor material layer SEM1L are sequentially formed on the third semiconductor material layer SEM3L. Thereafter, a plurality of light emitting elements LE are formed by etching the semiconductor material layer.

[0171] In detail, a plurality of mask patterns MP are formed on the first semiconductor material layer SEM1L. The mask pattern MP may include a hard mask including an inorganic material or a photoresist mask including an organic material. The mask pattern MP may reduce the possibility of etching the underlying semiconductor material layer or prevent the underlying semiconductor material layer from being etched. Subsequently, the semiconductor material layer is partially etched using the mask pattern MP as a mask, thereby forming a plurality of light emitting elements LE.

[0172] like Fig.13 As shown in , on the base substrate BSUB, portions of the semiconductor material layer not overlapping with the mask pattern MP are etched and removed, and other portions of the semiconductor material layer overlapping with the mask pattern MP and not etched may be formed into a plurality of light emitting elements LE.

[0173] The semiconductor material layer can be etched by a typical method. For example, the process of etching the semiconductor material layer can be a dry etching method, a wet etching method, a reactive ion etching (RIE) method, a deep reactive ion etching (DRIE) method, an inductively coupled plasma reactive ion etching (ICO-RIE) method, etc. In the case of the dry etching method, anisotropic etching can be performed, which makes it suitable for vertical etching. In the case of using the etching method, Cl 2 , O 2 However, the present disclosure is not limited to the above-mentioned embodiments.

[0174] The portion of the semiconductor material layer overlapping the mask pattern MP is not etched and thus formed into a plurality of light emitting elements LE. Thus, a plurality of light emitting elements LE including the third semiconductor layer SEM3, the second semiconductor layer SEM2, the superlattice layer SLT, the active layer MQW, the electron blocking layer EBL and the first semiconductor layer SEM1 are formed.

[0175] Thereafter, a connection electrode material layer is stacked on the base substrate BSUB, and then the connection electrode material layer is etched to form a connection electrode 125 on a plurality of light emitting elements LE. The connection electrode 125 may be formed directly on the upper surface of the first semiconductor layer SEM1 of each light emitting element LE. The connection electrode 125 may include a transparent conductive material. For example, the connection electrode 125 may be formed of a transparent conductive oxide (TCO) such as indium tin oxide (ITO) or indium zinc oxide (IZO). In addition, a highly reflective metal layer made of a metal such as aluminum (Au), copper (Cu) or gold (Au) may be additionally formed on the upper portion of the connection electrode 125 formed of the transparent conductive oxide.

[0176] refer to Fig.11 , Fig.14 and Fig.15 , the plurality of light emitting elements LE may be transferred onto / to the first film LFL1 (at operation S200). The first film LFL1 is attached to the plurality of light emitting elements LE formed on the base substrate BSUB. Therefore, the respective connection electrodes 125 of the plurality of light emitting elements LE may be attached to the first film LFL1. A relatively large number of light emitting elements LE are positioned and thus may be attached to the first film LFL1 without being removed.

[0177] The first film LFL1 may include a material that can be stretched. The material that can be stretched may include, for example, polyolefin, polyvinyl chloride (PVC), elastic silicone, elastic polyurethane and / or elastic polyisoprene. The first film LFL1 including a support layer and an adhesive layer may be used to adhere and support a plurality of light emitting elements LE.

[0178] Thereafter, the base substrate BSUB is separated from the light emitting elements LE by irradiating the base substrate BSUB with laser. In other words, the base substrate BSUB may be separated from the respective third semiconductor layers SEM3 of the plurality of light emitting elements LE.

[0179] refer to Fig.11 , Fig.16 and Fig.17, the first film LFL1 on which the plurality of light emitting elements LE are arranged may be fixed in place (at operation S300). The first film LFL1 on which the plurality of light emitting elements LE are arranged may be fixed in place by a fixing member FM. For example, the fixing member FM may include a fixing frame. The fixing frame may fix the first film LFL1 on which the plurality of light emitting elements LE are arranged. An O-ring may be located between the fixing member FM and the first film LFL1 on which the array of light emitting elements LE are arranged so as to reduce or prevent leakage of gas.

[0180] refer to Fig.17 , on the first film LFL1 fixed by the fixing member FM, a plurality of light emitting elements LE are arranged to have a first distance D1 therebetween.

[0181] refer to Fig.11 and Fig.18 , the fixed first film LFL1 may be stretched with gas under pressure (at operation S400). In one or more embodiments, the gas may be air, but is not limited thereto. The gas may be provided toward the rear surface of the first film LFL1, thereby pressurizing the rear surface of the first film LFL1 in the front direction of the first film LFL1. Therefore, the first film LFL1 may be stretched by the pressure of the gas. In one or more embodiments, the first film LFL1 may be stretched into a spherical shape. The pressure applied to the first film LFL1 by the gas may be substantially uniformly transmitted to the rear surface of the first film LFL1, thereby substantially uniformly stretching the first film LFL1. In other words, the first film LFL1 may be isotropically stretched by the pressure of the gas. For example, the first film LFL1 is stretched by the pressure of the gas, thereby reducing or preventing uneven stretching caused by friction with a stretching device that requires physical contact.

[0182] refer to Fig.19 On the elongated first film LFL1, the plurality of light emitting elements LE are arranged at intervals of a second distance D2. In other words, as the first film LFL1 is elongated, the plurality of light emitting elements LE may be substantially uniformly spaced apart from each other at a second distance D2 greater than the first distance D1.

[0183] refer to Fig. 20 In one or more embodiments, the first film LFL1 may be further elongated to a second film LFL2 spaced apart from the first film LFL1. The second film LFL2 fixed to the stage STG may be positioned above the first film LFL1 at a position spaced apart from the first film LFL1. In other words, maintaining the spherical shape, the first film LFL1 may be elongated to a position where the plurality of light emitting elements LE located on the first film LFL1 may be appropriately transferred to the second film LFL2.

[0184] refer to Fig.21On the elongated first film LFL1, the plurality of light emitting elements LE are arranged at intervals of a third distance D3. In other words, as the first film LFL1 is further elongated, the plurality of light emitting elements LE may be substantially uniformly spaced apart from each other at a third distance D3 greater than the second distance D2.

[0185] refer to Fig.11 and Fig. 22 , the plurality of light emitting elements LE rearranged by stretching the first film LFL1 may be transferred to the second film LFL2 fixed to the stage STG (at operation S500). Here, the portion of the first film LFL1 stretched into a spherical shape may be pressurized by a gas to make its shape flat. For example, the portion of the first film LFL1 where the rearranged light emitting elements LE are positioned may be pressurized with a gas to become parallel to the second film LFL2. Therefore, the plurality of light emitting elements LE may be appropriately transferred to the second film LFL2.

[0186] refer to Fig.23 , at operation S500, the stage STG may be moved downward toward the elongated first film LFL1. Therefore, the second film LFL2 fixed to the stage STG becomes close to the plurality of light emitting elements LE, whereby the light emitting elements LE may be appropriately and substantially uniformly transferred to the second film LFL2. In other words, as the stage STG moves downward, excessive elongation of the first film LFL1 for transfer may be reduced or prevented, thereby maintaining a constant distance between the plurality of light emitting elements LE.

[0187] refer to Fig.24 , at operation S500, the stage STG may be moved downward toward the elongated first film LFL1 while being tilted. Fig.23 , some of the plurality of light emitting elements LE located on the first film LFL1 are not parallel to the second film LFL2, thereby possibly reducing the transfer efficiency. In view of this, the stage STG is moved downward while being tilted so that the plurality of light emitting elements LE located on the first film LFL1 can be efficiently transferred to the second film LFL2. For example, the stage STG is moved downward while being tilted and rotated in one direction, thereby sequentially transferring the plurality of light emitting elements LE to the second film LFL2.

[0188] refer to Fig.25 , at operation S500, the elongated first film LFL1 may be moved upward toward the second film LFL2. When the stage STG is stationary, the first film LFL1 is moved upward to bring the second film LFL2 closer to the plurality of light emitting elements LE, thereby facilitating the transfer of the light emitting elements LE to the second film LFL2. In other words, as the first film LFL1 is moved upward, excessive elongation of the first film LFL1 for transfer may be reduced or prevented, thereby maintaining a constant distance between the plurality of light emitting elements LE.

[0189] refer to Fig.26 , at operation S500, the elongated first film LFL1 may be moved upward toward the second film LFL2 while being tilted. Fig.25 , some of the plurality of light emitting elements LE located on the first film LFL1 are not parallel to the second film LFL2, thereby possibly reducing the transfer efficiency. In view of this, the first film LFL1 is moved upward while being tilted, so that the plurality of light emitting elements LE located on the first film LFL1 can be effectively transferred to the second film LFL2. For example, the first film LFL1 is moved upward while being tilted and rotated in one direction, so that the plurality of light emitting elements LE are sequentially transferred to the second film LFL2.

[0190] refer to Fig.11 , Fig. 27 and Fig.28 , the second film LFL2 may be positioned on the cell mask CMK that is located on the display substrate 100 and defines a plurality of cell openings COP (at operation S600 ).

[0191] The unit mask CMK may include a mask frame MF and a plurality of unit openings COP. The mask frame MF may define the appearance of the unit mask CMK. The mask frame MF may be formed of a metal material including at least one of iron (Fe) and nickel (Ni). For example, the mask frame MF may include an alloy of iron and nickel. However, the present disclosure is not limited to the above example, and the mask frame MF may include stainless steel (SUS) or alloy( is a registered trademark of Aperam Alloys IMPHY Joint Stock Company).

[0192] A plurality of unit openings COP passing through the mask frame MF may be defined in the mask frame MF. Each unit opening COP may correspond to one display panel. In other words, one unit opening COP may be used in a process of manufacturing one display panel. Each of the unit openings COP may be formed in a shape corresponding to each of the display panels. For example, although in Fig. 27 , each of the unit openings COP has a rectangular shape, but the present disclosure is not limited thereto. Likewise, the number of unit openings COP is not limited to Fig. 27 The corresponding implementation method.

[0193] like Fig.28 As shown in , the cell mask CMK may be located on / over the display substrate 100 .

[0194] The second film LFL2 on which a plurality of light emitting elements LE are arranged may be located above the unit mask CMK, and a certain distance may be provided between the second film LFL2 and the unit mask CMK. In the second film LFL2, a plurality of first regions COA overlapping with a plurality of unit openings COP and a plurality of second regions MOA overlapping with the mask frame MF may be defined. Therefore, a plurality of light emitting elements LE located in a plurality of first regions COA overlapping with a plurality of unit openings COP may face the display substrate 100 through the plurality of unit openings COP. On the other hand, at least one light emitting element LE located in a plurality of second regions MOA overlapping with the mask frame MF may face the mask frame MF, but may not face the display substrate 100. In this way, the unit mask CMK may play a role in selecting a light emitting element LE to be transferred to the display substrate 100 from a plurality of light emitting elements LE arranged on the second film LFL2 based on the display panel.

[0195] refer to Fig.11 and Fig.29 , the portion of the second film LFL2 may be pressurized with gas (at operation S700). Here, the gas may be air, as described above, but is not limited thereto. In one or more embodiments, the portion of the second film LFL2 may be in contact with the plurality of cell openings COP (reference Fig.28 ) overlaps one of the plurality of first regions COA. In other words, operation S700 may be performed based on the cell opening COP. As the one first region COA is pressurized with gas, the plurality of light emitting elements LE located in the one first region COA may contact the display substrate 100. For example, each of the connection electrodes 125 (refer to Fig.15 ) may contact a pixel electrode of the display substrate 100, for example, a first pixel electrode PE1 (reference Figure 8 ). For example, the pressure formed by the gas is substantially uniformly transmitted to the plurality of light emitting elements LE located in the one first area COA. Therefore, the light emitting elements LE located in the one first area COA may substantially uniformly contact the display substrate 100 without deviation.

[0196] refer to Fig.11 and Fig.30 , laser may be irradiated onto the pressurized portion of the second film LFL2 (at operation S800). In order to transfer the plurality of light emitting elements LE to the display substrate 100, heating should be performed together with the pressurization at the above operation S700 so that the light emitting elements LE can be completely bonded to the display substrate 100. The above bonding scheme may be referred to as eutectic bonding. Fig.28) to perform operation S800. In other words, as the laser is irradiated onto the portion of the pressurized second film LFL2, the plurality of light emitting elements LE located in the one first area COA may be bonded to the display substrate 100. For example, the respective connection electrodes 125 (refer to Fig.15 ) may be bonded to a pixel electrode of the display substrate 100, for example, a first pixel electrode PE1 (reference Figure 8 ).

[0197] Operations S700 and S800 may be repeatedly performed on a cell opening COP basis (eg, on a display panel basis), whereby display panels may be continuously manufactured.

[0198] According to an embodiment of the present disclosure, the film is stretched using gas without physical friction, so that the distance between multiple light-emitting elements can be substantially uniformly changed. In addition, the film is pressurized using gas so that multiple light-emitting elements can be substantially uniformly arranged on the substrate of the display panel without deviation.

[0199] However, the effects of the present disclosure are not limited to the above-described effects, and various modifications may be made without departing from the spirit and scope of the present disclosure.

[0200] The embodiments described in detail above are provided to explain the present disclosure, but it should be noted that the embodiments are not intended to limit the scope of the present disclosure. It should be understood by those skilled in the art that various changes, substitutions and modifications may be made herein without departing from the scope of the present disclosure as defined by the appended claims and their functional equivalents that should be included in the appended claims.

[0201] The scope of the present disclosure is not limited by the detailed description of this specification, and should be defined by the appended claims. In addition, all changes or modifications of the present disclosure derived from the meaning and scope of the claims and their equivalents should be interpreted as being included in the scope of the present disclosure.

Claims

1. A method for manufacturing a display panel, the method comprising: forming a light emitting element on a base substrate; The light-emitting element is first transferred to a first film; fixing the first film on which the light emitting element is arranged; stretching the first film by pressurizing the first film with a gas; as well as The light emitting elements rearranged by stretching the first film are secondarily transferred to a second film fixed to a stage.

2. The method according to claim 1, wherein: Elongating the first film includes elongating the first film into a spherical shape.

3. The method according to claim 1, wherein: The gas includes air.

4. The method according to claim 1, wherein: The distance between the light emitting elements increases due to the elongation of the first film.

5. The method according to claim 1, wherein: Elongating the first film includes elongating the first film to the second film spaced apart from the first film.

6. The method according to claim 1, wherein: Secondarily transferring the light emitting element includes pressurizing a portion of the first film on which the rearranged light emitting element is positioned with the gas so that the portion is parallel to the second film.

7. The method according to claim 1, further comprising: positioning the second film on a cell mask over the display substrate and defining a cell opening; pressurizing a portion of the second membrane with the gas; as well as The portion of the second film is irradiated with laser light.

8. The method according to claim 7, wherein: The portion of the second film overlaps one of the cell openings.

9. The method according to claim 8, wherein: While the portion of the second film is pressurized, the light emitting element rearranged and positioned on the portion of the second film is brought into contact with the display substrate.

10. The method according to claim 7, wherein: The light emitting element rearranged and positioned on the portion of the second film is bonded to the display substrate while illuminating the portion.

11. The method according to claim 7, wherein: Pressurizing the portion of the second film and irradiating the portion are performed based on the cell opening.

12. The method according to claim 1, wherein: When the light emitting element is secondarily transferred, the stage is moved downward toward the first film.

13. The method according to claim 1, wherein: When the light emitting element is secondarily transferred, the stage is moved downward toward the first film while being tilted.

14. The method according to claim 1, wherein: When the light emitting element is secondarily transferred, the first film is moved upward toward the second film.

15. The method according to claim 1, wherein: When the light emitting element is secondarily transferred, the first film is moved upward toward the second film while being tilted.

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