Electronic device

Abstract

The invention provides an electronic device. The electronic device comprises a substrate, a first light-emitting unit, a second light-emitting unit, a first driving circuit, a second driving circuit and a conductive layer, the first light-emitting unit and the second light-emitting unit are arranged on the substrate. The first driving circuit is arranged on the substrate and comprises a first transistor, and the first transistor is used for driving the first light-emitting unit. The second driving circuit is arranged on the substrate and comprises a second transistor, and the second transistor is used for driving the second light-emitting unit. The conducting layer is arranged between the substrate and the first light-emitting unit and between the substrate and the second light-emitting unit and comprises a first part and a second part connected with the first part, the first transistor comprises a first semiconductor layer, the second transistor comprises a second semiconductor layer, and the first semiconductor layer and the second semiconductor layer are arranged in the normal direction of the substrate. The first portion at least partially overlaps the first semiconductor layer, and the second portion at least partially overlaps the second semiconductor layer. The yield of the electronic device provided by the invention can be improved.

Description

Technical Field

[0001] The present disclosure relates to an electronic device, and more particularly to an electronic device including a light emitting element. Background Art

[0002] When performing the process of forming an electronic device, the formed components and wirings are easily affected by subsequent processes and produce defects, so that the final electronic device has a relatively poor yield. Summary of the invention

[0003] The present disclosure is directed to an electronic device having an improved yield.

[0004] According to some embodiments of the present disclosure, an electronic device includes a substrate, a first light-emitting unit, a second light-emitting unit, a first driving circuit, a second driving circuit, and a conductive layer. The first light-emitting unit and the second light-emitting unit are disposed on the substrate. The first driving circuit is disposed on the substrate and includes a first transistor, and the first transistor is used to drive the first light-emitting unit. The second driving circuit is disposed on the substrate and includes a second transistor, and the second transistor is used to drive the second light-emitting unit. The conductive layer is disposed between the substrate and the first light-emitting unit and between the substrate and the second light-emitting unit, and includes a first portion and a second portion connected to the first portion, wherein the first transistor includes a first semiconductor layer, the second transistor includes a second semiconductor layer, and in the normal direction of the substrate, the first portion at least partially overlaps the first semiconductor layer, and the second portion at least partially overlaps the second semiconductor layer.

[0005] According to other embodiments of the present disclosure, an electronic device includes a substrate, a first light-emitting unit, a first driving circuit, and a conductive layer. The first light-emitting unit is disposed on the substrate, wherein the first light-emitting unit is located in one of a plurality of pixel regions. The first driving circuit is disposed on the substrate for driving the first light-emitting unit, wherein the first driving circuit is located in said one of the plurality of pixel regions. The conductive layer is disposed between the substrate and the first light-emitting unit, and at least a portion of the conductive layer is located in one of the plurality of pixel regions. In a top view of the electronic device, at least a portion of the conductive layer located in one of the plurality of pixel regions has a first area, and a ratio of the first area to a second area of ​​the pixel region is greater than or equal to 50% and less than or equal to 100%.

[0006] In order to make the above features and advantages of the present disclosure more obvious and understandable, embodiments are given below with reference to the accompanying drawings for detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A A schematic top view of an electronic device according to an embodiment of the present disclosure;

[0008] Figure 1B Based on Figure 1AAn enlarged schematic diagram of a pixel area of ​​an electronic device;

[0009] Figure 1C Based on Figure 1A An enlarged schematic diagram of a conductive layer in a pixel region of an electronic device;

[0010] Figure 1D Show Figure 1A A schematic diagram of the area of ​​a pixel region of an electronic device in FIG.

[0011] Figure 1E Show Figure 1A A schematic diagram of the area of ​​a switching transistor of an electronic device in FIG.

[0012] Figure 1F Show Figure 1A A schematic diagram of the area of ​​a driving transistor of an electronic device in FIG.

[0013] Figure 1G Show Figure 1A A schematic diagram of the area of ​​the storage capacitor of the electronic device;

[0014] Figure 1H Show Figure 1A A schematic diagram of the area of ​​a signal line of an electronic device in FIG.

[0015] Figure 2A A schematic top view of an electronic device according to another embodiment of the present disclosure;

[0016] Figure 2B Based on Figure 2A A schematic partial cross-sectional view of the section line A-A';

[0017] Figure 3A A partial cross-sectional schematic diagram of the arrangement relationship between the first semiconductor layer and the conductive layer in the electronic device of the first embodiment of the present disclosure;

[0018] Figure 3B A partial cross-sectional schematic diagram showing the arrangement relationship between the first semiconductor layer and the conductive layer in the electronic device of the second embodiment of the present disclosure;

[0019] Figure 3C A partial cross-sectional schematic diagram showing the disposition relationship between the first semiconductor layer and the conductive layer in the electronic device of the third embodiment of the present disclosure;

[0020] Figure 3D A partial cross-sectional schematic diagram showing the arrangement relationship between the first semiconductor layer and the conductive layer in the electronic device according to the fourth embodiment of the present disclosure;

[0021] Figure 3E A partial cross-sectional schematic diagram showing the disposition relationship between the first semiconductor layer and the conductive layer in the electronic device of the fifth embodiment of the present disclosure;

[0022] Figure 4A A partial cross-sectional schematic diagram showing the arrangement relationship between the storage capacitor and the conductive layer in the electronic device of the first embodiment of the present disclosure;

[0023] Figure 4B A partial cross-sectional schematic diagram showing the arrangement relationship between the storage capacitor and the conductive layer in the electronic device according to the second embodiment of the present disclosure;

[0024] Figure 4C A partial cross-sectional schematic diagram showing the arrangement relationship between the storage capacitor and the conductive layer in the electronic device according to the third embodiment of the present disclosure;

[0025] Figure 4D A partial cross-sectional schematic diagram showing the arrangement relationship between the storage capacitor and the conductive layer in the electronic device according to the fourth embodiment of the present disclosure;

[0026] Figure 4E A partial cross-sectional schematic diagram showing the arrangement relationship between the storage capacitor and the conductive layer in the electronic device according to the fifth embodiment of the present disclosure;

[0027] Figure 5A A partial cross-sectional schematic diagram of the arrangement relationship between the signal line and the conductive layer in the electronic device of the first embodiment of the present disclosure;

[0028] Figure 5B A partial cross-sectional schematic diagram showing the arrangement relationship between the signal line and the conductive layer in the electronic device according to the second embodiment of the present disclosure;

[0029] Figure 5C A partial cross-sectional schematic diagram showing the arrangement relationship between the signal line and the conductive layer in the electronic device according to the third embodiment of the present disclosure;

[0030] Figure 5D A partial cross-sectional schematic diagram showing the arrangement relationship between the signal line and the conductive layer in the electronic device according to the fourth embodiment of the present disclosure;

[0031] Figure 5E It is a partial cross-sectional schematic diagram of the arrangement relationship between the signal line and the conductive layer in the electronic device according to the fifth embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0033] The present disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that in order to facilitate the understanding of the readers and the simplicity of the drawings, the multiple drawings in the present disclosure only depict a portion of the electronic device, and the specific elements in the drawings are not drawn according to the actual scale. In addition, the number and size of each element in the drawings are only for illustration and are not intended to limit the scope of the present disclosure.

[0034] Certain words are used throughout the specification and the claims that follow to refer to specific components. It will be understood by those skilled in the art that electronic device manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that have the same function but different names. In the following specification and claims, words such as "include", "contain", "have" are open-ended words, and therefore should be interpreted as "including but not limited to..." Therefore, when the terms "include", "contain" and / or "have" are used in the description of the present disclosure, they specify the presence of corresponding features, regions, steps, operations and / or components, but do not exclude the presence of one or more corresponding features, regions, steps, operations and / or components.

[0035] Directional terms mentioned herein, such as "up", "down", "front", "back", "left", "right", etc., are only with reference to the directions of the accompanying drawings. Therefore, the directional terms used are for illustration and not for limiting the present disclosure. In the accompanying drawings, each figure shows the general characteristics of the methods, structures and / or materials used in a particular embodiment. However, these drawings should not be interpreted as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative size, thickness and position of each film layer, region and / or structure may be reduced or enlarged.

[0036] When a corresponding component (such as a film layer or region) is referred to as being "on another component", it may be directly on the other component, or other components may exist between the two. On the other hand, when a component is referred to as being "directly on another component", there is no component between the two. In addition, when a component is referred to as being "on another component", the two have a top-down relationship in a top-down direction, and the component may be above or below the other component, and the top-down relationship depends on the orientation of the device.

[0037] The terms "about," "substantially," or "approximately" are generally interpreted as meaning within a range of 10% of a given value, or within a range of 5%, 3%, 2%, 1% or 0.5% of a given value.

[0038] The ordinal numbers used in the specification and claims, such as "first", "second", etc., are used to modify the elements. They do not imply or represent any previous ordinal numbers of the element (or elements), nor do they represent the order of one element and another element, or the order of the manufacturing method. The use of these ordinal numbers is only used to make the element with a certain name clearly distinguishable from another element with the same name. The claims and the specification may not use the same words. Accordingly, the first component in the specification may be the second component in the claim.

[0039] It should be noted that the following embodiments may replace, reorganize, or mix features in several different embodiments to complete other embodiments without departing from the spirit of the present disclosure. Features between embodiments may be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

[0040] The electrical connection or coupling described in the present disclosure may refer to direct connection or indirect connection. In the case of direct connection, the endpoints of the components on the two circuits are directly connected or connected to each other by a conductor segment, and in the case of indirect connection, there are switches, diodes, capacitors, inductors, other suitable components, or combinations of the above components between the endpoints of the components on the two circuits, but it is not limited thereto.

[0041] In the present disclosure, the thickness, length and width can be measured by an optical microscope, and the thickness can be measured by a cross-sectional image in an electron microscope, but it is not limited to this. In addition, any two values ​​or directions used for comparison may have a certain error. If the first value is equal to the second value, it implies that there may be an error of about 10% between the first value and the second value; if the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

[0042] The electronic device disclosed herein may include a light-emitting device, a display device, a sensing device, an antenna device, or a splicing device, but is not limited thereto. The electronic device may include a bendable or flexible electronic device. The electronic device may include, for example, a liquid crystal layer or a light emitting diode (LED). The electronic device may include an electronic component. The electronic component may include passive components and active components, such as capacitors, resistors, inductors, variable capacitors, filters, diodes, transistors, sensors, micro-electromechanical system components (MEMS), liquid crystal chips, etc., but are not limited thereto. The diode may include a light-emitting diode or a photodiode. The light-emitting diode may include, for example, an organic light emitting diode (OLED), a sub-millimeter light-emitting diode (mini LED), a micro light-emitting diode (micro LED), a quantum dot light-emitting diode (quantum dot LED), fluorescence, phosphor or other suitable materials, or a combination thereof, but is not limited thereto. The sensor may include, for example, capacitive sensors, optical sensors, electromagnetic sensors, fingerprint sensors (FPS), touch sensors, antennas, or pen sensors, but is not limited thereto.

[0043] The following is an example of an exemplary embodiment of the present disclosure, in which the electronic device is described as a light emitting device, and the same reference numerals are used in the drawings and the description to represent the same or similar parts.

[0044] Figure 1A is a top view schematic diagram of an electronic device according to an embodiment of the present disclosure, Figure 1B Based on Figure 1A an enlarged schematic diagram of a pixel region of an electronic device in FIG. Figure 1C Based on Figure 1A A locally enlarged schematic diagram of a conductive layer in a pixel area of ​​an electronic device in FIG.

[0045] Please also refer to Figure 1A as well as Figure 1BThe electronic device 10 of the present embodiment includes a substrate SB, a light emitting unit LE, a driving circuit DC, and a conductive layer M. From another perspective, the electronic device 10 includes a plurality of pixel regions PX, wherein the plurality of pixel regions PX are arranged in an array. Specifically, the plurality of pixel regions PX may be arranged, for example, along the second direction X and / or the first direction Y, but the present disclosure is not limited thereto.

[0046] The material of the substrate SB may be, for example, glass, plastic, or a combination thereof. For example, the material of the substrate SB may include quartz, sapphire, silicon (Si), germanium (Ge), silicon carbide (SiC), gallium nitride (GaN), silicon germanium (SiGe), polymethyl methacrylate (PMMA), polycarbonate (PC), polyimide (PI), polyethylene terephthalate (PET), or other suitable materials or a combination of the above materials, but the present disclosure is not limited thereto.

[0047] The light emitting unit LE is, for example, disposed on the substrate SB, wherein the light emitting unit LE is located in one of the plurality of pixel regions PX. The light emitting unit LE may, for example, include a sub-millimeter light emitting diode (mini-LED), an organic light emitting diode (OLED), a micro-LED, or a quantum dot light emitting diode (QDLED). In the present embodiment, the light emitting unit LE includes a sub-millimeter light emitting diode, but the present disclosure is not limited thereto.

[0048] The driving circuit DC is, for example, disposed on the substrate SB, wherein the driving circuit DC is located in one of the plurality of pixel regions PX. In some embodiments, the driving circuit DC is coupled to the light emitting unit LE to drive the light emitting unit LE. Figure 1B As shown, the driving circuit DC includes a switch transistor ST, a driving transistor DT and a storage capacitor Cst, but the present disclosure is not limited thereto.

[0049] In some embodiments, the coupling method between the driving circuit DC and the light emitting unit LE may be as described below, but the present disclosure is not limited thereto.

[0050] The control terminal (not shown) of the switching transistor ST may be coupled to a scan line (not shown), for example, the first terminal (not shown) of the switching transistor ST may be coupled to a data line (not shown), for example, the second terminal (not shown) of the switching transistor ST may be coupled to a storage capacitor Cst, for example, the control terminal (not shown) of the driving transistor DT may be coupled to a storage capacitor Cst, for example, the first terminal (not shown) of the driving transistor DT may be coupled to a power line (not shown), for example, and the second terminal (not shown) of the driving transistor DT may be coupled to a light-emitting unit LE, for example.

[0051] Based on this, when the control end of the switch transistor ST receives a corresponding scan signal from the scan line and turns on the switch transistor ST, the data signal from the data line can reach the storage capacitor Cst through the first end and the second end of the switch transistor ST, and the data signal is stored in the storage capacitor Cst. Afterwards, when the control end of the driving transistor DT receives a corresponding data signal from the storage capacitor Cst and turns on the switch transistor ST, a corresponding driving current can be generated according to the power supply voltage received by the first end of the driving transistor DT from the power supply line, and the driving current flows to the light-emitting unit LE through the second end of the driving transistor DT, thereby driving the light-emitting unit LE.

[0052] In some embodiments, the number of switch transistors ST in one of the multiple pixel regions PX may be one, the number of drive transistors DT in one of the multiple pixel regions PX may be multiple, and the number of storage capacitors Cst in one of the multiple pixel regions PX may be multiple, but the present disclosure is not limited to this.

[0053] The conductive layer M is disposed on the substrate SB, for example, wherein at least a portion of the conductive layer M is located in one of the plurality of pixel regions PX. In the present embodiment, in the normal direction of the substrate SB, the conductive layer M is disposed between the substrate SB and the light emitting unit LE, but the present disclosure is not limited thereto. Figure 1C As shown, the conductive layer M may include, for example, a pad pattern P1, a pad pattern P2, a first power line VDD, and a second power line VSS, wherein the pad pattern P1 and the pad pattern P2 may be, for example, electrically connected to the light-emitting unit LE, and the first power line VDD and the second power line VSS extend, for example, along a first direction Y. It is worth noting that in the present disclosure, the range of the pad pattern P1 and the pad pattern P2 is defined as the conductive layer M due to the through hole (such as Figure 2B The portion exposed by the through hole TH7 and the through hole TH7').

[0054] In the present embodiment, the electronic device 10 further includes a third power line VDD' and a fourth power line VSS' extending along the second direction X. The pixel area PX is, for example, defined by a first power line VDD and a second power line VSS extending along the first direction Y, and a third power line VDD and a fourth power line VSS' extending along the second direction X. In detail, the pixel area PX is an area enclosed by a boundary line VC between adjacent first power lines VDD and second power lines VSS and a boundary line VC' between adjacent third power lines VDD' and fourth power lines VSS'. More specifically, there is a gap between the first power line VDD and the second power line VSS that are adjacent but correspond to different pixel areas PX to avoid electrical connection between the two, and the center line of the gap can be defined as the boundary line VC. Similarly, there is another gap between the third power line VDD' and the fourth power line VSS' that are adjacent but correspond to different pixel areas PX to avoid electrical connection between the two, and the center line of the gap can be defined as the boundary line VC'. It is also worth noting that in order to clearly illustrate the arrangement of each component, Figure 1A as well as Figure 1B The illustration of a portion of the conductive layer M is omitted so that the driving circuit DC is exposed. In some embodiments, the area of ​​the first power line VDD and the second power line VSS can be increased and Figure 1B The light emitting unit LE and the driving circuit DC in the embodiment are mostly overlapped.

[0055] Figure 1D Show Figure 1A A schematic diagram of the area of ​​a pixel region of an electronic device in FIG. Figure 1E Show Figure 1A Schematic diagram of the area of ​​the switching transistor in the electronic device, Figure 1F Show Figure 1A Schematic diagram of the area of ​​the driving transistor of the electronic device, Figure 1G Show Figure 1A A schematic diagram of the area of ​​the storage capacitor of the electronic device in FIG. 1 , and Figure 1H Show Figure 1A Schematic diagram of the area of ​​a signal line in an electronic device.

[0056] exist Figure 1C In one embodiment shown, it is shown that at least a portion of the conductive layer M located in one of the plurality of pixel regions PX has a first area Area_M; Figure 1DIn one embodiment shown, one of the plurality of pixel regions PX is shown to have a second area Area_PX. In this embodiment, the ratio of the first area Area_M of the conductive layer M in the pixel region PX to the second area Area_PX of the pixel region PX is greater than or equal to 50% and less than or equal to 100% (50%≤Area_M / Area_PX≤100%). It is worth noting that the second area Area_PX of one of the plurality of pixel regions PX does not include the pad area PA (such as Figure 1C The pad pattern P1 and the pad pattern P2 are shown in FIG.

[0057] exist Figure 1E In one embodiment shown, the switch transistor ST has a third area Area_ST. It is worth noting that the third area Area_ST of the switch transistor ST can be, for example, defined by the edge of the semiconductor layer SE1 of the switch transistor ST extending outward by a specific distance d1. For example, the third area Area_ST of the switch transistor ST can be defined by the edge of the semiconductor layer SE1 of the switch transistor ST extending toward the second direction X and / or the first direction Y by a specific distance d1, wherein the specific distance d1 is approximately 10 micrometers, but the present disclosure is not limited thereto. In other embodiments, the number of switch transistors ST in one of the plurality of pixel regions PX can be multiple, in which case the third area Area_ST of the switch transistor ST can be the sum of the individual third areas defined by each switch transistor ST according to the above method, but if the third areas of some of the switch transistors ST overlap, the area of ​​the overlapping area is not counted repeatedly. In some embodiments, the semiconductor layer ST_SE of the switch transistor ST and the conductive layer M at least partially overlap in the normal direction Z of the substrate SB. In this embodiment, the ratio of the overlapping area of ​​the semiconductor layer ST_SE and the conductive layer M of the switching transistor ST in the normal direction Z of the substrate SB to the third area Area_ST of the switching transistor ST is greater than or equal to 50% and less than or equal to 100% (50%≤overlapping area / Area_ST≤100%).

[0058] exist Figure 1FIn one embodiment shown, the driving transistor DT is shown to have a fourth area Area_DT. It is worth noting that the calculation method of the fourth area Area_DT of the driving transistor DT is similar to the calculation method of the third area Area_ST of the switching transistor ST, and both are defined by extending a specific distance (such as distance d2) outward from the edge of the semiconductor layer, wherein the specific distance d2 is approximately 10 microns, but the present disclosure is not limited thereto. And when multiple driving transistors DT are included at the same time, the calculation method of the fourth area Area_DT is also the same as the calculation method of the third area Area_ST when multiple switching transistors ST exist at the same time, and will not be repeated here. In some embodiments, the semiconductor layer DT_SE of the driving transistor DT and the conductive layer M at least partially overlap in the normal direction Z of the substrate SB. In this embodiment, the ratio of the area of ​​overlap between the semiconductor layer DT_SE of the driving transistor DT and the conductive layer M in the normal direction Z of the substrate SB to the fourth area Area_DT of the driving transistor DT is greater than or equal to 50% and less than or equal to 100% (50%≤overlapping area / Area_DT≤100%).

[0059] The materials of the semiconductor layer ST_SE and the semiconductor layer DT_SE may include, for example, low temperature polysilicon (LTPS), metal oxide, amorphous silicon (a-Si) or a combination thereof, but the present disclosure is not limited thereto. For example, the material of the semiconductor layer SE may include, but is not limited to, amorphous silicon, polycrystalline silicon, germanium, compound semiconductors (such as gallium nitride, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide), alloy semiconductors (such as SiGe alloy, GaAsP alloy, AlInAs alloy, AlGaAs alloy, GaInAs alloy, GaInP alloy, GaInAsP alloy), or a combination thereof. The material of the semiconductor layer SE may also include, but is not limited to, metal oxides, such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZTO), or organic semiconductors including polycyclic aromatic compounds, or a combination thereof.

[0060] exist Figure 1GIn one embodiment shown, the storage capacitor Cst is shown to have a fifth area Area_Cst. It is worth noting that the fifth area Area_Cst of the storage capacitor Cst can be, for example, defined by a specific distance d3 extending outward from the edge of the storage capacitor Cst, wherein the specific distance d3 is approximately 10 microns, but the present disclosure is not limited to this. Similar to the calculation method of the third area Area_ST, when the storage capacitor Cst is a combination of multiple storage capacitors, the fifth area Area_Cst is the sum of the fifth areas of the individual storage capacitors, but if the fifth areas of some storage capacitors overlap, the area of ​​the overlapping area is not counted repeatedly. The distance between adjacent storage capacitors Cst in this fifth area Area_Cst will be less than the specific distance d3. For example, if Figure 1G As shown, when the storage capacitors Cst are closely arranged (the spacing between the storage capacitors Cst is less than the distance d3), the fifth area Area_Cst can be defined by the edge of the outermost storage capacitor Cst extending a specific distance d3 in the second direction X and / or the first direction Y. In some embodiments, the storage capacitor Cst and the conductive layer M at least partially overlap in the normal direction Z of the substrate SB. In this embodiment, the ratio of the area where the storage capacitor Cst overlaps with the conductive layer M in the normal direction Z of the substrate SB to the fifth area Area_Cst of the driving transistor DT is greater than or equal to 50% and less than or equal to 100% (50%≤overlapping area / Area_Cst≤100%).

[0061] In some embodiments, the electronic device 10 further includes a signal line SI, wherein the signal line SI may include a scan line, a data line, a power line, and other suitable signal lines that are different from the conductive layer M, but the present disclosure is not limited thereto. Figure 1H In one embodiment shown, the signal line SI is shown to have a sixth area Area_SI. It is worth noting that the sixth area Area_SI of the signal line SI can be defined, for example, by extending a specific distance d4 outward from the edge of the signal line SI, wherein the specific distance d4 is approximately 10 microns, but the present disclosure is not limited to this. Similar to the calculation method of the third area Area_ST, when multiple signal lines SI are closely arranged (the spacing between the signal lines SI is less than the distance d4), the sixth area Area_SI is the sum of the sixth areas of the individual signal lines SI, but if the sixth areas of some signal lines SI overlap, the area of ​​the overlapping area is not counted repeatedly. For example, if Figure 1HAs shown, when a plurality of signal lines SI are closely arranged, the sixth area Area_SI of the signal line SI can be defined by the edge of the outermost data line moving outward by a specific distance d4 in the second direction X and / or the edge of the outermost scan line moving outward in the first direction Y. In some embodiments, the signal line SI and the conductive layer M at least partially overlap in the normal direction Z of the substrate SB. In this embodiment, the ratio of the overlapping area of ​​the signal line SI and the conductive layer M in the normal direction Z of the substrate SB to the sixth area Area_SI of the signal line SI is greater than or equal to 50% and less than or equal to 100% (50% ≤ overlapping area / Area_SI ≤ 100%).

[0062] Based on this, by making the ratio of the first area Area_M of the conductive layer M set in the pixel area PX to the second area Area_PX of the pixel area PX greater than or equal to 50% and less than or equal to 100%, the components formed in the pixel area PX can be at least partially shielded by the conductive layer M when the process of forming the remaining components is carried out, thereby reducing the possibility of defects. Therefore, the electronic device 10 of this embodiment can have a higher yield.

[0063] In addition, in this embodiment, Figure 1E to Figure 1H As shown, the third area Area_ST of the switching transistor ST, the fourth area Area_DT of the driving transistor DT, the fifth area Area_Cst of the storage capacitor Cst and / or the sixth area Area_SI of the signal line SI have the relationship as described above with the first area Area_M of the conductive layer M in the pixel area PX, so that the switching transistor ST, the driving transistor DT, the storage capacitor Cst and / or the signal line SI formed in the pixel area PX can be shielded by the conductive layer M when the process of forming the remaining components is carried out to reduce the possibility of defects. Therefore, the electronic device 10 of this embodiment can have a higher yield.

[0064] Figure 2A is a top view of an electronic device according to another embodiment of the present disclosure, and Figure 2B Based on Figure 2A It should be noted that: Figure 2A as well as Figure 2B The embodiments can be used Figures 1A to 1H The component numbers and partial contents of the embodiments are shown in the figure, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted.

[0065] Please also refer to Figure 2A as well as Figure 2BThe electronic device 20 of the present embodiment includes a substrate SB, a first light emitting unit LE1, a second light emitting unit LE2, a first driving circuit DC1, a second driving circuit DC2 and a conductive layer M4.

[0066] The description of the substrate SB may refer to the above embodiments, for example, and will not be repeated here.

[0067] The first light emitting unit LE1 and the second light emitting unit LE2 are, for example, disposed on the substrate SB, wherein the description of the first light emitting unit LE1 and the second light emitting unit LE2 may refer to the light emitting unit LE in the above embodiment, which will not be repeated herein.

[0068] The first driving circuit DC1 is, for example, disposed on the substrate SB and includes a first transistor T1, wherein the first transistor T1 is, for example, used to drive the first light emitting unit LE1. In this embodiment, the first transistor T1 includes a first semiconductor layer SE1, wherein the first semiconductor layer SE1 may include the semiconductor layer of the above embodiment, which will not be described in detail. It is worth noting that in Figure 2B Although only the driving transistor is shown, the first transistor T1 in the electronic device 20 of this embodiment also includes a switching transistor. The description of the switching transistor and the driving transistor can refer to the above embodiment, and will not be repeated here.

[0069] Similarly, the second driving circuit DC2 is, for example, disposed on the substrate SB and includes a second transistor T2, wherein the second transistor T2 is, for example, used to drive the second light-emitting unit LE2. In the present embodiment, the second driving circuit DC2 has the same or similar composition as the first driving circuit DC1, that is, the second transistor T2 also includes a switch transistor and a drive transistor, wherein the description of the switch transistor and the drive transistor can refer to the above embodiment, and will not be repeated here. In some embodiments, the second transistor T2 also includes a second semiconductor layer SE2, wherein the second semiconductor layer SE2 may include the semiconductor layer of the above embodiment, and will not be repeated here.

[0070] The conductive layer M4 is, for example, disposed between the substrate SB and the first light-emitting unit LE1 and between the substrate SB and the second light-emitting unit LE2, and includes a first portion M41 and a second portion M42 connected to the first portion M41. The first portion M41 may be, for example, a portion of the conductive layer M4 located in the pixel region PX where the first transistor T1 is located, and the second portion M42 may be, for example, a portion of the conductive layer M4 located in the pixel region PX where the second transistor T2 is located. In the present embodiment, in the normal direction Z of the substrate SB, the conductive layer M4 is located between the first semiconductor layer SE1 and the first light-emitting unit LE1 and between the second semiconductor layer SE2 and the second light-emitting unit LE2, but the present disclosure is not limited thereto. In addition, in the present embodiment, the conductive layer M4 is the uppermost conductive layer in the electronic device 20 except for the bonding structure BS, but the present disclosure is not limited thereto. In some embodiments, in the normal direction Z of the substrate SB, the first portion M41 at least partially overlaps the first semiconductor layer SE1, and the second portion M42 at least partially overlaps the second semiconductor layer SE2. In the present embodiment, the first semiconductor layer SE1 completely overlaps with the first portion M41 of the conductive layer M4 , and the second semiconductor layer SE2 completely overlaps with the second portion M42 of the conductive layer M4 , but the present disclosure is not limited thereto.

[0071] In general, the conductive layer M4 includes a first portion M41 and a second portion M42 that at least span two pixel regions PX, wherein the first portion M41 and the second portion M42 are connected to each other and each at least partially overlaps the first semiconductor layer SE1 of the first transistor T1 and the first semiconductor layer SE1 of the second transistor T2.

[0072] Based on this, in the present embodiment, the conductive layer M4 can at least be used to shield the first semiconductor layer SE1 and the second semiconductor layer SE2 that have been formed during the formation of the electronic device 20, thereby reducing the possibility of defects in the first semiconductor layer SE1 and the second semiconductor layer SE2 when the process of forming other components is carried out. Therefore, the electronic device 20 of the present embodiment can have a higher yield.

[0073] In some embodiments, the electronic device 20 further includes a conductive layer M1, an insulating layer IL1, an insulating layer IL2, a conductive layer M2, an insulating layer IL3, a conductive layer M3, an insulating layer IL4, a planar layer PL, an insulating layer IL5, an insulating layer IL6, and a bonding structure BS.

[0074] The conductive layer M1 is, for example, disposed on the substrate SB and may be, for example, used as a light shielding layer and / or a storage electrode (eg, as shown below). FIG. 4A to FIG. 4EIn some embodiments, a portion of the conductive layer M1 can also be used as a gate of a transistor and located below the semiconductor layers SE1 and SE2. Specifically, in this embodiment, the conductive layer M1 is disposed on the substrate SB and is at least located between the substrate SB and the channel region of the first semiconductor layer SE1 and the channel region of the second semiconductor layer SE2, thereby reducing the degradation of the channel region due to exposure to external ambient light. In some embodiments, the material of the conductive layer M1 may include a material with a transmittance lower than 30%, but the present disclosure is not limited thereto.

[0075] The insulating layer IL1 is, for example, disposed on the substrate SB. In the present embodiment, the insulating layer IL1 partially covers the conductive layer M1. Specifically, the insulating layer IL1 includes a through hole exposing a portion of the conductive layer M1, but the present disclosure is not limited thereto. The material of the insulating layer IL1 may be, for example, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), but the present disclosure is not limited thereto.

[0076] The insulating layer IL2 is, for example, disposed on the insulating layer IL1. In the present embodiment, the above-mentioned first semiconductor layer SE1 and the second semiconductor layer SE2 may be disposed between the insulating layer IL2 and the insulating layer IL1. The insulating layer IL2, for example, partially covers the first semiconductor layer SE1 and a portion of the second semiconductor layer SE2. In detail, the insulating layer IL2 includes a through hole exposing a portion of the first semiconductor layer SE1 and a portion of the second semiconductor layer SE2, but the present disclosure is not limited thereto. In addition, the insulating layer IL2 also includes a through hole exposing a portion of the conductive layer M1. In detail, this through hole included in the insulating layer IL2 may be connected to the through hole included in the above-mentioned insulating layer IL1 to form a through hole TH1 to expose a portion of the conductive layer M1 together. The material of the insulating layer IL2 may be, for example, an inorganic material (for example: silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above-mentioned materials), but the present disclosure is not limited thereto.

[0077] The conductive layer M2 is, for example, disposed on the insulating layer IL1. In the present embodiment, the conductive layer M2 may include a storage electrode SC2 and a gate electrode G. In some embodiments, the storage electrode SC2 may be electrically connected to the conductive layer M1 via a through hole TH1 penetrating the insulating layer IL1 and the insulating layer IL2, but the present disclosure is not limited thereto. The gate electrode G, for example, at least partially overlaps the first semiconductor layer SE1 of the first transistor T1 and the second semiconductor layer SE2 of the second transistor T2 in the normal direction Z of the substrate SB.

[0078] The insulating layer IL3 is, for example, disposed on the insulating layer IL2. In the present embodiment, the insulating layer IL3 partially covers the first semiconductor layer SE1 and the second semiconductor layer SE2. In detail, the insulating layer IL3 includes a through hole exposing a portion of the first semiconductor layer SE1 and the second semiconductor layer SE2, wherein the through hole included in the insulating layer IL3 can be connected with the through hole included in the insulating layer IL2 to form a through hole TH2 and a through hole TH3 to expose a portion of the first semiconductor layer SE1 and a portion of the second semiconductor layer SE2 together. The material of the insulating layer IL3 can be, for example, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), but the present disclosure is not limited thereto.

[0079] The conductive layer M3 is, for example, disposed on the insulating layer IL3. In the present embodiment, the conductive layer M3 may include a source S, a drain D, a third power line VDD', and a fourth power line VSS'. The source S is, for example, separated from the drain D, wherein the source S may be, for example, electrically connected to the first semiconductor layer SE1 or the second semiconductor layer SE2 through a through hole TH2 penetrating the insulating layer IL2 and the insulating layer IL3, and the drain D may be, for example, electrically connected to the first semiconductor layer SE1 or the second semiconductor layer SE2 through a through hole TH3 penetrating the insulating layer IL2 and the insulating layer IL3, but the present disclosure is not limited thereto. The third power line VDD', for example, extends along the second direction X, and may, for example, be used to provide a first power supply voltage to the first light-emitting unit LE1 and the second light-emitting unit LE2. The fourth power line VSS', for example, extends along the second direction X, and may, for example, be used to provide a second power supply voltage to the first light-emitting unit LE1 and the second light-emitting unit LE2, wherein the voltage level of the second power supply voltage is, for example, lower than the voltage level of the first power supply voltage.

[0080] The insulating layer IL4 is, for example, disposed on the insulating layer IL3. In the present embodiment, the insulating layer IL4 partially covers the drain electrode D, the third power line VDD', and the fourth power line VSS'. In detail, the insulating layer IL4 includes a plurality of through holes that each expose a portion of the drain electrode D, a portion of the third power line VDD', and a portion of the fourth power line VSS'. The material of the insulating layer IL4 may be, for example, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), but the present disclosure is not limited thereto.

[0081] The planar layer PL is, for example, disposed on the insulating layer IL4. In the present embodiment, the planar layer PL also partially covers the drain electrode D, the third power line VDD', and the fourth power line VSS'. In detail, the planar layer PL also includes a plurality of through holes that each expose a portion of the drain electrode D, a portion of the third power line VDD', and a portion of the fourth power line VSS'. The material of the planar layer PL may be, for example, an organic material (e.g., a polyimide resin, an epoxy resin, or an acrylic resin) or a combination thereof, but the present disclosure is not limited thereto.

[0082] The insulating layer IL5 is, for example, disposed on the planar layer PL. In the present embodiment, the insulating layer IL5 also partially covers the drain electrode D, the third power line VDD', and the fourth power line VSS'. Specifically, the insulating layer IL5 also includes a plurality of through holes that each expose a portion of the drain electrode D, a portion of the third power line VDD', and a portion of the fourth power line VSS', wherein the through holes included in the insulating layer IL5 can be connected with the plurality of through holes included in the planar layer PL and the plurality of through holes included in the insulating layer IL4 to form through holes TH4, through holes TH5 (shown in FIG. Figure 2A The insulating layer IL5 may be made of an inorganic material (eg, silicon oxide, silicon nitride, silicon oxynitride, or a stack of at least two of the above materials), but the present disclosure is not limited thereto.

[0083] The above-mentioned conductive layer M4 is, for example, disposed on the insulating layer IL5. In the present embodiment, the conductive layer M4 includes a pad pattern P1, a pad pattern P2, a first power line VDD, and a second power line VSS. The pad pattern P1 can be, for example, electrically connected to the drain D through a through hole TH4 penetrating the insulating layer IL4, the flat layer PL, and the insulating layer IL5, and the pad pattern P2 can be, for example, connected to the second power line VSS. The first power line VDD, for example, extends along the second direction X, and can be, for example, electrically connected to the first power line VDD' through a through hole TH5 penetrating the insulating layer IL4, the flat layer PL, and the insulating layer IL5. The second power line VSS, for example, extends along the second direction X, and can be, for example, electrically connected to the second power line VSS' through a through hole TH6 penetrating the insulating layer IL4, the flat layer PL, and the insulating layer IL5.

[0084] The insulating layer IL6 is, for example, disposed on the insulating layer IL5. In the present embodiment, the insulating layer IL6 partially covers the pad pattern P1 and the pad pattern P2. In detail, the insulating layer IL6 includes a through hole TH7 and a through hole TH7'. As described above, the range of the pad pattern P1 and the pad pattern P2 is defined as the portion of the conductive layer M exposed by the through hole TH7 and the through hole TH7'. The material of the insulating layer IL6 may be, for example, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), but the present disclosure is not limited thereto.

[0085] The bonding structure BS is, for example, disposed on the insulating layer IL6. In the present embodiment, the bonding structure BS may be electrically connected to the pad pattern P1 through the through hole TH7, and may be electrically connected to the pad pattern P2 through the through hole TH7'. In some embodiments, the bonding structure BS may include a bonding layer BS1 and a bonding layer BS2, wherein the bonding layer BS1 is disposed on the bonding layer BS2, and a portion of the bonding layer BS2 is disposed in the through hole TH7 and the through hole TH7' to be electrically connected to the pad pattern P1 and the pad pattern P2 respectively, but the present disclosure is not limited thereto. In some embodiments, the bonding structure BS may include solder, bumps, solder balls, conductive columns, other suitable structures or combinations thereof, but the present disclosure is not limited thereto. The material of the bonding structure BS may, for example, include a metal or an alloy. For example, the material of the bonding layer BS1 may include tin, and the material of the bonding layer BS2 may include nickel, but the present disclosure is not limited thereto.

[0086] It is worth noting that, from the above description, it can be known that the driving circuit in a pixel region may include a plurality of driving transistors. In this embodiment, a pixel region may include another driving transistor (not shown) and Figure 2B The driving transistor T1 or T2 is electrically connected, and the first power line VDD can be electrically connected to the other driving transistor through the through hole TH0. In some embodiments, the first power line VDD can be electrically connected to the through hole TH0. Figure 2B The driving transistor T1 or T2 is shown to be directly electrically connected.

[0087] The first light emitting unit LE1 and the second light emitting unit LE2 are, for example, disposed on the insulating layer IL6, and are electrically connected to the bonding structure BS respectively. Based on this, the first light emitting unit LE1 and the second light emitting unit LE2 can receive the driving current generated by the driving transistor (i.e., the first transistor T1 and the second transistor T2 of the present embodiment) through the bonding structure BS and the pad pattern P1 (generated by the power supply voltage transmitted to the driving transistor by the third power line VDD' through the first power line VDD and the electrical connection relationship described in the previous paragraph), and the first light emitting unit LE1 and the second light emitting unit LE2 can receive the ground voltage through the bonding structure BS, the pad pattern P2, the second power line VSS and the fourth power line VSS'. In some embodiments, the first light emitting unit LE1 and the second light emitting unit LE2 can have corresponding brightness according to the size of the driving current from the driving transistor.

[0088] Figure 3A is a partial cross-sectional schematic diagram of the arrangement relationship between the first semiconductor layer and the conductive layer in the electronic device of the first embodiment of the present disclosure, Figure 3B is a partial cross-sectional schematic diagram of the arrangement relationship between the first semiconductor layer and the conductive layer in the electronic device of the second embodiment of the present disclosure, Figure 3Cis a partial cross-sectional schematic diagram of the arrangement relationship between the first semiconductor layer and the conductive layer in the electronic device of the third embodiment of the present disclosure, Figure 3D is a partial cross-sectional schematic diagram of the arrangement relationship between the first semiconductor layer and the conductive layer in the electronic device of the fourth embodiment of the present disclosure, and Figure 3E This is a partial cross-sectional schematic diagram of the arrangement relationship between the first semiconductor layer and the conductive layer in the electronic device of the fifth embodiment of the present disclosure. It should be noted that, FIG. 3A to FIG. 3E The embodiments can be used Figure 2A as well as Figure 2B The component numbers and partial contents of the embodiments are shown in the figure, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted.

[0089] Please refer to Figure 3A , the electronic device 30a of this embodiment shows that the first semiconductor layer SE1 completely overlaps with the first portion M41 of the conductive layer M4 in the normal direction Z of the substrate SB. Figure 3A Not shown, the second semiconductor layer SE2 may also at least partially overlap with the second portion M42 of the conductive layer M4 in the normal direction Z of the substrate SB.

[0090] Based on this, the conductive layer M4 can shield the first semiconductor layer SE1 and the second semiconductor layer SE2 that have been formed during the formation of the electronic device 30 a , so as to reduce the possibility of defects in the first semiconductor layer SE1 and the second semiconductor layer SE2 .

[0091] Please refer to Figure 3B The main difference between the electronic device 30b of this embodiment and the aforementioned electronic device 30a is that the electronic device 30b further includes an insulating layer IL0 and a conductive layer M0.

[0092] The insulating layer IL0 is, for example, disposed between the substrate SB and the conductive layer M1 . The insulating layer IL0 may be made of, for example, an inorganic material (eg, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), but the present disclosure is not limited thereto.

[0093] The conductive layer M0 is, for example, disposed between the substrate SB and the insulating layer IL0 and is covered by the insulating layer IL0. In the present embodiment, the conductive layer M0 is located between the first semiconductor layer SE1 and the substrate SB. In some embodiments, the first semiconductor layer SE1 at least partially overlaps with the conductive layer M0 in the normal direction Z of the substrate SB. In the present embodiment, the first semiconductor layer SE1 completely overlaps with the conductive layer M0 in the normal direction Z of the substrate SB. In addition, although Figure 3BNot shown, the second semiconductor layer SE2 may also at least partially overlap with the conductive layer M0 in the normal direction Z of the substrate SB. That is, similar to the conductive layer M4, the conductive layer M0 may also be divided into two parts connected to each other, one of which at least partially overlaps with the first semiconductor layer SE1, and the other overlaps with the second semiconductor layer SE2. In some embodiments, the conductive layer M0 may be floating or may receive a corresponding signal (for example, receiving a ground signal for electromagnetic shielding), but the present disclosure is not limited thereto. In the present embodiment, the conductive layer M0 is the bottommost conductive layer in the electronic device 30b, but the present disclosure is not limited thereto.

[0094] Based on this, the conductive layer M0 and the conductive layer M4 can shield the first semiconductor layer SE1 and the second semiconductor layer SE2 formed during the formation of the electronic device 30 b , thereby reducing the possibility of defects in the first semiconductor layer SE1 and the second semiconductor layer SE2 .

[0095] Please refer to Figure 3C The main difference between the electronic device 30c of this embodiment and the aforementioned electronic device 30b is that the first semiconductor layer SE1 and the second semiconductor layer SE2 of the electronic device 30c completely overlap with the conductive layer M0 in the normal direction Z of the substrate SB, but do not overlap with the conductive layer M4.

[0096] Based on this, the conductive layer M0 can shield the first semiconductor layer SE1 and the second semiconductor layer SE2 that have been formed during the formation of the electronic device 30 c , so as to reduce the possibility of defects in the first semiconductor layer SE1 and the second semiconductor layer SE2 .

[0097] Please refer to Figure 3D The main difference between the electronic device 30d of this embodiment and the aforementioned electronic device 30a is that the electronic device 30d further includes a conductive layer M5.

[0098] The conductive layer M5 is, for example, disposed on the insulating layer IL6, and can be electrically connected to the conductive layer M41, for example, through a through hole TH8 penetrating the insulating layer IL6. In some embodiments, the first semiconductor layer SE1 at least partially overlaps with the conductive layer M5 in the normal direction Z of the substrate SB. In this embodiment, the first semiconductor layer SE1 completely overlaps with the conductive layer M5 in the normal direction Z of the substrate SB. In addition, although Figure 3D Not shown, the second semiconductor layer SE2 may also at least partially overlap with the conductive layer M5 in the normal direction Z of the substrate SB.

[0099] Based on this, the conductive layer M5 and the conductive layer M4 can shield the first semiconductor layer SE1 and the second semiconductor layer SE2 formed during the formation of the electronic device 30d, thereby reducing the possibility of defects in the first semiconductor layer SE1 and the second semiconductor layer SE2.

[0100] Please refer to Figure 3E The main difference between the electronic device 30e of this embodiment and the aforementioned electronic device 30c is that the electronic device 30e includes a conductive layer M5 but does not include a conductive layer M0.

[0101] The conductive layer M5 is, for example, disposed on the insulating layer IL6. In some embodiments, the first semiconductor layer SE1 at least partially overlaps with the conductive layer M5 in the normal direction Z of the substrate SB. In this embodiment, the first semiconductor layer SE1 completely overlaps with the conductive layer M5 in the normal direction Z of the substrate SB. Figure 3E Not shown, the second semiconductor layer SE2 may also at least partially overlap with the conductive layer M5 in the normal direction Z of the substrate SB. In some embodiments, the conductive layer M5 is floating, but the disclosure is not limited thereto.

[0102] In this embodiment, the electronic device 30e further includes an insulating layer IL7. The insulating layer IL7 is, for example, disposed on the conductive layer M5 and can cover the conductive layer M5. The material of the insulating layer IL7 can be, for example, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), but the present disclosure is not limited thereto.

[0103] Based on this, the conductive layer M5 can shield the first semiconductor layer SE1 and the second semiconductor layer SE2 that have been formed during the formation of the electronic device 30 e , thereby reducing the possibility of defects in the first semiconductor layer SE1 and the second semiconductor layer SE2 .

[0104] Figure 4A is a partial cross-sectional schematic diagram of the arrangement relationship between the storage capacitor and the conductive layer in the electronic device of the first embodiment of the present disclosure, Figure 4B FIG. 1 is a partial cross-sectional diagram of the arrangement relationship between the storage capacitor and the conductive layer in the electronic device of the second embodiment of the present disclosure. Figure 4C is a partial cross-sectional schematic diagram of the arrangement relationship between the storage capacitor and the conductive layer in the electronic device of the third embodiment of the present disclosure, Figure 4D is a partial cross-sectional schematic diagram of the arrangement relationship between the storage capacitor and the conductive layer in the electronic device of the fourth embodiment of the present disclosure, and Figure 4E This is a partial cross-sectional diagram of the arrangement relationship between the storage capacitor and the conductive layer in the electronic device of the fifth embodiment of the present disclosure. It should be noted that: FIG. 4A to FIG. 4E The embodiments can be used Figure 2A as well as Figure 2B The component numbers and partial contents of the embodiments are shown in the figure, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted.

[0105] Please refer to Figure 4AThe electronic device 40a of this embodiment shows that the storage capacitor Cst includes two parallel capacitors Cst1 and Cst2, wherein the capacitor Cst1 is formed by the storage electrode SC1 included in the conductive layer M1, the storage electrode SC2 included in the conductive layer M2, and the insulating layer disposed therebetween, and the capacitor Cst2 is formed by the storage electrode SC2 included in the conductive layer M2, the storage electrode SC3 included in the conductive layer M3, and the insulating layer disposed therebetween. However, the structure of the storage capacitor Cst disclosed in the present invention is not limited thereto.

[0106] In this embodiment, the conductive layer M4 further includes a third portion M43, and the third portion M43 at least partially overlaps with the storage capacitor Cst in the normal direction N of the substrate SB. In this embodiment, the storage capacitor Cst completely overlaps with the conductive layer M4 in the normal direction Z of the substrate SB.

[0107] Based on this, the conductive layer M4 can shield the storage capacitor Cst that has been formed during the formation of the electronic device 40 a to reduce the possibility of defects in the storage capacitor Cst.

[0108] Please refer to Figure 4B The main difference between the electronic device 40b of this embodiment and the aforementioned electronic device 40a is that the electronic device 40b further includes an insulating layer IL0 and a conductive layer M0. The storage capacitor Cst may at least partially overlap with the conductive layer M0 in the normal direction Z of the substrate SB. For example, in this embodiment, the storage capacitor Cst completely overlaps with the conductive layer M0 in the normal direction Z of the substrate SB. Figure 3B The insulating layer IL0 and the conductive layer M0 in the illustrated embodiment are the same or similar and are not described in detail herein.

[0109] Based on this, the conductive layer M0 together with the conductive layer M4 can shield the storage capacitor Cst formed during the formation of the electronic device 40 b to further reduce the possibility of defects in the storage capacitor Cst.

[0110] Please refer to Figure 4C The main difference between the electronic device 40c of this embodiment and the aforementioned electronic device 40b is that the storage capacitor Cst of the electronic device 40c completely overlaps with the conductive layer M0 in the normal direction Z of the substrate SB, but does not overlap with the conductive layer M4.

[0111] Based on this, the conductive layer M0 can shield the storage capacitor Cst that has been formed during the formation of the electronic device 40 c to reduce the possibility of defects in the storage capacitor Cst.

[0112] Please refer to Figure 4DThe main difference between the electronic device 40d of this embodiment and the aforementioned electronic device 40a is that the electronic device 40d further includes a conductive layer M5.

[0113] The conductive layer M5 is, for example, disposed on the insulating layer IL6, and may be electrically connected to the conductive layer M4, for example, through a through hole TH8 penetrating the insulating layer IL6. In some embodiments, the storage capacitor Cst at least partially overlaps with the conductive layer M5 in the normal direction Z of the substrate SB. In the present embodiment, the storage capacitor Cst completely overlaps with the conductive layer M5 in the normal direction Z of the substrate SB.

[0114] Based on this, the conductive layer M5 can shield the storage capacitor Cst formed during the formation of the electronic device 40d together with the conductive layer M4, thereby reducing the possibility of defects in the storage capacitor Cst.

[0115] Please refer to Figure 4E The main difference between the electronic device 40e of this embodiment and the aforementioned electronic device 40c is that the electronic device 40e includes a conductive layer M5 but does not include a conductive layer M0.

[0116] The conductive layer M5 is, for example, disposed on the insulating layer IL6. In some embodiments, the storage capacitor Cst at least partially overlaps with the conductive layer M5 in the normal direction Z of the substrate SB. In this embodiment, the storage capacitor Cst completely overlaps with the conductive layer M5 in the normal direction Z of the substrate SB. In some embodiments, the conductive layer M5 is floating, but the present disclosure is not limited thereto.

[0117] In this embodiment, the electronic device 40e further includes an insulating layer IL7. The insulating layer IL7 is, for example, disposed on the conductive layer M5 and can cover the conductive layer M5. The material of the insulating layer IL7 can be, for example, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), but the present disclosure is not limited thereto.

[0118] Based on this, the conductive layer M5 can shield the storage capacitor Cst that has been formed during the formation of the electronic device 40e, thereby reducing the possibility of defects in the storage capacitor Cst.

[0119] Figure 5A FIG. 1 is a partial cross-sectional diagram of the arrangement relationship between the signal line and the conductive layer in the electronic device of the first embodiment of the present disclosure. Figure 5B FIG. 1 is a partial cross-sectional diagram of the arrangement relationship between the signal line and the conductive layer in the electronic device of the second embodiment of the present disclosure. Figure 5C FIG. 1 is a partial cross-sectional diagram of the arrangement relationship between the signal line and the conductive layer in the electronic device of the third embodiment of the present disclosure. Figure 5D is a partial cross-sectional schematic diagram of the arrangement relationship between the signal line and the conductive layer in the electronic device of the fourth embodiment of the present disclosure, and Figure 5EThis is a partial cross-sectional diagram of the arrangement relationship between the signal line and the conductive layer in the electronic device of the fifth embodiment of the present disclosure. It should be noted that: FIG. 5A to FIG. 5E The embodiments can be used Figure 2A as well as Figure 2B The component numbers and partial contents of the embodiments are shown in the figure, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted.

[0120] Please refer to Figure 5A The electronic device 50a of this embodiment shows that the signal line SI may include a signal line formed by the signal line SI1 included in the conductive layer M1, the signal line SI2 included in the conductive layer M2 and / or the signal line SI3 included in the conductive layer M3, but the present disclosure is not limited thereto. In addition, the signal line SI may include the above-mentioned scan line SL, the data line DL' and / or other suitable signal lines, but the present disclosure is not limited thereto.

[0121] The signal line SI may, for example, at least partially overlap with the conductive layer M4 in the normal direction Z of the substrate SB. In the present embodiment, the signal line SI completely overlaps with the conductive layer M4 in the normal direction Z of the substrate SB.

[0122] Based on this, the conductive layer M4 can shield the signal line SI that has been formed during the formation of the electronic device 50a, so as to reduce the possibility of defects in the signal line SI.

[0123] Please refer to Figure 5B The main difference between the electronic device 50b of this embodiment and the aforementioned electronic device 50a is that the electronic device 50b further includes an insulating layer IL0 and a conductive layer M0. In some embodiments, the signal line SI may at least partially overlap with the conductive layer M0 in the normal direction Z of the substrate SB. In this embodiment, the signal line SI completely overlaps with the conductive layer M0 in the normal direction Z of the substrate SB. Figure 3B The insulating layer IL0 and the conductive layer M0 in the illustrated embodiment are the same or similar and are not described in detail herein.

[0124] Based on this, the conductive layer M0 and the conductive layer M4 can shield the signal line SI formed during the formation of the electronic device 50b to further reduce the possibility of defects in the signal line SI.

[0125] Please refer to Figure 5C The main difference between the electronic device 50c of this embodiment and the aforementioned electronic device 50b is that the signal line SI of the electronic device 50c completely overlaps with the conductive layer M0 in the normal direction Z of the substrate SB, but does not overlap with the conductive layer M4.

[0126] Based on this, the conductive layer M0 can shield the signal line SI that has been formed during the formation of the electronic device 50c, so as to reduce the possibility of defects in the signal line SI.

[0127] Please refer to Figure 5D The main difference between the electronic device 50d of this embodiment and the aforementioned electronic device 50a is that the electronic device 50d further includes a conductive layer M5.

[0128] The conductive layer M5 is, for example, disposed on the insulating layer IL6, and may be electrically connected to the conductive layer M4, for example, through a through hole TH8 penetrating the insulating layer IL6. In some embodiments, the signal line SI at least partially overlaps with the conductive layer M5 in the normal direction Z of the substrate SB. In the present embodiment, the signal line SI completely overlaps with the conductive layer M5 in the normal direction Z of the substrate SB.

[0129] Based on this, the conductive layer M5 can shield the signal line SI formed during the formation of the electronic device 50d together with the conductive layer M4, thereby reducing the possibility of defects in the signal line SI.

[0130] Please refer to Figure 5E The main difference between the electronic device 50e of this embodiment and the aforementioned electronic device 50c is that the electronic device 50e includes a conductive layer M5 but does not include a conductive layer M0.

[0131] The conductive layer M5 is, for example, disposed on the insulating layer IL6. In some embodiments, the signal line SI at least partially overlaps with the conductive layer M5 in the normal direction Z of the substrate SB. In the present embodiment, the signal line SI completely overlaps with the conductive layer M5 in the normal direction Z of the substrate SB. In some embodiments, the conductive layer M5 is floating, but the present disclosure is not limited thereto.

[0132] In this embodiment, the electronic device 50e further includes an insulating layer IL7. The insulating layer IL7 is, for example, disposed on the conductive layer M5 and can cover the conductive layer M5. The material of the insulating layer IL7 can be, for example, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), but the present disclosure is not limited thereto.

[0133] Based on this, the conductive layer M5 can shield the signal line SI formed during the formation of the electronic device 50e, reducing the possibility of defects in the signal line SI. It is worth noting that in the present disclosure, the conductive layer used to shield the semiconductor layer, storage capacitor and signal line in the electronic device is located at a different layer from the semiconductor layer, storage capacitor and signal line in the electronic device.

[0134] In summary, the electronic devices provided by some embodiments of the present disclosure make the ratio of the first area of ​​the conductive layer arranged in the pixel area to the second area of ​​the pixel area greater than or equal to 50% and less than or equal to 100%, so that the components formed in the pixel area (such as the first semiconductor layer, the second semiconductor layer, the storage capacitor and / or the signal line or other suitable components) can be at least partially shielded by the conductive layer when the process of forming the remaining components is carried out, thereby reducing the possibility of defects. Therefore, the electronic devices provided by some embodiments of the present disclosure can have a higher yield.

[0135] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An electronic device, characterized in that: include: substrate; A first light emitting unit and a second light emitting unit are disposed on the substrate; A first driving circuit, disposed on the substrate and comprising a first transistor, wherein the first transistor is used to drive the first light-emitting unit; A second driving circuit, disposed on the substrate and comprising a second transistor, wherein the second transistor is used to drive the second light emitting unit; as well as a conductive layer, disposed between the substrate and the first light-emitting unit and between the substrate and the second light-emitting unit, and comprising a first portion and a second portion connected to the first portion, The first transistor includes a first semiconductor layer, the second transistor includes a second semiconductor layer, and in the normal direction of the substrate, the first portion at least partially overlaps the first semiconductor layer, and the second portion at least partially overlaps the second semiconductor layer.

2. The electronic device according to claim 1, characterized in that: In the normal direction of the substrate, the first semiconductor layer completely overlaps with the first portion.

3. The electronic device according to claim 1, characterized in that: In the normal direction of the substrate, the second semiconductor layer completely overlaps with the second portion.

4. The electronic device according to claim 1, characterized in that: In the normal direction of the substrate, the conductive layer is located between the first semiconductor layer and the substrate.

5. The electronic device according to claim 1, characterized in that: In the normal direction of the substrate, the conductive layer is located between the first semiconductor layer and the first light emitting unit.

6. The electronic device according to claim 1, characterized in that: At least one of the first driving circuit and the second driving circuit includes a capacitor, the conductive layer further includes a third portion, and in the normal direction of the substrate, the third portion at least partially overlaps with the capacitor.

7. An electronic device, characterized in that: include: a substrate including a plurality of pixel regions; A first light emitting unit is disposed on the substrate, wherein the first light emitting unit is located in one of the plurality of pixel regions; a first driving circuit, disposed on the substrate, for driving the first light emitting unit, wherein the first driving circuit is located in the one of the plurality of pixel regions; as well as a conductive layer disposed between the substrate and the first light-emitting unit, and at least a portion of the conductive layer is located in one of the plurality of pixel regions, In the top view of the electronic device, at least a portion of the conductive layer located within one of the plurality of pixel regions has a first area, and a ratio of the first area to a second area of ​​the pixel region is greater than or equal to 50% and less than or equal to 100%.

8. The electronic device according to claim 7, characterized in that: The first driving circuit includes a first transistor, the first transistor includes a first semiconductor layer, and in a normal direction of the substrate, the conductive layer at least partially overlaps with the first semiconductor layer.

9. The electronic device according to claim 7, characterized in that: The first driving circuit includes a first transistor, the first transistor includes a first semiconductor layer, and in a normal direction of the substrate, the conductive layer is located between the first semiconductor layer and the substrate.

10. The electronic device according to claim 7, characterized in that: The first driving circuit includes a first transistor, the first transistor includes a first semiconductor layer, and in the normal direction of the substrate, the conductive layer is located between the first semiconductor layer and the first light emitting unit.

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