Selective covering of contact layer for CMOS device

Abstract

A method of forming an electrical contact in a semiconductor structure includes performing a patterning process to form a hardmask on the semiconductor structure, the semiconductor structure includes a first semiconductor region, a second semiconductor region, a dielectric layer having a first opening over the first semiconductor region and a second opening over the second semiconductor region, where the hardmask covers an exposed surface of the first semiconductor region within the first opening, a first selective deposition process is performed to form a contact layer on an exposed surface of the second semiconductor region within the second opening, and a second selective deposition process is performed to form a capping layer on the contact layer.

Description

background Technical Field

[0002] Embodiments described herein relate generally to semiconductor device fabrication, and more particularly to systems and methods for forming contacts within semiconductor structures. Background Art

[0003] Multi-gate metal-oxide-semiconductor field-effect transistors (MOSFETs) (e.g., complementary metal-oxide semiconductor (CMOS) devices) present challenges in terms of manufacturability due to their three-dimensional (3D) design and small size. In advanced CMOS devices, an epitaxial layer of silicon-containing material (e.g., boron-doped p-type silicon germanium or phosphorus-doped n-type silicon) formed at the bottom of the trench contact is often used to reduce the contact resistivity to 10 -9 Ω·cm 2 range, and achieve the performance required for advanced CMOS technology. Typically, the p-type epitaxial layer is formed of silicon germanium (SiGe) with a high germanium (Ge) concentration, such as a concentration between about 60% and about 80%, or in some cases 100%, in order to minimize contact resistance. However, the silicon germanium (SiGe) epitaxial layer with a high germanium (Ge) concentration is sensitive to oxidation and is also sensitive to wet etching chemistry, and therefore can be removed in a subsequent process step.

[0004] Therefore, there is a need for methods and systems that can form a capping material to protect a silicon germanium (SiGe) epitaxial layer having a high germanium (Ge) concentration from oxidation and contamination. Summary of the invention

[0005] Embodiments of the present disclosure provide a method for forming an electrical contact in a semiconductor structure. The method includes performing a patterning process to form a hard mask on a semiconductor structure, the semiconductor structure including a first semiconductor region, a second semiconductor region, a dielectric layer having a first opening above the first semiconductor region and a second opening above the second semiconductor region, wherein the hard mask covers an exposed surface of the first semiconductor region within the first opening, performing a first selective deposition process to form a contact layer on an exposed surface of the second semiconductor region within the second opening, and performing a second selective deposition process to form a capping layer on the contact layer.

[0006] The embodiments of the present disclosure also provide a method for forming an electrical contact in a semiconductor structure. The method includes performing a pre-cleaning process on an exposed surface of a semiconductor structure, the semiconductor structure including a first semiconductor region, a second semiconductor region, a dielectric layer having a first opening above the first semiconductor region and a second opening above the second semiconductor region, wherein the exposed surface of the semiconductor structure is arranged on the first semiconductor region in the first opening and on the second semiconductor region in the second opening, performing a patterning process to form a hard mask on the exposed surface of the first semiconductor region in the first opening, performing an etching process to form a groove at the exposed surface of the second semiconductor region, performing a first selective deposition process to form a contact layer on the exposed surface of the second semiconductor region in the second opening, performing a second selective deposition process to form a capping layer on the contact layer, performing a removal process to remove the hard mask, performing a third selective deposition process to form a metal layer on the exposed surface of the first semiconductor region and the capping layer, and performing a metal filling process to form a first contact plug in the first opening and a second contact plug in the second opening, wherein the first selective deposition process and the second selective deposition process are performed without destroying a vacuum environment.

[0007] An embodiment of the present disclosure also provides a processing system. The processing system includes a first processing chamber, a second processing chamber, a third processing chamber, and a system controller, wherein the system controller is configured to cause the processing system to perform a patterning process in the first processing chamber to form a hard mask on a semiconductor structure, the semiconductor structure including a first semiconductor region, a second semiconductor region, and a dielectric layer having a first opening above the first semiconductor region and a second opening above the second semiconductor region, wherein the hard mask covers an exposed surface of the first semiconductor region in the first opening, perform a first selective deposition process in the second processing chamber to form a contact layer on an exposed surface of the second semiconductor region in the second opening, and perform a second selective deposition process in the third processing chamber to form a capping layer on the contact layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to be able to understand in detail the manner in which the above-mentioned features of the present disclosure are achieved, a more specific description of the present disclosure briefly summarized above may be made by reference to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only typical embodiments of the present disclosure and are therefore not to be considered as limiting the scope of the present disclosure, as the present disclosure may admit of other equally effective embodiments.

[0009] Figure 1 is a schematic top view of a multi-chamber processing system according to one or more embodiments of the present disclosure.

[0010] Figure 2A is a cross-sectional view of a processing chamber according to one or more embodiments.

[0011] Figure 2B yes Figure 2A An enlarged view of a portion of a processing chamber.

[0012] Figure 3 is a cross-sectional view of a processing chamber according to one or more embodiments.

[0013] Figure 4 A process flow diagram depicting a method of forming a contact layer in a semiconductor structure according to one or more embodiments of the present disclosure.

[0014] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Fig. 5F , Figure 5G and Figure 5H is corresponding to Figure 4 A cross-sectional view of a portion of a semiconductor structure at various states of the method.

[0015] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation. DETAILED DESCRIPTION

[0016] Embodiments described herein provide methods and systems for forming contacts that include an epitaxial layer of a silicon-containing material (e.g., boron-doped p-type silicon germanium or phosphorus-doped n-type silicon) at selected portions of a structure used to form a CMOS device (e.g., on an exposed surface of a silicon layer or silicon germanium layer). The methods and systems may be particularly useful for selectively forming an epitaxial layer including silicon germanium on an exposed surface of a silicon germanium material within an opening or feature (e.g., a contact trench) formed in a dielectric layer in a semiconductor structure having a region including silicon, a region including silicon germanium, and a dielectric layer formed over these regions. The processes described herein are configured to form a capping layer to protect contacts formed in a semiconductor structure from oxidation and contamination.

[0017] Figure 11 is a schematic top view of a multi-chamber processing system 100 according to one or more embodiments of the present disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 with corresponding transfer robots 112, 114, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130. As described in detail herein, substrates in the processing system 100 can be processed in various chambers and transferred between various chambers without exposing the substrates to an ambient environment external to the processing system 100 (e.g., such as the ambient atmosphere that may exist in a wafer fab). For example, in various processes performed on substrates in the processing system 100, substrates can be processed in various chambers maintained in a low pressure (e.g., less than or equal to about 300 Torr) or vacuum environment and transferred between the various chambers without breaking the low pressure or vacuum environment. Accordingly, the processing system 100 may provide an integrated solution for some processing of a substrate.

[0018] Examples of processing systems that may be appropriately modified according to the teachings provided herein include or An integrated processing system or other suitable processing system is commercially available from Applied Materials, Inc. located in Santa Clara, Calif. It is contemplated that other processing systems, including processing systems from other manufacturers, may be adapted to benefit from the aspects described herein.

[0019] In such Figure 1 In the example shown, the factory interface 102 includes a docking station 132 and a factory interface robot 134 to facilitate the transfer of substrates. The docking station 132 is adapted to receive one or more front opening unified pods (FOUPs) 136. In some examples, each factory interface robot 134 generally includes a blade 138 disposed on one end of the corresponding factory interface robot 134, and the blade 138 is adapted to transfer the substrate from the factory interface 102 to the load lock chamber 104, 106.

[0020] The load lock chambers 104, 106 have respective ports 140, 142 coupled to the factory interface 102 and respective ports 144, 146 coupled to the transfer chamber 108. The transfer chamber 108 also has respective ports 148, 150 coupled to the holding chambers 116, 118, and respective ports 152, 154 coupled to the processing chambers 120, 122. Similarly, the transfer chamber 110 has respective ports 156, 158 coupled to the holding chambers 116, 118, and respective ports 160, 162, 164, 166 coupled to the processing chambers 124, 126, 128, 130. The ports 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, 166 may be, for example, slit valve openings with slit valves for passing substrates through the slit valve openings by the transfer robots 112, 114 and for providing a seal between the respective chambers to prevent gas from passing between the respective chambers. In general, any port may be opened for transferring a substrate through the port. Otherwise, the port is closed.

[0021] The load lock chambers 104, 106, the transfer chambers 108, 110, the holding chambers 116, 118, and the processing chambers 120, 122, 124, 126, 128, 130 may be fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system may include one or more gas pumps (e.g., turbo pumps, cryopumps, roughing pumps), gas sources, various valves, and conduits that are fluidly connected to the various chambers. In operation, the factory interface robot 134 transfers the substrate from the FOUP 136 to the load lock chamber 104 or 106 via the port 140 or 142. The gas and pressure control system then pumps down the load lock chamber 104 or 106. The gas and pressure control system further maintains the transfer chambers 108, 110 and the holding chambers 116, 118 with an internal low pressure or vacuum environment (the environment may include an inert gas). Thus, evacuation of the load lock chamber 104 or 106 facilitates the passage of substrates between, for example, the atmospheric environment of the factory interface 102 and the low pressure or vacuum environment of the transfer chamber 108 .

[0022] With the substrate in the already evacuated load lock chamber 104 or 106, the transfer robot 112 transfers the substrate from the load lock chamber 104 or 106 into the transfer chamber 108 via the port 144 or 146. The transfer robot 112 can then transfer the substrate to the processing chambers 120, 122 via the respective ports 152, 154 for processing, and to the holding chambers 116, 118 via the respective ports 148, 150 for holding awaiting further transfer, and / or transfer the substrate between any of these chambers. Similarly, the transfer robot 114 can access substrates in the holding chamber 116 or 118 via the port 156 or 158, and can transfer substrates to the processing chambers 124, 126, 128, 130 for processing via the corresponding ports 160, 162, 164, 166, and to the holding chambers 116, 118 via the respective ports 156, 158 for holding pending further transfer, and / or transfer substrates between any of these chambers. The substrates can be transferred and held within and between the various chambers in a low pressure or vacuum environment provided by the gas and pressure control system.

[0023] The processing chambers 120, 122, 124, 126, 128, 130 may be any suitable chamber for processing a substrate. In some examples, the processing chamber 120 may be capable of performing an etching process, the processing chamber 122 may be capable of performing a cleaning process, the processing chamber 124 may be capable of performing a selective removal process, and the processing chambers 126, 128, 130 may be capable of performing a corresponding epitaxial growth process. The processing chamber 120 may be a Selectra available from Applied Materials, Inc. of Santa Clara, California. TM Etch chamber. The processing chamber 122 may be a SiCoNi etch chamber available from Applied Materials, Inc. of Santa Clara, California. TM The processing chamber 126, 128, or 130 may be a Centura 1000 available from Applied Materials, Inc. of Santa Clara, California. TM Epitaxial chamber.

[0024] A system controller 168 is coupled to the processing system 100 for controlling the processing system 100 or controlling components of the processing system 100. For example, the system controller 168 may control the operation of the processing system 100 using direct control of the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130 of the processing system 100 or by controlling controllers associated with the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130. In operation, the system controller 168 enables data collection and feedback from the respective chambers to coordinate the execution of the processing system 100.

[0025] The system controller 168 generally includes a central processing unit (CPU) 170, a memory 172, and support circuits 174. The CPU 170 may be one of any form of general purpose processor that may be used in an industrial environment. The memory 172 or non-transitory computer readable medium may be accessed by the CPU 170 and may be one or more of a random access memory (RAM), a read only memory (ROM), a floppy disk, a hard disk, or any other form of digital storage, local or remote. The support circuits 174 are coupled to the CPU 170 and may include caches, clock circuits, input / output subsystems, power supplies, and the like. The various methods disclosed herein may generally be implemented under the control of the CPU 170 by the CPU 170 executing computer instruction codes stored in the memory 172 (or in the memory of a particular processing chamber) as, for example, software routines. When the computer instruction codes are executed by the CPU 170, the CPU 170 controls the chamber to perform processes according to the various methods.

[0026] Other processing systems may employ other configurations. For example, more or fewer processing chambers may be coupled to the transfer device. In the example shown, the transfer device includes transfer chambers 108, 110 and holding chambers 116, 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as a transfer device in a processing system.

[0027] Figure 2A is a cross-sectional view of a processing chamber 200 adapted to perform a pre-cleaning process as described in detail below, according to one or more embodiments. The processing chamber 200 may be Figure 1 The processing chamber 122 is shown in FIG. Figure 2B yes Figure 2AAn enlarged view of a portion of the processing chamber 200 is shown.

[0028] The processing chamber 200 can be particularly useful for performing thermal or plasma-based cleaning processes and / or plasma-assisted dry etching processes. The processing chamber 200 includes a chamber body 202, a lid assembly 204, and a support assembly 206. The lid assembly 204 is disposed at an upper end of the chamber body 202, and the support assembly 206 is at least partially disposed within the chamber body 202. A vacuum system can be used to remove gases from the processing chamber 200. The vacuum system includes a vacuum pump 208, which is coupled to a vacuum port 210 disposed in the chamber body 202. The processing chamber 200 also includes a controller 212 for controlling processes within the processing chamber 200.

[0029] The lid assembly 204 includes a stack of components adapted to provide a precursor gas and / or plasma to a processing region 214 within the processing chamber 200. A first plate 216 is coupled to a second plate 218. A third plate 220 is coupled to the second plate 218. The lid assembly 204 can be connected to a power source (not shown) for supplying plasma to a cone-shaped chamber 222 formed in the lid assembly 204. The lid assembly 204 can also be connected to a remote plasma source 224 that generates plasma upstream of the lid stack. The remote plasma chamber (e.g., Figure 2A to Figure 2B The processing region 214, the first plate 216 and the second plate 218 in the processing chamber 200 are coupled to the gas source 226 via the remote plasma source 224 (or in the absence of the remote plasma source 224, the gas source 226 is directly coupled to the lid assembly 204). The gas source 226 may include a gas source adapted to provide helium, argon or other inert gas. In some configurations, the gas provided by the gas source 226 can be excited into a plasma, which is provided to the lid assembly 204 using the remote plasma source 224. In alternative embodiments, the gas source 226 can provide a process gas, which can be activated by the remote plasma source 224 before being introduced to a surface of a substrate disposed within the processing chamber 200. Referring to Figure 2B The tapered chamber 222 has an opening 228 that allows the formed plasma to flow from the remote plasma source 224 to a volume 230 formed in a fourth plate 232 of the lid assembly 204 .

[0030] In some configurations of the lid assembly 204, plasma is generated within the conical chamber 222 by applying energy delivered from a plasma source. In one example, energy may be provided by biasing the lid assembly 204 to capacitively couple RF, VHF, and / or UHF energy to the gas located in the conical chamber 222. In this configuration of the lid assembly 204, the remote plasma source 224 may not be used or may not be mounted within the lid assembly 204.

[0031] The central conduit 234 formed in the fourth plate 232 is adapted to provide the plasma generated species provided from the volume 230 to the mixing chamber 238 formed in the sixth plate 240 of the lid assembly 204 via the fifth plate 236. The central conduit 234 communicates with the mixing chamber 238 via an opening 242 in the fifth plate 236. The opening 242 may have a diameter that is smaller than, larger than, or the same as the diameter of the central conduit 234. Figure 2B In the embodiment of the present invention, the opening 242 has the same diameter as the central conduit 234.

[0032] The fourth plate 232 also includes inlets 244 and 246 adapted to provide gas to the mixing chamber 238. The inlet 244 is coupled to a first gas source 248, and the inlet 246 is coupled to a second gas source 250. The first gas source 248 and the second gas source 250 may include a process gas and an inert gas used as a carrier gas, such as an inert gas such as argon and / or helium. The first gas source 248 may include ammonia (NH3) and argon (Ar). The second gas source 250 may contain a fluorine-containing gas, a hydrogen-containing gas, or a combination of the above gases. In one example, the second gas source 250 may contain hydrogen fluoride (HF) and argon (Ar).

[0033] like Figure 2BAs shown in FIG. 1 , in some configurations, the inlet 244 is coupled to the mixing chamber 238 via a cylindrical passage 252 (shown in phantom) and a hole 254 formed in the fifth plate 236. The inlet 246 is coupled to the mixing chamber 238 via a cylindrical passage 256 (shown in phantom) and a hole 258 formed in the fifth plate 236. The size of the holes 254, 258 formed in the fifth plate 236 is generally such that they enable uniform flow of gas provided from their respective gas sources 248, 250 into the mixing chamber 238. In one configuration, the hole 258 has a diameter that is less than the width of the opening defined by the opposing sidewalls of the cylindrical passage 256 formed in the fourth plate 232. The holes 258 are typically distributed circumferentially around the centerline of the cylindrical passage 256 to provide uniform fluid flow into the mixing chamber 238. In one configuration, the holes 254 have a diameter that is smaller than the width of the opening defined by the opposing sidewalls of the cylindrical passage 252 formed in the fourth plate 232. The holes 254 are generally distributed circumferentially around the centerline of the cylindrical passage 252 to provide uniform fluid flow into the mixing chamber 238.

[0034] Inlets 244 and 246 provide respective fluid flow paths that traverse transversely through fourth plate 232, turn and penetrate fifth plate 236 to reach mixing chamber 238. Cover assembly 204 also includes a seventh plate or first gas distributor 260, which may be a gas distribution plate, such as a showerhead, wherein the various gases mixed in cover assembly 204 flow through perforations 262 formed in seventh plate or first gas distributor 260. Perforations 262 are in fluid communication with mixing chamber 238 to provide a flow path from mixing chamber 238 through first gas distributor 260. Back Figure 2A A blocker plate 264 and a gas distribution plate, such as a second gas distributor 266 , are disposed below the cover assembly 204 . The second gas distributor 266 may be a gas distribution plate, such as a showerhead.

[0035] Alternatively, a different cleaning process may be used to clean the substrate surface. For example, a remote plasma containing helium (He) and ammonia (NH3) may be introduced into the processing chamber 200 via the lid assembly 204, while ammonia (NH3) may be directly injected into the processing chamber 200 via a separate gas inlet 268 disposed at a side of the chamber body 202 and coupled to a gas source (not shown).

[0036] The support assembly 206 may include a substrate support 270 to support a substrate 272 thereon during processing. The substrate support 270 may be coupled to an actuator 274 via a shaft 276 that extends through a centrally located opening formed in the bottom of the chamber body 202. The actuator 274 may be flexibly sealed to the chamber body 202 via a bellows (not shown) that prevents vacuum leakage around the shaft 276. The actuator 274 allows the substrate support 270 to move vertically within the chamber body 202 between a processing position and a loading position. The loading position is slightly below the opening of a channel (not shown) formed in the sidewall of the chamber body 202.

[0037] The substrate support 270 has a flat or substantially flat substrate support surface for supporting a substrate 272 to be processed on the substrate support surface. The substrate support 270 can be moved vertically within the chamber body 202 by an actuator 274, which is coupled to the substrate support 270 by a shaft 276. For some process operations, the substrate support 270 can be raised to a position adjacent to the lid assembly 204 to control the temperature of the substrate 272 being processed. As such, the substrate 272 can be heated via radiation emitted from the second gas distributor 266 or another radiation source, or by convection or conduction through the intermediate gas from the second gas distributor 266. In some process steps, the substrate can be placed on lift pins 278 to perform additional thermal processing operations, such as performing an annealing step.

[0038] Figure 3 is a cross-sectional view of a processing chamber 300 adapted to perform an epitaxial (Epi) deposition process as described below, according to one or more embodiments. The processing chamber 300 may be as follows: Figure 1 The processing chamber 126, 128 or 130 shown in FIG.

[0039] The processing chamber 300 includes a housing structure 302 made of a process resistant material, such as aluminum or stainless steel, such as 316L stainless steel. The housing structure 302 surrounds various functional elements of the processing chamber 300, such as a quartz chamber 304, which includes an upper quartz chamber 306 and a lower quartz chamber 308, containing a processing volume 310. Reactive species are provided to the quartz chamber 304 through a gas distribution assembly 312, and processing byproducts are removed from the processing volume 310 through an outlet port 314, which is typically connected to a vacuum source (not shown).

[0040] The substrate support 316 is adapted to receive a substrate 318 that is transferred to the processing volume 310. The substrate support 316 is disposed along a longitudinal axis 320 of the processing chamber 300. The substrate support 316 may be made of a ceramic material or a graphite material coated with a silicon material (e.g., silicon carbide) or other process resistant material. Reactive species from the precursor reactant material are applied to a surface 322 of the substrate 318, and byproducts may subsequently be removed from the surface 322 of the substrate 318. Heating of the substrate 318 and / or the processing volume 310 may be provided by a radiation source (e.g., an upper lamp module 324A and a lower lamp module 324B).

[0041] In one embodiment, the upper lamp module 324A and the lower lamp module 324B are infrared (IR) lamps. Non-thermal energy or radiation from the lamp modules 324A and 324B travels through the upper quartz window 326 of the upper quartz chamber 306 and through the lower quartz window 328 of the lower quartz chamber 308. If necessary, cooling gas for the upper quartz chamber 306 enters via the inlet 330 and exits via the outlet 332. Precursor reactant materials and diluent, purification and exhaust gases for the processing chamber 300 enter via the gas distribution assembly 312 and exit via the outlet port 314. Although the upper quartz window 326 is shown as curved or convex, the upper quartz window 326 can be flat or concave because the pressure on both sides of the upper quartz window 326 is substantially the same (i.e., atmospheric pressure).

[0042] Low wavelength radiation in the processing volume 310 is used to excite reactive species and assist in adsorption of reactants and desorption of process byproducts from the surface 322 of the substrate 318, and the low wavelength radiation is typically in the range of about 0.8 μm to about 1.2 μm, for example, about 0.95 μm to about 1.05 μm, with various wavelength combinations provided depending on, for example, the composition of the film being epitaxially grown.

[0043] Component gases enter the processing volume 310 via a gas distribution assembly 312. Gases flow from the gas distribution assembly 312 and exit via an outlet port 314, as generally indicated by a flow path 334. The combination of component gases used to clean / passivate the substrate surface or to form a silicon-containing and / or germanium-containing film being epitaxially grown is typically mixed before entering the processing volume 310. The total pressure in the processing volume 310 can be adjusted via a valve (not shown) on the outlet port 314. At least a portion of the interior surface of the processing volume 310 is covered by a liner 336. In one embodiment, the liner 336 comprises an opaque quartz material. In this way, the chamber wall is insulated from the heat in the processing volume 310.

[0044] The surface temperature in the processing volume 310 can be controlled within a temperature range of about 200° C. to about 600° C. or more by the flow of cooling gas entering through inlet 330 and exiting through outlet 332 in combination with radiation from an upper lamp module 324A positioned above the upper quartz window 326. The temperature in the lower quartz chamber 308 can be controlled within a temperature range of about 200° C. to about 600° C. or more by adjusting the speed of a blower unit, not shown, and by radiation from a lower lamp module 324B disposed below the lower quartz chamber 308. The pressure in the processing volume 310 can be between about 0.1 Torr and about 600 Torr, for example, between about 5 Torr and about 30 Torr.

[0045] The temperature at the surface 322 of the substrate 318 can be controlled by adjusting the power of the lower lamp module 324B in the lower quartz chamber 308, or by adjusting the power of both the upper lamp module 324A overlying the upper quartz window 326 and the lower lamp module 324B in the lower quartz chamber 308. The power density in the processing volume 310 can be controlled at about 40 W / cm 2 To about 400W / cm 2 Between, for example, about 80W / cm 2 To about 120W / cm 2 .

[0046] In one aspect, the gas distribution assembly 312 is disposed perpendicular to or relative to the longitudinal axis 320 of the processing chamber 300 or substrate 318 in a radial direction 338. In this orientation, the gas distribution assembly 312 is adapted to flow the process gas across or parallel to the surface 322 of the substrate 318 in the radial direction 338. In one processing application, the process gas is preheated at the point of introduction into the processing chamber 300 to initiate preheating of the gas prior to introduction into the processing volume 310, and / or to break specific bonds in the gas. In this manner, the surface reaction kinetics may be modified independent of the thermal temperature of the substrate 318.

[0047] In operation, precursors for forming blanket or selective epitaxial films of silicon (Si) and silicon germanium (SiGe) are provided to the gas distribution assembly 312 from one or more gas sources 340A and 340B. IR lamp 342 ( Figure 3334) can be used to heat precursors within the gas distribution assembly 312 and along the flow path 334. The gas sources 340A, 340B can be coupled to the gas distribution assembly 312 in a manner adapted to facilitate introduction into zones within the gas distribution assembly 312, such as radially outer regions and radially inner regions between the outer regions when viewed inwardly from a top plan view. The gas sources 340A, 340B can include valves (not shown) to control the rate of introduction into the zones.

[0048] Gas sources 340A, 340B may include silicon precursors, such as silane, including silane (SiH4), disilane (Si2H6), dichlorosilane (SiH2Cl2), hexachlorodisilane (Si2Cl6), dibromosilane (SiH2Br2), higher-order silanes, derivatives of the above items, and combinations of the above items. Gas sources 340A, 340B may also include germanium-containing precursors, such as germanium (GeH4), digermane (Ge2H6), germanium tetrachloride (GeCl4), dichlorogermane (GeH2Cl2), derivatives of the above items, and combinations of the above items. Precursors containing silicon and / or germanium may be used in combination with hydrogen chloride (HCl), chlorine (Cl2), hydrogen bromide (HBr), and combinations of the above items. Gas sources 340A, 340B may include one or more of silicon- and germanium-containing precursors in one or both of gas sources 340A, 340B.

[0049] The precursor material in this excited state passes through the opening or hole 344 ( Figure 3 In one embodiment, a perforated plate 346 is a quartz material having holes 344 formed through the perforated plate 346. The perforated plate 346 is transparent to IR energy and can be made of a clear quartz material. In other embodiments, the perforated plate 346 can be any material that is transparent to IR energy and resistant to process chemicals and other processing chemicals. The excited precursor material passes through the holes 344 in the perforated plate 346 and through the channel 348 ( Figure 3 310. A portion of the photons and non-thermal energy from the IR lamp 342 also passes through the holes 344, the perforated plate 346, and the channel 348, which is provided by the reflective material and / or surface on the inner surface of the gas distribution assembly 312, thereby irradiating the flow path 334 of the precursor material. In this way, the vibration energy of the precursor material can be maintained along the flow path from the point of introduction into the processing volume 310.

[0050] Figure 4 A process flow diagram depicts a method 400 of forming a contact layer in a semiconductor structure 500 according to a first embodiment of the present disclosure. Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Fig. 5F , Figure 5G and Figure 5H is a cross-sectional view of a portion of a semiconductor structure 500 corresponding to various states of method 400. It should be understood that Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Fig. 5F , Figure 5G and Figure 5H Only a partial schematic diagram of semiconductor structure 500 is shown, and semiconductor structure 500 may contain any number of transistor segments and additional materials having the aspects shown in the figure. It should also be noted that although described in order Figure 4 Other process sequences that do not conform to the methods shown in , but include one or more operations that have been omitted and / or added, and / or have been rearranged in another desired order, fall within the scope of embodiments of the present disclosure provided herein.

[0051] Reference Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Fig. 5F , Figure 5G and Figure 5H , the semiconductor structure 500 may include a first transistor device 502 and a second transistor device 504 formed on a substrate (not shown).

[0052] The term "substrate" as used herein refers to a layer of material used as a basis for subsequent processing operations and includes the surface to be cleaned. The substrate may be a silicon-based material or any suitable insulating or conductive material as desired. The substrate may include materials such as crystalline silicon (e.g., Si <100> or Si <111> ), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or unpatterned wafers, silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass or sapphire materials.

[0053] like Figure 5AAs shown in , a portion of a first transistor device 502 of a plurality of first transistor devices formed on a substrate includes a first semiconductor region 506 formed of a first material. A portion of a second transistor device 504 of a plurality of second transistor devices formed on a substrate includes a second semiconductor region 508 formed of a second material. The first material and the second material include materials having different compositions, so that the second material can be selectively etched relative to the first material (i.e., the etching rate of the second material is higher than the etching rate of the first material). The etching selectivity of the second material (i.e., the ratio of the etching rate of the second material to the etching rate of the first material) is between about 10:1 and 500:1. Example combinations of the first material and the second material include silicon (Si) / silicon germanium (SiGe), germanium (Ge) / silicon germanium (SiGe), or silicon (Si) / germanium tin (GeSn), respectively.

[0054] The first semiconductor region 506 may be doped with an n-type dopant (eg, phosphorus (P), antimony (Sb)) having a relative humidity of about 10 20 cm -3 and 5×10 21 cm -3 The second semiconductor region 508 may be doped with a p-type dopant (e.g., boron (B) or gallium (Ga)) with a concentration between about 10 20 cm -3 and about 5×10 21 cm -3 , depending on the desired conduction characteristics of the second transistor device 504 .

[0055] The semiconductor structure 500 also includes a dielectric layer 510 having a first opening 512 formed over each of the first semiconductor regions 506 and a second opening 514 formed over each of the second semiconductor regions 508. The dielectric layer 510 may be formed of a dielectric material, such as silicon dioxide (SiO2) or silicon nitride (Si3N4).

[0056] The first semiconductor region 506 and the second semiconductor region 508 may be formed using any suitable deposition technique, such as epitaxial (Epi) deposition, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), and the openings 512 and 514 are formed by patterning techniques, such as lithography and etching processes.

[0057] The method 400 begins with a pre-cleaning process in block 410. The pre-cleaning process may be performed in a processing chamber, such as Figure 1 or the processing chamber 122 shown in FIG. 2 or the processing chamber 200 shown in FIG. 2 .

[0058] The pre-cleaning process is configured to remove contaminants, such as a natural oxide layer or patterning residues (e.g., fluorocarbons) formed on the exposed surface of the first semiconductor region 506 within the first opening 512 and the exposed surface of the second semiconductor region 508 within the second opening 514. The pre-cleaning process is used to prepare the exposed surface of the first semiconductor region 506 within the first opening 512 and the exposed surface of the second semiconductor region 508 within the second opening 514, and an epitaxial layer can be formed on these exposed surfaces in a subsequent epitaxial deposition process.

[0059] The pre-cleaning process may include an anisotropic remote plasma assisted dry etching process, such as a reactive ion etching (RIE) process using a plasma formed by a gas including argon (Ar), helium (He), or a combination thereof. The plasma effluent directionally bombards and removes the remaining dielectric layer within the first opening 512 and the second opening 514.

[0060] The pre-cleaning process may include an isotropic plasma etching process such as SiCoNi TM A dry chemical etching process using a plasma formed from a gas including ammonia (NH3), nitrogen trifluoride (NF3), hydrogen fluoride (HF), or a combination of the foregoing and a carrier gas such as nitrogen (N2), hydrogen (H2), or a combination of the foregoing. The dry chemical etching process is selective for oxide layers and therefore does not readily etch silicon, germanium, or nitride layers, regardless of whether these layers are amorphous, crystalline, or polycrystalline. The selectivity of the dry chemical etching process for oxide relative to silicon or germanium is at least about 3:1, and typically 5:1 or better, and sometimes 10:1. The dry chemical etching process is also highly selective for oxide relative to nitride. The selectivity of the dry chemical etching process relative to nitride is at least about 3:1, typically 5:1 or better, and sometimes 10:1.

[0061] The pre-cleaning process may include an inductively coupled plasma (ICP) etching process using a plasma formed from gases including chlorine (Cl2) and hydrogen (H2) and a carrier gas including argon (Ar) and helium (He). The ICP etching process is used to form deep ridges with smooth sidewalls in silicon.

[0062] In block 420, a patterning process is performed to form a hard mask 516 in the first opening 512 of the dielectric layer 510 above the first semiconductor region 506, thereby covering the exposed surface of the first semiconductor region 506 in the first opening 512. Figure 5B The patterning process can be performed in a processing chamber, such as Figure 1 , or 130. The patterning process may be performed using any conventional deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, and a spin coating process, and then patterned using a patterned photoresist layer (not shown) covering the hard mask 516 by a conventional photolithography process.

[0063] The hard mask 516 may be formed of tetra-ethyl-orthosilicate (TEOS) or silicon oxynitride (SiON) and have a thickness of about 500 nm and about 2 μm.

[0064] In block 430, an etching process is performed to form a groove 508A at the exposed surface of the second semiconductor region 508 within the second opening 514, such as Figure 5C The etching process may be performed in an etching chamber, such as Figure 1 The processing chamber 120 is shown in FIG.

[0065] The groove 508A may have a V-shape, a U-shape, or any other shape, and expands a contact area of ​​a contact layer to be formed between the second semiconductor region 508 and a metal contact plug to be formed within the second opening 514 to minimize parasitic resistance.

[0066] In block 440, a first selective deposition is performed to epitaxially form a contact layer 518 on the exposed surface of the second semiconductor region 508 within the trench 508A and within the second opening 514, such as Figure 5D The first selective deposition may be performed in a process chamber, such as Figure 1 The processing chamber 126, 128 or 130 shown in FIG. Figure 3 The processing chamber 300 is shown in FIG.

[0067] The contact layer 518 is formed as an interface between the second semiconductor region 508 and a metal contact plug to be formed in the second opening 514 to minimize parasitic resistance. The contact layer 518 is formed of a third material. Examples of the third material include silicon germanium (SiGe) having a germanium (Ge) ratio in a range between 20% and 100% (e.g., between about 60% and about 80%, between about 60% and about 100%, or between about 80% and about 100%). The contact layer 518 may be doped with a p-type dopant (e.g., boron (B) or gallium (Ga)) at a concentration of about 10 20 cm -3 and 5×10 21 cm -3 between 0 and 1, depending on the desired conductive properties of the contact layer 518.

[0068] In some embodiments, the first selective deposition includes an epitaxial deposition process and an etching process. The selectivity in the first selective deposition may be caused by the difference in nucleation of the third material on the second semiconductor region 508 (e.g., silicon germanium (SiGe)) and the third material on the exposed surface of the dielectric layer 510 (e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4)). When the semiconductor structure 500 is exposed to a deposition gas in a deposition process, nucleation on the second semiconductor region 508 (e.g., silicon germanium (SiGe)) may occur at a faster rate than on the exposed surface of the dielectric layer 510 (e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4)), and therefore, an epitaxial layer of the third material may be selectively formed on the exposed surface of the second semiconductor region 508 (e.g., silicon (Si) or silicon germanium (SiGe)), while an amorphous layer of the third material may be formed on the exposed surface of the dielectric layer 510 (e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4)). In a subsequent etching process, the amorphous layer of the third material formed on the exposed surface of the dielectric layer 510 may be etched by an appropriate etching gas at a faster rate than the epitaxial layer of the third material formed on the exposed surface of the second semiconductor region 508. Therefore, the overall result of the epitaxial deposition process and the etching process combination may be epitaxial growth of the third material on the exposed surface of the second semiconductor region 508 while minimizing growth (if any) of the third material on the exposed surface of the dielectric layer 510.

[0069] In some embodiments, the deposition gas includes a silicon-containing precursor, a germanium-containing precursor, and a dopant source. The silicon-containing precursor may include silane (SiH4), disilane (Si2H6), tetrasilane (Si4H 10) or a combination of the above items. The germanium-containing precursor may include germane (GeH4), germanium tetrachloride (GeCl4) and digermane (Ge2H6). Depending on the desired conductive properties of the contact layer 518, the dopant source may include, for example, boron or gallium. The dopant source may include the precursor diborane (B2H6). The etching gas includes an etchant gas and a carrier gas. The etchant gas may include a halogen-containing gas, such as hydrogen chloride (HCl), chlorine (Cl2) or hydrogen fluoride (HF). The carrier gas may include nitrogen (N2), argon (Ar), helium (He) or hydrogen (H2).

[0070] The first selective deposition may be performed at a low temperature below about 450° C. and a pressure between 5 Torr and 600 Torr.

[0071] The epitaxial deposition and etching process cycle can be repeated as needed to obtain the desired thickness of the contact layer 518. The thickness of the contact layer 518 can be about Peace between.

[0072] In block 450, a second selective deposition process is performed to form a capping layer 520 on the contact layer 518, such as Figure 5E The second selective deposition process may be performed in a processing chamber, such as Figure 1 The processing chamber 126, 128 or 130 shown in FIG. Figure 3 , or the same processing chamber used for the first selective deposition in block 440. The first selective deposition in block 440 and the second selective deposition in block 450 may be performed without breaking the vacuum environment in a multi-chamber processing system, such as Figure 1 The multi-chamber processing system 100 shown in FIG.

[0073] The capping layer 520 can protect the contact layer 518 from oxidation and contamination in the atmospheric environment during the transition from the epitaxial process to the subsequent processes (such as silicidation and patterning), while maintaining the electrical connection through the contact layer 518 and reducing the parasitic resistance. The capping layer 520 can be formed of a first metal material, such as molybdenum (Mo), ruthenium (Ru), or silicides of the above items.

[0074] In some embodiments, the second selective deposition process includes a chemical vapor deposition (CVD) process and an etching process.

[0075] In some embodiments, the deposition gas used in the deposition process includes a metal source, such as a halide precursor containing molybdenum (Mo), or an organic metal containing ruthenium (Ru) including ruthenium (Ru). The second selective deposition process can be performed at a temperature between about 240°C and about 450°C and a pressure between 3°Torr and 300°Torr. For example, during the deposition process, argon (Ar) gas can be supplied at a flow rate between about 0 sccm and about 1000 sccm, and hydrogen (H2) gas can be supplied at a flow rate between about 500 sccm and about 15000 sccm.

[0076] The cycle of the second selective deposition process may be repeated as needed to obtain a desired thickness of the capping layer 520 , for example, between about 5 and about 1000 times.

[0077] In block 460, a removal process is performed to remove the hard mask 516, such as Fig. 5F The removal process may be a suitable etching process performed in an etching chamber, such as Figure 1 The processing chamber 120 is shown in FIG.

[0078] In block 470, a third selective deposition process is performed to form a metal layer 522 on the capping layer 520, such as Figure 5G The third selective deposition process may be performed in the processing chamber, for example Figure 1 The processing chamber 126, 128 or 130 shown in FIG. Figure 3 The processing chamber 300 is shown in FIG.

[0079] The metal layer 522 contacts the capping layer 520 and provides electrical connection between the contact plug to be formed in the second opening 514 and the second semiconductor region 508 while maintaining electrical connection via the metal layer 522. The metal layer 522 may be formed of a second metal material, such as titanium (Ti), cobalt (Co), nickel (Ni), molybdenum (Mo), or tantalum (Ta), or silicides thereof.

[0080] In some embodiments, the third selective deposition process includes a deposition process, such as epitaxial deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like, and an etching process.

[0081] In some embodiments, the deposition gas used in the deposition process includes a metal source, such as a precursor containing titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), or molybdenum (Mo), or a combination thereof. The third selective deposition process can be performed at a temperature between about 300° C. and about 800° C. and a pressure between 1° Torr and 50° Torr.

[0082] In the third selective deposition process, a barrier metal layer 524 may also be formed on the exposed inner surfaces of the first opening 512 and the second opening 514 and the exposed surface of the dielectric layer 510. The barrier metal layer 524 protects the metal layer 522 and allows the contact plug to nucleate and grow in the first opening 512 and the second opening 514. The barrier metal layer 524 may be formed of a barrier metal material, which is titanium nitride (TiN) or tantalum nitride (TaN). In some embodiments, the metal layer 522 is a silicide layer formed from a portion of the barrier metal layer 524 by using a spike annealing process.

[0083] In block 480, a metal filling process is performed to form a first contact plug 526 in the first opening 512 and a second contact plug 528 in the second opening 514, as shown in FIG. Figure 5G . The first contact plug 526 and the second contact plug 528 may be formed of a contact plug metal material, such as tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo). The first contact plug 526 and the second contact plug 528 may include a metal having a desired work function. The metal filling process in block 470 may include a process such as Figure 1 A chemical vapor deposition (CVD) process using a tungsten-containing precursor such as WF6 or a cobalt-containing precursor is used in the processing chambers 126, 128, or 130 shown in FIG.

[0084] After the metal filling process, the semiconductor structure 500 may be planarized by using a chemical mechanical planarization (CMP) process.

[0085] Embodiments described herein provide methods and systems for forming a contact epitaxial layer in a trench on a selected portion of a transistor structure and forming a capping layer on the contact epitaxial layer to protect the contact epitaxial layer from oxidation and contamination. The contact trench structure includes a metal contact plug formed in a trench between adjacent device modules, and a contact that docks between the contact plug and a silicon-based channel in the device module. The contact is formed by selective deposition, reducing parasitic resistance. The metal contact plug is formed to be void-free by a deposition-etching-deposition process, reducing contact resistance. The contact epitaxial layer can be a p-type silicon germanium formed on an exposed surface of a p-type MOS device (e.g., silicon germanium), and an epitaxial layer may not be formed on an n-type MOS (e.g., silicon) or on a dielectric layer formed on a p-type MOS device and an n-type MOS device. Due to the capping layer, damage to the manufactured contact epitaxial layer is reduced.

[0086] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope of the disclosure is determined by the claims that follow.

Claims

1. A method for forming an electrical contact in a semiconductor structure, comprising the steps of: performing a patterning process to form a hard mask on a semiconductor structure, the semiconductor structure comprising a first semiconductor region, a second semiconductor region, and a dielectric layer, the dielectric layer having a first opening above the first semiconductor region and a second opening above the second semiconductor region, wherein the hard mask covers an exposed surface of the first semiconductor region within the first opening; performing a first selective deposition process to form a contact layer on the exposed surface of the second semiconductor region within the second opening; and A second selective deposition process is performed to form a capping layer on the contact layer.

2. The method of claim 1, wherein The first semiconductor region includes silicon doped with an n-type dopant, The second semiconductor region includes silicon germanium doped with a p-type dopant, and The contact layer includes silicon germanium doped with a p-type dopant.

3. The method of claim 1, wherein The capping layer includes a material selected from molybdenum silicide (Mo) and ruthenium silicide (Ru).

4. The method of claim 1, further comprising the steps of: Prior to the patterning process, a pre-cleaning process is performed on the exposed surface of the first semiconductor region within the first opening and the exposed surface of the second semiconductor region within the second opening.

5. The method of claim 1, further comprising the steps of: Before the first selective deposition process, an etching process is performed to form a groove at the exposed surface of the second semiconductor region, wherein the groove has a V-shape, a U-shape, and any other shape to expand a contact area of ​​the contact layer.

6. The method of claim 5, wherein The first selective deposition process, the second selective deposition process, and the etching process are performed without destroying a vacuum environment.

7. The method of claim 1, further comprising the steps of: After the second selective deposition process, performing a removal process to remove the hard mask; performing a third selective deposition process to form a metal layer on the exposed surface of the first semiconductor region and the capping layer; and A metal filling process is performed to form a first contact plug in the first opening and a second contact plug in the second opening.

8. The method of claim 7, wherein The metal layer includes a material selected from titanium silicide (Ti), cobalt silicide (Co), nickel silicide (Ni), molybdenum silicide (Mo), and tantalum silicide (Ta).

9. A method of forming an electrical contact in a semiconductor structure, comprising the steps of: performing a pre-cleaning process on an exposed surface of a semiconductor structure, the semiconductor structure comprising a first semiconductor region, a second semiconductor region, a dielectric layer, the dielectric layer having a first opening above the first semiconductor region and a second opening above the second semiconductor region, wherein the exposed surface of the semiconductor structure is disposed on the first semiconductor region within the first opening and on the second semiconductor region within the second opening; performing a patterning process to form a hard mask on the exposed surface of the first semiconductor region within the first opening; performing an etching process to form a groove at the exposed surface of the second semiconductor region; performing a first selective deposition process to form a contact layer on the exposed surface of the second semiconductor region within the second opening; performing a second selective deposition process to form a capping layer on the contact layer; performing a removal process to remove the hard mask; performing a third selective deposition process to form a metal layer on the exposed surface of the first semiconductor region and the capping layer; and A metal filling process is performed to form a first contact plug in the first opening and a second contact plug in the second opening.

10. The method of claim 9, wherein: The etching process, the first selective deposition process, and the second selective deposition process are performed without destroying a vacuum environment.

11. The method of claim 9, wherein The first semiconductor region includes silicon doped with an n-type dopant, The second semiconductor region includes silicon germanium doped with a p-type dopant, and The contact layer includes silicon germanium doped with a p-type dopant.

12. The method of claim 9, wherein The capping layer includes a material selected from molybdenum silicide (Mo) and ruthenium silicide (Ru).

13. The method of claim 9, wherein The metal layer includes a material selected from titanium silicide (Ti), cobalt silicide (Co), nickel silicide (Ni), molybdenum silicide (Mo), and tantalum silicide (Ta).

14. A processing system comprising: a first processing chamber; a second processing chamber; a third processing chamber; and a system controller configured to cause the processing system to: performing a patterning process in the first processing chamber to form a hard mask on a semiconductor structure, the semiconductor structure comprising a first semiconductor region, a second semiconductor region, and a dielectric layer, the dielectric layer having a first opening above the first semiconductor region and a second opening above the second semiconductor region, wherein the hard mask covers an exposed surface of the first semiconductor region within the first opening; performing a first selective deposition process in the second processing chamber to form a contact layer on the exposed surface of the second semiconductor region within the second opening; and A second selective deposition process is performed in the third processing chamber to form a capping layer on the contact layer.

15. The processing system of claim 14, further comprising: A fourth processing chamber, wherein the system controller is further configured to: Before the first selective deposition process, an etching process is performed in the fourth processing chamber to form a groove at the exposed surface of the second semiconductor region, wherein the groove has a V-shape, a U-shape, and any other shape to expand a contact area of ​​the contact layer.

16. The processing system of claim 15, wherein the system controller is further configured to cause the processing system to transfer the semiconductor structure between the second processing chamber, the third processing chamber, and the fourth processing chamber without breaking a vacuum environment.

17. The processing system of claim 15, further comprising: A fifth processing chamber, wherein the system controller is further configured to: Prior to the patterning process, in the fifth processing chamber, a pre-cleaning process is performed on the exposed surface of the first semiconductor region within the first opening and the exposed surface of the second semiconductor region within the second opening.

18. The processing system of claim 17, further comprising: a sixth processing chamber; a seventh processing chamber; and an eighth processing chamber, wherein the system controller is further configured to cause the processing system to: After the second selective deposition process, performing a removal process in the sixth processing chamber to remove the hard mask; performing a third selective deposition process in the seventh processing chamber to form a metal layer on the exposed surface of the first semiconductor region and the capping layer; and A metal filling process is performed in the eighth processing chamber to form a first contact plug in the first opening and a second contact plug in the second opening.

19. The processing system of claim 14, wherein The first semiconductor region includes silicon doped with an n-type dopant, The second semiconductor region includes silicon germanium doped with a p-type dopant, and the contact layer includes silicon germanium doped with a p-type dopant.

20. The processing system of claim 14, wherein The capping layer includes a material selected from molybdenum silicide (Mo) and ruthenium silicide (Ru).

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