Semiconductor device and electronic apparatus

Abstract

The present disclosure relates to a semiconductor device and an electronic apparatus that make it possible to provide a semiconductor device capable of reducing manufacturing costs. The semiconductor device is configured by stacking a first semiconductor, a second semiconductor, and a third semiconductor in a vertical direction. The second semiconductor between the first semiconductor and the third semiconductor includes a conversion circuit that converts an electrical characteristic or a physical characteristic. The present disclosure can be applied to, for example, a solid-state imaging device.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and an electronic device, and more particularly, to a semiconductor device and an electronic device capable of reducing manufacturing costs. Background Art

[0002] In order to enhance the function of an imaging device, a solid-state imaging device has been proposed in which two semiconductor substrates are bonded to a circuit surface of a first semiconductor substrate on the side opposite to the light incident surface on which a photoelectric conversion element is formed by CuCu bonding. The two semiconductor substrates are: a second semiconductor substrate on which a memory circuit is mounted and a third semiconductor substrate on which a logic circuit is mounted (for example, see Patent Document 1).

[0003] Citation list

[0004] Patent Literature

[0005] Patent Document 1: WO 2019 / 087764 A Summary of the invention

[0006] Problem that the invention aims to solve

[0007] For example, in the solid-state imaging device having a stacked structure disclosed in Patent Document 1, in order to reduce manufacturing cost, it is desirable to use a general-purpose semiconductor chip as the second semiconductor substrate or the third semiconductor substrate to be bonded to the first semiconductor substrate.

[0008] The present disclosure has been made in view of such circumstances, and an object of the present disclosure is to reduce manufacturing costs by using a general-purpose semiconductor chip as a semiconductor substrate to be bonded.

[0009] Solutions to technical problems

[0010] A semiconductor device according to a first aspect of the present disclosure includes a first semiconductor, a second semiconductor, and a third semiconductor stacked in a vertical direction, and the second semiconductor provided between the first semiconductor and the third semiconductor includes a conversion circuit that converts electrical characteristics or physical characteristics.

[0011] An electronic device according to a second aspect of the present disclosure includes a semiconductor device including a first semiconductor, a second semiconductor, and a third semiconductor stacked in a vertical direction, and the second semiconductor disposed between the first semiconductor and the third semiconductor includes a conversion circuit that converts electrical characteristics or physical characteristics.

[0012] In the first and second aspects of the present disclosure, a first semiconductor, a second semiconductor, and a third semiconductor are stacked in a vertical direction, and the second semiconductor disposed between the first semiconductor and the third semiconductor includes a conversion circuit that converts electrical characteristics or physical characteristics.

[0013] Semiconductor devices and electronic devices may be independent devices or modules integrated into other devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a cross-sectional view of a first embodiment of an imaging device to which the technology of the present disclosure is applied.

[0015] Figure 2 is a cross-sectional view of a second embodiment of an imaging device to which the technology of the present disclosure is applied.

[0016] Figure 3 is a cross-sectional view of a third embodiment of an imaging device to which the technology of the present disclosure is applied.

[0017] Figure 4 is a cross-sectional view of a fourth embodiment of an imaging device to which the technology of the present disclosure is applied.

[0018] Figure 5 is a cross-sectional view of a fifth embodiment of an imaging device to which the technology of the present disclosure is applied.

[0019] Figure 6 is a block diagram showing a configuration example of an image forming apparatus according to the second to fifth embodiments.

[0020] Figure 7 This is a diagram for explaining a parallel-to-serial conversion circuit included in the conversion circuit.

[0021] Figure 8 It is a diagram for explaining a serial-to-parallel conversion circuit included in the conversion circuit.

[0022] Fig. 9 This is a diagram for explaining an example of using an image sensor.

[0023] Fig.10 : is a block diagram showing a configuration example of an imaging device as an electronic device to which the technology of the present disclosure is applied.

[0024] Fig.11 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0025] Fig.12 1 is an explanatory diagram showing an example of the installation positions of the vehicle exterior information detection section and the imaging section. DETAILED DESCRIPTION

[0026] A mode for implementing the present technology (hereinafter referred to as an embodiment) will be described below with reference to the drawings. The description will be made in the following order.

[0027] 1. First Embodiment of Imaging Device

[0028] 2. Second Embodiment of Imaging Device

[0029] 3. Third Embodiment of Imaging Device

[0030] 4. Fourth Embodiment of Imaging Device

[0031] 5. Fifth Embodiment of Imaging Device

[0032] 6. Block diagram of imaging device

[0033] 7. Specific example of conversion circuit configuration

[0034] 8. Summary

[0035] 9. Example of using imaging device

[0036] 10. Application examples of electronic devices

[0037] 11. Application examples for mobile objects

[0038] Note that in the drawings cited in the following description, the same or similar parts are represented by the same or similar reference numerals, and their descriptions will not be repeated as appropriate. The drawings are schematic diagrams, and the relationship between thickness and plane size, the ratio of each layer thickness, etc. are different from the actual ones. In addition, the drawings may include parts with different size relationships and ratios.

[0039] In addition, the definitions of directions such as up and down in the following description are only for convenience of explanation and do not limit the technical ideas of the present disclosure. For example, when an object is observed by rotating the object by 90°, up and down are converted and read as left and right, and when the object is observed by rotating the object by 180°, up and down are reversed and read.

[0040] Hereinafter, an embodiment of an imaging device to which the present technology is applied will be described, but the present technology can be applied to a general semiconductor device.

[0041] <1. First Embodiment of Imaging Device>

[0042] Figure 1 A cross-sectional view showing a first embodiment of an imaging device to which the present technology is applied.

[0043] Figure 1 The illustrated imaging device 1 is a CMOS solid-state imaging device in which pixels each including a photoelectric conversion element are arranged in a matrix form.

[0044] The imaging device 1 has a stacked structure in which a second semiconductor 12 and a third semiconductor 13 as a sub-substrate are directly bonded to a first semiconductor 11 as a main substrate, and the second semiconductor 12 and the third semiconductor 13 are silicon dies having a planar size smaller than that of the first semiconductor 11. The first semiconductor 11 to the third semiconductor 13 are stacked in a vertical direction (longitudinal direction in the figure), and the second semiconductor 12 is arranged between the first semiconductor 11 and the third semiconductor 13. A single-point chain line P represents a bonding surface between the first semiconductor 11 and the second semiconductor 12.

[0045] The stacked structure of the first semiconductor 11 to the third semiconductor 13 is connected to the support substrate 14. The planar size of the first semiconductor 11 is larger than the planar sizes of the second semiconductor 12 and the third semiconductor 13. Between the first semiconductor 11 and the support substrate 14, an insulating layer 15 is formed in a region except for the second semiconductor 12 and the third semiconductor 13, and the second semiconductor 12 and the third semiconductor 13 are embedded in the insulating layer 15.

[0046] The first semiconductor 11 is a sensor substrate in which a plurality of pixels including photoelectric conversion elements are arranged in a matrix form. The second semiconductor 12 is a chip-shaped substrate between the first semiconductor 11 and the third semiconductor 13 on which a conversion circuit 81 for converting electrical characteristics or physical characteristics is formed. The details of the conversion circuit 81 will be described later. The third semiconductor 13 is a chip-shaped substrate on which a logic circuit is formed. The logic circuit includes, for example, a signal processing circuit that processes a signal generated by each pixel of the first semiconductor 11, an AI processing circuit that performs AI processing (recognition processing) based on the signal generated by each pixel of the first semiconductor 11, and the like. The third semiconductor 13 can be a chip-shaped substrate on which a storage circuit for storing the signal generated by each pixel of the first semiconductor 11 is formed.

[0047] The first semiconductor 11 includes a semiconductor substrate 21 using, for example, silicon (Si) as a semiconductor. On the semiconductor substrate 21, a photodiode 22 as a photoelectric conversion element is formed in units of pixels. In the figure, a planarization film 23 is formed on the light incident surface side (upper side) of the semiconductor substrate 21, and a color filter 24 and an on-chip lens 25 are formed for each pixel on the planarization film 23.

[0048] A wiring layer 41 including a plurality of metal wirings 31 and an insulating layer 32 is formed on the circuit forming surface side (lower side in the figure) of the semiconductor substrate 21 opposite to the light incident surface side. Figure 1In the example of , the number of layers of the metal wiring 31 is 6, but the number of layers of the metal wiring 31 is not limited. In addition, a plurality of bonding electrodes 33 are formed on the bonding surface (the lower surface of the wiring layer 41) with the second semiconductor 12. The bonding electrode 33 is bonded to the bonding electrode 55CuCu of the second semiconductor 12, and electrically connects the first semiconductor 11 and the second semiconductor 12. As materials for the metal wiring 31 and the bonding electrode 33, for example, copper (Cu), tungsten (W), aluminum (Al), gold (Au), etc. can be used. In the present embodiment, the metal wiring 31 and the bonding electrode 33 are formed of copper. The insulating layer 32 is formed of, for example, a SiO2 film, a low-k film (low dielectric constant insulating film), a SiOC film, etc. The insulating layer 32 can be composed of a plurality of insulating films made of different materials.

[0049] The first semiconductor 11 includes a plurality of pads 34 electrically connected to an external device by wire bonding or the like. Each pad 34 is formed of, for example, aluminum, and is arranged on a peripheral portion located outside the pixel array unit in a plan view. The pixel array unit is a region in which a plurality of pixels formed with photodiodes 22 and the like are arranged in a matrix form, and is formed in a central portion of the first semiconductor 11 in a plan view. A through hole 35 penetrating the semiconductor substrate 21 and the planarization film 23 is formed above the pad 34, and the through hole 35 exposes a portion of the upper surface of the pad 34 on which the wire bonding ball is formed.

[0050] The second semiconductor 12 includes a semiconductor substrate 51 using, for example, silicon (Si) as a semiconductor and a wiring layer 54 on the front surface side (first semiconductor 11 side) of the semiconductor substrate 51. The wiring layer 54 includes a multilayer metal wiring 52 and an insulating layer 53. Figure 1In the example of , the number of layers of the metal wiring 52 is 4, but the number of layers of the metal wiring 52 is not limited. A plurality of MOS transistors Tr1 are formed on the interface of the front surface of the semiconductor substrate 51. The plurality of MOS transistors Tr1 are separated by an element separation unit 57 such as shallow trench isolation (STI). In addition, a plurality of bonding electrodes 55 are formed on the bonding surface (upper surface of the wiring layer 54) with the first semiconductor 11. The bonding electrode 55y is bonded to the bonding electrode 33CuCu of the first semiconductor 11 to electrically connect the first semiconductor 11 and the second semiconductor 12. Each bonding electrode 55 is respectively connected to the metal wiring 52 of the uppermost layer in an area not shown. In the semiconductor substrate 51, a through electrode (silicon through hole) 56 is formed that penetrates the substrate, and the wiring layer 54 of the second semiconductor 12 and the wiring layer 64 of the third semiconductor 13 are electrically connected via the through electrode 56. As the material of the metal wiring 52 and the bonding electrode 55, for example, copper (Cu), tungsten (W), aluminum (Al), gold (Au), etc. can be used. In this embodiment, the metal wiring 52 and the bonding electrode 55 are formed of copper. The insulating layer 53 is formed of, for example, a SiO2 film, a low-k film (low dielectric constant insulating film), a SiOC film, etc. The insulating layer 53 may be composed of a plurality of insulating films made of different materials.

[0051] In the second semiconductor 12 , a conversion circuit 81 that converts electrical characteristics or physical characteristics so as to make the electrical characteristics or physical characteristics compatible with the third semiconductor 13 is formed.

[0052] The third semiconductor 13 includes a semiconductor substrate 61 using, for example, silicon (Si) as a semiconductor and a wiring layer 64 on the front surface side (second semiconductor 12 side) of the semiconductor substrate 61. The wiring layer 64 includes a multilayer metal wiring 62 and an insulating layer 63. Figure 1 In the example of , the number of layers of the metal wiring 62 is 3, but the number of layers of the metal wiring 62 is not limited. In addition, a bonding electrode 65 bonded to the through electrode 56 of the second semiconductor 12 is formed on the upper surface of the wiring layer 64. The bonding electrode 65 is connected to a predetermined metal wiring 62 in an area not shown. A plurality of MOS transistors Tr2 are formed on the interface of the front surface of the semiconductor substrate 51. A plurality of MOS transistors Tr2 are separated by an element separation unit 66 such as STI. As materials for the metal wiring 62 and the bonding electrode 65, for example, copper (Cu), tungsten (W), aluminum (Al), gold (Au), etc. can be used. In the present embodiment, the metal wiring 62 and the bonding electrode 65 are formed of copper. The insulating layer 63 is formed of, for example, a SiO2 film, a low-k film (low dielectric constant insulating film), a SiOC film, etc. The insulating layer 63 can be composed of a plurality of insulating films made of different materials.

[0053] The support substrate 14 is composed of a semiconductor substrate using, for example, silicon (Si) as a semiconductor. The support substrate 14 is bonded to the second semiconductor 12 and the third semiconductor 13 via an insulating layer 15. More specifically, the outer sides of the second semiconductor 12 and the third semiconductor 13 are covered by an insulating film 16 formed when the first semiconductor 11 to the third semiconductor 13 are bonded, and the insulating layer 15 is embedded in a region where the second semiconductor 12 and the third semiconductor 13 are not stacked. In a region where neither the second semiconductor 12 nor the third semiconductor 13 is stacked, the support substrate 14 is bonded to the first semiconductor 11 via the insulating layer 15.

[0054] As described above, the imaging device 1 of the first embodiment is constituted by stacking the first semiconductor 11 to the third semiconductor 13 in the vertical direction. The second semiconductor 12 disposed between the first semiconductor 11 and the third semiconductor 13 includes a conversion circuit 81 that converts electrical characteristics or physical characteristics according to the third semiconductor 13. Therefore, a general semiconductor chip can be used as the third semiconductor 13, and the manufacturing cost is reduced.

[0055] A method of manufacturing the imaging device 1 will be briefly described.

[0056] The imaging device 1 is manufactured by a chip-on-wafer (CoW) technology in which the first semiconductor 11 in a wafer state is singulated after the second semiconductor 12 and the third semiconductor 13 (singulated silicon dies) are bonded and stacked on the first semiconductor 11 in a wafer state.

[0057] More specifically, on the semiconductor substrate 21 in a wafer state, a plurality of photodiodes 22 are formed in units of chip regions that will be the first semiconductor 11, and a wiring layer 41 is formed on one surface of the semiconductor substrate 21. One surface of the semiconductor substrate 21 on which the wiring layer 41 is formed will be the front surface of the semiconductor substrate 21. Next, the second semiconductor 12 and the third semiconductor 13 manufactured and singulated in a separate process are bonded to the first semiconductor 11 in a wafer state in units of chip regions. In the region where the singulated second semiconductor 12 and the third semiconductor 13 are not stacked, the insulating layer 15 is embedded, flattened, and then bonded to the support substrate 14.

[0058] Next, after being inverted so that the support substrate 14 in a wafer state is the lower surface and the semiconductor substrate 21 in a wafer state is the upper surface, the semiconductor substrate 21 in a wafer state is thinned until the photodiode 22 formed in each chip region of the semiconductor substrate 21 is located near the interface. Then, a planarization film 23, a color filter 24, and an on-chip lens 25 are formed on the thinned semiconductor substrate 21.

[0059] Finally, through holes 35 are formed at the positions of the pads 34 on the peripheral portion of each chip region of the semiconductor substrate 21, and the upper surfaces of the pads 34 are exposed. As described above, a plurality of imaging devices 1 in a wafer state are completed and singulated as chips, thereby obtaining Figure 1 The state of the imaging device 1 in .

[0060] <2. Second Embodiment of Imaging Device>

[0061] Figure 2 A cross-sectional view showing a second embodiment of an imaging device to which the present technology is applied.

[0062] In referring to Figures 2 to 5 In the second to fifth embodiments described, the same parts as those in each of the above-described embodiments are given the same reference numerals, and the description of these parts will be appropriately omitted, and the description will be focused on the different parts.

[0063] Figure 2 The imaging device 1 according to the second embodiment shown in FIG. Figure 1 The first embodiment shown is common in that the imaging device 1 is constituted by stacking the first semiconductor 11 to the third semiconductor 13 in the vertical direction. However, the imaging device 1 of the second embodiment is different from the first embodiment in that, in addition to the first semiconductor 11 to the third semiconductor 13, the fourth semiconductor 101 is also bonded to the first semiconductor 11. The fourth semiconductor 101 is bonded to a plane region different from a region bonded to the second semiconductor 12 in the bonding surface of the first semiconductor 11 indicated by the single-dot chain line P. The bonding electrode 33 of the wiring layer 41 of the first semiconductor 11 includes a bonding electrode 33A bonded to the bonding electrode 71 of the second semiconductor 12 and a bonding electrode 33B bonded to the bonding electrode 115 of the fourth semiconductor 101.

[0064] exist Figure 1 In the first embodiment, the first semiconductor 11 and the second semiconductor 12 are bonded in such a manner that their wiring layers face each other. However, in the second embodiment, the wiring layer 54 of the second semiconductor 12 is bonded in such a manner that it faces the wiring layer 64 of the third semiconductor 13. The bonding electrode 71 and the insulating layer 72 are formed on the back side of the semiconductor substrate 51 of the second semiconductor 12, and the bonding electrode 33A formed on the wiring layer 41 of the first semiconductor 11 is electrically connected to the bonding electrode 71 formed on the back side of the semiconductor substrate 51 of the second semiconductor 12 by CuCu bonding. The bonding electrode 71 is connected to the metal wiring 52 of the wiring layer 54 on the front surface side via the through electrode 73 that penetrates the semiconductor substrate 51.

[0065] The single-dot chain line Q indicates the junction surface between the second semiconductor 12 and the third semiconductor 13 , and the junction electrode 74 of the wiring layer 54 of the second semiconductor 12 and the junction electrode 65 of the wiring layer 64 of the third semiconductor 13 are CuCu-joined to electrically connect the second semiconductor 12 and the third semiconductor 13 .

[0066] On the other hand, the fourth semiconductor 101 includes a semiconductor substrate 111 using, for example, silicon (Si) as a semiconductor and a wiring layer 114 on the front surface (first semiconductor 11 side) of the semiconductor substrate 111. The wiring layer 114 includes a multilayer metal wiring 112 and an insulating layer 113. Figure 2 In the example of FIG. 1 , the number of layers of the metal wiring 112 is 4, but the number of layers of the metal wiring 112 is not limited. A plurality of bonding electrodes 115 are formed on the uppermost layer of the wiring layer 114, and the bonding electrodes 115 are CuCu bonded to the bonding electrodes 33B on the first semiconductor 11 side to electrically connect the first semiconductor 11 and the fourth semiconductor 101. Each bonding electrode 115 is respectively connected to the uppermost metal wiring 112 in an area not shown.

[0067] A plurality of MOS transistors Tr3 are formed on the interface of the front surface of the semiconductor substrate 111. The plurality of MOS transistors Tr3 are separated by an element separation unit 116 such as STI. As the material of the metal wiring 112 and the bonding electrode 115, for example, copper (Cu), tungsten (W), aluminum (Al), gold (Au), etc. can be used. In the present embodiment, the metal wiring 112 and the bonding electrode 115 are formed of copper. The insulating layer 113 is formed of, for example, a SiO2 film, a low-k film (low dielectric constant insulating film), a SiOC film, etc. The insulating layer 113 can be composed of a plurality of insulating films made of different materials.

[0068] As described above, the imaging device 1 of the second embodiment is constituted by stacking the first semiconductor 11 to the third semiconductor 13 in the vertical direction. In addition, in the first semiconductor 11, the fourth semiconductor 101 is bonded to a region different from the second semiconductor 12. The planar size of the first semiconductor 11 is larger than any of the second semiconductor 12, the third semiconductor 13, and the fourth semiconductor 101. One or more metal wirings 31 and the bonding electrode 33 formed in the region 82 of the wiring layer 41 of the first semiconductor 11 are used to electrically connect the fourth semiconductor 101 and the second semiconductor 12. Since the conversion circuit 81 of the second semiconductor 12 is connected to the third semiconductor 13, the third semiconductor 13 is electrically connected to the fourth semiconductor 101 via the conversion circuit 81 of the second semiconductor 12 and the metal wiring 31 in the region 82 of the first semiconductor 11. The conversion circuit 81 includes a circuit that converts electrical characteristics or physical characteristics between the fourth semiconductor 101 and the third semiconductor 13. Therefore, a general semiconductor chip can be used for the third semiconductor 13 and the fourth semiconductor 101, and the manufacturing cost can be further reduced.

[0069] One of the third semiconductor 13 and the fourth semiconductor 101 may be, for example, an AI chip equipped with an AI processing circuit that performs AI processing based on a signal generated in each pixel of the first semiconductor 11, and the other may be a memory chip equipped with a memory circuit that stores a signal generated in each pixel of the first semiconductor 11, etc.

[0070] For example, the imaging device 1 of the second embodiment can be manufactured, for example, by the following method: a chip (silicon wafer) stacked by bonding the second semiconductor 12 and the third semiconductor 13 and a chip (silicon wafer) of the fourth semiconductor 101 are manufactured in a separate process, and the chips are bonded to the first semiconductor 11 in a wafer state.

[0071] <3. Third Implementation of Imaging Device>

[0072] Figure 3 A cross-sectional view showing a third embodiment of an imaging device to which the present technology is applied.

[0073] In the above-described first and second embodiments, the first semiconductor 11 has a structure including one semiconductor substrate 21. However, in Figure 3 In the third embodiment shown, the first semiconductor 11 has a stacked structure of two semiconductor substrates.

[0074] Specifically, Figure 3 The first semiconductor 11 of the imaging device 1 according to the third embodiment is constituted by stacking a semiconductor substrate 21 and a semiconductor substrate 151. Of the semiconductor substrate 21 and the semiconductor substrate 151, the semiconductor substrate 21 is arranged on the light incident surface side which is the upper side in the figure, and the semiconductor substrate 151 is arranged on the side close to the second semiconductor 12 and the fourth semiconductor 101.

[0075] In the semiconductor substrate 21, similarly to the first and second embodiments, the photodiode 22 is formed in units of pixels, and the color filter 24, the on-chip lens 25, etc. are formed on the back surface serving as the light incident surface of the semiconductor substrate 21. The wiring layer 41 is formed on the front surface side of the semiconductor substrate 21, which is also similar to the first and second embodiments.

[0076] However, a wiring layer 163 including a multilayer metal wiring 161 and an insulating layer 162 is formed on the semiconductor substrate 21 side as the front surface side of the semiconductor substrate 151. Figure 3In the example of , the number of layers of the metal wiring 161 is 4, but the number of layers of the metal wiring 161 is not limited. In the multi-layer metal wiring 161, a part of the metal wiring 161U of the uppermost layer constitutes the pad 34. As the material of the metal wiring 161, for example, copper (Cu), tungsten (W), aluminum (Al), gold (Au), etc. can be used. However, for example, aluminum is used as the material of the metal wiring 161U of the uppermost layer that is partially used as the pad 34, and for example, copper is used for other metal wirings 161.

[0077] In addition, a plurality of bonding electrodes 164 are formed on the upper surface of the wiring layer 163. As the material of the bonding electrode 164, for example, copper (Cu), tungsten (W), aluminum (Al), gold (Au), etc. can be used, but in the present embodiment, the bonding electrode 164 is formed of copper. Each bonding electrode 164 of the wiring layer 163 is connected to the bonding electrode 33 of the wiring layer 41 of the semiconductor substrate 21 by CuCu bonding. The single-dot chain line R represents the bonding surface between the wiring layer 41 on the semiconductor substrate 21 side and the wiring layer 163 on the semiconductor substrate 151 side.

[0078] On the back side (lower side in the figure) of the semiconductor substrate 151, a wiring layer 183 including a multilayer metal wiring 181 and an insulating layer 182 is formed. The multilayer metal wiring 181 is formed by rewiring (RDL). Figure 3 In the example of , the number of layers of the metal wiring 181 is 4, but the number of layers of the metal wiring 181 is not limited. In addition, on the bonding surface between the wiring layer 183 and the second semiconductor 12 and the fourth semiconductor 101 indicated by the single-dot chain line P, a plurality of bonding electrodes 184 are formed. In the bonding surface, some of the bonding electrodes 184 are bonded to the bonding electrode 71CuCu of the second semiconductor 12 to electrically connect the first semiconductor 11 and the second semiconductor 12. The other bonding electrodes 184 are bonded to the bonding electrode 115CuCu of the fourth semiconductor 101 to electrically connect the first semiconductor 11 and the fourth semiconductor 101. As the material of the metal wiring 181 and the bonding electrode 184, for example, copper (Cu), tungsten (W), aluminum (Al), gold (Au), etc. can be used, but in the present embodiment, the metal wiring 181 and the bonding electrode 184 are formed of copper. The insulating layers 162 and 182 are formed of, for example, a SiO2 film, a low-k film (low dielectric constant insulating film), a SiOC film, etc. The insulating layers 162 and 182 may be composed of a plurality of insulating films made of different materials.

[0079] A plurality of MOS transistors Tr4 are formed at the interface on the front surface side of the semiconductor substrate 151. The plurality of MOS transistors Tr4 are separated by an element separation unit 165 such as STI.

[0080] A plurality of through electrodes 191 penetrating the substrate are formed on the semiconductor substrate 151 , and the wiring layer 163 on the front surface side and the wiring layer 183 on the back surface side are electrically connected via the through electrodes 191 .

[0081] As described above, in the imaging device 1 of the third embodiment, the second semiconductor 12 and the third semiconductor 13 stacked in the vertical direction are bonded to the first semiconductor 11, and the fourth semiconductor 101 is bonded to a region different from the second semiconductor 12. Further, in addition, the first semiconductor 11 has a stacked structure of the semiconductor substrate 21 and the semiconductor substrate 151. In the multilayer metal wiring 181 formed by rewiring on the back side of the semiconductor substrate 151, one or more metal wirings 181 and the bonding electrode 184 in the region 82 are used to electrically connect the fourth semiconductor 101 and the second semiconductor 12. Since the conversion circuit 81 of the second semiconductor 12 is electrically connected to the third semiconductor 13, the third semiconductor 13 is electrically connected to the fourth semiconductor 101 via the conversion circuit 81 of the second semiconductor 12 and the metal wiring 31 in the region 82 of the first semiconductor 11. The conversion circuit 81 includes a circuit that converts electrical characteristics or physical characteristics between the fourth semiconductor 101 and the third semiconductor 13. Therefore, since a general-purpose semiconductor chip can be used for the third semiconductor 13 and the fourth semiconductor 101, the manufacturing cost can be further reduced.

[0082] According to the third embodiment, since the first semiconductor 11 has a stacked structure of the semiconductor substrate 21 and the semiconductor substrate 151, the circuit area of ​​the first semiconductor 11 can be increased compared to the first and second embodiments. For example, an analog processing circuit before converting a pixel signal output from each pixel arranged in a matrix form into a digital signal can be formed in the first semiconductor 11.

[0083] <4. Fourth Embodiment of Imaging Device>

[0084] Figure 4 A cross-sectional view showing a fourth embodiment of an imaging device to which the present technology is applied.

[0085] Figure 4 The imaging device 1 according to the fourth embodiment shown in FIG. Figure 2 The second embodiment shown is common in that the second semiconductor 12 and the third semiconductor 13 stacked in the vertical direction are bonded to a portion of the planar region of the first semiconductor 11 , and the fourth semiconductor 101 is bonded to a planar region of the first semiconductor 11 different from the second semiconductor 12 .

[0086] However, the thickness of the second semiconductor 12 and the third semiconductor 13 stacked therein is different from the thickness of the fourth semiconductor 101. Figure 2 Compared to the second embodiment shown, Figure 4 The fourth embodiment is different from the second embodiment in that the thickness of the second semiconductor 12 and the third semiconductor 13 is the same as the thickness of the fourth semiconductor 101. In other words, in the imaging device 1 of the fourth embodiment, the thickness of the semiconductor substrate 111 is formed thick so that the thickness of the fourth semiconductor 101 is the same as the thickness of the second semiconductor 12 and the third semiconductor 13. The imaging device 1 of the fourth embodiment is configured similarly to the second embodiment except for the thickness of the semiconductor substrate 111.

[0087] Similar to the second embodiment, the imaging device 1 of the fourth embodiment can be manufactured, for example, by manufacturing a chip stacked by bonding the second semiconductor 12 and the third semiconductor 13 and a chip of the fourth semiconductor 101 in separate processes, and bonding the chips to the first semiconductor 11 in a wafer state. By making the thickness of the chip of the fourth semiconductor 101 equal to the thickness of the chip obtained by bonding the second semiconductor 12 and the third semiconductor 13, the process of bonding to the first semiconductor 11 in a wafer state can be facilitated.

[0088] Note that Figure 4 In the fourth embodiment shown, similar to the second embodiment, the first semiconductor 11 has a single-layer structure using a semiconductor substrate 21, but may also have Figure 3 The third embodiment is similar to the stacked structure in which the semiconductor substrate 21 and the semiconductor substrate 151 are stacked.

[0089] <5. Fifth Embodiment of Imaging Device>

[0090] Figure 5 A cross-sectional view showing a fifth embodiment of an imaging device to which the present technology is applied.

[0091] Figure 5 The imaging device 1 according to the fifth embodiment shown in FIG. Figure 2 The second embodiment shown is common in that the second semiconductor 12 and the third semiconductor 13 stacked in the vertical direction are bonded to a portion of the planar region of the first semiconductor 11 , and the fourth semiconductor 101 is connected to a planar region of the first semiconductor 11 different from the second semiconductor 12 .

[0092] However, Figure 5 The fifth embodiment is different from the second embodiment in that a fifth semiconductor 201 including only a semiconductor substrate 211 is further stacked on the lower side (support substrate 14 side) of the fourth semiconductor 101. Figure 5In the fifth embodiment of the present invention, the fifth semiconductor 201 is stacked on the lower side of the fourth semiconductor 101 so that the total thickness of the fourth semiconductor 102 and the fifth semiconductor 201 is formed to be the same as the total thickness of the second semiconductor 12 and the third semiconductor 13. In other words, in the imaging device 1 of the fifth embodiment, the fifth semiconductor 201 is added so that the combined thickness of the fourth semiconductor 101 and the fifth semiconductor 201 is the same as the combined thickness of the second semiconductor 12 and the third semiconductor 13. The semiconductor substrate 211 constituting the fifth semiconductor 201 is a virtual substrate on which no circuit or the like is formed. The outside of the semiconductor substrate 211 is covered with an insulating film 16, and the semiconductor substrate 111 of the fourth semiconductor 101 and the semiconductor substrate 211 of the fifth semiconductor 201 are connected by oxide film bonding of the insulating film 16. The fourth embodiment is configured similarly to the second embodiment except that the fifth semiconductor 201 is added.

[0093] Similar to the second embodiment, for example, the imaging device 1 of the fifth embodiment can be manufactured by manufacturing a chip stacked by bonding the second semiconductor 12 and the third semiconductor 13 and a chip stacked by bonding the fourth semiconductor 101 and the fifth semiconductor 201 formed to be aligned with the thickness of the chip in separate processes, and bonding the chip to the first semiconductor 11 in a wafer state. By adjusting the thickness of the bonded chip of the fourth semiconductor 101 and the fifth semiconductor 201 to the thickness of the bonded chip of the second semiconductor 12 and the third semiconductor 13, the process of bonding to the first semiconductor 11 in a wafer state can be facilitated.

[0094] Note that Figure 5 In the fifth embodiment shown, similar to the second embodiment, the first semiconductor 11 has a single-layer structure using a semiconductor substrate 21, but may also have Figure 3 The third embodiment is similar to the stacked structure in which the semiconductor substrate 21 and the semiconductor substrate 151 are stacked.

[0095] <6. Imaging Device Block Diagram>

[0096] Figure 6 1 is a block diagram showing a configuration example of the imaging device 1 in the case where the imaging device 1 includes first to fourth semiconductors similar to those of the second to fifth embodiments described above.

[0097] The first semiconductor 11 includes a pixel array unit 251 in which a plurality of pixels formed with the photodiode 22 and the like are arranged in a matrix form, and pad portions 252A and 252B. The pad portions 252A and 252B include Figure 1The plurality of pads 34 are shown and correspond to the input / output unit of the imaging device 1. The pad section 252A includes the plurality of pads 34 electrically connected to the second semiconductor 12, and the pad section 252B includes the plurality of pads 34 electrically connected to the fourth semiconductor 101.

[0098] The second semiconductor 12 includes at least a conversion circuit 81. The conversion circuit 81 converts electrical characteristics or physical characteristics between the first semiconductor 11 and the third semiconductor 13, and converts electrical characteristics or physical characteristics between the third semiconductor 13 and the fourth semiconductor 101. By providing the second semiconductor 12 including at least the conversion circuit 81, compatibility with the third semiconductor 13 to be bonded can be improved.

[0099] The third semiconductor 13 includes a memory circuit 261 composed of, for example, a frame memory. The memory circuit 261 stores data supplied from the logic circuit 272 of the fourth semiconductor 101 via the conversion circuit 81.

[0100] The fourth semiconductor 101 includes an analog / AD conversion circuit 271, a logic circuit 272, and an IF circuit 273. The analog / AD conversion circuit 271 includes an analog signal processing circuit that processes an analog signal output from each pixel of the pixel array unit 251 and an AD conversion circuit that converts the analog signal into a digital signal. The analog / AD conversion circuit 271 outputs the signal converted (AD-converted) into a digital signal to the logic circuit 272. The logic circuit 272 performs various types of digital signal processing such as black level adjustment and column variation correction on the signal provided from the analog / AD conversion circuit 271, for example. The logic circuit 272 outputs the processed signal to the IF circuit 273, and stores the processed signal in the storage circuit 261 of the third semiconductor 13 as needed. The IF circuit 273 converts the signal provided from the logic circuit 272 into a predetermined format such as the Mobile Industry Processor Interface (MIPI) standard, for example, and outputs the signal to an external device via the pad portion 252B.

[0101] In the case where the imaging device 1 includes the first to fourth semiconductors, the logic circuit 272 may be provided in the third semiconductor 13, and the storage circuit 261 may be provided in the fourth semiconductor. Alternatively, one or both of the storage circuit 261 and the logic circuit 272 may be provided in both the third semiconductor 13 and the fourth semiconductor. The logic circuit 272 includes a signal processing circuit that processes a signal generated in each pixel and an AI processing circuit that performs AI processing based on the signal generated in each pixel.

[0102] <7. Specific Configuration Example of Conversion Circuit>

[0103] Next, a specific configuration example of the conversion circuit 81 provided in the second semiconductor 12 will be described.

[0104] <Parallel-to-serial conversion circuit>

[0105] The conversion circuit 81 may include, for example, a parallel-to-serial conversion circuit. The parallel-to-serial conversion circuit is an example of a conversion circuit that converts electrical characteristics between the first semiconductor 11 and the third semiconductor 13.

[0106] Figure 7 A specific configuration example and a timing chart of the parallel-to-serial conversion circuit included in the conversion circuit 81 are shown.

[0107] The parallel-to-serial conversion circuit 301 includes three selectors 311 and a D flip-flop 312, and converts three parallel signals D0, D1 and D2 into serial signals and outputs the serial signals. One of the parallel signals D0, D1 and D2 and the SH signal for controlling the sampling timing are input to each selector 311. When the SH signal is low, each selector 311 outputs a signal D0, D1 or D2 of input B. When the clock signal CK rises, each D flip-flop 312 stores a signal output from the selector 311 of the previous stage and provided to the input D, and outputs the signal from the output Q. As a result, the output OUT of the parallel-to-serial conversion circuit 301 outputs signals D0, D1 and D2 in sequence. The parallel-to-serial conversion circuit 301 can convert a low-speed parallel signal into a high-speed serial signal and output a serial signal.

[0108] <Serial-to-parallel conversion circuit>

[0109] The conversion circuit 81 may include, for example, a serial-parallel conversion circuit. The serial-parallel conversion circuit is an example of a conversion circuit that converts electrical characteristics between the first semiconductor 11 and the third semiconductor 13.

[0110] Figure 8 A specific configuration example and a timing chart of the serial-to-parallel conversion circuit included in the conversion circuit 81 are shown.

[0111] The serial-to-parallel conversion circuit 321 is formed by connecting three D flip-flops 331, and converts three sequentially input signals D0, D1, and D2 into parallel signals and outputs the parallel signals. When the clock signal CK rises, each D flip-flop 331 stores the signal provided to the input D, and outputs the signal from the output Q. As a result, the signals D0, D1, and D2 are simultaneously output from the outputs OUT0, OUT1, and OUT2 of the serial-to-parallel conversion circuit 321. The serial-to-parallel conversion circuit 321 can convert high-speed serial signals into low-speed parallel signals and output parallel signals.

[0112] In the case where a general semiconductor chip is used as the third semiconductor 13 and the fourth semiconductor 101, the parallel number is limited by the number of pads of the semiconductor chip. By setting the parallel-to-serial conversion circuit 301 or the serial-to-parallel conversion circuit 321 as at least a part of the conversion circuit 81, the parallel number of data signals can be increased and the data rate can be improved.

[0113] <Wiring pitch conversion unit>

[0114] For example, in a general-purpose semiconductor chip used as a memory circuit 261 ( Figure 6 ), it is conceivable that the wiring pitch of the third semiconductor 13 and the wiring pitch of the first semiconductor 11 are different from each other. For example, the wiring pitch of the third semiconductor 13 using a general semiconductor chip is larger (wider) than the wiring pitch of the first semiconductor 11. The conversion circuit 81 may include a wiring pitch conversion unit that converts the wiring pitch between the first semiconductor 11 and the third semiconductor 13. The wiring pitch conversion unit is an example of a conversion circuit that converts physical properties between the first semiconductor 11 and the third semiconductor 13. By providing the wiring pitch conversion unit, compatibility with the third semiconductor 13 to be bonded can be improved.

[0115] <Logic Circuit Unit>

[0116] For example, the conversion circuit 81 may include a logic circuit unit, such as an arithmetic operation circuit that performs arithmetic operations on a plurality of images stored in the storage circuit 261, performs arithmetic operations on a plurality of pixels in the image, and the like, and a clock generation circuit that generates a clock signal CK such as the above-mentioned serial-to-parallel conversion circuit, etc. The logic circuit unit is an example of a conversion circuit that converts electrical characteristics between the first semiconductor 11 and the third semiconductor 13. By providing the logic circuit unit, the circuit area of ​​the first semiconductor 11 can be reduced.

[0117] <Format Conversion Unit>

[0118] The conversion circuit 81 may include, for example, a format conversion unit. The format conversion unit is, for example, a circuit that converts a signal format into a signal format that complies with a standard such as DDR4, DDR5, or MIPI and outputs a signal in the converted signal format. The format conversion unit is an example of a conversion circuit that converts electrical characteristics between the first semiconductor 11 and the third semiconductor 13. By providing the format conversion unit, the signal format can be converted, and the degree of freedom of the communication method can be increased.

[0119] <Power supply unit>

[0120] The conversion circuit 81 may include, for example, a power supply unit. The power supply unit is, for example, a circuit that supplies a power supply voltage input from the pad portion 252A or 252B to the third semiconductor 13. The power supply unit is an example of a conversion circuit that converts electrical characteristics between the first semiconductor 11 and the third semiconductor 13.

[0121] <Test Circuit>

[0122] The conversion circuit 81 may include, for example, a test circuit for testing the operation of the third semiconductor 13. For example, in the case where the analog / AD conversion circuit 271 or the logic circuit 272 is provided in the third semiconductor 13, the test circuit is a circuit for testing the operation of these circuits. The test circuit is an example of a conversion circuit that converts electrical characteristics between the first semiconductor 11 and the third semiconductor 13.

[0123] <8. Conclusion>

[0124] In the imaging device 1, the first semiconductor 11, the second semiconductor 12, and the third semiconductor 13 are stacked in the vertical direction, and the second semiconductor 12 provided between the first semiconductor 11 and the third semiconductor 13 includes a conversion circuit 81 that converts electrical characteristics or physical characteristics. By providing the conversion circuit 81 in the second semiconductor 12, a general semiconductor chip can be used as the third semiconductor 13, and the manufacturing cost of the imaging device 1 can be reduced. In the case where the fourth semiconductor 101 is also bonded, a general semiconductor chip can also be used as the fourth semiconductor 101, and the manufacturing cost of the imaging device 1 can be further reduced. The first semiconductor 11 is formed to have a larger plane size than any of the second semiconductor 12, the third semiconductor 13, and the fourth semiconductor 101, and the second semiconductor 12 and the fourth semiconductor 101 are arranged in different plane areas of the first semiconductor 11.

[0125] <9. Example of use of imaging device>

[0126] Fig. 9 : is a diagram showing a usage example of an image sensor using the above-described imaging device 1 .

[0127] The above-described imaging device can be used as an image sensor, for example, in various cases of sensing light such as visible light, infrared light, ultraviolet light, and X-rays.

[0128] - Devices that capture images for viewing, such as digital cameras and portable devices with camera functions.

[0129] -Devices for traffic purposes, such as on-board sensors that capture images of the front, rear, surroundings, and interior of a car for safe driving such as automatic stopping and for identifying the driver's status; surveillance cameras for monitoring moving vehicles and roads; and ranging sensors for measuring the distance between vehicles.

[0130] - Devices for home appliances such as televisions, refrigerators, and air conditioners that capture images of user gestures and operate the device based on the gestures.

[0131] - Devices used in medical care, such as endoscopes or devices for angiography by receiving infrared light.

[0132] -Devices used for security, such as security surveillance cameras or personal authentication cameras.

[0133] - Devices for beauty care, such as skin measurement instruments for taking images of the skin and microscopes for taking images of the scalp.

[0134] -Devices for sports, such as action cameras or wearable cameras for sports applications, etc.

[0135] -Devices for use in agriculture, such as cameras for monitoring the condition of fields and crops.

[0136] <10. Application examples of electronic equipment>

[0137] The present technology is not limited to application to imaging devices. That is, the present technology can be applied to imaging devices such as digital cameras or video cameras, mobile terminal devices with imaging functions, and general electronic devices that use imaging devices as image capturing units (photoelectric conversion elements), such as copiers that use imaging devices as image reading units. The imaging device can be formed as a chip, or can be in the form of a module with imaging functions in which an imaging unit and a signal processing unit or an optical system are packaged together.

[0138] Fig.10 This is a block diagram showing a configuration example of an electronic device to which the present technology is applied.

[0139] Fig.10 The electronic device 600 includes an optical unit 601 having a lens group, etc., using Figure 1 The electronic device 600 includes a solid-state imaging device (imaging device) 602 and a digital signal processor (DSP) circuit 603 as a camera signal processing circuit. In addition, the electronic device 600 further includes a frame memory 604, a display portion 605, a recording unit 606, an operation unit 607, and a power supply unit 608. The DSP circuit 603, the frame memory 604, the display portion 605, the recording unit 606, the operation unit 607, and the power supply unit 608 are connected to each other via a bus 609.

[0140] The optical unit 601 captures incident light (image light) from the subject and forms an image on the imaging surface of the solid-state imaging device 602. The solid-state imaging device 602 converts the light amount of the incident light formed on the imaging surface by the optical unit 601 into an electrical signal in units of pixels, and outputs the electrical signal as a pixel signal. As the solid-state imaging device 602, a Figure 1 An imaging device 1, i.e., an imaging device formed by vertically bonding a first semiconductor 11 as a main substrate to a second semiconductor 12 and a third semiconductor 13 as a silicon wafer having a smaller plane size than the first semiconductor, wherein a conversion circuit 81 is provided in the second semiconductor 12 arranged between the first semiconductor 11 and the third semiconductor 13.

[0141] The display section 605 includes, for example, a thin display such as a liquid crystal display (LCD) or an organic electroluminescent (EL) display, and displays a moving image or a still image captured by the solid-state imaging device 602. The recording unit 606 records the moving image or the still image captured by the solid-state imaging device 602 on a recording medium such as a hard disk or a semiconductor memory.

[0142] The operation unit 607 issues operation commands regarding various functions of the electronic device 600 under the operation of the user. The power supply unit 608 appropriately supplies various power sources as operation power sources of the DSP circuit 603, the frame memory 604, the display portion 605, the recording unit 606, and the operation unit 607 to these supply targets.

[0143] As described above, by using the imaging device 1 to which any of the above-described embodiments is applied as the solid-state imaging device 602, the manufacturing cost can be reduced and the yield rate can be improved. Therefore, even in electronic devices 600 such as video cameras, digital cameras, and camera modules for mobile devices such as mobile phones, the manufacturing cost can be reduced and the yield rate can be improved.

[0144] <11. Application examples of mobile objects>

[0145] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device installed on any type of mobile body such as a car, an electric car, a hybrid electric car, a motorcycle, a bicycle, a personal mobile device, an airplane, an unmanned aerial vehicle, a ship, or a robot.

[0146] Fig.11 : is a block diagram showing an example of a schematic configuration of a vehicle control system as an example of a mobile body control system to which the technology according to the present disclosure can be applied.

[0147] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.11 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown as the functional configuration of the integrated control unit 12050.

[0148] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 serves as a control device for the following devices: a drive force generating device such as an internal combustion engine or a drive motor for generating a drive force for the vehicle; a drive force transmitting mechanism for transmitting the drive force to the wheels; a steering mechanism for adjusting the steering angle of the vehicle; and a braking device for generating a braking force for the vehicle, etc.

[0149] The body system control unit 12020 controls the operation of various devices provided to the vehicle body according to various programs. For example, the body system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a taillight, a brake light, a turn signal light, or a fog light. In this case, radio waves transmitted from a portable device as a substitute for a key or signals of various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls the door lock device, the power window device, and lights of the vehicle.

[0150] The vehicle exterior information detection unit 12030 detects information about the exterior of the vehicle having the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to image the exterior of the vehicle and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform detection processing on objects such as people, vehicles, obstacles, signs, or symbols on the road surface, or detection processing of the distance to these objects.

[0151] The imaging unit 12031 is an optical sensor for receiving light and outputting an electrical signal corresponding to the amount of light received. The imaging unit 12031 may output the electrical signal as an image, or may output the electrical signal as information about the measured distance. In addition, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared rays.

[0152] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 that detects the driver's state. The driver state detection unit 12041 includes, for example, a camera that images the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or the driver's concentration level, or can determine whether the driver is dozing off.

[0153] The microcomputer 12051 can calculate the control target value of the driving force generating device, the steering mechanism or the braking device based on the information about the inside or outside of the vehicle (the information is obtained by the outside information detection unit 12030 or the inside information detection unit 12040), and output the control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform the coordinated control aimed at realizing the functions of the advanced driver assistance system (ADAS), which includes: collision avoidance or collision mitigation of the vehicle, following driving based on the vehicle-to-vehicle distance, vehicle speed maintenance driving, vehicle collision warning or vehicle lane departure warning, etc.

[0154] In addition, the microcomputer 12051 can perform collaborative control intended for autonomous driving, which enables the vehicle to drive autonomously by controlling a driving force generating device, a steering mechanism, or a braking device, etc. based on information about the interior or exterior of the vehicle (the information is obtained by the exterior information detection unit 12030 or the interior information detection unit 12040), without relying on the driver's operation.

[0155] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on information about the exterior of the vehicle, which is obtained by the exterior information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights to change from high beam to low beam according to the position of the preceding vehicle or the oncoming vehicle detected by the exterior information detection unit 12030.

[0156] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device that can visually or auditorily notify the vehicle's passengers or the outside of the vehicle of information. Fig.11 In the example of FIG. 1 , an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown as output devices. For example, the display portion 12062 may include at least one of an in-vehicle display and a head-up display.

[0157] Fig.12 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0158] exist Fig.12 In the figure, vehicle 12100 includes imaging units 12101, 12102, 12103, 12104 and 12105 as imaging unit 12031.

[0159] The imaging units 12101, 12102, 12103, 12104 and 12105 are provided, for example, at locations such as the front nose, side mirrors, rear bumpers, rear doors, and the upper portion of the inner windshield of the vehicle 12100. The imaging unit 12101 provided to the front nose and the imaging unit 12105 provided to the upper portion of the inner windshield of the vehicle mainly obtain images in front of the vehicle 12100. The imaging units 12102 and 12103 provided to the side mirrors mainly obtain images on the sides of the vehicle 12100. The imaging unit 12104 provided to the rear bumper or rear door mainly obtains images of the rear of the vehicle 12100. The front images obtained by the imaging units 12101 and 12105 are mainly used to detect the front vehicle, pedestrians, obstacles, traffic signals, traffic signs or lanes, etc.

[0160] Notice, Fig.12 An example of the shooting range of the imaging units 12101 to 12104 is shown. Imaging range 12111 represents the imaging range of the imaging unit 12101 provided to the front nose. Imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging units 12102 and 12103 provided to the side mirrors. Imaging range 12114 represents the imaging range of the imaging unit 12104 provided to the rear bumper or the rear door. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above is obtained.

[0161] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0162] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging range 12111 to 12114 and the time change of the distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting the nearest three-dimensional object as the front vehicle, in particular, the three-dimensional object exists on the driving path of the vehicle 12100 and travels in the same direction as the vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h). In addition, the microcomputer 12051 can set the following distance to be maintained between the vehicle in front and the front vehicle, and perform automatic braking control (including follow-up stop control) or automatic acceleration control (including follow-up start control), etc. Therefore, it is possible to perform cooperative control intended for automatic driving, which allows the vehicle to travel autonomously without relying on the driver's operation, etc.

[0163] For example, the microcomputer 12051 can classify the three-dimensional object data about the three-dimensional object into three-dimensional object data of two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually identified by the driver of the vehicle 12100 and obstacles that are difficult for the driver of the vehicle 12100 to visually identify. Then, the microcomputer 12051 determines a collision risk representing the risk of collision with each obstacle. When the collision risk is equal to or higher than the set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062, and performs forced deceleration or evasive steering through the drive system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collision.

[0164] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether there is a pedestrian in the captured images of the imaging units 12101 to 12104. For example, such identification of pedestrians is performed by a program that extracts feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras and a program that determines whether it is a pedestrian by performing pattern matching processing on a series of feature points representing the outline of an object. When the microcomputer 12051 determines that there is a pedestrian in the captured images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so that a square contour line for emphasis is displayed in a manner superimposed on the identified pedestrian. The sound / image output unit 12052 may also control the display unit 12062 so that an icon or the like representing a pedestrian is displayed at a desired position.

[0165] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. For example, the technology according to the present disclosure can be applied to the imaging unit 12031 in the above-mentioned configuration. The technology according to the present disclosure can be applied to the imaging unit 12031 in the above-mentioned configuration. Specifically, the imaging device 1 according to each of the above-mentioned embodiments can be adopted as the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to obtain a captured image that is easier to view and acquire distance information while reducing manufacturing costs and size. In addition, by using the captured images and distance information obtained, it is possible to reduce the fatigue of the driver and the safety of the driver and the vehicle.

[0166] In addition, the present disclosure is not limited to application to solid-state imaging devices that detect the distribution of the amount of incident visible light and capture the distribution as an image, and can be applied to all solid-state imaging devices (physical quantity distribution detection devices), such as solid-state imaging devices that capture the distribution of the amount of incident infrared rays, X-rays, particles, etc. as an image, and fingerprint detection sensors that detect the distribution of other physical quantities such as pressure and capacitance in a broad sense and capture the distribution as an image.

[0167] Furthermore, the present technology can be applied not only to solid-state imaging devices but also to general-purpose semiconductor devices having other semiconductor integrated circuits.

[0168] The embodiments of the present disclosure are not limited to the above-described embodiments, and various modifications may be made without departing from the technical gist of the present disclosure.

[0169] For example, a mode obtained by combining all or some of the above-described multiple embodiments may be adopted.

[0170] Note that the effects described in this specification are merely examples and are not restrictive, and there may be effects other than those described in this specification.

[0171] Note that the technology of the present disclosure may have the following configurations.

[0172] (1) A semiconductor device comprising:

[0173] A first semiconductor, a second semiconductor, and a third semiconductor stacked in a vertical direction, wherein

[0174] The second semiconductor provided between the first semiconductor and the third semiconductor includes a conversion circuit that converts electrical characteristics or physical characteristics.

[0175] (2) The semiconductor device according to (1) above, wherein

[0176] A fourth semiconductor is further bonded to the first semiconductor in a different plane region from that of the second semiconductor.

[0177] (3) The semiconductor device according to (2) above, wherein

[0178] The third semiconductor is connected to the fourth semiconductor via the conversion circuit of the second semiconductor and wiring of the first semiconductor.

[0179] (4) The semiconductor device according to (2) or (3) above, wherein

[0180] The first semiconductor is formed by stacking a plurality of semiconductor substrates, and

[0181] The third semiconductor is connected to the fourth semiconductor via the conversion circuit of the second semiconductor and the rewiring of the first semiconductor.

[0182] (5) The semiconductor device according to any one of (2) to (4) above, wherein

[0183] The thickness of the fourth semiconductor is different from the thickness of the second semiconductor and the third semiconductor stack.

[0184] (6) The semiconductor device according to any one of (2) to (4) above, wherein

[0185] The thickness of the fourth semiconductor is equal to the thickness of the stack of the second semiconductor and the third semiconductor.

[0186] (7) The semiconductor device according to (6) above, wherein

[0187] The total thickness of the fourth semiconductor and the dummy substrate is equal to the thickness of the second semiconductor and the third semiconductor stack.

[0188] (8) The semiconductor device according to any one of (1) to (7) above, wherein

[0189] The conversion circuit includes a parallel-to-serial conversion circuit.

[0190] (9) The semiconductor device according to any one of (1) to (8) above, wherein

[0191] The conversion circuit includes a serial-to-parallel conversion circuit.

[0192] (10) The semiconductor device according to any one of (1) to (9) above, wherein

[0193] The conversion circuit includes a wiring pitch conversion unit that converts a wiring pitch.

[0194] (11) The semiconductor device according to any one of (1) to (10) above, wherein

[0195] The conversion circuit includes a logic circuit unit.

[0196] (12) The semiconductor device according to any one of (1) to (11) above, wherein

[0197] The conversion circuit includes a format conversion unit for converting a signal format.

[0198] (13) The semiconductor device according to any one of (1) to (12) above, wherein

[0199] The conversion circuit includes a power supply unit that supplies a power supply voltage to the third semiconductor.

[0200] (14) The semiconductor device according to any one of (1) to (13) above, wherein

[0201] The conversion circuit includes a test circuit for the third semiconductor.

[0202] (15) The semiconductor device according to any one of (1) to (14) above, wherein

[0203] A planar size of the first semiconductor is larger than a planar size of any one of the second semiconductor and the third semiconductor.

[0204] (16) The semiconductor device according to any one of (1) to (15) above, wherein

[0205] The first semiconductor includes photoelectric conversion elements arranged in a matrix form.

[0206] (17) The semiconductor device according to any one of (1) to (16) above, wherein

[0207] The third semiconductor includes a logic circuit, and the logic circuit includes a signal processing circuit or an AI processing circuit.

[0208] (18) The semiconductor device according to any one of (1) to (17) above, wherein

[0209] The third semiconductor includes a memory circuit.

[0210] (19) An electronic device comprising:

[0211] A semiconductor device comprising:

[0212] A first semiconductor, a second semiconductor, and a third semiconductor stacked in a vertical direction, wherein

[0213] The second semiconductor provided between the first semiconductor and the third semiconductor includes a conversion circuit that converts electrical characteristics or physical characteristics.

[0214] Reference numerals list

[0215] 1 Imaging device

[0216] 11First Semiconductor

[0217] 12 Second Semiconductor

[0218] 13Third Semiconductor

[0219] 14 Support substrate

[0220] 15 Insulation layer

[0221] 16 Insulation film

[0222] 21Semiconductor substrate

[0223] 22 Photodiode

[0224] 23 Flattening film

[0225] 24 color filters

[0226] 25 on-chip lenses

[0227] 31 Metal wiring

[0228] 34 pads

[0229] 41 wiring layer

[0230] 51Semiconductor substrate

[0231] 61Semiconductor substrate

[0232] 81 conversion circuit

[0233] 82 Area

[0234] 101 Fourth Semiconductor

[0235] 201 Fifth Semiconductor

[0236] 301 Parallel to serial conversion circuit

[0237] 321 Serial-to-parallel conversion circuit

[0238] 600 Electronic equipment

[0239] 602 Solid-state imaging device

Claims

1. A semiconductor device comprising: A first semiconductor, a second semiconductor, and a third semiconductor stacked in a vertical direction, wherein The second semiconductor provided between the first semiconductor and the third semiconductor includes a conversion circuit that converts electrical characteristics or physical characteristics.

2. The semiconductor device according to claim 1, wherein A fourth semiconductor is further bonded to the first semiconductor in a different plane region from that of the second semiconductor.

3. The semiconductor device according to claim 2, wherein The third semiconductor is connected to the fourth semiconductor via the conversion circuit of the second semiconductor and wiring of the first semiconductor.

4. The semiconductor device according to claim 2, wherein The first semiconductor is formed by stacking a plurality of semiconductor substrates, and The third semiconductor is connected to the fourth semiconductor via the conversion circuit of the second semiconductor and the rewiring of the first semiconductor.

5. The semiconductor device according to claim 2, wherein The thickness of the fourth semiconductor is different from the thickness of the second semiconductor and the third semiconductor stack.

6. The semiconductor device according to claim 2, wherein The thickness of the fourth semiconductor is equal to the thickness of the stack of the second semiconductor and the third semiconductor.

7. The semiconductor device according to claim 6, wherein The total thickness of the fourth semiconductor and the dummy substrate is equal to the thickness of the second semiconductor and the third semiconductor stack.

8. The semiconductor device according to claim 1, wherein The conversion circuit includes a parallel-to-serial conversion circuit.

9. The semiconductor device according to claim 1, wherein The conversion circuit includes a serial-to-parallel conversion circuit.

10. The semiconductor device according to claim 1, wherein The conversion circuit includes a wiring pitch conversion unit that converts a wiring pitch.

11. The semiconductor device according to claim 1, wherein The conversion circuit includes a logic circuit unit.

12. The semiconductor device according to claim 1, wherein The conversion circuit includes a format conversion unit for converting a signal format.

13. The semiconductor device according to claim 1, wherein The conversion circuit includes a power supply unit that supplies a power supply voltage to the third semiconductor.

14. The semiconductor device according to claim 1, wherein The conversion circuit includes a test circuit for the third semiconductor.

15. The semiconductor device according to claim 1, wherein A planar size of the first semiconductor is larger than a planar size of any one of the second semiconductor and the third semiconductor.

16. The semiconductor device according to claim 1, wherein The first semiconductor includes photoelectric conversion elements arranged in a matrix form.

17. The semiconductor device according to claim 1, wherein The third semiconductor includes a logic circuit, and the logic circuit includes a signal processing circuit or an AI processing circuit.

18. The semiconductor device according to claim 1, wherein The third semiconductor includes a memory circuit.

19. An electronic device comprising: A semiconductor device comprising: A first semiconductor, a second semiconductor, and a third semiconductor stacked in a vertical direction, wherein The second semiconductor provided between the first semiconductor and the third semiconductor includes a conversion circuit that converts electrical characteristics or physical characteristics.

Images