Method for manufacturing multi-color device and multi-color display apparatus

Abstract

A method (100) for manufacturing a multicolor display or imaging device is provided. The method comprises the steps of: processing (101) a plurality of first semiconductor light-emitting or light-detecting devices on a first semiconductor wafer, each first semiconductor light-emitting or light-detecting device configured to emit or detect light of a first color; processing (102) at least a plurality of second semiconductor light emitting or light detecting devices on at least a second semiconductor wafer, each second semiconductor light emitting or light detecting device configured to emit or detect light of a second color; processing (103), on a third semiconductor wafer, an integrated circuit having a driving device for driving the plurality of first semiconductor light emitting or light detecting devices and the plurality of second semiconductor light emitting or light detecting devices; and bonding (104) the first semiconductor wafer, the at least second semiconductor wafer and the third semiconductor wafer in a stacked manner.

Description

Technical Field

[0001] The present invention relates to multicolor optics operating on different wavelengths of light, and in particular to multicolor displays or imagers or sensors comprising monochromatic optics, especially for augmented reality (AR) applications. Background Art

[0002] In recent years, microdisplay technology has been improved in terms of resolution, brightness and energy consumption, especially improving the performance of AR applications. A promising microdisplay technology is a microdisplay with one or more micro-light emitting devices (e.g., micro-light emitting diodes, micro-LEDs) on a complementary metal oxide semiconductor (CMOS).

[0003] For example, document EP 3 667 721 A1 proposes a monochrome device made by integrating a micro-LED (front plane) with a CMOS readout circuit (backplane). However, for a multicolor device, each different emission color requires a different epitaxial stack, and an efficient backplane integration is also required to drive the individual pixels, such as RGB pixels.

[0004] Another microdisplay technology is a microdisplay with independent monochrome dies (i.e., RGB dies) and light combining optics. In particular, three independent displays of three colors can be manufactured in independent batches and can be packaged in a single module. The resulting output light can be optically combined using optical waveguides, prismatic combiners, linear combiners, or a combination thereof. However, this approach is costly and further increases the volume of the waveguide assembly. Summary of the invention

[0005] Therefore, an object of the present invention is to provide a method for manufacturing a multi-color device and a multi-color display or imaging device, especially to help provide a monolithic multi-color device in an integrated process compatible with existing CMOS foundries (CMOS wafer factories).

[0006] This object is solved by the features of the first independent claim directed to a method and by the features of the second independent claim directed to a multi-color display or imaging device. The dependent claims contain further developments.

[0007] According to a first aspect of the present invention, a method for manufacturing a multicolor display or imaging device is provided. The method comprises the following steps: processing a plurality of first semiconductor light emitting or light detecting devices on a first semiconductor wafer, each of which is configured to emit or detect light of a first color. In addition, the method comprises the following steps: processing at least a plurality of second semiconductor light emitting or light detecting devices on at least a second semiconductor wafer, each of which is configured to emit or detect light of a second color.

[0008] Furthermore, the method comprises the following steps: processing an integrated circuit having a driver device on a third semiconductor wafer, the driver device being used to drive the plurality of first semiconductor light emitting or light detecting devices and the plurality of second semiconductor light emitting or light detecting devices. Furthermore, the method comprises the following steps: bonding the first semiconductor wafer, the at least second semiconductor wafer and the third semiconductor wafer in a stacked manner.

[0009] Preferably, the first semiconductor wafer and the second semiconductor wafer are to be understood as process wafers. For example, the first semiconductor wafer may be stacked on top of the third semiconductor wafer or CMOS wafer, and the second semiconductor wafer may be stacked on top of the first semiconductor wafer. In this regard, the substrate of the first semiconductor wafer may be removed or etched after being stacked on top of the third semiconductor wafer or CMOS wafer, thereby leaving the film containing the plurality of first light emitting or light detecting devices and / or any additional processes applied to the plurality of light emitting or light detecting devices intact.

[0010] Similarly, the substrate of the second semiconductor wafer can be removed or etched after being stacked on top of the first semiconductor wafer (which has been processed to remove the substrate of the first semiconductor wafer), thereby leaving the film containing the plurality of second light emitting or light detecting devices and / or any additional processes applied to the plurality of second light emitting or light detecting devices intact. In other words, the substrates of the first semiconductor wafer and the second semiconductor wafer can be removed or etched separately after they are each bonded in a stacked manner.

[0011] Therefore, the present invention proposes a multi-color (e.g., RGB) pixel-by-pixel approach by realizing individual colors in individual epitaxial layers, which are formed in a stacked manner on a single CMOS backplane. Thus, each light emitting or light detecting device of each individual epitaxial layer can be individually addressed by the CMOS IC.

[0012] In addition, the multi-color pixels, especially the optical coupling and isolation of each multi-color pixel, can be optimized for each wavelength. In addition, the stacked structure of different semiconductor wafers helps to provide separate common rail voltages for each light emitting or light detecting device on different semiconductor wafers.

[0013] Advantageously, a 3D stacked configuration for a multicolor display device can be realized, which can include multiple semiconductor wafers with arrays of light emitting devices (e.g., LEDs). Each layer of the 3D stacked structure can operate on a different wavelength of light (e.g., red, green, or blue), and the light emitting devices can be driven or read out by a CMOS IC, for example, individually or in a matrix.

[0014] In addition, a 3D stacked configuration for an imaging device can be implemented, which can include multiple semiconductor wafers with arrays of light detection devices (e.g., gratings, phototransistors, or photodiodes). Each layer of the 3D stacked structure can operate on a different wavelength of light (e.g., near infrared (IR), ultraviolet (UV), etc.), and the light detection devices can be driven or read out by a CMOS IC, for example, individually or in a matrix form.

[0015] Preferably, the method comprises the following steps: bonding the first semiconductor wafer, the at least second semiconductor wafer and the third semiconductor wafer according to a hybrid bonding technique. Additionally or alternatively, the method comprises the following steps: bonding the first semiconductor wafer, the at least second semiconductor wafer and the third semiconductor wafer according to a dielectric bonding technique (e.g. fusion bonding).

[0016] Further alternatively, the bonding between the first semiconductor wafer, the at least second semiconductor wafer and the third semiconductor wafer may include at least one dielectric bond and at least one hybrid bond.

[0017] Preferably, the method comprises the step of processing a plurality of first contacts corresponding to each of the plurality of first semiconductor light emitting or light detecting devices on the first semiconductor wafer. Furthermore, the method comprises the step of processing a plurality of second contacts corresponding to each of the plurality of second semiconductor light emitting or light detecting devices on the at least second semiconductor wafer. Furthermore, the method comprises the step of processing a plurality of third contacts connected to the integrated circuit (preferably a complementary metal oxide semiconductor integrated circuit) on the third semiconductor wafer.

[0018] Furthermore, the method comprises the step of bonding the first semiconductor wafer, the at least second semiconductor wafer and the third semiconductor wafer in a stacked manner such that the plurality of first semiconductor light emitting or light detecting devices are individually connected to the integrated circuit via the first contact and the third contact, and the at least plurality of second semiconductor light emitting or light detecting devices are individually connected to the integrated circuit via the second contact and the third contact. Advantageously, a monolithic multi-color display or imaging or sensor die that can be driven by a single ASIC can be realized.

[0019] Preferably, the method comprises the following steps: processing the electrical connection between the plurality of first semiconductor light emitting or light detecting devices and the integrated circuit (preferably complementary metal oxide semiconductor integrated circuit) and / or the electrical connection between the at least plurality of second semiconductor light emitting or light detecting devices and the integrated circuit by through-holes. Advantageously, vertical interconnection between stacked wafers can be effectively realized to realize compact 3D realization of multi-color display or imager, especially 3D components with small form factor.

[0020] Preferably, the method comprises the steps of: processing the electrical connections between the plurality of first semiconductor light emitting or light detecting devices and the integrated circuit, and the electrical connections between the at least a plurality of second semiconductor light emitting or light detecting devices and the integrated circuit simultaneously or sequentially. Advantageously, additional design flexibility and trade-off factors have been incorporated, such as a trade-off between simultaneous via implementation using multiple hard masks and sequential via implementation using a reduced number of hard masks.

[0021] Preferably, the method includes the following steps: processing a first plurality of optical structures corresponding to each of the plurality of first semiconductor light emitting or light detecting devices on the first semiconductor wafer, and processing at least a second plurality of optical structures corresponding to each of the plurality of second semiconductor light emitting or light detecting devices on the at least second semiconductor wafer.

[0022] Alternatively, the method includes the following steps: processing a first plurality of optical structures corresponding to each of the plurality of first semiconductor light emitting or light detecting devices, and at least a second plurality of optical structures corresponding to each of the plurality of second semiconductor light emitting or light detecting devices, in particular after bonding the first semiconductor wafer, the at least second semiconductor wafer and the third semiconductor wafer in a stacked manner.

[0023] In this regard, the first plurality of optical structures and the second plurality of optical structures include digital lenses, digital lens systems, resonant cavity structures, light scattering layers, or combinations thereof. Advantageously, the optical coupling of individual light emitting or light detecting devices on different semiconductor wafers can be effectively optimized for the respective wavelengths of the emitted or detected light, in particular by combining wafer-level optical devices.

[0024] Preferably, the method comprises the following steps: processing a first plurality of side wall reflectors corresponding to each of the plurality of first semiconductor light emitting or light detecting devices on the first semiconductor wafer, and processing at least a second plurality of side wall reflectors corresponding to each of the plurality of second semiconductor light emitting or light detecting devices on the at least second semiconductor wafer.

[0025] Advantageously, the optical and / or electrical isolation of individual light emitting or light detecting devices on different semiconductor wafers can be effectively optimized for the respective wavelengths of the emitted or detected light.

[0026] Preferably, the method further includes the following steps: cutting a first epitaxial wafer configured to emit or detect light of a first color and transferring it to the first semiconductor wafer so as to process the multiple first light emitting or light detecting devices on the first semiconductor wafer, and repeating the above steps for at least a second epitaxial wafer configured to emit or detect light of a second color so as to process the at least multiple second light emitting or light detecting devices on the at least second semiconductor wafer.

[0027] In this regard, the substrate size of the first semiconductor wafer and the second semiconductor wafer (e.g., 300 mm) may correspond to the substrate size of the third semiconductor wafer (e.g., 300 mm CMOS wafer). In addition, the substrate size of the above-mentioned epitaxial wafer may be different from (e.g., smaller than) the substrate size of the semiconductor wafer and / or CMOS wafer. This advantageously helps to provide an integrated flow that is compatible with existing CMOS wafer factories, and thus can be manufactured in large quantities.

[0028] Preferably, the method comprises the following steps: bonding the first semiconductor wafer, the at least second semiconductor wafer and the third semiconductor wafer in a stacked manner to form individual pixel elements of a multi-color display or imaging device, the pixel elements comprising at least one first semiconductor light emitting or light detecting device, and at least one second semiconductor light emitting or light detecting device. In this regard, the at least one first semiconductor light emitting or light detecting device and the at least one second light emitting or light detecting device are arranged as a group of adjacent pixels to form individual pixel elements of the multi-color display or imaging device.

[0029] Preferably, the method comprises the step of forming individual pixel elements of the multi-color display or imaging device with a pixel pitch preferably less than 5 microns, more preferably with a pixel pitch of 3 microns. Advantageously, a high spatial resolution can be achieved.

[0030] According to a second aspect of the present invention, a multicolor display or imaging device is provided. The multicolor display or imaging device comprises: a first semiconductor wafer, the first semiconductor wafer comprises a plurality of first semiconductor light emitting or light detecting devices, each of which is configured to emit or detect light of a first color; at least a second semiconductor wafer, the second semiconductor wafer comprises at least a plurality of second semiconductor light emitting or light detecting devices, each of which is configured to emit or detect light of a second color; and a third semiconductor wafer, the third semiconductor wafer comprises an integrated circuit having a driving device, the driving device being used to drive the plurality of first semiconductor light emitting or light detecting devices and the plurality of second semiconductor light emitting or light detecting devices.

[0031] In this regard, the first semiconductor wafer, the at least second semiconductor wafer and the third semiconductor wafer are bonded together in a stacked manner. Preferably, the first semiconductor wafer, the at least second semiconductor wafer and the third semiconductor wafer are bonded together according to a hybrid bonding technique. Additionally or alternatively, the first semiconductor wafer, the at least second semiconductor wafer and the third semiconductor wafer are bonded together according to a dielectric bonding technique. Further alternatively, the bonding between the first semiconductor wafer, the at least second semiconductor wafer and the third semiconductor wafer may include at least one dielectric bond and at least one hybrid bond.

[0032] Preferably, the first semiconductor wafer and the second semiconductor wafer may be handle wafers, so that substrates of the first semiconductor wafer and the second semiconductor wafer may be removed or etched respectively after they are each bonded in a stacked manner.

[0033] Preferably, the first semiconductor chip includes a first plurality of optical structures corresponding to each of the plurality of first semiconductor light emitting or light detecting devices, and the at least second semiconductor chip includes at least a second plurality of optical structures corresponding to each of the plurality of second semiconductor light emitting or light detecting devices.

[0034] Alternatively, the multi-color display or imaging device includes a first plurality of optical structures corresponding to each of the plurality of first semiconductor light emitting or light detecting devices and at least a second plurality of optical structures corresponding to each of the plurality of second semiconductor light emitting or light detecting devices.

[0035] In this regard, the first plurality of optical structures and the second plurality of optical structures include digital lenses, digital lens systems, resonant cavity structures, light scattering layers, or combinations thereof.

[0036] Preferably, the first semiconductor wafer comprises a first plurality of side wall reflectors corresponding to each of the plurality of first semiconductor light emitting or light detecting devices, and the at least second semiconductor wafer comprises at least a second plurality of side wall reflectors corresponding to each of the plurality of second semiconductor light emitting or light detecting devices.

[0037] In this regard, the first plurality of sidewall reflectors and the second plurality of sidewall reflectors include distributed Bragg reflectors, metal mirrors, absorbing layers, or combinations thereof.

[0038] Preferably, the first semiconductor wafer comprises a substrate wafer having at least one compound semiconductor layer (especially a silicon wafer or a sapphire wafer or a germanium wafer or a GaAs wafer), or is a compound semiconductor wafer.

[0039] Furthermore, the second semiconductor wafer comprises a substrate wafer (in particular a silicon wafer or a sapphire wafer or a germanium wafer or a GaAs wafer) having at least one compound semiconductor layer, or is a compound semiconductor wafer.

[0040] Preferably, the plurality of first semiconductor light emitting or light detecting devices and the at least plurality of second semiconductor light emitting or light detecting devices are compound semiconductor light emitting or light detecting devices, preferably III-V compound semiconductor light emitting or light detecting devices.

[0041] Alternatively, the plurality of first semiconductor light emitting or light detecting devices belong to semiconductor light emitting or light detecting devices of a first group of compounds, especially gallium nitride (GaN), and the at least plurality of second semiconductor light emitting or light detecting devices belong to semiconductor light emitting or light detecting devices of a second group of compounds, especially indium gallium arsenide (InGaAs), aluminum indium gallium phosphide (AlInGaP).

[0042] It should be noted that the multi-color display or imaging device according to the second aspect corresponds to the method according to the first aspect and its implementation form. Therefore, the multi-color display or imaging device according to the second aspect achieves the same advantages and effects as the method of the first aspect and its corresponding implementation form. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Exemplary embodiments of the present invention will now be further explained by way of example only and not limitation with reference to the accompanying drawings. In the drawings:

[0044] Figure 1 An exemplary embodiment of the method according to the first aspect of the present invention is shown;

[0045] Figure 2A-2B An exemplary scheme for processing a light emitting device on a semiconductor wafer is shown;

[0046] Figure 3A-Figure 3F A first exemplary scheme for manufacturing a multi-color display device is shown;

[0047] Figure 4A-4D A second exemplary approach to manufacturing a multi-color display device is shown;

[0048] Figure 5 An exemplary RGB pixel arrangement for a multi-color display device is shown;

[0049] Figure 6A-Figure 6I A third exemplary approach to manufacturing a multi-color display device is shown; and

[0050] Figure 7A-7C A fourth exemplary approach to fabricating a multi-color display device is shown. DETAILED DESCRIPTION

[0051] Reference will now be made in detail to embodiments of the present invention, examples of which are shown in the accompanying drawings. However, the following embodiments of the present invention may be variously modified, and the scope of the present invention is not limited by the following embodiments. The reference numerals of similar entities in different embodiments are partially omitted.

[0052] exist Figure 1 , an exemplary embodiment of a method 100 according to the first aspect of the present invention is shown. In a first step 101, a plurality of first semiconductor light emitting or light detecting devices are processed on a first semiconductor wafer, each of which is configured to emit or detect light of a first color. In a second step 102, at least a plurality of second semiconductor light emitting or light detecting devices are processed on at least a second semiconductor wafer, each of which is configured to emit or detect light of a second color.

[0053] In a third step 103, an integrated circuit is processed on the third semiconductor wafer, in particular an integrated circuit having a driver device for driving a plurality of first semiconductor light emitting or light detecting devices and a plurality of second semiconductor light emitting or light detecting devices. In a fourth step 104, the first semiconductor wafer, at least the second semiconductor wafer and the third semiconductor wafer are bonded together in a stacked manner.

[0054] Reference Figure 2A-2B , shows an exemplary scheme for processing a light emitting device 2011 on a blank semiconductor wafer 202. Figure 2A-2B The processing of light emitting devices (eg, LEDs) is exemplarily shown, but the basic processing techniques can be similarly used to process light detecting devices (eg, PDs).

[0055] In particular, Figure 2A The process of adjusting an epitaxial wafer 201 (e.g., a GaN epitaxial wafer) from a smaller substrate size (e.g., 100 mm-200 mm) to a target substrate size (e.g., 300 mm) is shown. In this regard, the epitaxial wafer 201 is cut into die sizes corresponding to a target display size (e.g., a target light emitting area of ​​6 mm x 4 mm for full high definition (FHD)). Thereafter, a blank silicon wafer 202 having a target substrate size (e.g., 300 mm) is refilled with the cut epitaxial dies to form a semiconductor wafer 203 in accordance with one or more aspects of the present invention.

[0056] Figure 2B The semiconductor wafer 203 is shown in detail. In particular Figure 2BTwo tube cores (for example, tube core 2011) on the wafer 203 are shown, in which light-emitting devices (not shown) will be formed. Therefore, the transferred epitaxial tube core 2011 is further processed to form a light-emitting device. In particular, the gap between the tube cores can be filled with a filling material 215 (for example, SiO2, SiN), and the original epitaxial growth substrate 210 can be removed. After that, the light-emitting mesa structure can be formed. In addition, an ohmic contact, such as a cathode contact, can be formed for each mesa structure.

[0057] The transferred epitaxial die 2011 may include a first highly doped layer (e.g., an n-type doped layer) 211, a light emitting layer (e.g., an MQW layer) 212, and a second highly doped layer (e.g., a p-type doped layer) 213 in a stacked arrangement, wherein the stack is bonded to the blank semiconductor wafer 202 via a dielectric layer 214 (e.g., on the side of the p-type doped layer 213). A light emitting mesa structure may be formed on the stacked arrangement of the epitaxial die 2011. The mesa sidewalls may be covered by a sidewall reflector (e.g., a distributed Bragg reflector (DBR)), which may be used for the purpose of mesa sidewall passivation.

[0058] The process can be applied to three separate epitaxial wafers corresponding to three wavelengths of light, such as epitaxial wafers for emitting red light, green light, and blue light, thereby realizing different semiconductor wafers with a target substrate size having respective red, green, or blue light-emitting mesa structures or light-emitting devices or light-emitting diodes.

[0059] Reference Figure 3A-Figure 3F , shows a first exemplary scheme for manufacturing a multi-color display device. Figure 3A-Figure 3F The processing of a multicolor display device including a light emitting device (e.g., LED) is exemplarily shown, but the basic processing technology can be similarly used for processing an imaging or sensor device including a light detecting device (e.g., PD). In particular, Figure 3A A process of bonding a first semiconductor wafer 310 to a CMOS wafer 300 is shown.

[0060] The CMOS wafer may be, for example, a 300 mm CMOS wafer. The CMOS wafer 300 may be processed, for example, by a Cu damascene process or a dual damascene process to include a CMOS IC 304 and a plurality of contacts electrically connected to the CMOS IC 304, the contacts being exemplarily a first contact to the CMOS IC 301, in particular, a plurality of first contacts to the CMOS IC 301, a first contact to the CMOS IC 302, in particular, a plurality of second contacts to the CMOS IC 302, and a third contact to the CMOS IC 303, in particular, a plurality of third contacts to the CMOS IC 303.

[0061] The first semiconductor wafer 310 may correspond to the semiconductor wafer 203, wherein additional post-processing may be performed, such as removing the blank wafer substrate 202 by chemical mechanical planarization (CMP) and / or grinding. The first semiconductor wafer 310 includes a plurality of first light emitting devices, illustratively light emitting devices or light emitting diodes (LEDs) 3101.

[0062] LED 3101 may include an n-type doped layer 312, an MQW layer 313, and a p-type doped layer 314 provided with a cathode contact or n-type contact 311, and may be configured to emit blue light. LED 3101 may be further processed to include a lens or lens system 315 and an anode contact or p-type contact 316, preferably a common p-type contact for a plurality of first light emitting devices. P-type contact 316 or common p-type contact may include or be a transparent ohmic contact.

[0063] The lens or lens system 315 may include or be a digital lens, a digital lens system, a resonant cavity structure, a light scattering layer, or a combination thereof. In this regard, the lens or lens system 315 may be optimized for the emission wavelength of the LED 3101 (eg, emission of blue light).

[0064] The LED 3101 can be further processed to include a bonding pad electrically coupled to the n-type contact 311 to facilitate metal bonding. The processing of the bonding pad can be performed by a Cu damascene process or a dual damascene process. Afterwards, the first semiconductor wafer 310 can be hybrid bonded 317 to the CMOS wafer 300, i.e., wafer-to-wafer bonding, in particular by forming a dielectric bond between the first semiconductor wafer 310 and the CMOS wafer 300, and by forming a metal bond between the bonding pad of the LED 3101 (i.e., the top bonding pad) and the first contact with the CMOS IC 301 (i.e., the bottom bonding pad).

[0065] Preferably, additional processing of the first semiconductor wafer 310 (eg, removal of blank wafer substrate), lens processing, and p-type contact processing may be performed after hybrid bonding of the first semiconductor wafer 110 to the CMOS wafer 300. Alternatively, additional processing may be performed before hybrid bonding.

[0066] exist Figure 3B , a process of implementing a via is shown, particularly through the first semiconductor wafer 310. For example, a first via 305 may be formed to electrically extend a second contact to the CMOS IC 302, and a second via 307 may be formed to electrically extend a third contact to the CMOS IC 303, particularly through the first semiconductor wafer 310.

[0067] In this example, the first through hole 305 and the second through hole 307 can be formed simultaneously. For example, two hard masks (e.g., SiN or SiO2-based etching masks) can be used to etch corresponding deep through holes to the second contact 302 and the third contact 303, respectively. Afterwards, these deep through holes can be filled with copper, for example, by a copper damascene process. At this stage, another bonding pad 306 corresponding to the second contact 302 can be formed on the first through hole 305, for example, by a Cu damascene process, to facilitate metal bonding.

[0068] Illustratively, in this example, the first through hole 305 and the second through hole 307 may have a width of 1 micrometer to 2 micrometers and a depth of 2 micrometers, and in this example, the other bonding pad 306 may have a width of 1 micrometer and a depth of about 500 nanometers.

[0069] exist Figure 3C , a process of bonding the second semiconductor wafer 320 to the CMOS wafer 300 is shown, particularly a process of bonding by stacking the second semiconductor wafer 320 on top of the first semiconductor wafer 310.

[0070] The second semiconductor wafer 320 may correspond to the semiconductor wafer 203, wherein additional post-processing may be performed, such as removing the blank wafer substrate 202 by CMP and / or grinding and / or etching. The second semiconductor wafer 320 includes a plurality of second light emitting devices, exemplarily light emitting devices or LEDs 3201.

[0071] LED 3201 may include an n-type doped layer 322, an MQW layer 323, and a p-type doped layer 324 provided with a cathode contact or n-type contact 321, and may be configured to emit green light. LED 3201 may be further processed to include a lens or lens system 325 and an anode contact or p-type contact 326, preferably a common p-type contact for a plurality of second light emitting devices. P-type contact 326 or common p-type contact may include or be a transparent ohmic contact.

[0072] The lens or lens system 325 may include or be a digital lens, a digital lens system, a resonant cavity structure, a light scattering layer, or a combination thereof. In this regard, the lens or lens system 325 may be optimized for the emission wavelength of the LED 3201 (eg, emitted green light).

[0073] The LED 3201 can be further processed to include a bonding pad electrically coupled to the n-type contact 321 to facilitate metal bonding. The processing of the bonding pad can be performed by a Cu damascene process or a dual damascene process. Afterwards, the second semiconductor wafer 320 can be hybrid bonded 327 to the CMOS wafer 300, in particular by forming a dielectric bond between the second semiconductor wafer 320 and the first semiconductor wafer 310, and by forming a metal bond between the bonding pad of the LED 3201 (i.e., the top bonding pad) and another bonding pad 306 (i.e., the bottom bonding pad) corresponding to the second contact to the CMOS IC 302.

[0074] Preferably, additional processing of the second semiconductor wafer 320 (eg, removal of blank wafer substrate), lens processing, and p-type contact processing may be performed after hybrid bonding of the second semiconductor wafer 320 to the CMOS wafer 300. Alternatively, additional processing may be performed before hybrid bonding.

[0075] exist Figure 3D , a process for extending a via is shown, particularly through the second semiconductor wafer 320. For example, the second via 307 may be extended to electrically extend the third contact to the CMOS IC 303, particularly through the first semiconductor wafer 310 and further through the second semiconductor wafer 320.

[0076] For example, another hard mask (e.g., an etching mask based on SiN or SiO2) may be used to etch a deep via toward the second via 307, especially to the edge of the second via 307 at the bonding interface 327. Afterwards, the deep via may be filled with copper, for example, by a copper damascene process. At this stage, another bonding pad 308 corresponding to the third contact 303 may be formed on the extended second via 307, for example, by a Cu damascene process, to facilitate metal bonding.

[0077] Exemplarily, the extension of the second through hole 307 may have, for example, a width of 1 micron-2 microns and a depth of 2 microns, and the further bonding pad 308 may have, for example, a width of 1 micron and a depth of 500 nanometers.

[0078] exist Figure 3E , a process of bonding the third semiconductor wafer 330 to the CMOS wafer 300 is shown, particularly a process of bonding by stacking the third semiconductor wafer 330 on top of the second semiconductor wafer 320.

[0079] The third semiconductor wafer 330 may correspond to the semiconductor wafer 203 , wherein additional post-processing may be performed, such as removing the blank wafer substrate 202 by CMP and / or grinding and / or etching. The third semiconductor wafer 330 includes a plurality of third light emitting devices, exemplarily light emitting devices or LEDs 3301 .

[0080] LED 3301 may include an n-type doped layer 332, an MQW layer 333, and a p-type doped layer 334 provided with a cathode contact or n-type contact 331, and may be configured to emit red light. LED 3301 may be further processed to include a lens or lens system 335 and an anode contact or p-type contact 336, preferably a common p-type contact for a plurality of third light emitting devices. P-type contact 336 or common p-type contact may include or be a transparent ohmic contact.

[0081] The lens or lens system 335 may include or be a digital lens, a digital lens system, a resonant cavity structure, a light scattering layer, or a combination thereof. In this regard, the lens or lens system 335 may be optimized for the emission wavelength of the LED 3301 (eg, emitted red light).

[0082] The LED 3301 can be further processed to include a bonding pad electrically coupled to the n-type contact 331 to facilitate metal bonding. The processing of the bonding pad can be performed by a Cu damascene process or a dual damascene process. Afterwards, the third semiconductor wafer 330 can be hybrid bonded 337 to the CMOS wafer 300, in particular by forming a dielectric bond between the third semiconductor wafer 330 and the second semiconductor wafer 320, and by forming a metal bond between the bonding pad of the LED 3301 (i.e., the top bonding pad) and another bonding pad 308 (i.e., the bottom bonding pad) corresponding to the third contact to the CMOS IC 303.

[0083] Preferably, additional processing of the third semiconductor wafer 330 (eg, removal of blank wafer substrate), lens processing, and p-type contact processing may be performed after hybrid bonding of the third semiconductor wafer 330 to the CMOS wafer 300. Alternatively, additional processing may be performed before hybrid bonding.

[0084] exist Figure 3F, a process of implementing PASS / METPASS contacts is shown, in particular to facilitate electrical access to LED 3101, LED 3201, and LED 3301. A first PASS / METPASS contact 318 may be formed by using a first mask and by etching (e.g., dry etching) dielectric layers of the third semiconductor wafer 330 and the second semiconductor wafer 320, and by stopping the etching process at the first semiconductor wafer 310, in particular at a probe pad electrically connected to the p-type contact 316 of the first semiconductor wafer 310. Preferably, the etching may be configured to stop selectively (i.e., selective to copper) at the probe pad of the first semiconductor wafer 310.

[0085] In addition, the second PASS / METPASS contact 328 can be formed by using a second mask and by etching (e.g., dry etching) the dielectric layer of the third semiconductor wafer 330, and by stopping the etching process at the second semiconductor wafer 320, especially at the probe pad electrically connected to the p-type contact 326 of the second semiconductor wafer 320. Preferably, the etching can be configured to stop selectively (i.e., selective to copper) at the probe pad of the second semiconductor wafer 320.

[0086] In addition, the third PASS / METPASS contact 338 can be formed by using a third mask and by etching (e.g., dry etching) the dielectric layers of the third semiconductor wafer 330, the second semiconductor wafer 320, and the first semiconductor wafer 310, and by stopping the etching process at the CMOS wafer 300, especially at the probe pad electrically connected to the CMOS IC 304. Preferably, the etching can be configured to stop selectively (i.e., selective to copper) at the probe pad of the CMOS wafer 300.

[0087] Thus, PASS / METPASS contacts 318, 328, 338 may be formed by etching corresponding large vias through the stack, filling the large vias with metal (e.g., aluminum), and subsequently isolating by etching the metal. Due to the common contact nature of the p-type contacts, one PASS / METPASS contact per layer may be sufficient to contact the LEDs (e.g., one contact 318 may be sufficient to contact all of the LEDs 3101). However, multiple PASS / METPASS contacts may be processed per layer in accordance with the techniques described above.

[0088] The PASS / METPASS contacts 318, 328, 338 may have a size of about 40 μm x 60 μm. The first PASS / METPASS contact 318, the second PASS / METPASS contact 328, and the third PASS / METPASS contact 338 may be formed simultaneously, i.e., three simultaneous etching processes. Alternatively, the first PASS / METPASS contact 318, the second PASS / METPASS contact 328, and the third PASS / METPASS contact 338 may be formed sequentially, i.e., three sequential etching processes.

[0089] Thus, there is shown a pixel-level arrangement of a multi-color or RGB display device 350. Exemplarily, the RGB display device 350 may include: a first semiconductor wafer 310 including blue LEDs 3101, a second semiconductor wafer 320 including green LEDs 3201, and a third semiconductor wafer 330 including red LEDs 3301, which are stacked in a three-dimensional configuration (3D stack) and hybrid-bonded to the CMOS wafer 300. Each of the blue LEDs 3101, the green LEDs 3201, and the red LEDs 3301 is provided with respective wafer-level optics optimized for the respective emission wavelengths.

[0090] Reference Figure 4A-4D , shows a second exemplary approach to manufacturing a multi-color display device. Figure 4A-4D The processing of a multi-color display device including a light emitting device (eg, LED) is exemplarily shown, but the basic processing technology can be similarly used for processing an imaging or sensor device including a light detecting device (eg, PD).

[0091] A second exemplary method for manufacturing a multi-color display device and a method according to Figure 3A-Figure 3F The first exemplary embodiment is different in that the through holes are implemented sequentially to reduce the number of hard masks. However, the manufacturing sequence and structure of the multi-color display device remain unchanged.

[0092] exist Figure 4A , a process for realizing a first through hole, in particular a process for realizing a first through hole through the first semiconductor wafer 310, is shown. The process may be followed by reference to Figure 3A The process shown and / or can be used as a reference Figure 3B For example, a first through hole 405 may be formed to electrically extend the second contact to the CMOS IC 302 , in particular, to electrically extend through the first semiconductor wafer 310 .

[0093] For example, a deep via hole to the second contact 302 may be etched using a hard mask (e.g., an SiN or SiO2-based etch mask). Afterwards, the deep via hole may be filled with copper, for example, by a copper damascene process. At this stage, another bonding pad 406 corresponding to the second contact 302 may be formed on the first via hole 405, for example, by a Cu damascene process, to facilitate metal bonding.

[0094] By way of example, the first through hole 405 may have a width of 1 micron-2 microns and a depth of 2 microns, and the other bonding pad 406 may have a width of 1 micron and a depth of 500 nanometers.

[0095] exist Figure 4B , a process of bonding the second semiconductor wafer 320 to the CMOS wafer 300 is shown, in particular, a process of bonding by stacking the second semiconductor wafer 320 on top of the first semiconductor wafer 310. This process may correspond to the process described in reference to Figure 3C The process shown is the same, and the processing of the second semiconductor wafer 320 may remain unchanged.

[0096] Thus, the second semiconductor chip 320 can be hybrid bonded 327 to the CMOS chip 300, in particular by forming a dielectric bond between the second semiconductor chip 320 and the first semiconductor chip 310, and by forming a metal bond between a bonding pad of the LED 3201 (i.e., the top bonding pad) and another bonding pad 406 (i.e., the bottom bonding pad) corresponding to a second contact to the CMOS IC 302.

[0097] exist Figure 4C , the process of implementing the second through hole is shown, especially the process of implementing the second through hole through the second semiconductor wafer 320 and further through the first semiconductor wafer 310. This process can be followed by reference to Figure 3C The process shown and / or can be used as a reference Figure 3D For example, a second through-hole 407 may be formed to electrically extend the third contact to the CMOS IC 303 , in particular through the first semiconductor wafer 310 and further through the second semiconductor wafer 320 .

[0098] For example, a deep via hole to the third contact 303 may be etched using a hard mask (e.g., an SiN or SiO2-based etch mask). Afterwards, the deep via hole may be filled with copper, for example, by a copper damascene process. At this stage, another bonding pad 408 corresponding to the third contact 303 may be formed on the second via hole 407, for example, by a Cu damascene process, to facilitate metal bonding.

[0099] By way of example, the second through hole 407 may have a width of, for example, 1 micron to 2 microns and a depth of 4 microns, and the further bonding pad 408 may have a width of, for example, 1 micron and a depth of 500 nanometers.

[0100] exist Figure 4D , a process of bonding the third semiconductor wafer 330 to the CMOS wafer 300 is shown, in particular, a process of bonding by stacking the third semiconductor wafer 330 on top of the second semiconductor wafer 320. This process may correspond to the following Figure 3E The process shown is the same, and the processing of the third semiconductor wafer 330 may remain unchanged.

[0101] Thus, the third semiconductor chip 330 can be hybrid bonded 337 to the CMOS chip 300, in particular by forming a dielectric bond between the third semiconductor chip 330 and the second semiconductor chip 320, and by forming a metal bond between a bonding pad of the LED 3301 (i.e., the top bonding pad) and another bonding pad 408 (i.e., the bottom bonding pad) corresponding to the third contact to the CMOS IC 303.

[0102] exist Figure 5 , an exemplary RGB pixel arrangement of a multi-color display device 350 is shown. The arrangement exemplarily shows four red LEDs 4101-4104 implemented, for example, on a first stacked semiconductor wafer, three green LEDs 4201-4204 implemented, for example, on a second stacked semiconductor wafer, and four blue LEDs 4301-4304 implemented, for example, on a third stacked semiconductor wafer, whereby the semiconductor wafers are hybrid-bonded to a CMOS wafer to drive the respective LEDs.

[0103] Herein, one or more LEDs may correspond to sub-pixels of the display device 350, and an RGB pixel may include at least one red LED 4101-4104, at least one green LED 4201-4204, and at least one blue LED 4301-4304. In addition, semiconductor wafers may be configured such that when stacked on top of each other, a pixel pitch of less than 5 microns may be achieved.

[0104] In addition, the stacked semiconductor wafers can be configured so that when stacked on top of each other, the top LED does not block the emission of the bottom LED or hinder the emission width or angle of the bottom LED, such as green LEDs 4201-4204 on top of blue LEDs 4301-4304 in the stacked arrangement, green LEDs 4201-4204 and / or red LEDs 4101-4104 on top of blue LEDs 4301-4304. The above-described exemplary RGB pixel arrangement can be similarly performed for imaging or sensor devices including pixelated light detection devices (e.g., PDs), especially at different levels of the stacked arrangement.

[0105] Reference Figure 6A-Figure 6I , shows a third exemplary approach to manufacturing a multi-color display device. Figure 6A-Figure 6I The processing for a multicolor display device including a light emitting device (e.g., LED) is exemplarily shown, but the basic processing technology can be similarly used for processing for an imaging or sensor device including a light detecting device (e.g., PD). In particular, Fig. 6A The process of bonding a first semiconductor wafer 610 to a blank carrier wafer 600 is shown.

[0106] The carrier wafer may be a 300 mm silicon wafer. The first semiconductor wafer 610 may correspond to the semiconductor wafer 203, wherein additional post-processing may be performed, such as removing the growth substrate 210 by CMP and / or grinding and / or etching. The first semiconductor wafer 610 includes a plurality of first light emitting devices, illustratively light emitting devices or light emitting diodes (LEDs) 6101.

[0107] LED 6101 may include n-type doped layer 612 provided with cathode contact or n-type contact 611 , MQW layer 613 , and p-type doped layer 614 , and may be configured to emit blue light. First semiconductor wafer 610 may include substrate 615 corresponding to blank silicon wafer 202 .

[0108] In this regard, the first semiconductor wafer 610 may be flipped over and may be dielectrically bonded 616 (i.e., wafer-to-wafer dielectric bonding) to the carrier wafer 600, that is, the polished n-type doped layer 611 side of the first semiconductor wafer 610 may be bonded to the carrier wafer 600 through a dielectric layer. Thereafter, the substrate 615 corresponding to the blank silicon wafer 202 may be removed by CMP and / or grinding and / or etching.

[0109] Figure 6BThe process of bonding the second semiconductor wafer 620 to the first semiconductor wafer 610 is shown. The second semiconductor wafer 620 may correspond to the semiconductor wafer 203, where additional post-processing may be performed, such as removing the growth substrate 210 by CMP and / or grinding and / or etching. The second semiconductor wafer 620 includes a plurality of second light emitting devices, such as light emitting devices or light emitting diodes (LEDs) 6201.

[0110] The LED 6201 may include an n-type doped layer 622 provided with a cathode contact or n-type contact 621 , an MQW layer 623 , and a p-type doped layer 624 , and may be configured to emit green light. The second semiconductor wafer 620 may include a substrate 625 corresponding to the blank silicon wafer 202 .

[0111] In this regard, the second semiconductor wafer 620 can be flipped over and can be dielectrically bonded 626 (i.e., wafer-to-wafer dielectric bonding) to the top of the first semiconductor wafer 610, that is, the polished n-type doped layer 621 side of the second semiconductor wafer 620 can be bonded through a dielectric layer to the polished p-type doped layer 614 side of the first semiconductor wafer 610. Afterwards, the substrate 625 corresponding to the blank silicon wafer 202 can be removed by CMP and / or grinding and / or etching.

[0112] Figure 6C The process of bonding the third semiconductor wafer 630 to the second semiconductor wafer 620 is shown. The third semiconductor wafer 630 may correspond to the semiconductor wafer 203, where additional post-processing may be performed, such as removing the growth substrate 210 by CMP and / or grinding and / or etching. The third semiconductor wafer 630 includes a plurality of third light emitting devices, such as light emitting devices or light emitting diodes (LEDs) 6301.

[0113] The LED 6301 may include an n-type doped layer 632 provided with a cathode contact or n-type contact 631 , an MQW layer 633 , and a p-type doped layer 634 , and may be configured to emit red light. The third semiconductor wafer 630 may include a substrate 625 corresponding to the blank silicon wafer 202 .

[0114] In this regard, the third semiconductor wafer 630 can be flipped over and can be dielectrically bonded 636 (i.e., wafer-to-wafer dielectric bonding) to the top of the second semiconductor wafer 620, that is, the polished n-type doped layer 631 side of the third semiconductor wafer 630 can be bonded to the polished p-type doped layer 624 side of the second semiconductor wafer 620 via a dielectric layer.

[0115] Fig.6DThe process of removing the upper side of the stacked semiconductor wafers is shown. In this regard, the stacked arrangement can be turned over, in particular the stacked arrangement of the carrier wafer 600, the first semiconductor wafer 601 on top of the carrier wafer 600, the second semiconductor wafer 602 on top of the first semiconductor wafer 601, and the third semiconductor wafer 603 on top of the second semiconductor wafer 602. Afterwards, the substrate of the carrier wafer 600 can be removed by CMP and / or grinding and / or etching.

[0116] exist Fig. 6E , a process for realizing a through hole, in particular a process for realizing a through hole through a semiconductor wafer is shown. For example, a first through hole 604 can be formed by etching (e.g., dry etching) a first deep through hole to the n-type contact 611 of the LED 6101 according to a first hard mask (e.g., based on a SiN or SiO2 etching mask), and by filling the first deep through hole with copper (e.g., by a Cu damascene process). A second through hole 605 can be formed by etching a second deep through hole to the n-type contact 621 of the LED 6201 according to a second hard mask, and by filling the second deep through hole with copper (e.g., by a Cu damascene process).

[0117] Similarly, the third through hole 606 can be formed by etching a third deep through hole to the n-type contact 631 of the LED 6301 according to the third hard mask, and by filling the third deep through hole with copper (e.g., by a Cu damascene process). In this regard, the first through hole 604, the second through hole 605, and the third through hole 606 can have a width of 1 micron-2 microns and a depth of 500 nanometers, 2 microns, and 4 microns, respectively, for example.

[0118] Alternatively, the first through hole 604, the second through hole 605, and the third through hole 606 can be realized by etching a first deep through hole, a second deep through hole, and a third deep through hole, respectively, according to a common hard mask, especially a common hard mask having a high etch stop selectivity to the material of the n-type contact (e.g., not having a high selectivity to the titanium nitride contact).

[0119] exist Fig. 6F , a process of implementing bonding pads, particularly for LEDs, is shown. For example, a first bonding pad 607 may be formed on a first through hole 604, a second bonding pad 608 may be formed on a second through hole 605, and a third bonding pad 609 may be formed on a third through hole 606, particularly for facilitating metal bonding.

[0120] The first bonding pad 607, the second bonding pad 608 and the third bonding pad 609 can be formed according to a 500 nanometer Cu damascene process, and the corresponding surfaces can be planarized or polished. Therefore, the first bonding pad 607, the second bonding pad 608, and the third bonding pad 609 can have a width of 1 micrometer and a depth of 500 nanometers, for example.

[0121] Figure 6G The process of bonding the stacked semiconductor wafers, especially the first semiconductor wafer 610, the second semiconductor wafer 620, and the third semiconductor wafer 630 to the CMOS wafer 300 is shown. The stacked semiconductor wafers may be flipped and hybrid bonded to the CMOS wafer 300. In particular, the polished surfaces at the bonding pads of the stacked semiconductor wafers may be dielectrically bonded to the CMOS wafer 300 through a dielectric material.

[0122] Furthermore, the first bonding pad 607 of the first semiconductor wafer 610, i.e., the bonding pad 607 of the LED 6101, can be metal-bonded to the first contact 301 of the CMOS wafer 300. Furthermore, the second bonding pad 608 of the second semiconductor wafer 620, i.e., the bonding pad 608 of the LED 6201, can be metal-bonded to the second contact 302 of the CMOS wafer 300.

[0123] In addition, the third bonding pad 609 of the third semiconductor wafer 630, i.e., the bonding pad 609 of the LED 6301, can be metal-bonded to the third contact 303 of the CMOS wafer 300. Afterwards, the substrate 635 corresponding to the blank silicon wafer 202 can be removed from the third semiconductor wafer 630 by CMP and / or grinding and / or etching.

[0124] Figure 6H A process for realizing an anode or p-type contact, particularly for an LED, is shown. In this regard, a first anode or p-type contact 617 can be formed on the first semiconductor wafer 610, for example, by a Cu damascene or dual damascene process through the third semiconductor wafer 630 and further through the second semiconductor wafer 620, particularly for electrically coupling the p-type doped layer 614 of the LED 6101.

[0125] In addition, a second anode or p-type contact 627 can be formed on the second semiconductor wafer 620 through the third semiconductor wafer 630, for example, by a Cu damascene or dual damascene process, in particular for electrically coupling the p-type doped layer 624 of the LED 6201. In addition, a third anode or p-type contact 637 can be formed on the third semiconductor wafer 630, for example, by a Cu damascene or dual damascene process, in particular for electrically coupling the p-type doped layer 634 of the LED 6301.

[0126] In this regard, the first anode 617 can be a common anode for all blue LEDs 6101 , the second anode 627 can be a common anode for all green LEDs 6201 , and the third anode 637 can be a common anode for all red LEDs 6301 .

[0127] Fig.6I A process for implementing a lens, particularly a wafer-level lens, for an LED is shown. In this regard, the LED 6101 can be further processed to include a first lens or lens system 618, preferably a first lens or lens system 618 optimized for the emission wavelength of the LED 6101 (eg, emitted blue light).

[0128] Additionally, LED 6201 can be further processed to include a second lens or lens system 628, preferably a second lens or lens system 628 optimized for the emission wavelength (e.g., emitted green light) of LED 6201. Additionally, LED 6301 can be further processed to include a third lens or lens system 638, preferably a third lens or lens system 638 optimized for the emission wavelength (e.g., emitted red light) of LED 6301.

[0129] The first lens or lens system 618, the second lens or lens system 628, and the third lens or lens system 638 may include or may be digital lenses, digital lens systems, resonant cavity structures, light scattering layers, or combinations thereof.

[0130] In addition, a process of implementing a PASS / METPASS contact is shown, in particular for facilitating electrical access to the CMOS IC 304. The PASS / METPASS contact 619 can be formed by using a mask and by etching (e.g., dry etching) the dielectric layers of the third semiconductor wafer 630, the second semiconductor wafer 620, and the first semiconductor wafer 610, and by stopping the etching process at the CMOS wafer 300, in particular at the probe pads electrically connected to the CMOS IC 304.

[0131] For example, the PASS / METPASS contact 619 may be formed by etching a large via through the stack, filling the large via with metal (e.g., aluminum), and then isolating by etching the metal. Preferably, the etching may be configured to stop selectively (i.e., selective to copper) at the probe pads of the CMOS wafer 300. The PASS / METPASS contact 619 may, for example, have dimensions of approximately 40 μm x 60 μm.

[0132] Thus, there is shown a pixel-level arrangement of a multi-color or RGB display device 650. Exemplarily, the RGB display device 650 may include: a first semiconductor wafer 610 including blue LEDs 6101, a second semiconductor wafer 620 including green LEDs 6201, and a third semiconductor wafer 630 including red LEDs 6301, which are stacked in a three-dimensional configuration (3D stack) and hybrid-bonded to the CMOS wafer 300. Each of the blue LEDs 6101, the green LEDs 6201, and the red LEDs 6301 is provided with respective wafer-level optics 618, 628, 638, which are optimized for the respective emission wavelengths.

[0133] Reference Figure 7A-7C , shows a fourth exemplary approach to manufacturing a multi-color display device. Figure 7A-7C The processing of a multi-color display device including a light emitting device (such as an LED) is exemplarily shown, but the basic processing technology can be similarly used for processing for an imaging or sensor device including a light detecting device (such as a PD).

[0134] A fourth exemplary method for manufacturing a multi-color display device and a method according to Figure 6A-Figure 6I The third exemplary embodiment differs in that the lens or lens system of the LED is already processed during the processing of the respective semiconductor wafer. However, the manufacturing sequence according to the third exemplary embodiment may remain unchanged.

[0135] Fig. 7A The process of implementing the first lens or lens system 718 on the first semiconductor wafer 610 is shown. This process can be used as a reference to the above Fig. 6A In this regard, after the substrate 615 of the first semiconductor wafer 610 corresponding to the blank silicon wafer 202 is removed by CMP and / or grinding and / or etching, a first anode or p-type contact 717 can be formed on the first semiconductor wafer 410, for example, by a Cu damascene or dual damascene process, in particular for electrically coupling the p-type doped layer 614 of the LED 6101.

[0136] Additionally, the LED 6101 can be further processed to include a first lens or lens system 718, preferably a first lens or lens system 718 optimized for the emission wavelength (e.g., emitted blue light) of the LED 6101. In this regard, the first lens or lens system 718 can include or be a digital lens, a digital lens system, a resonant cavity structure, a light scattering layer, or a combination thereof.

[0137] Figure 7B The process of implementing the second lens or lens system 728 on the second semiconductor wafer 620 is shown. This process can be used as a reference for the above Figure 6B In this regard, after the substrate 625 of the second semiconductor wafer 620 corresponding to the blank silicon wafer 202 is removed by CMP and / or grinding and / or etching, a second anode or p-type contact 727 can be formed on the second semiconductor wafer 610, for example, by a Cu damascene or dual damascene process, and the first anode or p-type contact 717 can be extended, in particular for electrically coupling the p-type doped layer 624 of the LED 6201 and the p-type doped layer 614 of the LED 6101, respectively.

[0138] Additionally, the LED 6201 can be further processed to include a second lens or lens system 728, preferably a second lens or lens system 728 optimized for the emission wavelength (e.g., emitted green light) of the LED 6201. In this regard, the second lens or lens system 728 can include or be a digital lens, a digital lens system, a resonant cavity structure, a light scattering layer, or a combination thereof.

[0139] Figure 7C The process of implementing the third lens or lens system 738 on the third semiconductor wafer 630 is shown. This process can be referred to as Figure 6G In this regard, after the substrate 635 of the third semiconductor wafer 630 corresponding to the blank silicon wafer 202 is removed by CMP and / or grinding and / or etching, a third anode or p-type contact 737 may be formed on the third semiconductor wafer 630, for example, by a Cu damascene or dual damascene process, and the second anode or p-type contact 727 and the first anode or p-type contact 717 may be extended, in particular, to electrically couple the p-type doped layer 634 of the LED 6301, the p-type doped layer 624 of the LED 6201, and the p-type doped layer 614 of the LED 6101, respectively.

[0140] Additionally, the LED 6301 can be further processed to include a third lens or lens system 738, preferably a third lens or lens system 738 optimized for the emission wavelength (e.g., emitted red light) of the LED 6201. In this regard, the third lens or lens system 738 can include or be a digital lens, a digital lens system, a resonant cavity structure, a light scattering layer, or a combination thereof.

[0141] In this regard, the extended first anode or p-type contact 717 may include or be a spacer portion for light outcoupling of the light emitted by LED 6101, the extended second anode or p-type contact 727 may include or be a spacer portion for light outcoupling of the light emitted by LED 6201, and the third anode or p-type contact 737 may include or be a spacer portion for light outcoupling of the light emitted by LED 6301.

[0142] Thus, there is shown a pixel-level arrangement of a multi-color or RGB display device 750. Exemplarily, the RGB display device 750 may include: a first semiconductor wafer 610 including blue LEDs 6101, a second semiconductor wafer 620 including green LEDs 6201, and a third semiconductor wafer 630 including red LEDs 6301, which are stacked in a three-dimensional configuration (3D stack) and hybrid bonded to the CMOS wafer 300.

[0143] Each of the blue LED 6101, the green LED 6201 and the red LED 6301 is provided with respective wafer-level optical devices 718, 728, 738 optimized for respective emission wavelengths, in particular at different depths corresponding to the first semiconductor wafer 610, the second semiconductor wafer 620, and the third semiconductor wafer 630, respectively.

[0144] It is important to note that the word "coupled" means that the elements can be directly connected together or can be coupled through one or more intermediate elements. Furthermore, in the specification and claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single element or other unit may fulfil the functions of several entities or items described in the claims. Furthermore, the description of any aspect is also relevant to the other aspects of the invention.

[0145] Although the present invention has been illustrated and described for one or more implementations, other persons skilled in the art will recognize equivalent changes and modifications upon reading and understanding this specification and the accompanying drawings. In addition, although a particular feature of the present invention may be disclosed for only one of several implementations, such feature may be combined with one or more other features of other implementations, which may be desirable and advantageous for any given or specific application.

Claims

1. A method (100) for manufacturing a multi-color display or imaging device, the method comprising the following steps: processing (101) a plurality of first semiconductor light emitting or light detecting devices (3101, 6101) on a first semiconductor wafer (310, 610), each of the first semiconductor light emitting or light detecting devices being configured to emit or detect light of a first color, processing (102) at least a plurality of second semiconductor light emitting or light detecting devices (3201, 6201) on at least a second semiconductor wafer (320, 620), each second semiconductor light emitting or light detecting device being configured to emit or detect light of a second color, processing (103) an integrated circuit (304) having a driving device on a third semiconductor wafer (300), the driving device being used to drive the plurality of first semiconductor light emitting or light detecting devices (3101, 6101) and the plurality of second semiconductor light emitting or light detecting devices (3201, 6201), and The first semiconductor wafer (310, 610), the at least second semiconductor wafer (320, 620), and the third semiconductor wafer (300) are bonded (104) in a stacked manner.

2. The method according to claim 1, wherein: The method further comprises the step of bonding the first semiconductor wafer (310, 610), the at least second semiconductor wafer (320, 620) and the third semiconductor wafer (300) according to a hybrid bonding technique and / or a dielectric bonding technique.

3. The method according to claim 1 or 2, in, The method further comprises the following steps: processing a plurality of first contacts (311, 611) corresponding to each of the plurality of first semiconductor light emitting or light detecting devices (3101, 6101) on the first semiconductor wafer (310, 610), processing a plurality of second contacts (321, 621) corresponding to each of the plurality of second semiconductor light emitting or light detecting devices (3201, 6201) on the at least second semiconductor wafer (320, 620), processing on said third semiconductor wafer (300) a plurality of third contacts (301, 302, 303) connected to said integrated circuit (304), preferably a complementary metal oxide semiconductor integrated circuit, and The first semiconductor wafer (310, 610), the at least second semiconductor wafer (320, 620) and the third semiconductor wafer (300) are bonded in a stacked manner, so that the plurality of first semiconductor light emitting or light detecting devices (3101, 6101) are individually connected to the integrated circuit (304) through the first contacts (311, 611) and the third contacts (301), and the at least plurality of second semiconductor light emitting or light detecting devices (3201, 6201) are individually connected to the integrated circuit (304) through the second contacts (321, 621) and the third contacts (302).

4. The method according to any one of claims 1 to 3, wherein: The method further comprises the following steps: utilizing through holes (305, 405, 604, 605) to process electrical connections between the plurality of first semiconductor light emitting or light detecting devices (3101, 6101) and the integrated circuit (304), preferably a complementary metal oxide semiconductor integrated circuit, and / or electrical connections between the at least plurality of second semiconductor light emitting or light detecting devices (3201, 6201) and the integrated circuit (304).

5. The method according to claim 4, wherein: The method further comprises the following steps: simultaneously or sequentially processing the electrical connection between the plurality of first semiconductor light emitting or light detecting devices (3101, 6101) and the integrated circuit (304), and the electrical connection between the at least plurality of second semiconductor light emitting or light detecting devices (3201, 6201) and the integrated circuit (304).

6. The method according to any one of claims 1 to 5, in, The method further comprises the steps of processing a first plurality of optical structures (315, 718) corresponding to each of the plurality of first semiconductor light emitting or light detecting devices (3101, 6101) on the first semiconductor wafer (310, 610), and processing at least a second plurality of optical structures (325, 728) corresponding to each of the plurality of second semiconductor light emitting or light detecting devices (3201, 6201) on the at least second semiconductor wafer (320, 620), or The method further includes the following steps: processing a first plurality of optical structures (618) corresponding to each of the plurality of first semiconductor light-emitting or light-detecting devices (3101, 6101), and at least a second plurality of optical structures (628) corresponding to each of the plurality of second semiconductor light-emitting or light-detecting devices (3201, 6201), especially after bonding the first semiconductor chip (310, 610), the at least second semiconductor chip (320, 620) and the third semiconductor chip (300) in a stacked manner.

7. The method according to claim 6, wherein: The first plurality of optical structures (315, 618, 718) and the second plurality of optical structures (325, 628, 728) include digital lenses, digital lens systems, resonant cavity structures, light scattering layers, or combinations thereof.

8. The method according to any one of claims 1 to 7, wherein: The method also includes the following steps: processing a first plurality of side wall reflectors corresponding to each of the plurality of first semiconductor light emitting or light detecting devices (3101, 6101) on the first semiconductor wafer (310, 610), and processing at least a second plurality of side wall reflectors corresponding to each of the plurality of second semiconductor light emitting or light detecting devices (3201, 620) on the at least second semiconductor wafer (320, 620).

9. The method according to any one of claims 1 to 8, wherein: The method further comprises the following steps: a) cutting a first epitaxial wafer configured to emit or detect light of the first color and transferring it to the first semiconductor wafer (310, 610) so as to process the plurality of first semiconductor light emitting or light detecting devices (3101, 6101) on the first semiconductor wafer (310, 610), and b) Repeating step a) on at least a second epitaxial wafer configured to emit or detect light of the second color to process the at least a plurality of second semiconductor light emitting or light detecting devices (3201, 6201) on the at least second semiconductor wafer (320, 620).

10. The method according to any one of claims 1 to 9, in, The method further comprises the steps of: bonding the first semiconductor wafer (310, 610), the at least second semiconductor wafer (320, 620) and the third semiconductor wafer (300) in a stacked manner to form respective pixel elements of the multi-color display or imaging device, the pixel elements comprising at least one first semiconductor light emitting or light detecting device (3101, 6101) and at least one second semiconductor light emitting or light detecting device (3201, 6201), and Wherein, the at least one first semiconductor light emitting or light detecting device (3101, 6101) and the at least one second semiconductor light emitting or light detecting device (3201, 6201) are arranged as a group of adjacent pixels to form the individual pixel elements of the multi-color display or imaging device.

11. The method according to claim 10, wherein: The method further comprises the step of forming the individual pixel elements of the multi-color display or imaging device, the individual pixel elements having a pixel pitch preferably less than 5 microns.

12. A multicolor display or imaging device (350, 650, 750), comprising: a first semiconductor wafer (310, 610), the first semiconductor wafer comprising a plurality of first semiconductor light emitting or light detecting devices (3101, 6101), each of the first semiconductor light emitting or light detecting devices being configured to emit or detect light of a first color, at least a second semiconductor wafer (320, 620), the second semiconductor wafer comprising at least a plurality of second semiconductor light emitting or light detecting devices (3201, 6201), each second semiconductor light emitting or light detecting device being configured to emit or detect light of a second color, and a third semiconductor wafer (300), the third semiconductor wafer comprising an integrated circuit (304) having a driving device, the driving device being used to drive the plurality of first semiconductor light emitting or light detecting devices (3101, 6101) and the plurality of second semiconductor light emitting or light detecting devices (3201, 6201), The first semiconductor wafer (310, 610), the at least second semiconductor wafer (320, 620) and the third semiconductor wafer (300) are bonded together in a stacked manner.

13. The multi-color display or imaging device according to claim 12, in, The first semiconductor wafer (310, 610) includes a first plurality of optical structures (315, 718) corresponding to each of the plurality of first semiconductor light emitting or light detecting devices (3101, 6101), and the at least second semiconductor wafer (320, 620) includes at least a second plurality of optical structures (325, 728) corresponding to each of the plurality of second semiconductor light emitting or light detecting devices (3201, 6201), or wherein the multicolor display or imaging device comprises a first plurality of optical structures (618) corresponding to each of the plurality of first semiconductor light emitting or light detecting devices (3101, 6101) and at least a second plurality of optical structures (628) corresponding to each of the plurality of second semiconductor light emitting or light detecting devices (3201, 6201), and Wherein, the first plurality of optical structures (315, 618, 718) and the second plurality of optical structures (325, 628, 728) include digital lenses, digital lens systems, resonant cavity structures, light scattering layers, or a combination thereof.

14. A multi-color display or imaging device according to claim 12 or 13, in, The first semiconductor wafer (310, 610) includes a first plurality of sidewall reflectors corresponding to each of the plurality of first semiconductor light emitting or light detecting devices (3101, 6101), and the at least second semiconductor wafer (320, 620) includes at least a second plurality of sidewall reflectors corresponding to each of the plurality of second semiconductor light emitting or light detecting devices (3201, 6201), and Wherein, the first plurality of side wall reflectors and the second plurality of side wall reflectors include distributed Bragg reflectors, metal mirrors, absorption layers, or a combination thereof.

15. A multi-color display or imaging device according to any one of claims 12 to 14, in, The first semiconductor wafer (310, 610) comprises a substrate wafer having at least one compound semiconductor layer, in particular a silicon wafer or a sapphire wafer or a germanium wafer or a GaAs wafer, or a compound semiconductor wafer, and The second semiconductor wafer (320, 620) comprises a substrate wafer having at least one compound semiconductor layer, in particular a silicon wafer, a sapphire wafer, a germanium wafer, or a GaAs wafer, or a compound semiconductor wafer.

16. A multi-color display or imaging device according to any one of claims 12 to 15, in, The plurality of first semiconductor light emitting or light detecting devices (3101, 6101) and the at least plurality of second semiconductor light emitting or light detecting devices (3201, 6201) are compound semiconductor light emitting or light detecting devices, preferably III-V compound semiconductor light emitting or light detecting devices, or Among them, the multiple first semiconductor light-emitting or light-detecting devices (3101, 6101) belong to the first group of compounds, especially gallium nitride (GaN) semiconductor light-emitting or light-detecting devices, and the at least multiple second semiconductor light-emitting or light-detecting devices (3201, 6201) belong to the second group of compounds, especially indium gallium arsenide InGaAs, aluminum indium gallium phosphide AlInGaP semiconductor light-emitting or light-detecting devices.

Images