Array substrate, display panel and display device

Abstract

The invention provides an array substrate, a display panel and a display device, and relates to the technical field of display. The array substrate comprises a substrate, a first conductive layer and a second conductive layer, the first conductive layer and the second conductive layer are arranged on the substrate in a stacked mode, the first conductive layer comprises a plurality of first line sets, each first line set comprises a first longitudinal line, a second longitudinal line and a third longitudinal line which extend in the second direction, the first line sets are arranged at intervals in the first direction, and the first direction intersects with the second direction; the second conductive layer comprises a plurality of second line groups, each second line group comprises a first transverse line and a second transverse line which extend along the first direction, and the plurality of second line groups are arranged at intervals along the second direction; the first longitudinal line is electrically connected with the first transverse line through a first via hole to form a coil structure for near field communication, and the second longitudinal line is electrically connected with the second transverse line through a second via hole; the second longitudinal line and the third longitudinal line are used for being electrically connected with a display driving chip.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] The display effect of electronic paper display devices is close to the effect of natural paper, which reduces the eye fatigue of users during use, so electronic paper display devices have been widely used. Near Field Communication (NFC) technology provides a safe and fast communication method for electronic products used in our daily lives. However, electronic paper display devices equipped with NFC function are relatively thick. Summary of the invention

[0003] Embodiments of the present disclosure provide an array substrate, a display panel, and a display device, which are integrated with an NFC function and are relatively thin.

[0004] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0005] In one aspect, an array substrate is provided, comprising a switch transistor and a pixel electrode, wherein the switch transistor comprises a first electrode, a second electrode and a gate electrode, wherein the first electrode is electrically connected to the pixel electrode, and the array substrate comprises a substrate and a first conductive layer and a second conductive layer stacked on the substrate.

[0006] The first conductive layer includes a plurality of first line groups, the first line groups include first longitudinal lines, second longitudinal lines and third longitudinal lines extending along a second direction, the plurality of first line groups are arranged at intervals along the first direction, and the first direction intersects the second direction;

[0007] The second conductive layer includes a plurality of second line groups, the second line groups include first horizontal lines and second horizontal lines extending along the first direction, and the plurality of second line groups are arranged at intervals along the second direction;

[0008] The first longitudinal line is electrically connected to the first transverse line through a first via hole to form a coil structure for near field communication, and the second longitudinal line is electrically connected to the second transverse line through a second via hole;

[0009] The second vertical line and the third vertical line are used to be electrically connected to a display driver chip.

[0010] In some embodiments, the first electrode and the second electrode are located in the second conductive layer, and the second horizontal line is electrically connected to the second electrode; the gate is located in the first conductive layer, and the third vertical line is electrically connected to the gate;

[0011] Alternatively, the first electrode and the second electrode are located in the first conductive layer, and the third longitudinal line is electrically connected to the second electrode; the gate is located in the second conductive layer, and the second transverse line is electrically connected to the gate.

[0012] In some embodiments, the array substrate has a communication area and a non-communication area.

[0013] The first vertical line includes a first line and a second line which are disconnected, the first line is located in the communication area, and the second line is located in the non-communication area;

[0014] The first horizontal line includes a third line and a fourth line which are disconnected, the third line is located in the communication area, and the fourth line is located in the non-communication area;

[0015] The first line and the third line are electrically connected through the first via to form the coil structure.

[0016] In some implementations, the communication area includes a plurality of the first wires and a plurality of the third wires, and the plurality of the first wires and the plurality of the third wires are electrically connected through a plurality of the first vias to form a mesh structure.

[0017] In some embodiments, the communication area includes a first sub-area and a second sub-area, the non-communication area includes a third sub-area and a fourth sub-area, the first sub-area at least partially surrounds the third sub-area, the fourth sub-area at least partially surrounds the first sub-area, and the second sub-area at least partially surrounds the fourth sub-area;

[0018] The first sub-region and the second sub-region are both provided with the first line and the third line, and the third sub-region and the fourth sub-region are both provided with the second line and the fourth line.

[0019] In some embodiments, the array substrate also includes a first signal line, a second signal line, a third signal line, and a fourth signal line, the first signal line is electrically connected to the coil structure in the first sub-area, the second signal line and the third signal line are electrically connected to the coil structure in the second sub-area, and the fourth signal line is electrically connected to the second line and the fourth line in the third sub-area and the fourth sub-area.

[0020] In some embodiments, a third conductive layer is disposed between the pixel electrode and the coil structure, and the orthographic projection of the third conductive layer on the substrate at least partially covers the orthographic projection of the coil structure on the substrate.

[0021] In some embodiments, an orthographic projection of the third conductive layer on the substrate covers an orthographic projection of the first wire group and an orthographic projection of the second wire group on the substrate.

[0022] In some embodiments, the second vertical line is located between the first vertical line and the third vertical line, and the third vertical line is disposed adjacent to the switch transistor electrically connected thereto.

[0023] In some embodiments, a region where the first longitudinal line is opposite to the second via hole is bent in a direction away from the second via hole; and / or a region where the third longitudinal line is opposite to the second via hole is bent in a direction away from the second via hole.

[0024] In some embodiments, a portion of the first longitudinal line that is bent in a direction away from the second via hole is a first bent portion, and the first bent portion is electrically connected to the first transverse line through the first via hole.

[0025] In some embodiments, the number of the second line group is greater than the number of the first line group, the first conductive layer further includes a third line group, the third line group includes second longitudinal lines and third longitudinal lines, and the number of the third longitudinal lines in the third line group is greater than the number of the third longitudinal lines in the first line group.

[0026] In some embodiments, at least one of the first line groups and at least one of the third line groups form a repeating unit, the first conductive layer includes a plurality of the repeating units, and the plurality of the repeating units are arranged along the first direction.

[0027] On the other hand, a display panel is provided, comprising the array substrate and an electronic paper film connected to the array substrate.

[0028] On the other hand, a display device is provided, including a control board, a flexible circuit board and the display panel, wherein the flexible circuit board electrically connects the control board and the display panel.

[0029] In the array substrate, display panel and display device provided by the embodiments of the present disclosure, since the first longitudinal line extends along the second direction, the first transverse line extends along the first direction, the first direction and the second direction intersect, and the first longitudinal line and the first transverse line are electrically connected through the first via hole, the conductive structure formed by the electrical connection of the first longitudinal line and the first transverse line can be bent multiple times in the display area to form a coil structure, so that the display device can achieve near-field communication with an external device through the coil structure. Compared with the related art, the coil structure for near-field communication is integrated in the array substrate, and does not need to be connected to the outside of the display panel in an external manner, thereby reducing the thickness of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 The front view structure of a display device is exemplarily shown;

[0032] Figure 2 A partial structural diagram of a display device is exemplarily shown;

[0033] Figure 3 A cross-sectional view of a display panel is exemplarily shown;

[0034] Figure 4 The schematic diagram of three working states of the display panel is exemplarily shown;

[0035] Figure 5 A structural diagram of a display panel is exemplarily shown;

[0036] Figure 6 for Figure 5 A local enlarged view of position I in FIG.

[0037] Figure 7 for Figure 6 A local enlarged view of position II;

[0038] Figure 8 for Figure 7 The cross-sectional view of CC in

[0039] Fig. 9 for Figure 7 The cross-sectional view of DD in

[0040] Fig.10 Another partial enlarged view at position I is shown as an example;

[0041] Fig.11 A partial structural diagram of a display panel is exemplarily shown.

[0042] Reference numerals:

[0043] 1000-display device;

[0044] 100-display panel;

[0045] 200-Flexible circuit board;

[0046] 300-control panel;

[0047] 110 - array substrate; 111 - substrate; 112 - first conductive layer; 113 - gate insulating layer; 114 - active layer; 115 - second conductive layer; 116 - source-drain insulating layer; 117a - first passivation layer; 117b - second passivation layer; 118 - third conductive layer; 119 - fourth conductive layer;

[0048] 120-electronic paper film; 121-adhesive layer; 122-electronic paper layer; 123-common electrode; 124-substrate;

[0049] 130-protective layer;

[0050] 140-display driver chip;

[0051] 150-fan-out routing;

[0052] 161 - first signal line 161; 162 - second signal line; 163 - third signal line; 164 - fourth signal line;

[0053] 14-gate; 24-first pole;

[0054] 1-first line group; 11-first longitudinal line; 12-second longitudinal line; 13-third longitudinal line; 11a-first bending portion; 13a-second bending portion;

[0055] 2- second line group; 21- first horizontal line; 22- second horizontal line. DETAILED DESCRIPTION

[0056] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0057] In the embodiments of the present disclosure, words such as "first", "second", "third", and "fourth" are used to distinguish between identical or similar items with substantially the same functions and effects. This is only for the purpose of clearly describing the technical solutions of the embodiments of the present disclosure and shall not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0058] In the embodiments of the present disclosure, “plurality” means two or more than two, and “at least one” means one or more than one, unless otherwise clearly and specifically defined.

[0059] In the embodiments of the present disclosure, the orientation or positional relationship indicated by the terms "upper" and "lower" etc. is based on the orientation or positional relationship shown in the accompanying drawings and is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0060] The transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors (such as oxide thin film transistors) or other switching devices with the same characteristics. The embodiments of the present disclosure are all described by taking thin film transistors as examples. The control pole of each transistor used is the gate of the transistor, the first pole is one of the source and drain of the transistor, and the second pole is the other of the source and drain of the transistor. Since the source and drain of the transistor may be symmetrical in structure, the source and drain thereof may be indistinguishable in structure, that is, the first pole and the second pole of the transistor in the embodiments of the present disclosure may be indistinguishable in structure.

[0061] Figure 1 The front view structure of a display device is shown as an example. Figure 1 As shown, some embodiments of the present application provide a display device 1000, which can be any device that displays whether it is moving (e.g., video) or fixed (e.g., still image) and whether it is text or image. More specifically, it is expected that the embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controls and / or displays, displays of camera views (e.g., displays of rear-view cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc. Figure 1 In the figure, the display device 1000 is taken as a reader as an example for illustration.

[0062] Figure 2 A partial structural diagram of a display device is shown as an example. Figure 2 As shown, the display device 1000 includes a display panel 100. The display panel 100 may be an electronic paper display panel or other types of display panels. In the embodiments of the present disclosure, only the electronic paper display panel is taken as an example for detailed description.

[0063] Continue to refer Figure 2The display device 1000 may further include a flexible circuit board 200 and a control board 300, wherein one end of the flexible circuit board 200 is electrically connected to the display panel 100, and the other end of the flexible circuit board 200 is electrically connected to the control board 300. During the operation of the display device 1000, the image signal in the control board 300 is sent to the display panel 100 through the flexible circuit board 200.

[0064] Figure 3 A cross-sectional view of a display panel is shown as an example. Figure 3 As shown, the display panel 100 may include an array substrate 110 , an electronic paper sheet 120 stacked on the array substrate 110 , and a protection layer 130 located on a side of the electronic paper sheet 120 away from the array substrate 110 .

[0065] The electronic paper film 120 includes an adhesive layer 121, an electronic paper layer 122, a common electrode 123 and a substrate 124 stacked in sequence. The electronic paper film 120 is bonded to the array substrate 110 via the adhesive layer 121, and the protective layer 130 is connected to the side of the substrate 124 away from the array substrate 110.

[0066] The electronic paper layer 122 is provided with charged particles, and the charged particles can display images under the drive of the working voltage. According to the different display principles of the electronic paper layer 120, the electronic paper layer 120 can be an E-Ink microcapsule electronic paper layer, a SiPix microcup electronic paper layer, a Bridgestone electronic liquid powder electronic paper layer, a cholesterol liquid crystal electronic paper layer, a micro-electromechanical system electronic paper layer, an electrowetting electronic paper layer, etc., and the embodiments of the present disclosure are not limited to this.

[0067] The adhesive layer 121 can be a flexible adhesive or a rigid adhesive. When the display panel 100 is a flexible display panel, the adhesive layer 121 is a flexible adhesive to facilitate the bending of the display panel 100. Exemplarily, the adhesive layer 121 is an optically clear adhesive (OCA) or a pressure sensitive adhesive (PSA).

[0068] The common electrode 123 is made of a transparent conductor to reduce the blocking of light by the common electrode 123. Exemplarily, the common electrode 123 is made of indium tin oxide (ITO). A pixel electrode is provided in the array substrate 110, and an electric field is formed between the pixel electrode and the common electrode 123 to drive the movement of charged particles in the electronic paper layer 122, thereby displaying an image.

[0069] Figure 4 The schematic diagram of three working states of the display panel is shown exemplarily. Figure 4As shown, a microcapsule is arranged between the common electrode and the pixel electrode, and a plurality of white charged particles and a plurality of black charged particles are arranged in the microcapsule, the white charged particles are positively charged, and the black charged particles are negatively charged. When the common electrode and the pixel electrode are not energized, the white charged particles and the black charged particles in the microcapsule are mixed and arranged irregularly; when the common electrode and the pixel electrode are energized so that an electric field pointing to the common electrode is formed between the common electrode and the pixel electrode, the white charged particles are arranged at one end of the microcapsule facing the common electrode, and the black charged particles are arranged at one end of the microcapsule facing the pixel electrode, and the light is reflected after being irradiated by the white charged particles, presenting a white picture; when the common electrode and the pixel electrode are energized so that an electric field pointing to the pixel electrode is formed between the common electrode and the pixel electrode, the black charged particles are arranged at one end of the microcapsule facing the common electrode, and the white charged particles are arranged at one end of the microcapsule facing the pixel electrode, and the light is reflected after being irradiated by the black charged particles, presenting a black picture.

[0070] The substrate 124 serves as a skeleton of the electronic paper film 120, and is used to support and connect other film layer structures in the electronic paper film 120. For example, the substrate 124 may be a polyethylene terephthalate (PET) substrate.

[0071] The protection film 130 is used to protect the electronic paper film 120 and prevent the electronic paper film 120 from being scratched.

[0072] Figure 5 The structure diagram of a display panel is shown as an example. Figure 5 As shown, the display panel has a display area AA and a non-display area NA connected to the display area AA. The non-display area NA may be located on one side, two sides, or three sides of the display area AA, or the non-display area NA may be arranged around the display area AA. For example, Figure 5 The area within the dotted line is the display area AA, and the area outside the dotted line is the non-display area NA, that is, Figure 5 A case where the non-display area AA is disposed around the display area AA is shown.

[0073] A plurality of sub-pixels are provided in the display area AA. Exemplarily, the plurality of sub-pixels may be arranged in an array. For example, after the plurality of sub-pixels are arranged in an array, a plurality of sub-pixel rows and a plurality of sub-pixel columns are formed, and a plurality of sub-pixels in a sub-pixel row are arranged along a first direction X, and a plurality of sub-pixels in a sub-pixel column are arranged along a second direction Y. The first direction X and the second direction Y intersect with each other. The angle between the first direction X and the second direction Y may be selected and set according to actual needs. Exemplarily, the angle between the first direction X and the second direction Y may be 85°, 88°, 90°, 92° or 95°, etc.

[0074] The sub-pixel includes a switching transistor, a pixel electrode, a common electrode, and charged particles located between the pixel electrode and the common electrode. The switching transistor includes a first electrode, a second electrode, and a gate electrode. The first electrode of the switching transistor is electrically connected to the data line, and the second electrode of the switching transistor is electrically connected to the pixel electrode. When working, the gate electrode of the switching transistor receives a scanning signal to turn on the switching transistor, so that the data signal in the data line is written into the pixel electrode through the switching transistor, so that an electric field corresponding to the data signal is formed between the pixel electrode and the common electrode. Among them, the switching transistor and the pixel electrode can be located on the array substrate 110, and the common electrode and the charged particles are located on the electronic paper 120.

[0075] The array substrate of the present disclosure is described in detail below in conjunction with specific embodiments.

[0076] Embodiment 1

[0077] Figure 6 for Figure 5 The local enlarged view of I in the figure, Figure 7 for Figure 6 The enlarged view of the part II in the figure, Figure 8 for Figure 7 The cross-sectional view of CC in Figures 6 to 8 As shown, the array substrate 110 may include a substrate 111 and a first conductive layer 112 and a second conductive layer 115 stacked on the substrate 111 .

[0078] The substrate 111 may be a rigid substrate or a flexible substrate. The substrate 111 is used to support and protect other film structures of the display panel 100. The substrate 111 may be a single-layer structure or may be formed by stacking multiple layers.

[0079] Exemplarily, the substrate 111 is a rigid substrate, such as a glass substrate or a PMMA (Polymethyl methacrylate) substrate.

[0080] Exemplarily, the substrate 111 is a flexible substrate, for example, the flexible substrate may be a polyethylene terephthalate (PET) substrate, a polyethylene naphthalate diformic acid glycol ester (PEN) substrate, or a polyimide (PI) substrate.

[0081] The first conductive layer 112 is provided with a plurality of first line groups 1, and a plurality of lines extending along the second direction Y are provided in the first line group 1. The second conductive layer 115 is provided with a plurality of second line groups 2, and a plurality of lines extending along the first direction X are provided in the second line group 2. The plurality of first line groups 1 are arranged at intervals along the first direction X, and the plurality of second line groups 2 are arranged at intervals along the second direction Y. The first line groups 1 and the second line groups 2 define a quadrilateral space for setting sub-pixels. Exemplarily, one first line group 1 is provided for each sub-pixel column, and one second line group 2 is provided for each sub-pixel row.

[0082] Continue to refer Figure 6 and Figure 7 The first line group 1 includes a third vertical line 13, the third vertical line 13 extends along the second direction Y, and the third vertical line 13 is electrically connected to the gate 14 of the switch transistor, for example, the third vertical line 13 is electrically connected to the gate 14 of each switch transistor in the same sub-pixel column. The second line group 2 includes a second horizontal line 22, the second horizontal line 22 extends along the first direction X, and the second horizontal line 22 is electrically connected to the second electrode of the switch transistor, for example, the second horizontal line 22 is electrically connected to the second electrode of each switch transistor in the same sub-pixel row. That is, the third vertical line 13 serves as a gate line, and the second horizontal line 22 serves as a data line.

[0083] The second line group 2 further includes a second longitudinal line 12 . The second longitudinal line 12 extends along the second direction Y. The second longitudinal line 12 is electrically connected to one of the second transverse lines 22 through a second via H2 .

[0084] The second vertical line 12 and the third vertical line 13 may be electrically connected to the display driver chip 140, for example, the display driver chip 140 is electrically connected to the second vertical line 12 and the third vertical line 13 via the fan-out wiring 150. The display driver chip 140 provides a gate drive signal to the third vertical line 13, and the display driver chip 140 provides a data signal to the second vertical line 12.

[0085] Continue to refer Figure 6 and Figure 7 A first longitudinal line 11 is further provided in the first line group 1, and a first transverse line 21 is further provided in the second line group 2. The first longitudinal line 11 extends along the second direction Y, and the first transverse line 21 extends along the first direction X. The first longitudinal line 11 and the first transverse line 21 are electrically connected through a first via H1.

[0086] In practical applications, an insulating layer is provided between the first conductive layer 112 and the second conductive layer 115 , and the first via hole H1 and the second via hole H2 are provided in the insulating layer.

[0087] Since the first longitudinal line 11 extends along the second direction Y, the first transverse line 21 extends along the first direction X, the first direction X intersects the second direction Y, and the first longitudinal line 11 and the first transverse line 21 are electrically connected through the first via H1, so that the conductive structure formed by the electrical connection of the first longitudinal line 11 and the first transverse line 21 can be bent multiple times in the display area AA to form a coil structure, so that the display device can achieve near field communication with an external device through the coil structure. Compared with the related art, the coil structure for near field communication is integrated in the array substrate 110, and does not need to be connected to the outside of the display panel 100 in an external manner, thereby reducing the thickness of the display panel 100.

[0088] The first conductive layer 112 may be a gate layer (Gate layer), that is, the gate 14 of the switch transistor and the first wire group 1 are both located in the first conductive layer 112. The second conductive layer 115 may be a source-drain layer (SD layer), that is, the source, drain and second wire group 2 of the switch transistor are both located in the second conductive layer 115.

[0089] For example, continue to refer to Figure 8 The array substrate 110 includes a substrate 111 and a first conductive layer 112, a gate insulating layer 113, an active layer 14, and a second conductive layer 115 which are sequentially stacked on the substrate 111. The switch transistor has a bottom gate structure, the first conductive layer 112 is located on the side of the active layer 14 facing the substrate 111, and the second conductive layer 115 is located on the side of the active layer 14 away from the substrate 111. The first via hole H1 and the second via hole H2 are provided in the gate insulating layer 113.

[0090] The third vertical line 13 is electrically connected to the gate 14, and the display driver chip 140 sends a gate 14 driving signal to the switch transistor through the third vertical line 13. The second vertical line 12 is electrically connected to the second horizontal line 22, and the second horizontal line 22 is electrically connected to the second electrode. The display driver chip 140 provides a data signal to the second electrode through the second vertical line 12.

[0091] Continue to refer Figure 2 and Figure 5 The display area AA may have a communication area (A1, A2) and a non-communication area (B1, B2, B3), and the coil structure is arranged in the communication area. The communication area refers to an area for implementing near field communication, and the non-communication area refers to an area other than the communication area in the display area AA.

[0092] The first longitudinal line 11 includes a first line and a second line that are disconnected, the first line is located in the communication area, and the second line is located in the non-communication area. Exemplarily, the first line and the second line both extend along the second direction Y and are co-linearly arranged, and the first line and the second line are disconnected at the junction of the communication area and the non-communication area, so that different signals can be passed into the first line and the second line.

[0093] The first horizontal line 21 includes a third line and a fourth line that are disconnected, the third line is located in the communication area, and the fourth line is located in the non-communication area. Exemplarily, the third line and the fourth line both extend along the first direction X and are co-linearly arranged, and the third line and the fourth line are disconnected at the junction of the communication area and the non-communication area, so that different signals can be passed into the third line and the fourth line.

[0094] The first wire and the third wire are electrically connected through the first via H1 to form a coil structure.

[0095] Exemplarily, a coil turn includes at least two first wires and at least one third wire, the two first wires are arranged opposite to each other and spaced apart, the third wire is located between the two first wires and is electrically connected to the first ends of the two first wires, forming a coil of a U-shaped structure. The second ends of the two first wires are electrically connected to the signal wire to receive the near field communication signal of the signal wire.

[0096] The first line and the third line in the communication area are disconnected from the second line and the fourth line in the non-communication area, so that the coil structure can pass different signals from the second line and the fourth line in the non-communication area. Exemplarily, when the display device performs near-field communication, the first line and the third line pass the near-field communication signal, and the second line and the fourth line pass the Vcom signal; when the display device does not perform near-field communication, the first line, the second line, the third line and the fourth line all pass the Vcom signal.

[0097] Continue to refer Figure 6 A plurality of first wires and a plurality of third wires may be provided in the communication area, and the plurality of first wires and the plurality of third wires are electrically connected through a plurality of first vias H1 to form a mesh structure. After the mesh structure is formed, the resistance of the coil structure can be reduced, and the communication quality of the near field communication can be improved.

[0098] Continue to refer Figure 5 The communication area may include a first sub-area A1 and a second sub-area A2, the non-communication area includes a third sub-area B1 and a fourth sub-area B2, the first sub-area A1 at least partially surrounds the third sub-area B1, the fourth sub-area B2 at least partially surrounds the first sub-area A1, and the second sub-area A2 at least partially surrounds the fourth sub-area B2.

[0099] The first sub-area A1 and the second sub-area A2 are both provided with a first wire and a third wire. The first wire and the third wire in the first sub-area A1 are electrically connected to form a grid structure that is a first coil. The first wire and the third wire in the second sub-area A2 are electrically connected to form a grid structure that is a second coil. The second coil is sleeved around the first coil. In actual application, the first near-field communication signal can be passed into the first coil, and the second near-field communication signal can be passed into the second coil.

[0100] Exemplarily, the first longitudinal lines 11 may include a plurality of first lines and a plurality of second lines, and the first lines and the second lines are arranged at intervals.

[0101] Exemplarily, the non-communication area may further include a fifth sub-area B3, in which the second line and the fourth line are disposed.

[0102] The third sub-area B1 and the fourth sub-area B2 are both provided with a second line and a fourth line, and the second line and the fourth line may be electrically connected or disconnected, which is not limited in the embodiment of the present disclosure.

[0103] Continue to refer Figure 2 The array substrate 110 also includes a first signal line 161, a second signal line 162, a third signal line 163 and a fourth signal line 164. The first signal line 161 is electrically connected to the coil structure in the first sub-area, the second signal line 162 and the third signal line 163 are electrically connected to the coil structure in the second sub-area, and the fourth signal line 164 is electrically connected to the second line and the fourth line in the third sub-area and the fourth sub-area.

[0104] In actual application, when the display device performs near field communication, the display device sends a first near field communication signal to the first coil structure through the first signal line 161, sends a second near field communication signal to the second coil through the second signal line 162 and the third signal line 163, and sends a Vcom signal to the second line and the fourth line in the third sub-area and the fourth sub-area through the fourth signal line 164. When the display device does not perform near field communication, the display device sends a Vcom signal to the first signal line 161, the second signal line 162, the third signal line 163, and the fourth signal line 164.

[0105] Exemplarily, the first signal line 161, the second signal line 162, the third signal line 163 and the fourth signal line 164 are located in the non-display area NA, and one end of the first signal line 161, the second signal line 162 and the third signal is electrically connected to the near field communication chip in the control board 300 through the flexible circuit board 200, and the other end of the first signal line 161, the second signal line 162 and the third signal is electrically connected to the first vertical line 11.

[0106] A third conductive layer 118 is provided between the pixel electrode and the coil structure, and the orthographic projection of the third conductive layer 118 on the substrate 111 at least partially covers the orthographic projection of the coil structure on the substrate 111. Since the third conductive layer 118 is located between the pixel electrode and the coil structure, the third conductive layer 118 can shield the signal in the coil structure, thereby preventing the signal in the coil structure from interfering with the signal of the pixel electrode.

[0107] In practical applications, the third conductive layer 118 may be made of indium tin oxide (ITO), and the third conductive layer 118 may be passed with a Vcom signal.

[0108] Fig. 9 for Figure 7 For example, Figure 8 and Fig. 9 As shown, the array substrate 110 also includes a source-drain insulating layer, a first passivation layer 117a, a third conductive layer 118, a second passivation layer 117b and a fourth conductive layer 119 which are sequentially stacked on the third conductive layer 118, and the pixel electrode is located in the fourth conductive layer 119, and the pixel electrode is electrically connected to the first electrode 24 of the switching transistor through a via.

[0109] The orthographic projection of the third conductive layer 118 on the substrate 111 covers the orthographic projection of the first line group 1 and the second line group 2 on the substrate 111, so that the third conductive layer 118 can shield the signals in the first line group 1 and the second line group 2. For example, the third conductive layer 118 shields the gate 14 driving signal in the third vertical line 13 and the data signal in the second vertical line 12 and the second horizontal line 22.

[0110] Exemplarily, the orthographic projection of the third conductive layer 118 on the substrate 111 is in a grid shape, and the grid-shaped solid portion extending along the first direction X covers the side of the second line group 2 away from the substrate 111, and the grid-shaped solid portion extending along the second direction Y covers the side of the first line group 1 away from the substrate 111.

[0111] Continue to refer Figure 7 The second vertical line 12 is located between the first vertical line 11 and the third vertical line 13, and the third vertical line 13 is disposed adjacent to the switch transistor electrically connected thereto. For example, the third vertical line 13 is electrically connected to the gate 14 of the switch transistor, and the third vertical line 13 is closer to the gate 14 than the first vertical line 11 and the second vertical line 12, which facilitates the electrical connection between the third vertical line 13 and the gate 14 and simplifies the wiring.

[0112] The second vertical line 12 is electrically connected to the second horizontal line 22 through the second via hole H2 . During the manufacturing process, poor overlap may occur at the via hole overlap, thereby causing poor display of the display panel 100 .

[0113] In view of this, continue to refer to Figure 7 The area of ​​the first longitudinal line 11 opposite to the second via hole H2 is bent in a direction away from the second via hole H2 to form a first bent portion 11a. The distance between the first bent portion 11a and the second longitudinal line 12 is greater than the distance between the other parts of the first longitudinal line 11 and the second longitudinal line 12, thereby preventing poor overlap.

[0114] like Fig.10 As shown, the area of ​​the third longitudinal line 13 opposite to the second via hole H2 is bent away from the second via hole H2 to form a second bent portion 13a. The distance between the second bent portion 13a and the second longitudinal line 12 is greater than the distance between the other parts of the third longitudinal line 13 and the second longitudinal line 12, thereby preventing poor overlap.

[0115] In actual application, the first bending portion 11a may be provided only on the first longitudinal line 11 , the second bending portion 13a may be provided only on the third longitudinal line 13 , or the first bending portion 11a may be provided on the first longitudinal line 11 and the second bending portion 13a may be provided on the third longitudinal line 13 .

[0116] The first bending portion 11a can be electrically connected to the first horizontal line 21 through the first via H1. Since the distance between the first bending portion 11a and the second vertical line 12 is increased, the first bending portion 11a is electrically connected to the first horizontal line 21 through the first via H1, which can prevent poor overlap caused by the via overlap structure being too close to the second vertical line 12.

[0117] The number of third vertical lines 13 included in the same first line group 1 may be one or more. In practical applications, the number of third vertical lines 13 in the first line group 1 may be determined according to the resolution of the display panel 100. For example, the resolution of the display panel 100 is 1680*2240, that is, the display panel 100 includes 2240 sub-pixel rows and 1680 sub-pixel columns. The number of sub-pixel rows is greater than the number of sub-pixel columns, that is, the number of second line groups 2 is greater than the number of first line groups 1, and each second line group 2 is provided with a second horizontal line 22. In order to match the number of second vertical lines 12 with the number of second horizontal lines 22, a plurality of second vertical lines 12 may be provided in the first line group 1.

[0118] Of course, a plurality of third line groups may be provided in the first conductive layer 112, the third line group including a third longitudinal line 13 extending along the second direction Y and a plurality of second longitudinal lines 12 extending along the second direction Y, the plurality of second longitudinal lines 12 being electrically connected to different second transverse lines 22 respectively. The number of the third longitudinal lines 13 in the third line group is greater than the number of the third longitudinal lines 13 in the first line group 1.

[0119] At least one first line group 1 and at least one third line group form a repeating unit. The first conductive layer 112 includes a plurality of repeating units. The plurality of repeating units are arranged along the first direction X.

[0120] Figure 6 One of the repeating units is shown in FIG. 1 , and a plurality of repeating units are arranged along a first direction X.

[0121] Exemplarily, each repeating unit includes two first thread groups 1 and one third thread group.

[0122] Embodiment 2

[0123] The main difference between the second embodiment and the first embodiment is that the film layer where the first line group 1 and the second line group 2 are located in the second embodiment is different from that in the first embodiment, and the connection relationship between the third vertical line 13 and the second horizontal line 22 and the switch transistor is different.

[0124] Fig.11 A partial structural diagram of a display panel 100 is exemplarily shown. Fig.11 As shown, the first conductive layer 112 may be a source-drain layer (SD layer), that is, the first electrode 24, the second electrode and the first wire group 1 of the switch transistor are all located in the first conductive layer 112. The second conductive layer 115 may be a gate layer (Gate layer), that is, the gate 14 of the switch transistor and the second wire group 2 are all located in the second conductive layer 115.

[0125] At this time, the third vertical line 13 is electrically connected to the second electrode of the switch transistor, and the second horizontal line 22 is electrically connected to the gate 14 of the switch transistor.

[0126] Exemplarily, the array substrate 110 includes a substrate 111, and a second conductive layer 115, a gate insulating layer 113, an active layer 14, and a first conductive layer 112 which are sequentially stacked on the substrate 111. The switch transistor has a bottom gate structure, the second conductive layer 115 is located on the side of the active layer 14 facing the substrate 111, and the first conductive layer 112 is located on the side of the active layer 14 away from the substrate 111. The first via H1 and the second via H2 are provided in the gate insulating layer 113.

[0127] Since the first longitudinal line 11 extends along the second direction Y, the first transverse line 21 extends along the first direction X, the first direction X intersects the second direction Y, and the first longitudinal line 11 and the first transverse line 21 are electrically connected through the first via H1, so that the conductive structure formed by the electrical connection of the first longitudinal line 11 and the first transverse line 21 can be bent multiple times in the display area to form a coil structure, so that the display device can achieve near field communication with an external device through the coil structure. Compared with the related art, the coil structure for near field communication is integrated in the array substrate 110, and does not need to be connected to the outside of the display panel 100 in an external manner, thereby reducing the thickness of the display panel 100.

[0128] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. An array substrate, comprising a switch transistor and a pixel electrode, wherein the switch transistor comprises a first electrode, a second electrode and a gate electrode, wherein the first electrode is electrically connected to the pixel electrode, wherein: The array substrate includes a substrate and a first conductive layer and a second conductive layer stacked on the substrate. The first conductive layer includes a plurality of first line groups, the first line groups include first longitudinal lines, second longitudinal lines and third longitudinal lines extending along a second direction, the plurality of first line groups are arranged at intervals along the first direction, and the first direction intersects the second direction; The second conductive layer includes a plurality of second line groups, the second line groups include first horizontal lines and second horizontal lines extending along the first direction, and the plurality of second line groups are arranged at intervals along the second direction; The first longitudinal line is electrically connected to the first transverse line through a first via hole to form a coil structure for near field communication, and the second longitudinal line is electrically connected to the second transverse line through a second via hole; The second vertical line and the third vertical line are used to be electrically connected to a display driver chip.

2. The array substrate according to claim 1, characterized in that: The first electrode and the second electrode are located in the second conductive layer, and the second horizontal line is electrically connected to the second electrode; the gate is located in the first conductive layer, and the third vertical line is electrically connected to the gate; Alternatively, the first electrode and the second electrode are located in the first conductive layer, and the third longitudinal line is electrically connected to the second electrode; the gate is located in the second conductive layer, and the second transverse line is electrically connected to the gate.

3. The array substrate according to claim 1, characterized in that: The array substrate has a communication area and a non-communication area. The first vertical line includes a first line and a second line which are disconnected, the first line is located in the communication area, and the second line is located in the non-communication area; The first horizontal line includes a third line and a fourth line which are disconnected, the third line is located in the communication area, and the fourth line is located in the non-communication area; The first line and the third line are electrically connected through the first via to form the coil structure.

4. The array substrate according to claim 3, characterized in that: The communication area includes a plurality of the first wires and a plurality of the third wires, and the plurality of the first wires and the plurality of the third wires are electrically connected through a plurality of the first vias to form a mesh structure.

5. The array substrate according to claim 4, characterized in that: The communication area includes a first sub-area and a second sub-area, the non-communication area includes a third sub-area and a fourth sub-area, the first sub-area at least partially surrounds the third sub-area, the fourth sub-area at least partially surrounds the first sub-area, and the second sub-area at least partially surrounds the fourth sub-area; The first sub-region and the second sub-region are both provided with the first line and the third line, and the third sub-region and the fourth sub-region are both provided with the second line and the fourth line.

6. The array substrate according to claim 5, characterized in that: The array substrate also includes a first signal line, a second signal line, a third signal line and a fourth signal line, the first signal line is electrically connected to the coil structure in the first sub-area, the second signal line and the third signal line are electrically connected to the coil structure in the second sub-area, and the fourth signal line is electrically connected to the second line and the fourth line in the third sub-area and the fourth sub-area.

7. The array substrate according to any one of claims 1 to 6, characterized in that: A third conductive layer is disposed between the pixel electrode and the coil structure, and the orthographic projection of the third conductive layer on the substrate at least partially covers the orthographic projection of the coil structure on the substrate.

8. The array substrate according to claim 7, characterized in that: The orthographic projection of the third conductive layer on the substrate covers the orthographic projections of the first line group and the second line group on the substrate.

9. The array substrate according to any one of claims 1 to 6, characterized in that: The second vertical line is located between the first vertical line and the third vertical line, and the third vertical line is disposed adjacent to the switch transistor electrically connected thereto.

10. The array substrate according to claim 9, characterized in that: The area of ​​the first longitudinal line opposite to the second via hole is bent in a direction away from the second via hole; and / or the area of ​​the third longitudinal line opposite to the second via hole is bent in a direction away from the second via hole.

11. The array substrate according to claim 10, characterized in that: A portion of the first longitudinal line that is bent in a direction away from the second via hole is a first bent portion, and the first bent portion is electrically connected to the first transverse line through the first via hole.

12. The array substrate according to any one of claims 1 to 6, characterized in that: The number of the second line group is greater than the number of the first line group. The first conductive layer further includes a third line group, the third line group includes second longitudinal lines and third longitudinal lines, and the number of the third longitudinal lines in the third line group is greater than the number of the third longitudinal lines in the first line group.

13. The array substrate according to claim 12, characterized in that: At least one of the first line groups and at least one of the third line groups form a repeating unit, the first conductive layer includes a plurality of the repeating units, and the plurality of the repeating units are arranged along the first direction.

14. A display panel, characterized in that: The invention comprises an array substrate as claimed in any one of claims 1 to 13 and an electronic paper film connected to the array substrate.

15. A display device, characterized in that: The device comprises a control board, a flexible circuit board and the display panel as claimed in claim 14, wherein the flexible circuit board electrically connects the control board and the display panel.

Images