Self-biased low-temperature-drift band-gap reference voltage source

Abstract

The invention discloses a self-biased low-temperature-drift band-gap reference voltage source, which is characterized in that a pre-voltage-stabilizing circuit is introduced to isolate a power supply voltage from a self-biased operational amplifier and a band-gap reference core circuit, so that a bias current and an output voltage of the band-gap reference voltage source do not depend on the change of the power supply voltage; the low-frequency power supply rejection ratio of the band-gap reference voltage source is improved; a biasing circuit of the operational amplifier is simplified by utilizing a self-biasing technology, and reference voltage which is less influenced by temperature drift is provided for the pre-voltage-stabilizing circuit; considering that the temperature drift coefficient of the first-order reference voltage output by the band-gap reference core circuit is large, a low-power-consumption segmented compensation circuit with a simple structure is adopted, high and low temperature compensation currents with different magnitudes are output in set high and low temperature intervals, high-order compensation of the first-order reference voltage is achieved, the temperature range of the reference voltage is widened, and meanwhile the temperature drift coefficient of the first-order reference voltage is increased. The temperature drift coefficient of the reference voltage is greatly reduced, and the precision of the output reference voltage is improved.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, and in particular to a self-biased low-temperature drift bandgap reference voltage source. Background Art

[0002] With the rapid development of microelectronics technology, the performance requirements for analog circuits are getting higher and higher. The bandgap reference voltage source is one of the important modules in analog circuits. Its principle is to add two voltages with different temperature coefficients, positive and negative, to obtain a reference voltage that is approximately independent of temperature and power supply. Bandgap reference voltage sources are widely used in circuits such as low dropout linear regulators (LDOs), analog-to-digital converters (ADCs), and digital-to-analog converters (DACs). The output voltage of a traditional first-order bandgap reference voltage source drifts greatly with temperature over a wide temperature range. Its power supply rejection ratio cannot be increased to a high enough level at low frequencies due to the limited gain of the loop, resulting in the inability to meet the accuracy requirements of the reference voltage in practical applications. Therefore, how to reduce temperature drift and improve power supply rejection ratio is the key to studying bandgap reference voltage sources. Summary of the invention

[0003] The present invention aims to solve the problem that the output voltage temperature drift of a first-order bandgap reference voltage source is large and the low-frequency power supply suppression is relatively poor, and provides a self-biased low-temperature drift bandgap reference voltage source.

[0004] To solve the above problems, the present invention is achieved through the following technical solutions:

[0005] A self-biased low-temperature drift bandgap reference voltage source is characterized in that it is composed of a pre-stabilizing circuit, a self-biased operational amplifier, a bandgap reference core circuit and a segmented compensation circuit; the input of the pre-stabilizing circuit is connected to a power supply VDD, a ground GND and an internal feedback reference voltage VBN of the self-biased operational amplifier, and the output of the pre-stabilizing circuit sends out a pre-stabilizing voltage VDDA; the input of the self-biased operational amplifier is connected to the pre-stabilizing voltage VDDA of the pre-stabilizing circuit, the ground GND and the in-phase voltage VNP and the reverse phase voltage VNM of the bandgap reference core circuit; the output of the self-biased operational amplifier sends out an internal feedback reference voltage VBN and a positive temperature coefficient voltage VPTAT; the bandgap reference The input of the core circuit is connected to the pre-regulated voltage VDDA of the pre-regulated circuit, the ground GND, the positive temperature coefficient voltage VPTAT of the self-biased operational amplifier and the high-order compensation current IBC of the segmented compensation circuit, and the output of the bandgap reference core circuit sends out the common-phase voltage VNP, the reverse-phase voltage VNM, the negative temperature coefficient voltage VCTAT and the output reference voltage VREF; the input of the segmented compensation circuit is connected to the pre-regulated voltage VDDA of the pre-regulated circuit, the ground GND, the positive temperature coefficient voltage VPTAT of the self-biased operational amplifier and the negative temperature coefficient voltage VCTAT of the bandgap reference core circuit, and the output of the segmented compensation circuit sends out the high-order compensation current IBC.

[0006] In the above scheme, the pre-regulator circuit is composed of a PMOS tube MP1, resistors R1, R2 and an error amplifier OPAMP; the source of the PMOS tube MP1 is connected to the power supply VDD; one end of the resistor R2 is connected to the ground GND; the inverting input end of the error amplifier OPAMP is connected to the internal feedback reference voltage VBN; the non-inverting input end of the error amplifier OPAMP, the other end of the resistor R2 and one end of the resistor R1 are connected; the output end of the error amplifier OPAMP is connected to the gate of the PMOS tube MP1; the drain of the PMOS tube MP1 is connected to the other end of the resistor R1 and then the pre-regulator voltage VDDA is sent out.

[0007] In the above scheme, the self-biased operational amplifier is composed of NMOS tubes MN1 to MN8, PMOS tubes MP2 to MP7 and resistor R3; the sources of PMOS tubes MP2, MP4 and MP6 are connected and then connected to the pre-regulated voltage VDDA; the sources of NMOS tubes MN1, MN4, MN6 and MN8 are connected and then connected to the ground GND; the gate of NMOS tube MN2 is connected to the in-phase voltage VNP; the gate of NMOS tube MN3 is connected to the reverse voltage VNM; the source of PMOS tube MP3 is connected to the drain of PMOS tube MP2; the gates of PMOS tubes MP2, MP3, MP5 and MP7 are connected to the drain of PMOS tube MP3 and NMOS tube MN1; the source of PMOS tube MP5 is connected to the drain of PMOS tube MP4 and NMOS tube MN2 The gate of the NMOS tubes MN5 and MN7, the drain of the PMOS tube MP5 and one end of the resistor R3 are connected; the gate of the NMOS tubes MN1, MN4, MN6 and MN8 and the other end of the resistor R3 are connected to send out the internal feedback reference voltage VBN; the gate of the PMOS tubes MP4 and MP6 and the drain of the PMOS tubes MP7 and NMOS tube MN7 are connected to send out the positive temperature coefficient voltage VPTAT.

[0008] In the above scheme, the bandgap reference core circuit is composed of PMOS tubes MP8-MP10, NMOS tubes MN9, MN10, PNP transistors Q1-Q3 and resistors R4-R6; the source of PMOS tubes MP8, MP9 and MP10 is connected and then connected to the pre-regulated voltage VDDA; the base and collector of PNP transistors Q1, Q2 and Q3 are connected and then connected to the ground GND; the gate of PMOS tubes MP8, MP9 and MP10 is connected and then connected to the positive temperature coefficient voltage VPTAT; one end of resistor R5 and one end of resistor R6 are connected and then connected to the high-order compensation current IBC; PMOS tube MP8 and NMOS tube MN9 are connected and then connected to the ground GND; The drain of the PNP transistor Q2 is connected; the emitter of the PNP transistor Q3 is connected to the other end of the resistor R6; the source of the NMOS tube MN10 is connected to the other end of the resistor R4 to send out the in-phase voltage VNP; the source of the NMOS tube MN9 is connected to the emitter of the PNP transistor Q1 to send out the reverse voltage VNM; the gates of the NMOS tubes MN9 and MN10 and the drains of the NMOS tubes MN10 and the PMOS tube MP9 are connected to send out the negative temperature coefficient voltage VCTAT; the drain of the PMOS tube MP10 is connected to the other end of the resistor R5 to send out the output reference voltage VREF.

[0009] In the above scheme, the segmented compensation circuit is composed of NMOS tubes MN11 to MN15, PMOS tube MP11 and resistor R7; the source of PMOS tube MP11 is connected to the pre-regulated voltage VDDA; the sources of NMOS tubes MN12 and MN15 are connected to the ground GND; the gate of PMOS tube MP11 is connected to the positive temperature coefficient voltage VPTAT; the gate of NMOS tube MN13 is connected to the negative temperature coefficient voltage VCTAT; the PMOS tube MP11 is connected to the drain of NMOS tube MN13; the gates of NMOS tubes MN11 and MN14, the source of NMOS tube MN13 and one end of resistor R7 are connected; the gates of NMOS tubes MN12 and MN15, the drain of NMOS tube MN14 and the other end of resistor R7 are connected; the source of NMOS tube MN11 is connected to the drain of NMOS tube MN12, the source of NMOS tube MN14 is connected to the drain of NMOS tube MN15; the drain of NMOS tube MN11 sends out the high-order compensation current IBC.

[0010] Compared with the prior art, the present invention has the following characteristics:

[0011] 1. Taking into account the principle that the temperature characteristic curve of the output voltage of the first-order reference source is usually a curve opening downward, and an upward curve is needed to be added to it for compensation, the present invention designs a simple-structured low-power segmented compensation circuit to achieve high-order compensation, so that the temperature drift coefficient of the compensated reference voltage in a wide temperature range is significantly reduced.

[0012] 2. A pre-regulator circuit is used to isolate the power supply voltage from the bandgap reference core circuit, and self-bias technology is used to provide a current bias for the operational amplifier while also providing the pre-regulator circuit with a reference voltage that is less affected by temperature, which significantly improves the low-frequency power supply rejection ratio of the bandgap reference circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A circuit diagram of a self-biased low-temperature drift bandgap reference voltage source;

[0014] Figure 2 A schematic diagram of the temperature characteristics of the first-order reference voltage output by the bandgap reference core circuit;

[0015] Figure 3 A schematic diagram of the temperature characteristics of a segmented compensation current of a self-biased low-temperature drift bandgap reference voltage source;

[0016] Figure 4 The figure is a simulation diagram of the output voltage temperature characteristic of a self-biased low-temperature drift bandgap reference voltage source;

[0017] Figure 5 The figure is a schematic diagram of the output voltage power supply rejection ratio of a self-biased low temperature drift bandgap reference voltage source. DETAILED DESCRIPTION

[0018] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in combination with specific examples and with reference to the accompanying drawings.

[0019] A self-biased low temperature drift bandgap reference voltage source, such as Figure 1As shown, it is composed of a pre-regulator circuit, a self-biased operational amplifier, a bandgap reference core circuit and a segmented compensation circuit. The input of the pre-regulator circuit is connected to the power supply VDD, the ground GND and the internal feedback reference voltage VBN of the self-biased operational amplifier, and the output of the pre-regulator circuit sends out the pre-regulator voltage VDDA. The input of the self-biased operational amplifier is connected to the pre-regulator voltage VDDA of the pre-regulator circuit, the ground GND and the in-phase voltage VNP and the inverting voltage VNM of the bandgap reference core circuit; the output of the self-biased operational amplifier sends out the internal feedback reference voltage VBN and the positive temperature coefficient voltage VPTAT. The input of the bandgap reference core circuit is connected to the pre-regulator voltage VDDA of the pre-regulator circuit, the ground GND, the positive temperature coefficient voltage VPTAT of the self-biased operational amplifier and the high-order compensation current IBC of the segmented compensation circuit, and the output of the bandgap reference core circuit sends out the in-phase voltage VNP, the inverting voltage VNM, the negative temperature coefficient voltage VCTAT and the output reference voltage VREF. The input of the segmented compensation circuit is connected to the pre-regulated voltage VDDA of the pre-regulated circuit, the ground GND, the positive temperature coefficient voltage VPTAT of the self-biased operational amplifier and the negative temperature coefficient voltage VCTAT of the bandgap reference core circuit, and the output of the segmented compensation circuit sends out a high-order compensation current IBC.

[0020] The pre-stabilization circuit is composed of a PMOS tube MP1, resistors R1, R2 and an error amplifier OPAMP. The source of the PMOS tube MP1 is connected to the power supply VDD; one end of the resistor R2 is connected to the ground GND; the inverting input of the error amplifier OPAMP is connected to the internal feedback reference voltage VBN. The non-inverting input of the error amplifier OPAMP, the other end of the resistor R2 and one end of the resistor R1 are connected; the output of the error amplifier OPAMP is connected to the gate of the PMOS tube MP1. The drain of the PMOS tube MP1 is connected to the other end of the resistor R1 and then the pre-stabilization voltage VDDA is sent out. The error amplifier OPAMP of the pre-stabilization circuit amplifies the difference between the internal feedback reference voltage VBN and the sampling voltage to output an error voltage, thereby driving the PMOS tube MP1 to generate a pre-stabilization voltage VDDA for powering the subsequent stage, so as to improve the low-frequency power supply rejection ratio of the circuit.

[0021] The self-biased operational amplifier is composed of NMOS tubes MN1-MN8, PMOS tubes MP2-MP7 and resistor R3. The sources of PMOS tubes MP2, MP4 and MP6 are connected and then connected to the pre-regulated voltage VDDA; the sources of NMOS tubes MN1, MN4, MN6 and MN8 are connected and then connected to the ground GND; the gate of NMOS tube MN2 is connected to the in-phase voltage VNP; the gate of NMOS tube MN3 is connected to the reverse voltage VNM. The source of the PMOS tube MP3 is connected to the drain of the PMOS tube MP2; the gates of the PMOS tubes MP2, MP3, MP5 and MP7 are connected to the drain of the PMOS tube MP3 and the NMOS tube MN1; the source of the PMOS tube MP5 is connected to the drain of the PMOS tube MP4 and the NMOS tube MN2; the source of the PMOS tube MP7 is connected to the drain of the PMOS tube MP6 and the NMOS tube MN3; the sources of the NMOS tubes MN2 and MN3 are connected to the drain of the NMOS tube MN4; the source of the NMOS tube MN5 is connected to the drain of the NMOS tube MN6; the source of the NMOS tube MN7 is connected to the drain of the NMOS tube MN8; the gates of the NMOS tubes MN5 and MN7, the drain of the PMOS tube MP5 and one end of the resistor R3 are connected. The gates of NMOS tubes MN1, MN4, MN6 and MN8 are connected to the other end of resistor R3 to send out the internal feedback reference voltage VBN; the gates of PMOS tubes MP4 and MP6 and the drains of PMOS tubes MP7 and NMOS tube MN7 are connected to send out the positive temperature coefficient voltage VPTAT. The self-biased operational amplifier uses self-biasing technology to generate bias current that is independent of the power supply, and improves the loop gain, accuracy and stability of the reference voltage by participating in the construction of positive and negative feedback loops.

[0022] The bandgap reference core circuit is composed of PMOS tubes MP8-MP10, NMOS tubes MN9, MN10, PNP transistors Q1-Q3 and resistors R4-R6. The source of PMOS tubes MP8, MP9 and MP10 is connected to the pre-regulated voltage VDDA; the base and collector of PNP transistors Q1, Q2 and Q3 are connected to the ground GND; the gate of PMOS tubes MP8, MP9 and MP10 is connected to the positive temperature coefficient voltage VPTAT; one end of resistor R5 and one end of resistor R6 are connected to the high-order compensation current IBC. PMOS tube MP8 is connected to the drain of NMOS tube MN9; the emitter of PNP transistor Q2 is connected to one end of resistor R4; the emitter of PNP transistor Q3 is connected to the other end of resistor R6. The source of NMOS tube MN10 is connected to the other end of resistor R4 to send out the in-phase voltage VNP; the source of NMOS tube MN9 is connected to the emitter of PNP transistor Q1 to send out the reverse voltage VNM; the gates of NMOS tubes MN9 and MN10 and the drains of NMOS tubes MN10 and PMOS tube MP9 are connected to send out the negative temperature coefficient voltage VCTAT; the drain of PMOS tube MP10 is connected to the other end of resistor R5 to send out the output reference voltage VREF. The bandgap reference core circuit adds the positive and negative temperature coefficient voltages through a certain proportional coefficient and outputs the first-order compensated bandgap reference voltage.

[0023] The segmented compensation circuit is composed of NMOS tubes MN11 to MN15, PMOS tube MP11 and resistor R7. The source of PMOS tube MP11 is connected to the pre-regulated voltage VDDA; the sources of NMOS tubes MN12 and MN15 are connected to the ground GND; the gate of PMOS tube MP11 is connected to the positive temperature coefficient voltage VPTAT; the gate of NMOS tube MN13 is connected to the negative temperature coefficient voltage VCTAT. PMOS tube MP11 is connected to the drain of NMOS tube MN13; the gates of NMOS tubes MN11 and MN14, the source of NMOS tube MN13 and one end of resistor R7 are connected; the gates of NMOS tubes MN12 and MN15, the drain of NMOS tube MN14 and the other end of resistor R7 are connected; the source of NMOS tube MN11 is connected to the drain of NMOS tube MN12, and the source of NMOS tube MN14 is connected to the drain of NMOS tube MN15. The drain of NMOS tube MN11 sends out the high-order compensation current IBC. The segmented compensation circuit improves the temperature drift coefficient of the bandgap reference output voltage by outputting high and low temperature compensation currents of different sizes in the set high and low temperature ranges.

[0024] The working principle of the present invention is:

[0025] The core circuit of the bandgap reference generates a first-order compensated reference voltage that is less affected by temperature by adding a negative temperature coefficient voltage and a positive temperature coefficient voltage at a certain coefficient; the negative temperature coefficient voltage is generated by using the junction voltage V between the emitter and base of the PNP transistors Q1 and Q3. EB The positive temperature coefficient voltage is generated by using PNP transistors Q1 and Q2 with different sizes but the same current flowing through them, so that the junction voltage V between the emitter and the base EB The relationship between the difference and temperature is a positive proportional coefficient characteristic, and the positive temperature coefficient voltage ΔV BE It can be expressed as;

[0026] ΔV BE =V BE1 -V BE2 =V T *lnn

[0027] Where n = 8, V T is the thermal voltage. Assuming I is the current flowing through the PNP transistors Q1 and Q2, it can be expressed as:

[0028]

[0029] When using resistors R1 to R7 with the same temperature coefficient and block value in circuit design, the reference voltage for the output first-order compensation can be expressed as:

[0030]

[0031] Here, k is a ratio coefficient of the number of transistors of the PMOS tube MP9 and the PMOS tube MP10.

[0032] Figure 2 This is a schematic diagram of the temperature characteristics of the first-order reference voltage output by the bandgap reference core circuit. It can be seen from the figure that the temperature characteristic curve of the first-order reference voltage output by the bandgap reference core circuit is a downward-opening curve. A compensation circuit is designed to extract a downward-opening current, which is added to the upward-opening voltage generated by the resistor to achieve high-order compensation.

[0033] Figure 3This is a schematic diagram of the temperature characteristics of the segmented compensation current of a self-biased low-temperature drift bandgap reference voltage source. It can be seen from the figure that the output current drawn before the set temperature node increases with the increase of temperature, and the output current drawn after the set temperature node decreases with the increase of temperature. Since the high-order compensation current is the current drawn through the resistor, the voltage compensation curve with an opening upward is obtained by inverting it. When the negative temperature coefficient current ICTAT is greater than the positive temperature coefficient current IPTAT, the NMOS tube MN13 operates in the linear region, and the IBC output terminal draws the positive temperature coefficient current; when the positive temperature coefficient current IPTAT is greater than the negative temperature coefficient current ICTAT, the PMOS tube MP11 changes from the saturation region to the linear region, and the IBC output terminal draws the negative temperature coefficient current. The compensated segmented current can be expressed as:

[0034]

[0035] T0 is a set temperature node, and the proportionality coefficient k1 is changed by changing the ratio of the number of transistors of the PMOS tube MP9 to the PMOS tube MP11 , and the proportionality coefficient k2 is changed by changing the ratio of the number of transistors of the NMOS tube MN10 to the NMOS tube MN12 .

[0036] Figure 4 This is a simulation diagram of the output voltage temperature characteristics of a self-biased low-temperature drift bandgap reference voltage source. It can be seen from the figure that the output voltage of the reference source after high-order compensation has multiple turning points, and the fluctuation is 0.582mV at -60℃ ~ 130℃, which is 78.28% lower than the 2.68mV fluctuation of the first-order reference voltage output by the bandgap reference core circuit at -60℃ ~ 130℃, making the temperature drift coefficient only 2.43ppm.

[0037] Figure 5 This is a simulation diagram of the output voltage power supply rejection ratio of a self-biased low-temperature drift bandgap reference voltage source. It can be seen from the figure that the low-frequency power supply rejection ratio of the circuit is 63dB when the pre-regulator circuit is not added. After adding the pre-regulator circuit, the low-frequency power supply rejection ratio of the circuit is 125dB, and the low-frequency power supply rejection is significantly improved.

[0038] The present invention isolates the power supply voltage from the self-biased operational amplifier and the bandgap reference core circuit by introducing a pre-stabilizing circuit, so that the bias current and output voltage of the bandgap reference voltage source do not depend on the change of the power supply voltage, thereby improving the low-frequency power supply rejection ratio of the bandgap reference voltage source; the bias circuit of the operational amplifier is simplified by using the self-biasing technology, and a reference voltage that is less affected by temperature drift is provided for the pre-stabilizing circuit; considering that the temperature drift coefficient of the first-order reference voltage output by the bandgap reference core circuit is relatively large, a simple-structured low-power segmented compensation circuit is adopted to output high and low temperature compensation currents of different sizes within the set high and low temperature ranges, thereby realizing high-order compensation of the first-order reference voltage, and while widening the temperature range of the reference voltage, the temperature drift coefficient of the reference voltage is greatly reduced, thereby improving the accuracy of the output reference voltage.

[0039] It should be noted that although the embodiments of the present invention described above are illustrative, they are not intended to limit the present invention, and therefore the present invention is not limited to the above specific embodiments. Without departing from the principles of the present invention, any other embodiments obtained by those skilled in the art under the guidance of the present invention are deemed to be within the protection of the present invention.

Claims

1. A self-biased low temperature drift bandgap reference voltage source, characterized in that: It is composed of a pre-regulator circuit, a self-biased operational amplifier, a bandgap reference core circuit and a segmented compensation circuit; The input of the pre-regulator circuit is connected to the power supply VDD, the ground GND and the internal feedback reference voltage VBN of the self-biased operational amplifier, and the output of the pre-regulator circuit sends out the pre-regulated voltage VDDA; The input of the self-biased operational amplifier is connected to the pre-regulated voltage VDDA of the pre-regulated circuit, the ground GND, and the in-phase voltage VNP and the reverse voltage VNM of the bandgap reference core circuit; the output of the self-biased operational amplifier sends out the internal feedback reference voltage VBN and the positive temperature coefficient voltage VPTAT; The input of the bandgap reference core circuit is connected to the pre-regulator voltage VDDA of the pre-regulator circuit, the ground GND, the positive temperature coefficient voltage VPTAT of the self-biased operational amplifier and the high-order compensation current IBC of the segmented compensation circuit. The output of the bandgap reference core circuit sends out the in-phase voltage VNP, the reverse voltage VNM, the negative temperature coefficient voltage VCTAT and the output reference voltage VREF. The input of the segmented compensation circuit is connected to the pre-regulated voltage VDDA of the pre-regulated circuit, the ground GND, the positive temperature coefficient voltage VPTAT of the self-biased operational amplifier and the negative temperature coefficient voltage VCTAT of the bandgap reference core circuit, and the output of the segmented compensation circuit sends out a high-order compensation current IBC.

2. A self-biased low temperature drift bandgap reference voltage source according to claim 1, characterized in that: The pre-regulator circuit is composed of a PMOS tube MP1, resistors R1, R2 and an error amplifier OPAMP; The source of the PMOS tube MP1 is connected to the power supply VDD; one end of the resistor R2 is connected to the ground GND; the inverting input end of the error amplifier OPAMP is connected to the internal feedback reference voltage VBN; The non-inverting input terminal of the error amplifier OPAMP, the other end of the resistor R2 and one end of the resistor R1 are connected; the output terminal of the error amplifier OPAMP is connected to the gate of the PMOS tube MP1; The drain of the PMOS tube MP1 is connected to the other end of the resistor R1 to output a pre-regulated voltage VDDA.

3. The self-biased low temperature drift bandgap reference voltage source according to claim 1, characterized in that: The self-biased operational amplifier is composed of NMOS tubes MN1 to MN8, PMOS tubes MP2 to MP7 and resistor R3; The sources of the PMOS tubes MP2, MP4 and MP6 are connected and then connected to the pre-regulated voltage VDDA; the sources of the NMOS tubes MN1, MN4, MN6 and MN8 are connected and then connected to the ground GND; the gate of the NMOS tube MN2 is connected to the in-phase voltage VNP; the gate of the NMOS tube MN3 is connected to the reverse voltage VNM; The source of the PMOS tube MP3 is connected to the drain of the PMOS tube MP2; the gates of the PMOS tubes MP2, MP3, MP5 and MP7 are connected to the drain of the PMOS tube MP3 and the NMOS tube MN1; the source of the PMOS tube MP5 is connected to the drain of the PMOS tube MP4 and the NMOS tube MN2; the source of the PMOS tube MP7 is connected to the drain of the PMOS tube MP6 and the NMOS tube MN3; the sources of the NMOS tubes MN2 and MN3 are connected to the drain of the NMOS tube MN4; the source of the NMOS tube MN5 is connected to the drain of the NMOS tube MN6; the source of the NMOS tube MN7 is connected to the drain of the NMOS tube MN8; the gates of the NMOS tubes MN5 and MN7, the drain of the PMOS tube MP5 and one end of the resistor R3 are connected; The gates of the NMOS tubes MN1, MN4, MN6 and MN8 are connected to the other end of the resistor R3 to send out the internal feedback reference voltage VBN; the gates of the PMOS tubes MP4 and MP6 and the drains of the PMOS tubes MP7 and NMOS tube MN7 are connected to send out the positive temperature coefficient voltage VPTAT.

4. The self-biased low temperature drift bandgap reference voltage source according to claim 1, characterized in that: The bandgap reference core circuit is composed of PMOS tubes MP8-MP10, NMOS tubes MN9, MN10, PNP transistors Q1-Q3 and resistors R4-R6; The sources of the PMOS tubes MP8, MP9 and MP10 are connected and then connected to the pre-regulated voltage VDDA; the bases and collectors of the PNP transistors Q1, Q2 and Q3 are connected and then connected to the ground GND; the gates of the PMOS tubes MP8, MP9 and MP10 are connected and then connected to the positive temperature coefficient voltage VPTAT; one end of the resistor R5 and one end of the resistor R6 are connected and then connected to the high-order compensation current IBC; The drain of the PMOS transistor MP8 is connected to the drain of the NMOS transistor MN9; the emitter of the PNP transistor Q2 is connected to one end of the resistor R4; the emitter of the PNP transistor Q3 is connected to the other end of the resistor R6; The source of the NMOS tube MN10 is connected to the other end of the resistor R4 to send out the in-phase voltage VNP; the source of the NMOS tube MN9 is connected to the emitter of the PNP transistor Q1 to send out the reverse voltage VNM; the gates of the NMOS tubes MN9 and MN10 and the drains of the NMOS tubes MN10 and the PMOS tube MP9 are connected to send out the negative temperature coefficient voltage VCTAT; the drain of the PMOS tube MP10 is connected to the other end of the resistor R5 to send out the output reference voltage VREF.

5. The self-biased low temperature drift bandgap reference voltage source according to claim 1, characterized in that: The segmented compensation circuit is composed of NMOS tubes MN11 to MN15, PMOS tube MP11 and resistor R7; The source of the PMOS tube MP11 is connected to the pre-regulated voltage VDDA; the sources of the NMOS tubes MN12 and MN15 are connected to the ground GND; the gate of the PMOS tube MP11 is connected to the positive temperature coefficient voltage VPTAT; the gate of the NMOS tube MN13 is connected to the negative temperature coefficient voltage VCTAT; The PMOS transistor MP11 is connected to the drain of the NMOS transistor MN13; the gates of the NMOS transistors MN11 and MN14, the source of the NMOS transistor MN13 and one end of the resistor R7 are connected; the gates of the NMOS transistors MN12 and MN15, the drain of the NMOS transistor MN14 and the other end of the resistor R7 are connected; the source of the NMOS transistor MN11 is connected to the drain of the NMOS transistor MN12, and the source of the NMOS transistor MN14 is connected to the drain of the NMOS transistor MN15; The drain of the NMOS tube MN11 sends out a high-order compensation current IBC.

Images