Method and device for generating top-layer file of system on chip and program product

Abstract

The embodiment of the invention provides a method and device for generating a top-layer file of a system on chip and a program product, and the method comprises the steps: obtaining a first design file of the system on chip, the first design file being a code file pre-generated based on a hardware description language, the first design file comprises a parameter design file and a port design file of each component in the system on chip; analyzing the first design file, and converting a first analysis result into a file in a first preset format to obtain a first file library; generating a port file library and a parameter file library based on the first file library; a target top-layer file is generated through the port file library, the parameter file library and the target configuration file, the target top-layer file is used for configuring operation parameters of all the assemblies, and the target configuration file comprises information for declaring the first design file. Through the method and the device, the problem of low top-layer file design efficiency in related technologies is solved, and the effect of efficiently generating the top-layer file is achieved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computers, and in particular, to a method and device for generating a top-level file of a system on a chip, and a program product. Background Art

[0002] The system on chip integrates a complete information processing system on a single chip. The R&D and production process of the system on chip mainly includes functional requirements, system-level design verification, architecture, hardware design verification, software design verification and manufacturing. Among them, the main work of the hardware design verification stage is to integrate multiple modules with different functions through the top-level file to form a complete hardware design process of the system on chip. In order to combine the various modules together, the top-level file not only defines the input and output interfaces, but also needs to define the clock and reset signals, as well as the communication with peripheral devices.

[0003] As the functional requirements of the system-on-chip increase, the number of modules that need to be integrated in the system-on-chip increases, and the number of ports described in the top-level file also increases, and the complexity of the register transfer level code (RTL code) of the top-level file further increases. At present, the top-level file of the system-on-chip is mostly written by manually writing RTL code. Since there are many ports that need to be instantiated in the top-level file of the system-on-chip, if the design engineer of the system-on-chip manually integrates each module, it is difficult to ensure the correctness of the port description in the top-level file, which will increase the development cycle of the system-on-chip.

[0004] In recent years, in order to shorten the development cycle of the system on chip, some R&D personnel have used Verilog mode software to automatically generate combinational logic sensitivity lists, module ports, and port mappings, etc., to reduce the workload of top-level file writing. However, Verilog mode software can only operate on output ports and instantiated ports. In addition, during the development of the system on chip, the interface signal needs to be constantly modified. However, when the function automatically instantiated by the Verilog mode software is executed, if the module port name is modified, the top-level file will be restored to the default state, which forces the design engineer to manually modify the top-level file repeatedly, increasing the time cost and the error rate of the RTL code. Summary of the invention

[0005] The embodiments of the present application provide a method and device for generating a top-level file of a system on chip, and a program product, so as to at least solve the problem of low efficiency of top-level file design in related technologies.

[0006] According to one embodiment of the present application, a method for generating a top-level file of a system on chip is provided, comprising: obtaining a first design file of the system on chip, wherein the first design file is a code file pre-generated based on a hardware description language, and the first design file includes parameter design files and port design files of each component in the system on chip; parsing the first design file, and converting the first parsing result into a file in a first preset format to obtain a first file library, wherein the first preset format is a lightweight data exchange format; generating a port file library and a parameter file library based on the first file library, wherein the port file library includes port information in the port design file, and the parameter file library includes parameter information in the parameter design file, and both the port design file and the parameter design file are in the lightweight data exchange format; generating a target top-level file using the port file library, the parameter file library and the target configuration file, wherein the target top-level file is used to configure the operating parameters of each of the above components, and the target configuration file includes information declaring the first design file.

[0007] In an exemplary embodiment, obtaining a first design file of a system on chip includes: accessing a file database according to an acquired first storage path, wherein the file database includes a plurality of stored design files; searching the design database for a design file that matches the parameters and / or ports of each of the above components, and reading the design file to obtain the first design file.

[0008] In an exemplary embodiment, parsing a first design file and converting the first parsing result into a file in a first preset format to obtain a first file library includes: parsing the first design file into an abstract syntax tree, wherein the abstract syntax tree includes the file structure of the first design file and the syntax structure used to generate the first design file; converting the abstract syntax tree into a file in the first preset format to obtain the first file library.

[0009] In an exemplary embodiment, parsing the first design file into an abstract syntax tree includes: dividing the first design file into N lexical units, wherein the lexical unit is the smallest grammatical unit of the first design file, and N is a positive integer; combining the N lexical units according to preset grammatical rules to obtain M grammatical structures, wherein the grammatical structures are grammatical rules of the hardware description language, and M is a positive integer less than or equal to N; and generating the abstract syntax tree based on the M grammatical structures.

[0010] In an exemplary embodiment, a port file library and a parameter file library are generated based on a first file library, including: parsing the above-mentioned first file library, and integrating the parsed port information in the above-mentioned port design files and the parameter information in the above-mentioned parameter design files to obtain a first set; storing the above-mentioned first set to obtain a second file library; generating the above-mentioned port file library and the above-mentioned parameter file library based on the above-mentioned second file library.

[0011] In an exemplary embodiment, a port file library and a parameter file library are generated based on a second file library, including: obtaining a port name from the second file library; extracting port information in the port design file from the first file library according to the port name, and storing the port information to obtain the port file library; extracting information whose information attribute is a parameter from the second file library to obtain parameter information in the parameter design file, and storing the parameter information to obtain the parameter file library.

[0012] In an exemplary embodiment, a target top-level file is generated using a port file library, a parameter file library and a target configuration file, including: extracting the name of the top-level file from the above-mentioned target configuration file; parsing the names of the above-mentioned port file library, the above-mentioned parameter file library and the above-mentioned top-level file to obtain a second parsing result, wherein the above-mentioned second parsing result includes the connection relationship between each of the above-mentioned ports; and generating the above-mentioned target top-level file using the above-mentioned second parsing result.

[0013] In an exemplary embodiment, the names of the port file library, the parameter file library and the top-level file are parsed to obtain a second parsing result, including: parsing the connection status of the ports between each of the above-mentioned components from the names of the above-mentioned port file library, the above-mentioned parameter file library and the above-mentioned top-level file to obtain the above-mentioned second parsing result.

[0014] In an exemplary embodiment, the connection status of the ports between the various components is parsed from the names of the port file library, the parameter file library and the top-level file to obtain a second parsing result, including: parsing the first connection relationship between the above-mentioned ports from the above-mentioned port file library to obtain a first connection sub-file; determining the first target port whose connection status is not specified from the above-mentioned first connection sub-file; setting the first parameter to establish an association relationship between the above-mentioned first target port and each of the above-mentioned components, and generating the above-mentioned second parsing result using the above-mentioned parameter file library, the name of the above-mentioned top-level file and the above-mentioned first parameter.

[0015] In an exemplary embodiment, after parsing the connection status of the ports between the various components from the names of the port file library, the parameter file library and the top-level file to obtain the second parsing result, the method further includes: determining the connection mode of the second target port based on the connection status of the ports between the various components and the connection priority of the preset port, wherein the second target port is any port included in the above parsing result; determining whether the port information between the second target port and the third target port is consistent based on the connection mode of the second target port, wherein the third target port is a port connected to the second target port; in the case where the port information between the second target port and the third target port is consistent, generating the target top-level file using the second parsing result; in the case where the port information between the second target port and the third target port is inconsistent, issuing an exception message, wherein the exception message is used to indicate that there is an exception in the port information in the first file library.

[0016] In an exemplary embodiment, after generating a target top-level file using the parsing result, the method further includes: storing the target top-level file in a file database and generating a second storage path; in response to a fetch instruction, searching for a second design file of the system on chip from the file database according to the second storage path in response to the fetch instruction when receiving the fetch instruction, wherein the second design file is a file other than the target top-level file and is used to configure the operating parameters of each of the components; parsing the second design file and converting the third parsing result obtained into a file in the first preset format to obtain a fifth file library, wherein the fifth file library includes the port information and the parameter information; performing a verification operation on the fifth file library and updating the second design file based on the verification result, wherein the verification result is used to indicate that all design files in the system on chip allow the operating parameters of each of the components to be configured.

[0017] In an exemplary embodiment, a verification operation is performed on a fifth file library, and a second design file is updated based on the verification result, including: performing the verification operation on the fifth file library according to preset verification rules to obtain the verification result, wherein the preset verification rule includes at least one of the following: whether there are duplications in the port names of the ports, whether there are duplications in the naming of the plurality of parameter information, whether there are dangling instantiated ports included in the ports, whether the port signals of the ports are connected to the target device, whether the preset port connection priority is satisfied between the target port signals in the ports and the corresponding source port signals, whether the signal transmission directions between the target port signals in the ports and the corresponding source port signals match, whether the bit widths between the target port signals in the ports and the corresponding source port signals match, and whether the naming of each design file of the system on chip is repeated; and updating the second design file according to the verification result.

[0018] In an exemplary embodiment, updating the second design file according to the verification result includes: when it is determined from the verification result that there is an abnormality in the fifth file library, obtaining a log file indicating the abnormality in the fifth file library; generating a sixth file library based on the log file and the fifth file library, wherein the sixth file library is a file library obtained after performing an update operation on the abnormal information in the fifth file library, and the sixth file library is a file library verified by the preset verification rule; and updating the second design file according to the sixth file library.

[0019] In an exemplary embodiment, the target top-level file is generated using the second parsing result, including: obtaining connection information between each of the above-mentioned ports from the above-mentioned second parsing result; configuring the connection between each of the above-mentioned ports according to the connection information between each of the above-mentioned ports to obtain port configuration information; and determining the above-mentioned target top-level file based on the above-mentioned port configuration information.

[0020] According to another embodiment of the present application, a module generation device is provided, including: an input device, used to transmit a first design file of a system on chip, the first design file is a code file pre-generated based on a hardware description language, and the first design file includes parameter design files and port design files of each component in the system on chip; a memory, connected to the input device, used to store the first design file and file generation instructions; a processor, connected to the memory, on which the method described in any one of the above items is deployed; an output device, connected to the processor, used to transmit a target top-level file generated by the processor to the system on chip; wherein the input device, the memory, the processor, and the output device are all connected via a communication bus.

[0021] According to another embodiment of the present application, a system on chip is provided, comprising the above-mentioned module generating device.

[0022] According to another embodiment of the present application, a device for generating a top-level file of a system on chip is provided, comprising: an acquisition module for acquiring a first design file of the system on chip, wherein the first design file is a code file pre-generated based on a hardware description language, and the first design file includes a parameter design file and a port design file of each component in the system on chip; a parsing module for parsing the first design file and converting the first parsing result into a file in a first preset format to obtain a first file library, wherein the first preset format is a lightweight data exchange format; a first generating module for generating a port file library and a parameter file library based on the first file library, wherein the port file library includes the port information in the port design file, and the parameter file library includes the parameter information in the parameter design file, and both the port design file and the parameter design file are in the lightweight data exchange format; a second generating module for generating a target top-level file using the port file library, the parameter file library and the target configuration file, wherein the target top-level file is used to configure the operating parameters of each of the above components, and the target configuration file includes information declaring the first design file.

[0023] According to another embodiment of the present application, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0024] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any one of the above method embodiments when running.

[0025] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0026] Through the present application, the first design file is parsed to obtain the first file library, the first file library is parsed to obtain the port file library and the parameter file library, and based on the preset port connection priority, the port information is verified, the connection method between the ports of each component is determined to obtain the parsing result, and then the target top-level file is generated according to the parsing result, the name of the top-level file is obtained, all the design files of the system on chip are verified based on the preset verification rules, and the target top-level file finally generated is determined after the verification is correct. Therefore, the problem of low efficiency of top-level file design in the related technology can be solved, and the effect of efficiently generating top-level files can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a hardware environment schematic diagram of a method for generating a top-level file of a system on chip according to an embodiment of the present application;

[0028] Figure 2 is a flow chart of a method for generating a top-level file of a system on chip according to an embodiment of the present application;

[0029] Figure 3 is a schematic diagram of converting a first design file into a first file library according to an embodiment of the present application;

[0030] Figure 4 is a structural schematic diagram of a module generation device according to an embodiment of the present application;

[0031] Figure 5 is a schematic diagram of a process for generating a top-level file of a system on chip according to an embodiment of the present application;

[0032] Figure 6 It is a structural schematic diagram of a top-level file generation device of a system on chip according to an embodiment of the present application. DETAILED DESCRIPTION

[0033] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0034] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0035] The method embodiments provided in the embodiments of the present application can be executed in a server device or a similar computing device. Taking running on a server device as an example, Figure 1 FIG. 1 is a schematic diagram of the hardware environment of a method for generating a top-level file of a system on a chip according to an embodiment of the present application. Figure 1 As shown, the server device may include one or more ( Figure 1Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the above-mentioned server device may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above server device. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown.

[0036] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the method for generating the top-level file of the system on chip in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the server device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0037] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the server device. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0038] In this embodiment, a method for generating a top-level file of a system on chip is provided. Figure 2 is a flow chart of a method for generating a top-level file of a system on chip according to an embodiment of the present application, such as Figure 2 As shown, the process includes the following steps:

[0039] Step S202, obtaining a first design file of the system on chip, wherein the first design file is a code file pre-generated based on a hardware description language, and the first design file includes parameter design files and port design files of each component of the system on chip;

[0040] Step S204, parsing the first design file, and converting the first parsing result into a file in a first preset format to obtain a first file library, wherein the first preset format is a lightweight data exchange format;

[0041] Step S206, generating a port file library and a parameter file library based on the first file library, wherein the port file library includes the port information in the port design file, and the parameter file library includes the parameter information in the parameter design file, and both the port design file and the parameter design file are in the lightweight data exchange format;

[0042] Step S208, generating a target top-level file using the port file library, the parameter file library and the target configuration file, wherein the target top-level file is used to configure the operating parameters of each of the above components, and the target configuration file includes information declaring the first design file.

[0043] Optionally, in this embodiment, the system on chip is a complete information processing system integrated on a processing unit, and the system on chip integrates multiple components in a traditional computer or other electronic system, such as: processor core, memory, input / output devices and various modules.

[0044] Optionally, in this embodiment, the hardware description language may be a synthesizable RTL code written by a front-end design engineer using Verilog HDL or System Verilog HDL.

[0045] Optionally, in this embodiment, the format of the first design file is ".v" or ".sv".

[0046] Optionally, in this embodiment, the first preset format is a lightweight data exchange format, and the first preset format specifically refers to a file in the ".json" format.

[0047] Optionally, in this embodiment, the port information is information of ports of each module, including but not limited to: input ports, output ports and bidirectional ports.

[0048] Optionally, in this embodiment, the parameter information is related to parameters of each module, including but not limited to: port width, port signal type, and port name.

[0049] Optionally, in this embodiment, the target top-level file is used to configure the operating parameters of each of the above components, including but not limited to: parameters related to the integration of multiple modules, clock management, reset control, register configuration, pin multiplexing and system partitioning.

[0050] Through this embodiment, the first design file is parsed to obtain the first file library, and the target top-level file is generated based on the port file library and parameter file library obtained by parsing the first file library and the obtained target configuration file. Therefore, the problem of low efficiency of top-level file design in the related art can be solved, and the effect of efficiently generating top-level files can be achieved.

[0051] In an exemplary embodiment, obtaining a first design file of a system on chip includes: accessing a file database according to an acquired first storage path, wherein the file database includes a plurality of stored design files; searching the design database for a design file that matches the parameters and / or ports of each of the above components, and reading the design file to obtain the first design file.

[0052] Optionally, in this embodiment, the format of the first design file has been described above and will not be repeated here.

[0053] Through this embodiment, the file database is accessed according to the obtained first storage path, and the design files matching the parameters and / or ports of each component are integrated to generate a first design file. The first design file is saved in a specified path, which can shorten the time for finding related design files and thereby improve the efficiency of generating the target top-level file.

[0054] In an exemplary embodiment, parsing a first design file and converting the first parsing result into a file in a first preset format to obtain a first file library includes: parsing the first design file into an abstract syntax tree, wherein the abstract syntax tree includes the file structure of the first design file and the syntax structure used to generate the first design file; converting the abstract syntax tree into a file in the first preset format to obtain the first file library.

[0055] Optionally, in this embodiment, the Abstract Syntax Tree (AST) is a tree representation of the abstract syntax structure of the first design file. In compilation theory, it is used to represent the source code structure of a programming language and is usually generated by a compiler in the syntax analysis phase.

[0056] Optionally, in this embodiment, the key features of the abstract syntax tree include but are not limited to: nodes, each node represents a construct in the first design file; information that the syntax analyzer cares about, excluding information that does not affect the program logic, such as spaces, comments, or text formatting; the nodes in the tree correspond to the grammatical rules of the programming language, such as expressions, statements, declarations, etc.; and represent the hierarchical relationship between grammatical elements.

[0057] Through this embodiment, by parsing the file into an abstract syntax tree and then converting the abstract syntax tree into a file of a preset format, the readability, maintainability, portability and security of the design file can be improved, while supporting various operations such as analysis, conversion, and optimization of the design file.

[0058] In an exemplary embodiment, parsing the first design file into an abstract syntax tree includes: dividing the first design file into N lexical units, wherein the lexical unit is the smallest grammatical unit of the first design file, and N is a positive integer; combining the N lexical units according to preset grammatical rules to obtain M grammatical structures, wherein the grammatical structures are grammatical rules of the hardware description language, and M is a positive integer less than or equal to N; and generating the abstract syntax tree based on the M grammatical structures.

[0059] Optionally, in this embodiment, a lexical unit is composed of a lexical unit name and an optional attribute value, the lexical unit name is an abstract symbol representing the lexical unit, and the attribute value represents the relevant information of the lexical unit. For example, a lexical unit "id" represents an identifier of a programming language, and its attribute value is a pointer to the specific identifier information (in the symbol table); a lexical unit "number" represents a numeric constant, and its attribute value is the specific value of the numeric constant.

[0060] Optionally, in this embodiment, the attribute values ​​included in the lexical unit include, but are not limited to: numbers, character strings, identifiers, operators, keywords, and the like.

[0061] Optionally, in this embodiment, the priority of operators is from high to low, as shown in Table 1:

[0062] Table 1:

[0063]

[0064] Optionally, in this embodiment, the preset grammar rules may be given in the form of Backus-Naur Form or extended Backus-Naur Form, or may be given using a formal grammar, such as Context-Free Grammar (CFG for short).

[0065] Optionally, in this embodiment, the grammatical structure is used to represent the grammatical rules of the hardware description language, including but not limited to: basic expressions, process statements (always / always_ff / always_comb / always_latch statements), block statements (serial block begin-end, parallel block fork-join), assignment statements (assign), conditional statements (if-else statements, case / casex / casez statements), loop statements (for statements, repeat statements, while statements, forever statements), compilation wizards (`define macro replacement, `include file inclusion, `ifdef / `else / `endif conditional compilation), functions (function), tasks (task), types (typedef) and packages (package), etc.

[0066] Optionally, in this embodiment, if Figure 3 As shown, it is a schematic diagram of converting a first design file into a first file library. The first design file is divided into N lexical units through a lexical analysis module. The N lexical units are combined in the syntax analysis module according to preset grammar rules to obtain M grammatical structures, and an abstract syntax tree is generated based on the M grammatical structures. Finally, the syntax analysis module outputs the first file library.

[0067] Through this embodiment, the first design file is divided into lexical units, and then the lexical units are combined based on preset grammar rules to generate a standardized grammatical structure, and an abstract syntax tree is generated according to the grammatical structure, so that the first design file is converted into a standardized language display, which facilitates the subsequent conversion of the first design file into a file in the first preset format.

[0068] In an exemplary embodiment, a port file library and a parameter file library are generated based on a first file library, including: parsing the above-mentioned first file library, and integrating the parsed port information in the above-mentioned port design files and the parameter information in the above-mentioned parameter design files to obtain a first set; storing the above-mentioned first set to obtain a second file library; generating the above-mentioned port file library and the above-mentioned parameter file library based on the above-mentioned second file library.

[0069] Optionally, in this embodiment, in addition to port information and parameter information, the first set also includes but is not limited to: write type data, reg type data, memory type data, integer data, large type data, medium type data, small type data, scalared type data, tri type data, triand type data, trior type data, trireg type data, vectored type data, wand type data, wor type data, supply0 type data, supply1 type data, instantiation, function, procedure (always / always_ff / always_comb / always_latch statements), begin-end, fork-join, assign, if-else, case (case / casex / casez), for, repeat, while and forever, etc.

[0070] Optionally, in this embodiment, the second file library is also a file library in the first preset format.

[0071] Through this embodiment, by integrating and storing the port information, parameter information and other types of data in the second file library, and then using the second file library to generate a port file library and a parameter file library, it is convenient to verify the port information and some parameters later.

[0072] In an exemplary embodiment, a port file library and a parameter file library are generated based on a second file library, including: obtaining a port name from the second file library; extracting port information in the port design file from the first file library according to the port name, and storing the port information to obtain the port file library; extracting information whose information attribute is a parameter from the second file library to obtain parameter information in the parameter design file, and storing the parameter information to obtain the parameter file library.

[0073] Optionally, in this embodiment, the port name should be a combination of letters and numbers, consisting of letters (AZ, az), numbers (0-9), and may also contain underscores (_), but cannot contain spaces and special characters.

[0074] Optionally, in this embodiment, the contents included in the port information have been described above and will not be repeated here.

[0075] Optionally, in this embodiment, the contents included in the parameter information have been described above and will not be repeated here.

[0076] Through this embodiment, port information is obtained by filtering from the second file library, parameter information is obtained according to the attributes of the information, and then they are stored as a port file library and a parameter file library respectively. Storing in the form of a file library can improve the reusability of related parameters. When the port or parameter needs to be modified, it only needs to be updated once in the file library, and all referenced places will be automatically updated, thereby improving the efficiency of modification and maintenance.

[0077] In an exemplary embodiment, a target top-level file is generated using a port file library, a parameter file library and a target configuration file, including: extracting the name of the top-level file from the above-mentioned target configuration file; parsing the names of the above-mentioned port file library, the above-mentioned parameter file library and the above-mentioned top-level file to obtain a second parsing result, wherein the above-mentioned second parsing result includes the connection relationship between each of the above-mentioned ports; and generating the above-mentioned target top-level file using the above-mentioned second parsing result.

[0078] Optionally, in this embodiment, the target configuration file may include not only the name of the top-level file but also the connection status between the ports of each module and the setting of parameters.

[0079] Optionally, in this embodiment, the connection status between ports can be expressed as follows: a high-width port of a module is connected to a low-width port of another module, for example, TOP.port1[4]>>module1.port, module2.port1[3:0]>>module1.port2[3:0]; or a port of a module is connected to a port of another module, for example, module1.port1 >> module2.port2.

[0080] Through this embodiment, by obtaining the target configuration file and the previously obtained parameter file library and target configuration file, the above files are parsed to obtain the parsing results, and the connection status between the ports is further determined. The target top-level file is generated according to the parsing situation, and the port connection method of each module is determined to facilitate the subsequent generation of the target top-level file.

[0081] In an exemplary embodiment, the names of the port file library, the parameter file library and the top-level file are parsed to obtain a second parsing result, including: parsing the connection status of the ports between each of the above-mentioned components from the names of the above-mentioned port file library, the above-mentioned parameter file library and the above-mentioned top-level file to obtain the above-mentioned second parsing result.

[0082] Optionally, in this embodiment, the contents included in the target configuration file and the connection between the ports have been described above and will not be repeated here.

[0083] Through this embodiment, a second parsing result is obtained based on the port file library, parameter file library and target configuration file, and the connection status between the ports of each module is determined based on the second parsing result. The port connection method of each module is determined to facilitate the subsequent generation of the target top-level file.

[0084] In an exemplary embodiment, the connection status of the ports between the various components is parsed from the names of the port file library, the parameter file library and the top-level file to obtain a second parsing result, including: parsing the first connection relationship between the above-mentioned ports from the above-mentioned port file library to obtain a first connection sub-file; determining the first target port whose connection status is not specified from the above-mentioned first connection sub-file; setting the first parameter to establish an association relationship between the above-mentioned first target port and each of the above-mentioned components, and generating the above-mentioned second parsing result using the above-mentioned parameter file library, the name of the above-mentioned top-level file and the above-mentioned first parameter.

[0085] Optionally, in this embodiment, the first connection sub-file records the connection status between various ports recorded in the port file library, the parameter file library and the target configuration file.

[0086] Optionally, in this embodiment, the first target port is connected to each component by default, and the types of the input port, output port, bidirectional port of the component's port and the bit width of the above ports all inherit the types of the input port, output port, bidirectional port and the bit width of the first target port.

[0087] Through this embodiment, by setting the first parameter, an association relationship between the first target port whose connection status is not specified in the first connection sub-file and the ports of each component is established, and then the second parsing result is generated according to the parameter file library, the name of the top-level file and the first parameter, so that the connection status of the ports of each module in the on-chip system is recorded in the file, so that the content recorded in the subsequent target top-level file is complete.

[0088] In an exemplary embodiment, after parsing the connection status of the ports between the various components from the names of the port file library, the parameter file library and the top-level file to obtain the second parsing result, the method further includes: determining the connection mode of the second target port based on the connection status of the ports between the various components and the connection priority of the preset port, wherein the second target port is any port included in the above parsing result; determining whether the port information between the second target port and the third target port is consistent based on the connection mode of the second target port, wherein the third target port is a port connected to the second target port; in the case where the port information between the second target port and the third target port is consistent, generating the target top-level file using the second parsing result; in the case where the port information between the second target port and the third target port is inconsistent, issuing an exception message, wherein the exception message is used to indicate that there is an exception in the port information in the first file library.

[0089] Optionally, in this embodiment, the preset port connection priority is used to match the four elements of port connection, port width, port signal type and port name keyword recorded in the target configuration file. The preset port connection priority is shown in Table 2.

[0090] Table 2:

[0091]

[0092] Through this embodiment, the connection mode of the second target port is determined based on the connection status of the ports between the various components and the connection priority of the preset port, and based on the connection mode of the second target port, it is determined whether the port information between the second target port and the third target port is consistent. When the port information is consistent, a target top-level file is generated, thereby ensuring the validity of the port information in the target top-level file.

[0093] In an exemplary embodiment, after generating a target top-level file using the parsing result, the method further includes: storing the target top-level file in a file database and generating a second storage path; in response to a fetch instruction, searching for a second design file of the system on chip from the file database according to the second storage path in response to the fetch instruction when receiving the fetch instruction, wherein the second design file is a file other than the target top-level file and is used to configure the operating parameters of each of the components; parsing the second design file and converting the third parsing result obtained into a file in the first preset format to obtain a fifth file library, wherein the fifth file library includes the port information and the parameter information; performing a verification operation on the fifth file library and updating the second design file based on the verification result, wherein the verification result is used to indicate that all design files in the system on chip allow the operating parameters of each of the components to be configured.

[0094] Optionally, in this embodiment, the second design file includes files for generating various modules, layout and routing information of the system on chip, etc.

[0095] Through this embodiment, by searching the second design file of the system on chip and the target top-level file from the file database, all design files of the system on chip are converted into files of a first preset format to obtain a fifth file library, and then the fifth file library is verified, and the second design file is updated based on the verification result, thereby ensuring that all design files of the system on chip can successfully configure various components of the system on chip.

[0096] In an exemplary embodiment, a verification operation is performed on a fifth file library, and a second design file is updated based on the verification result, including: performing the verification operation on the fifth file library according to preset verification rules to obtain the verification result, wherein the preset verification rule includes at least one of the following: whether there are duplications in the port names of the ports, whether there are duplications in the naming of the plurality of parameter information, whether there are dangling instantiated ports included in the ports, whether the port signals of the ports are connected to the target device, whether the preset port connection priority is satisfied between the target port signals in the ports and the corresponding source port signals, whether the signal transmission directions between the target port signals in the ports and the corresponding source port signals match, whether the bit widths between the target port signals in the ports and the corresponding source port signals match, and whether the naming of each design file of the system on chip is repeated; and updating the second design file according to the verification result.

[0097] Optionally, in this embodiment, the fifth file library is verified based on preset verification rules by a verification module, which is a software package written in Python language and mainly consists of five Python files (bind_analyzer.py, checker.py, merge.py, _init_.py and main.py).

[0098] Optionally, in this embodiment, instantiating a port is in a hardware description language, especially in Verilog software, and refers to connecting a port of a module to a specific signal or value during the instantiation of the module. In Verilog, module instantiation can be performed in two ways: sequential port connection, which depends on the order of port definition; and name-based port connection, which allows the order of port connection to be inconsistent with the order of module definition, as long as the port name matches the external signal.

[0099] Optionally, in this embodiment, when instantiating a module in Verilog, the ports can be connected according to the following rules: input ports can be connected to variables of type `wire` or `reg`; output ports must be connected to variables of type `wire`; input and output ports must be connected to variables of type `wire`; if some output ports do not need to be connected externally, they can be left floating or even deleted during instantiation.

[0100] Through this embodiment, a verification operation is performed on the fifth file library through preset verification rules to ensure that the port information, parameter information and other contents meet the preset rules, and the design files with abnormalities are updated according to the verification results, which can ensure the integrity, security and reliability of the data and further achieve the effect of improving the overall performance of the on-chip system.

[0101] In an exemplary embodiment, updating the second design file according to the verification result includes: when it is determined from the verification result that there is an abnormality in the fifth file library, obtaining a log file indicating the abnormality in the fifth file library; generating a sixth file library based on the log file and the fifth file library, wherein the sixth file library is a file library obtained after performing an update operation on the abnormal information in the fifth file library, and the sixth file library is a file library verified by the preset verification rule; and updating the second design file according to the sixth file library.

[0102] Optionally, in this embodiment, the log file records the exception information in the fifth file library that does not meet the preset verification rules. The specific record content is as follows: if the port naming is repeated, add a comment " / / ERROR"; if the parameter naming is repeated, add a comment " / / ERROR"; if the instantiated port is suspended, add a comment " / / TODO"; if the port signal is not connected to the target device, add a comment " / / TODO"; if the target port signal and the corresponding source port signal do not meet the preset port connection priority, add a comment " / / ERROR"; if the target port signal and the corresponding source port signal transmission direction (input>>output) do not match, add a comment " / / ERROR"; if the target port signal and the corresponding source port signal bit width do not match, add a comment " / / ERROR"; if the second design file of the system on chip is named repeatedly, add a comment " / / REPEAT".

[0103] Through this embodiment, when it is determined from the verification result that there is an abnormality in the fifth file library, a log file indicating the existence of the abnormality in the fifth file library is obtained, and then a sixth file library is generated based on the log file and the fifth file library, and the second design file is updated according to the sixth file library, and the abnormal information in all design files of the on-chip system is updated and replaced, ensuring that the various components configured according to the target top-level file can operate normally afterwards.

[0104] In an exemplary embodiment, the target top-level file is generated using the second parsing result, including: obtaining connection information between each of the above-mentioned ports from the above-mentioned second parsing result; configuring the connection between each of the above-mentioned ports according to the connection information between each of the above-mentioned ports to obtain port configuration information; and determining the above-mentioned target top-level file based on the above-mentioned port configuration information.

[0105] Optionally, in this embodiment, the connection information between ports includes but is not limited to port information and parameter information.

[0106] Optionally, in this embodiment, the contents included in the port information have been described above and will not be repeated here.

[0107] Optionally, in this embodiment, the contents included in the parameter information have been described above and will not be repeated here.

[0108] Through this embodiment, the port configuration information determined from the connection information between the above-mentioned ports obtained from the second analysis result is determined as the target top-level file, and verification operations are performed on all design files of the on-chip system. After the abnormal file is updated, the content in the target top-level file will also be updated accordingly, ensuring the consistency of relevant information and ensuring that the subsequent components configured according to the target top-level file can operate normally.

[0109] It should be noted that, through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, disk, CD), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the above methods of each embodiment of the present application.

[0110] In an exemplary embodiment, a module generation device is also provided, such as Figure 4 According to the structural schematic diagram of a module generation device in an embodiment of the present application, the module generation device includes an input device, a memory, a processor, an output device and a communication bus, and the input device, the memory, the processor and the output device are all connected through the communication bus.

[0111] In an exemplary embodiment, Figure 5 is a schematic diagram of a process for generating a top-level file of a system on chip according to an embodiment of the present application, such as Figure 5 As shown:

[0112] Step S5002, inputting the first design file into the code parsing module;

[0113] Step S5004, the code parsing module is used to divide the first design file into N lexical units, then combine the N lexical units according to preset grammar rules to obtain M grammatical structures, generate an abstract syntax tree based on the M grammatical structures, and finally convert them into a first file library;

[0114] Step S5006, after receiving the first file library, the data flow analysis module performs parsing to generate a port file library and a parameter file library;

[0115] Step S5008, the top-level file generation module is used to extract the name of the top-level file from the target configuration file, and then parse the names of the port file library, the parameter file library and the top-level file to obtain a second parsing result, and generate the target top-level file using the second parsing result;

[0116] Step S5010, after obtaining the target top-level file, verify the target top-level file and the second design file of the system on chip to verify whether there are duplications in the port names, whether there are duplications in the naming of parameter information, whether the instantiated ports included in the ports are dangling, whether the port signals of each port are connected to the target device, whether the target port signals in each port and the corresponding source port signals meet the preset port connection priority, whether the signal transmission directions between the target port signals in each port and the corresponding source port signals match, whether the bit widths between the target port signals in each port and the corresponding source port signals match, and whether the naming of each design file of the system on chip is repeated. If the verification fails, update the second design file and verify again until the verification passes;

[0117] Step S5012, after verification, determine the target top-level file that is finally generated.

[0118] In this embodiment, a device for generating the top-level file of a system on chip is also provided, and the device is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made are not repeated here. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0119] Figure 6 is a structural block diagram of a top-level file generation device of a system on chip according to an embodiment of the present application, such as Figure 6 As shown, the device comprises:

[0120] An acquisition module 62 is used to acquire a first design file of the system on chip, wherein the first design file is a code file pre-generated based on a hardware description language, and the first design file includes a parameter design file and a port design file of each component of the system on chip;

[0121] The parsing module 64 is used to parse the first design file and convert the first parsing result into a file in a first preset format to obtain a first file library, wherein the first preset format is a lightweight data exchange format;

[0122] A first generating module 66, configured to generate a port file library and a parameter file library based on the first file library, wherein the port file library includes the port information in the port design file, and the parameter file library includes the parameter information in the parameter design file, and both the port design file and the parameter design file are in the lightweight data exchange format;

[0123] The second generation module 68 is used to generate a target top-level file using the above-mentioned port file library, the above-mentioned parameter file library and the target configuration file, wherein the above-mentioned target top-level file is used to configure the operating parameters of each of the above-mentioned components, and the above-mentioned target configuration file includes information declaring the above-mentioned first design file.

[0124] In an exemplary embodiment, the above-mentioned device is also used to access a file database according to the acquired first storage path, wherein the above-mentioned file database includes a plurality of stored design files; search the above-mentioned design database for design files matching the parameters and / or ports of each of the above-mentioned components, and read the above-mentioned design files to obtain the above-mentioned first design file.

[0125] In an exemplary embodiment, the above-mentioned device is also used to parse the first design file into an abstract syntax tree, wherein the above-mentioned abstract syntax tree includes the file structure of the above-mentioned first design file and the syntax structure used to generate the above-mentioned first design file; convert the above-mentioned abstract syntax tree into a file in the above-mentioned first preset format to obtain the above-mentioned first file library.

[0126] In an exemplary embodiment, the above-mentioned device is also used to divide the first design file into N lexical units, wherein the above-mentioned lexical units are the smallest grammatical units of the above-mentioned first design file, and the above-mentioned N is a positive integer; the above-mentioned N lexical units are combined according to preset grammatical rules to obtain M grammatical structures, wherein the above-mentioned grammatical structures are the grammatical rules of the above-mentioned hardware description language, and the above-mentioned M is a positive integer less than or equal to the above-mentioned N; the above-mentioned abstract syntax tree is generated based on the above-mentioned M grammatical structures.

[0127] In an exemplary embodiment, the above-mentioned device is also used to parse the first file library, and integrate the port information in the parsed port design file and the parameter information in the parameter design file to obtain a first set; store the above-mentioned first set to obtain a second file library; and generate the above-mentioned port file library and the above-mentioned parameter file library based on the above-mentioned second file library.

[0128] In an exemplary embodiment, the above-mentioned device is also used to obtain the port name from the second file library; extract the port information in the above-mentioned port design file from the above-mentioned first file library according to the above-mentioned port name, and store the above-mentioned port information to obtain the above-mentioned port file library; extract information whose information attribute is a parameter from the above-mentioned second file library, obtain the parameter information in the above-mentioned parameter design file, and store the above-mentioned parameter information to obtain the above-mentioned parameter file library.

[0129] In an exemplary embodiment, the above-mentioned device is also used to extract the name of the top-level file from the target configuration file; parse the name of the above-mentioned port file library, the above-mentioned parameter file library and the above-mentioned top-level file to obtain a second parsing result, wherein the above-mentioned second parsing result includes the connection relationship between each of the above-mentioned ports; and use the above-mentioned second parsing result to generate the above-mentioned target top-level file.

[0130] In an exemplary embodiment, the above-mentioned device is also used to parse the connection status of the ports between the various components from the names of the port file library, the parameter file library and the top-level file to obtain a second parsing result.

[0131] In an exemplary embodiment, the above-mentioned device is also used to parse the first connection relationship between each port from the port file library to obtain a first connection sub-file; determine the first target port whose connection situation is not specified from the above-mentioned first connection sub-file; set the first parameter to establish an association relationship between the above-mentioned first target port and the above-mentioned top-level file; and generate the above-mentioned second parsing result using the above-mentioned parameter file library, the name of the above-mentioned top-level file and the above-mentioned first parameter.

[0132] In an exemplary embodiment, the above-mentioned device is also used to determine the connection mode of the second target port based on the connection status of the ports between the various components and the connection priority of the preset port, wherein the above-mentioned second target port is any port included in the above-mentioned parsing result; based on the connection mode of the above-mentioned second target port, determine whether the port information between the above-mentioned second target port and the third target port is consistent, wherein the above-mentioned third target port is a port connected to the above-mentioned second target port; when the port information between the above-mentioned second target port and the third target port is consistent, generate the above-mentioned target top-level file using the above-mentioned second parsing result; when the port information between the above-mentioned second target port and the third target port is inconsistent, issue an exception message, wherein the above-mentioned exception message is used to indicate that there is an exception in the port information in the above-mentioned first file library.

[0133] In an exemplary embodiment, the above-mentioned device is also used to store the above-mentioned target top-level file in a file database and generate a second storage path; in the case of receiving an acquisition instruction, responding to the above-mentioned acquisition instruction, searching the second design file of the above-mentioned system on chip from the above-mentioned file database according to the above-mentioned second storage path, wherein the above-mentioned second design file is a file other than the above-mentioned target top-level file and is used to configure the operating parameters of each of the above-mentioned components; parsing the above-mentioned second design file, and converting the third parsing result obtained into a file in the above-mentioned first preset format to obtain a fifth file library, and the above-mentioned fifth file library includes the above-mentioned port information and the above-mentioned parameter information; performing a verification operation on the above-mentioned fifth file library, and updating the above-mentioned second design file based on the verification result, wherein the above-mentioned verification result is used to indicate that all design files in the above-mentioned system on chip allow the configuration of the operating parameters of each of the above-mentioned components.

[0134] In an exemplary embodiment, the above-mentioned device is also used to perform a verification operation on the fifth file library according to preset verification rules to obtain a verification result, wherein the above-mentioned preset verification rules include at least one of the following: whether there are duplications in the port names of each of the above-mentioned ports, whether there are duplications in the naming of multiple of the above-mentioned parameter information, whether the instantiated ports included in each of the above-mentioned ports are suspended, whether the port signals of each of the above-mentioned ports are connected to the target device, whether the preset port connection priority is satisfied between the target port signals in each of the above-mentioned ports and the corresponding source port signals, whether the signal transmission directions between the target port signals in each of the above-mentioned ports and the corresponding source port signals match, whether the bit widths between the target port signals in each of the above-mentioned ports and the corresponding source port signals match, and whether the naming of each design file of the above-mentioned system on chip is repeated; the above-mentioned second design file is updated according to the above-mentioned verification results.

[0135] In an exemplary embodiment, the above-mentioned device is also used to obtain a log file indicating the existence of an abnormality in the fifth file library when it is determined from the verification result that there is an abnormality in the fifth file library; generate a sixth file library based on the above-mentioned log file and the above-mentioned fifth file library, wherein the above-mentioned sixth file library is a file library obtained after performing an update operation on the abnormal information in the above-mentioned fifth file library, and the above-mentioned sixth file library is a file library verified by the above-mentioned preset verification rules; and update the above-mentioned second design file according to the above-mentioned sixth file library.

[0136] In an exemplary embodiment, the above-mentioned device is also used to obtain connection information between each port from the second parsing result; configure the connection between each of the above-mentioned ports according to the connection information between each of the above-mentioned ports to obtain port configuration information; and determine the above-mentioned target top-level file based on the above-mentioned port configuration information.

[0137] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0138] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0139] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0140] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0141] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0142] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above method embodiments are implemented.

[0143] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0144] The embodiments of the present application also provide a computer program, which includes computer instructions, which are stored in a computer-readable storage medium; a processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the steps of any one of the above method embodiments.

[0145] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0146] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0147] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for generating a top-level file of a system on chip, characterized in that: Applied to a module generation device, the method comprises: Acquire a first design file of the system on chip, wherein the first design file is a code file pre-generated based on a hardware description language, and the first design file includes a parameter design file and a port design file of each component of the system on chip; Parsing the first design file, and converting the first parsing result into a file in a first preset format to obtain a first file library, wherein the first preset format is a lightweight data exchange format; Generate a port file library and a parameter file library based on the first file library, wherein the port file library includes the port information in the port design file, the parameter file library includes the parameter information in the parameter design file, and the port design file and the parameter design file are both in the lightweight data exchange format; A target top-level file is generated using the port file library, the parameter file library and the target configuration file, wherein the target top-level file is used to configure the operating parameters of each of the components, and the target configuration file includes information declaring the first design file.

2. The method according to claim 1, characterized in that Obtaining a first design file of the system on chip, including: Accessing a file database according to the acquired first storage path, wherein the file database includes a plurality of stored design files; A design file matching the parameters and / or ports of each of the components is searched in a design database, and the design file is read to obtain the first design file.

3. The method according to claim 1, characterized in that Parsing the first design file and converting the first parsing result into a file in a first preset format to obtain a first file library, including: Parsing the first design file into an abstract syntax tree, wherein the abstract syntax tree includes a file structure of the first design file and a syntax structure used to generate the first design file; The abstract syntax tree is converted into a file in the first preset format to obtain the first file library.

4. The method according to claim 3, characterized in that Parsing the first design file into an abstract syntax tree includes: Divide the first design file into N lexical units, wherein the lexical unit is the smallest grammatical unit of the first design file, and N is a positive integer; Combining the N lexical units according to preset grammatical rules to obtain M grammatical structures, wherein the grammatical structures are grammatical rules of the hardware description language, and M is a positive integer less than or equal to N; The abstract syntax tree is generated based on the M syntax structures.

5. The method according to claim 1, characterized in that: Generating a port file library and a parameter file library based on the first file library includes: Parsing the first file library, and integrating the parsed port information in the port design file and the parameter information in the parameter design file to obtain a first set; storing the first set to obtain a second file library; The port file library and the parameter file library are generated based on the second file library.

6. The method according to claim 5, characterized in that Generating the port file library and the parameter file library based on the second file library includes: Obtaining a port name from the second file library; Extracting the port information in the port design file from the first file library according to the port name, and storing the port information to obtain the port file library; The information whose information attribute is parameter is extracted from the second file library to obtain the parameter information in the parameter design file, and the parameter information is stored to obtain the parameter file library.

7. The method according to claim 1, characterized in that Generate a target top-level file using the port file library, the parameter file library and the target configuration file, including: Extracting the name of the top-level file from the target configuration file; Parsing the names of the port file library, the parameter file library and the top-level file to obtain a second parsing result, wherein the second parsing result includes a connection relationship between each of the ports; The target top-level file is generated using the second parsing result.

8. The method according to claim 7, characterized in that Parsing the names of the port file library, the parameter file library, and the top-level file to obtain a second parsing result includes: The connection status of the ports between the components is parsed from the names of the port file library, the parameter file library and the top-level file to obtain the second parsing result.

9. The method according to claim 8, characterized in that Parsing the connection status of the ports between the components from the names of the port file library, the parameter file library and the top-level file to obtain the second parsing result includes: Parsing the first connection relationship between the ports from the port file library to obtain a first connection sub-file; Determine a first target port for which a connection condition is not specified from the first connection subfile; A first parameter is set to establish an association relationship between the first target port and each of the components, and the second parsing result is generated using the parameter file library, the name of the top-level file and the first parameter.

10. The method according to claim 8, characterized in that After parsing the connection status of the ports between the components from the names of the port file library, the parameter file library and the top-level file and obtaining the second parsing result, the method further includes: Determine a connection mode of a second target port based on the connection conditions of ports between the components and the connection priorities of the preset ports, wherein the second target port is any port included in the parsing result; Based on the connection mode of the second target port, determining whether the port information between the second target port and a third target port is consistent, wherein the third target port is a port connected to the second target port; In the case where the port information between the second target port and the third target port is consistent, generating the target top-level file using the second parsing result; When the port information between the second target port and the third target port is inconsistent, an exception message is issued, wherein the exception message is used to indicate that an exception exists in the port information in the first file library.

11. The method according to claim 7, characterized in that After generating the target top-level file using the parsing result, the method further includes: Storing the target top-level file in a file database and generating a second storage path; In response to the acquisition instruction, searching the file database for a second design file of the system on chip according to the second storage path in response to the acquisition instruction, wherein the second design file is a file other than the target top-level file and is used to configure the operating parameters of each of the components; Parsing the second design file, and converting the obtained third parsing result into a file in the first preset format to obtain a fifth file library, wherein the fifth file library includes the port information and the parameter information; A verification operation is performed on the fifth file library, and the second design file is updated based on a verification result, wherein the verification result is used to indicate that all design files in the system on chip allow the operation parameters of each component to be configured.

12. The method according to claim 11, characterized in that Performing a verification operation on the fifth file library and updating the second design file based on the verification result, comprising: Performing the verification operation on the fifth file library according to preset verification rules to obtain the verification result, wherein the preset verification rules include at least one of the following: whether there are duplications in the port names of the ports, whether there are duplications in the naming of the plurality of parameter information, whether the instantiated ports included in the ports are dangling, whether the port signals of the ports are connected to the target device, whether the preset port connection priority is satisfied between the target port signals in the ports and the corresponding source port signals, whether the signal transmission directions between the target port signals in the ports and the corresponding source port signals match, whether the bit widths between the target port signals in the ports and the corresponding source port signals match, and whether the naming of each design file of the system on chip is repeated; The second design file is updated according to the verification result.

13. The method according to claim 12, characterized in that Updating the second design file according to the verification result includes: When it is determined from the verification result that the fifth file library has an abnormality, obtaining a log file indicating that the fifth file library has an abnormality; Generate a sixth file library based on the log file and the fifth file library, wherein the sixth file library is a file library obtained after performing an update operation on the abnormal information in the fifth file library, and the sixth file library is a file library verified by the preset verification rule; The second design file is updated according to the sixth file library.

14. The method according to claim 7, characterized in that Generating the target top-level file using the second parsing result includes: Acquire connection information between each of the ports from the second parsing result; Configure the connection between the ports according to the connection information between the ports to obtain the port configuration information; Based on the port configuration information, the target top-level file is determined.

15. A module generation device, characterized in that: include: An input device, used for transmitting a first design file of the system on chip, wherein the first design file is a code file pre-generated based on a hardware description language, and the first design file includes a parameter design file and a port design file of each component of the system on chip; A memory, connected to the input device, and used to store the first design file and the file generation instruction; A processor connected to the memory, wherein the method according to any one of claims 1 to 14 is deployed on the processor; an output device, connected to the processor, for transmitting the target top-level file generated by the processor to the system on chip; Wherein, the input device, the memory, the processor, and the output device are all connected via a communication bus.

16. A system on chip, characterized in that: It comprises the module generating device as claimed in claim 15.

17. A device for generating a top-level file of a system on chip, characterized in that: include: An acquisition module, configured to acquire a first design file of a system on chip, wherein the first design file is a code file pre-generated based on a hardware description language, and the first design file includes a parameter design file and a port design file of each component of the system on chip; A parsing module, used for parsing the first design file and converting the first parsing result into a file in a first preset format to obtain a first file library, wherein the first preset format is a lightweight data exchange format; A first generating module, configured to generate a port file library and a parameter file library based on the first file library, wherein the port file library includes the port information in the port design file, the parameter file library includes the parameter information in the parameter design file, and the port design file and the parameter design file are both in the lightweight data exchange format; The second generation module is used to generate a target top-level file using the port file library, the parameter file library and the target configuration file, wherein the target top-level file is used to configure the operating parameters of each of the components, and the target configuration file includes information declaring the first design file.

18. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method described in any one of claims 1 to 14 are implemented.

19. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in any one of claims 1 to 14 when executed by a processor.

20. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method described in any one of claims 1 to 14 are implemented.

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