Processing system for control and inter-board communication of test machine

Abstract

The invention relates to a processing system for control and inter-board communication of a test machine, which comprises a main control board and 16 functional boards, and is characterized in that signals and signal buses between the main control board and the plurality of functional boards are connected through a signal backboard; the main control board comprises a main control board FPGA module; the data network transmission system, the high-speed and low-speed clock system, the synchronization system, the trigger system and the diagnosis system are connected with the main control board FPGA module. The signal backboard and the function board are separated and flexibly configured, and different function boards can be configured according to needs; according to the invention, communication, synchronization, clock and triggering among a plurality of board cards are comprehensively considered, and the method has the advantages of high performance, high-speed triggering, high-speed clock, high-speed synchronization and low time delay.

Description

Technical Field

[0001] The present invention relates to the field of computer technology and semiconductor test related technical fields, and in particular to a control system of a test machine and a processing system for inter-board communication. Background Art

[0002] ATE (Automatic Test Equipment, abbreviated as ATE) test platform refers to power electronic equipment, electronic loads, measuring instruments, sensors, devices under test, PLC and other hardware equipment connected to the ATE test platform in the form of communication or IO interface, and uniformly managed, controlled and scheduled by the ATE test platform to achieve standard or customized test process requirements; it is widely used in testing institutions, factory production lines, automation laboratories and other institutions.

[0003] ATE integrates a large number of test instrument boards, which can provide power supply for the DUT and measure the voltage, current, leakage current of the DUT. Programmable digital signals are used to send test vectors and other functions. The time domain measurement system is used to measure timing, frequency, edge, synchronization, etc.; it also supports multi-channel testing (a single test machine can support hundreds of channels, which can be expanded to thousands of channels).

[0004] After massive searches, it was found that the prior art publication number is CN219085413U, which discloses a PC embedded ATE device, which relates to the field of electronic equipment. The device includes: a backplane, a main control board, a function board, and a high-speed connector. The main control board is connected to the backplane via a high-speed connector, and the main control board includes a PC module. The PC embedded ATE device described in the utility model has a small size and saves installation space. At the same time, the signaling interaction speed during the test is fast, which greatly improves the test efficiency of the ATE device.

[0005] After massive searches, it was found that the prior art publication number is CN218481612U, which discloses a universal MCU test board based on an ATE system, which includes a main controller, a PMU measurement unit, a digital channel and a DPS power supply module; the PMU measurement unit and the digital channel are switched to the GPIO of the IC to be tested through an analog switch; the DPS power supply module provides the required working voltage and current to the IC to be tested; the PMU measurement unit, the digital channel and the DPS power supply module are all connected to the main controller signal; the main controller interacts with the PC through the USART interface. The beneficial effects of the utility model are: simulating the ATE test process, and realizing the functional test of the general MCU at the lowest cost. The device can not only realize the main functions of the ATE test equipment, but also greatly reduce its cost compared to the ATE equipment. And the device can be modified accordingly for different MCU chips to realize more MCU chip test functions.

[0006] However, existing test platforms generally have poor flexibility, cannot be configured with different functional boards as needed, have poor scalability, and have poor integration.

[0007] In view of the above-mentioned defects, the designers have actively carried out research and innovation in order to create a control system for the test machine and a processing system for inter-board communication to make it more valuable for industrial use. Summary of the invention

[0008] In order to solve the above technical problems, the object of the present invention is to provide a control system for a test machine and a processing system for inter-board communication.

[0009] To achieve the above object, the present invention adopts the following technical solution:

[0010] A control and inter-board communication processing system for a test machine, including a main control board and 16 function boards, and connecting the signals between the main control board and several function boards and a signal bus through a signal backplane;

[0011] The main control board includes a main control board FPGA module; and a data network transmission system, a high-speed and low-speed clock system, a synchronization system, a trigger system and a diagnostic system connected to the above-mentioned main control board FPGA module;

[0012] The data network transmission system builds a 16-port switch system combined with the main control board FPGA module. The 16-port switch system can communicate directly with the main control board FPGA module or work independently of the main control board FPGA module.

[0013] High-speed and low-speed clock systems can configure different clocks by sending commands through the main control board FPGA module;

[0014] The synchronization system includes a unidirectional point-to-point synchronization module and a bidirectional point-to-point synchronization module;

[0015] The one-way point-to-point synchronization module is sent from the main control board to 16 function boards for synchronizing other function boards;

[0016] The bidirectional point-to-point synchronization module is initiated by the function board, uploaded to the main control board, and then processed by the main control board and sent to the function board or all function boards that need to be triggered using a unidirectional point-to-point synchronization line;

[0017] The trigger system includes a unidirectional trigger module and a bidirectional trigger module;

[0018] The one-way trigger module is sent from the main control board to 16 function boards for triggering functions;

[0019] The bidirectional trigger module is initiated by the function board, sent to the main control board, and then processed by the main control board and sent to the function board or all function boards that need to be triggered;

[0020] The diagnostic system uses a separate point-to-point IIC communication, which connects the main control board FPGA module to each functional board through the signal backplane, and uses ADC on the main control board to collect information on key parameter points; other functional boards use the IIC bus to achieve point-to-point communication with the main control board, and combined with different card slot addresses, the working status and other information of all functional boards can be monitored in real time.

[0021] As a further improvement of the present invention, adjacent functional boards are connected via an inter-board data transmission bus and used for data exchange of large amounts of data and high bandwidth between adjacent functional boards, using differential transmission.

[0022] As a further improvement of the present invention, the data network transmission system outputs two RJ45 network ports and two 10G SFP+ optical ports, specifically including:

[0023] The RJ45 network port downstream of the switch can be used for data exchange with the main control boards of other parallel test machines;

[0024] The RJ45 network port connected to the FPGA module of the main control board is used for debugging and monitoring functions of this machine;

[0025] The 10G SFP+ optical port connected to the switch is used for data transmission between this test machine and the host computer. The test program or test content can be sent from the host computer, and the test results stored in this machine can be uploaded;

[0026] The 10G SFP+ optical port connected to the FPGA module of the main control board can be used to transmit the test program and test content sent by the host computer, and can also transmit the processed test results to the host computer.

[0027] As a further improvement of the present invention, the high-speed and low-speed clock systems include two groups of homologous clocks, which are fanned out to 16 functional boards by two fan-out chips respectively, providing stable homologous clocks. The original clock output by the FPGA module of the main control board is configured by PLL to generate the required clock input, which is respectively transmitted to two 16-channel LVDS fan-out drivers, one of which is used for high-speed clock and the other for low-speed clock. The two clocks are fanned out to the functional boards of each card slot respectively, and the functional boards select different clocks to use according to needs.

[0028] As a further improvement of the present invention, the high-speed and low-speed clock systems use a phase-locked loop chip on the main control board. The phase-locked loop chip can receive the original clock output by the FPGA module of the main control board for input, or use the local TCXO for original clock generation, or use an external clock input as the clock source of the phase-locked loop chip.

[0029] As a further improvement of the present invention, LVDS differential routing is used from the output of the phase-locked loop chip to the input of the main control board FPGA module of the function board.

[0030] As a further improvement of the present invention, the unidirectional point-to-point synchronization module is a synchronization requirement initiated by the main control board FPGA module or after an external synchronization signal is input to the main control board FPGA module, and is used for some or all functional boards to synchronously test a certain function; or simultaneously output a synchronization signal to other parallel test hosts for synchronous testing of multiple test hosts;

[0031] The bidirectional point-to-point synchronization module is initiated by the test function board, transmitted to the main control board FPGA module for processing, and then sent to a certain function board or all function boards to perform the synchronization function.

[0032] As a further improvement of the present invention, both the unidirectional point-to-point synchronization module and the bidirectional point-to-point synchronization module can be initiated by an external synchronization signal input to the main control board FPGA module, and the main control board FPGA module can also output a synchronization signal to any functional board or output it to other parallel test machines or test units for use.

[0033] As a further improvement of the present invention, the one-way trigger module receives an external trigger signal from the main control board FPGA module for processing and then sends it to a certain function board or all function boards to realize the trigger function required for external testing; or the internal test program is processed by the main control board FPGA module and then sent to a certain function board or all function boards to realize the trigger function required for internal testing;

[0034] The bidirectional trigger module executes the test program by a certain function board. The function board is used when it needs cooperation from other function boards. The function board can directly trigger other function boards or the function board can send the trigger signal to the main control board FPGA module, which is processed by the main control board FPGA module and then sent to other function boards or all function boards that need cooperation to realize the trigger function required for the test.

[0035] As a further improvement of the present invention, a separate power supply system is used to ensure the power supply of the IIC circuit, which includes an ADC configured in the function board to collect the main system power supply voltage. The FPGA of each function board connects the IIC to the system main control board. When necessary, the main control board can issue commands to query the power status, working status, temperature status, and protection circuit status of each function board, and preset different alarm steps. When certain fatal errors or protection status occur, the normal state of the test is interrupted and an alarm message is prompted.

[0036] By means of the above scheme, the present invention has at least the following advantages:

[0037] The signal backplane and the function board of the present invention are separated and flexibly configured, and different function boards can be configured as needed;

[0038] The present invention has strong scalability and can expand up to 30 functional boards;

[0039] The present invention takes into comprehensive consideration the communication, synchronization, clock and trigger among a plurality of boards and cards, and has the advantages of high performance, high-speed triggering, high-speed clock, high-speed synchronization and low delay.

[0040] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiments of the present invention in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0042] Figure 1 It is a schematic diagram of the main structure of a control and inter-board communication processing system of a test machine of the present invention;

[0043] Figure 2 It is a schematic diagram of the basic principle of the main structure of a control and inter-board communication processing system of a test machine of the present invention;

[0044] Figure 3 is a schematic diagram of a data network transmission system of the present invention;

[0045] Figure 4 It is a schematic frame of data network transmission of the present invention;

[0046] Figure 5 is a schematic diagram of a high-speed and low-speed clock system of the present invention;

[0047] Figure 6 yes Figure 5 The clock selection principle block diagram;

[0048] Figure 7 is a schematic diagram of a unidirectional point-to-point synchronization module of the present invention;

[0049] Figure 8 is a schematic diagram of a bidirectional point-to-point synchronization module of the present invention;

[0050] Fig. 9 is a schematic diagram of the inter-board data transmission bus of the present invention;

[0051] Fig.10 is a schematic diagram of the trigger system of the present invention;

[0052] Fig.11 yes Fig.10 Schematic diagram of the unidirectional trigger module;

[0053] Fig.12 yes Fig.10 Schematic diagram of the bidirectional trigger module;

[0054] Fig.13 Schematic diagram of the address management system of the present invention. DETAILED DESCRIPTION

[0055] The specific implementation of the present invention is further described in detail below in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0056] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, rather than all the embodiments. The components of the embodiment of the present invention generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiment of the present invention provided in the drawings is not intended to limit the scope of the invention claimed for protection, but merely represents the selected embodiment of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present invention.

[0057] Example

[0058] like Figures 1 to 13 As shown,

[0059] A control and inter-board communication processing system for a test machine, including a main control board and 16 function boards, and connecting the signals between the main control board and several function boards and a signal bus through a signal backplane;

[0060] The main control board includes a main control board FPGA module; and a data network transmission system, a high-speed and low-speed clock system, a synchronization system, a trigger system and a diagnostic system connected to the above-mentioned main control board FPGA module;

[0061] The data network transmission system builds a 16-port switch system combined with the main control board FPGA module. The 16-port switch system can communicate directly with the main control board FPGA module or work independently of the main control board FPGA module.

[0062] High-speed and low-speed clock systems can configure different clocks by sending commands through the main control board FPGA module;

[0063] The synchronization system includes a unidirectional point-to-point synchronization module and a bidirectional point-to-point synchronization module;

[0064] The one-way point-to-point synchronization module is sent from the main control board to 16 function boards for synchronizing other function boards;

[0065] The bidirectional point-to-point synchronization module is initiated by the function board, uploaded to the main control board, and then processed by the main control board and sent to the function board or all function boards that need to be triggered using a unidirectional point-to-point synchronization line;

[0066] The trigger system includes a unidirectional trigger module and a bidirectional trigger module;

[0067] The one-way trigger module is sent from the main control board to 16 function boards for triggering functions;

[0068] The bidirectional trigger module is initiated by the function board, sent to the main control board, and then processed by the main control board and sent to the function board or all function boards that need to be triggered;

[0069] The diagnostic system uses a separate point-to-point IIC communication, which connects the main control board FPGA module to each functional board through the signal backplane, and uses ADC on the main control board to collect information on key parameter points; other functional boards use the IIC bus to achieve point-to-point communication with the main control board, and combined with different card slot addresses, the working status and other information of all functional boards can be monitored in real time.

[0070] Preferably, adjacent functional boards are connected via an inter-board data transmission bus and are used for data exchange of large amounts of data and high bandwidth between adjacent functional boards, using differential transmission.

[0071] Preferably, the data network transmission system has two RJ45 network ports and two 10G SFP+ optical ports for external output, specifically including:

[0072] The RJ45 network port downstream of the switch can be used for data exchange with the main control boards of other parallel test machines;

[0073] The RJ45 network port connected to the FPGA module of the main control board is used for debugging and monitoring functions of this machine;

[0074] The 10G SFP+ optical port connected to the switch is used for data transmission between this test machine and the host computer. The test program or test content can be sent from the host computer, and the test results stored in this machine can be uploaded;

[0075] The 10G SFP+ optical port connected to the FPGA module of the main control board can be used to transmit the test program and test content sent by the host computer, and can also transmit the processed test results to the host computer.

[0076] Preferably, the high-speed and low-speed clock systems include two groups of homologous clocks, which are fanned out to 16 functional boards by two fan-out chips respectively, providing stable homologous clocks. The original clock output by the FPGA module of the main control board is configured by PLL to generate the required clock input, which is respectively transmitted to two 16-channel LVDS fan-out drivers, one of which is used for high-speed clock and the other for low-speed clock. The two clocks are fanned out to the functional boards of each card slot respectively, and the functional boards select different clocks to use according to needs.

[0077] Preferably, the high-speed and low-speed clock systems use a phase-locked loop chip on the main control board. The phase-locked loop chip can receive the original clock output by the FPGA module of the main control board for input, or use the local TCXO for original clock generation, or use an external clock input as the clock source of the phase-locked loop chip.

[0078] Preferably, LVDS differential routing is used from the output of the phase-locked loop chip to the input of the main control board FPGA module of the function board.

[0079] Preferably, the unidirectional point-to-point synchronization module is a synchronization requirement initiated by the main control board FPGA module or after an external synchronization signal is input to the main control board FPGA module, and is used for some or all functional boards to synchronously test a certain function; or simultaneously output a synchronization signal to other parallel test hosts for synchronous testing of multiple test hosts;

[0080] The bidirectional point-to-point synchronization module is initiated by the test function board, transmitted to the main control board FPGA module for processing, and then sent to a certain function board or all function boards to perform the synchronization function.

[0081] Preferably, both the unidirectional point-to-point synchronization module and the bidirectional point-to-point synchronization module can be initiated by an external synchronization signal input to the main control board FPGA module, and the main control board FPGA module can also output a synchronization signal to any functional board or output it to other parallel test machines or test units for use.

[0082] Preferably, the one-way trigger module receives an external trigger signal from the main control board FPGA module for processing and then sends it to a certain function board or all function boards to realize the trigger function required for external testing; or receives an internal test program from the main control board FPGA module for processing and then sends it to a certain function board or all function boards to realize the trigger function required for internal testing;

[0083] The bidirectional trigger module executes the test program by a certain function board. The function board is used when it needs cooperation from other function boards. The function board can directly trigger other function boards or the function board can send the trigger signal to the main control board FPGA module, which is processed by the main control board FPGA module and then sent to other function boards or all function boards that need cooperation to realize the trigger function required for the test.

[0084] Preferably, a separate power supply system is used to ensure the power supply of the IIC circuit, which includes an ADC configured in the function board to collect the main system power supply voltage. The FPGA of each function board connects the IIC to the system main control board. When necessary, the main control board can issue commands to query the power status, working status, temperature status, and protection circuit status of each function board, and preset different alarm steps. When certain fatal errors or protection status occur, the normal state of the test is interrupted and an alarm message is prompted.

[0085] For example, the comparative document CN219085413U requires an embedded PC system, while the system of the present invention does not require an embedded PC system, but only uses an FPGA system as a main control, and flexibly configures the required functional boards according to requirements.

[0086] Different from the comparative document CN218481612U, the present invention makes specific implementation elaboration on the clock, synchronization, triggering and high-speed inter-board communication for the functional board.

[0087] The first embodiment of the present invention:

[0088] 1. Platform architecture:

[0089] like Figure 1 and Figure 2 As shown, a main control board plus a function board is used, and the signals and signal buses of the main control board and the function board are connected through a signal backplane. All transmission lines are transmitted in a differential manner to avoid interference.

[0090] Each location uses a different address to distinguish the location of the function board and is used to identify the main control board. The network transmission is 10G upstream and 1000M downstream.

[0091] The low-speed clock and high-speed clock can be configured by sending commands to different clocks through the main control board FPGA module. For example, the high-speed sampling function board can use the high-speed clock, and the programmable power supply board for power supply can use the low-speed clock.

[0092] The unidirectional trigger module is sent from the main control board to 16 function boards for triggering functions; the bidirectional trigger module is initiated by the function board, uploaded to the main control board, and then processed by the main control board and sent to the function board or all function boards that need to be triggered.

[0093] The one-way point-to-point synchronization module is sent from the main control board to 16 function boards for synchronizing other function boards.

[0094] The bidirectional point-to-point synchronization module can be initiated by the function board, uploaded to the main control board, and then processed by the main control board and sent down to the function board or all function boards that need to be triggered using a unidirectional point-to-point synchronization line.

[0095] High-speed, high-bandwidth inter-board data transmission is used for large-volume, high-bandwidth data exchange between adjacent functional boards. The theoretical maximum transmission rate of each pair of differential lines is 1.923Gbps, and 20 pairs of differential lines can provide a maximum data volume communication of approximately 40Gbps.

[0096] Using a point-to-point IIC diagnostic circuit from the main control board to the functional board of a separate power supply system, the main control board can issue commands to query the power status, working status, temperature status, and protection circuit status of each functional board, and preset different alarm steps. When certain fatal errors or protection status occur, the normal state of the test is interrupted and an alarm message is prompted.

[0097] In addition, when 16 card slots are not enough, a parallel test machine system can be added, with external clock, trigger, and synchronization connected to another 16-card slot unit, which can effectively expand the test capacity.

[0098] 2. Data network transmission system:

[0099] The data network transmission system builds a 16-port switch system combined with the main control board FPGA module, such as Figure 3 and Figure 4 As shown, the switch system can communicate directly with the main control board FPGA module or work independently of the main control board FPGA module, with an uplink rate of 10G bps.

[0100] The external output consists of two RJ45 (1000M) network ports and two 10G SFP+ optical ports, which respectively realize the following functions:

[0101] The RJ45 network port downstream of the switch can be used for data exchange with the main control boards of other parallel test machines, thus doubling the capacity of the test machines.

[0102] The 10G SFP+ optical port connected to the switch is used for data transmission between this test machine and the host computer. The test program or test content can be sent from the host computer, and the test results stored in this machine can be uploaded.

[0103] The RJ45 network port connected to the main control board FPGA module is mainly used for the debugging and monitoring functions of this machine.

[0104] The 10G SFP+ optical port connected to the FPGA module of the main control board can also be used to transmit the test program and test content sent by the host computer, and can also transmit the processed test results to the host computer.

[0105] The main control board is usually implemented with a high-speed FPGA and an external large-capacity DDR, which can process a large amount of data interaction in parallel and perform various control, status monitoring, test result processing, storage and upload functions on the lower-level functional boards.

[0106] For example, if the FPGA uses Xilinx's KU+ series, with external DDR memory and SSD, it can achieve 10GByte-level large-capacity data exchange capability and 100G-level storage capability.

[0107] The 16 downstream 1000M ports of the main control board switch are connected to the 16 function board slots via the signal backplane to achieve data communication between the function board and the main control board.

[0108] 3. High-speed and low-speed clock systems:

[0109] The clock system includes two sets of homologous clocks, which are fanned out from two fan-out chips to 16 functional boards, providing stable homologous clocks. Figure 5 shown.

[0110] The high-speed and low-speed clock systems use a wide-range phase-locked loop chip with extremely low jitter on the main control board. The phase-locked loop chip can receive the original clock output by the FPGA module of the main control board for input, or use the local TCXO for original clock generation, or use an external clock input as the clock source of the phase-locked loop chip.

[0111] The original clock is configured by PLL to generate the required clock input, which is sent to two 16-channel LVDS fan-out drivers, one for high-speed clock and the other for low-speed clock. The two clocks are fanned out to the function board of each card slot. The function board selects different clocks according to the needs. The basic principle of clock selection is as follows Figure 6 shown.

[0112] The high-speed clock can reach a clock frequency range of 100 to 800Mhz, and the low-speed clock can reach a clock frequency range of 1Hz to 100Mhz, which can be flexibly configured by the parameters sent by the main control board FPGA.

[0113] From the phase-locked loop output to the main control board FPGA module input of the function board, all LVDS differential routing is used to increase anti-shake processing and improve clock stability.

[0114] 4. Synchronous system:

[0115] One-way point-to-point synchronization module such as Figure 7 As shown:

[0116] The one-way point-to-point synchronization module is initiated by the main control board FPGA module or by the external synchronization signal input to the main control board FPGA module. Its function is used for some or all functional boards to synchronize and test a certain function.

[0117] It can also output a synchronization signal to other parallel test hosts at the same time, which is used for synchronous testing of multiple test hosts, such as expanding a parallel test host.

[0118] Bidirectional point-to-point synchronization module such as Figure 8 As shown:

[0119] The bidirectional point-to-point synchronization module can be initiated by the test function board, transmitted to the main control board FPGA module for processing, and then sent to a certain function board or all function boards to perform the synchronization function.

[0120] The functions of the unidirectional point-to-point synchronization module or the bidirectional point-to-point synchronization module can be initiated by an external synchronization signal input to the main control board FPGA module, and the main control FPGA module can also output a synchronization signal to any functional board or output it to other parallel testers or test units for use.

[0121] 5. High-speed and high-bandwidth inter-board data transmission bus:

[0122] High-speed, high-bandwidth inter-board data transmission is used for large-volume, high-bandwidth data exchange between adjacent functional boards. The theoretical maximum transmission rate of each pair of differential lines is 1.923Gbps, and 20 pairs of differential lines can provide a maximum data volume communication of approximately 40Gbps.

[0123] High-speed inter-board data transmission bus is used for multi-function boards to cooperate to realize a certain complex function of instruments or equipment. Using multiple function boards to realize pipeline data processing and segmented work can greatly improve performance, such as Fig. 9 shown.

[0124] 6. Trigger system:

[0125] like Fig.10 As shown, the trigger system includes a unidirectional trigger module and a bidirectional trigger module.

[0126] like Fig.11 As shown, the unidirectional trigger module receives an external trigger signal from the input to the main control board FPGA module for processing and then sends it to a certain function board or all function boards to realize the triggering function required for external testing, or receives an internal test program from the main control board FPGA module for processing and then sends it to a certain function board or all function boards to realize the triggering function required for internal testing.

[0127] like Fig.12 As shown, the bidirectional trigger module is used by a certain function board to execute the test program, and the function board needs to be used when other function boards cooperate. The function board can directly trigger other function boards or the function board sends the trigger signal to the main control board FPGA module, which is processed by the main control board FPGA module and sent to other function boards or all function boards that need to cooperate to realize the trigger function required for the test.

[0128] The trigger function also provides output signals to other parallel testers or other test equipment to expand the trigger function of the test.

[0129] 7. Diagnostic system:

[0130] The diagnostic system uses a separate point-to-point IIC communication to connect the main control board FPGA to each functional board through the signal backplane, and uses ADC on the main control board to collect information on key parameter points; other functional boards use the IIC bus to communicate with the main control board to achieve point-to-point communication, combined with different card slot addresses (such as Fig.13 As shown), the working status and other information of all functional boards can be monitored in real time.

[0131] A separate power supply system is used to ensure the power supply of the IIC circuit, which includes the ADC configured in the function board to collect the main system power supply voltage. The FPGA of each function board connects the IIC to the system main control board. When necessary, the main control board can issue commands to query the power status, working status, temperature status, and protection circuit status of each function board, and preset different alarm steps. When certain fatal errors or protection status occur, the normal state of the test is interrupted and an alarm message is prompted.

[0132] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and the like are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly referring to the number of technical features indicated. Thus, features defined as "first", "second", and the like may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0133] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood by specific circumstances.

[0134] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the technical principles of the present invention, and these improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A control and inter-board communication processing system for a test machine, including a main control board and 16 function boards, and connecting the signals between the main control board and several function boards and the signal bus through a signal backplane; Features: The main control board includes a main control board FPGA module; and a data network transmission system, a high-speed and low-speed clock system, a synchronization system, a trigger system and a diagnostic system connected to the main control board FPGA module; The data network transmission system constructs a 16-port switch system combined with the main control board FPGA module. The 16-port switch system can communicate directly with the main control board FPGA module or work independently of the main control board FPGA module. The high-speed and low-speed clock systems can configure different clocks by sending commands through the main control board FPGA module; The synchronization system includes a unidirectional point-to-point synchronization module and a bidirectional point-to-point synchronization module; The one-way point-to-point synchronization module is sent from the main control board to 16 function boards for synchronizing other function boards; The bidirectional point-to-point synchronization module is initiated by the function board, goes up to the main control board, and then is processed by the main control board and sent down to the function board or all function boards that need to be triggered using a unidirectional point-to-point synchronization line; The trigger system includes a unidirectional trigger module and a bidirectional trigger module; The one-way trigger module is sent from the main control board to 16 function boards for triggering functions; The bidirectional trigger module is initiated by the function board, sent to the main control board, and then processed by the main control board and sent to the function board or all function boards that need to be triggered; The diagnostic system adopts a separate point-to-point IIC communication, connects the main control board FPGA module to each functional board through the signal backplane, and uses ADC on the main control board to collect information on key parameter points; other functional boards all use the IIC bus to achieve point-to-point communication with the main control board, and combined with different card slot addresses, the working status and other information of all functional boards can be monitored in real time.

2. A test machine control and inter-board communication processing system as claimed in claim 1, characterized in that: The adjacent function boards are connected via an inter-board data transmission bus and are used for data exchange with large amounts of data and high bandwidth between the adjacent function boards, and are transmitted in a differential manner.

3. A control and inter-board communication processing system for a test machine as claimed in claim 1, characterized in that: The data network transmission system is composed of two RJ45 network ports and two 10G SFP+ optical ports for external output, specifically including: The RJ45 network port downstream of the switch can be used for data exchange with the main control board of other parallel test machines; The RJ45 network port connected to the FPGA module of the main control board is used for debugging and monitoring functions of this machine; The 10G SFP+ optical port connected to the switch is used for data transmission between this test machine and the host computer. The test program or test content can be sent from the host computer, and the test results stored in this machine can be uploaded; The 10G SFP+ optical port connected to the FPGA module of the main control board can be used to transmit the test program and test content sent by the host computer, and can also transmit the processed test results to the host computer.

4. A test machine control and inter-board communication processing system as claimed in claim 1, characterized in that: The high-speed and low-speed clock system includes two groups of homologous clocks, which are fanned out to 16 functional boards by two fan-out chips respectively, providing stable homologous clocks. The original clock output by the FPGA module of the main control board generates the required clock input after PLL configuration and is respectively transmitted to two 16-channel LVDS fan-out drivers, one of which is used for high-speed clock and the other for low-speed clock. The two clocks are fanned out to the functional boards of each card slot respectively, and the functional boards select different clocks to use according to needs.

5. A test machine control and inter-board communication processing system as claimed in claim 4, characterized in that: The high-speed and low-speed clock systems use a phase-locked loop chip on the main control board. The phase-locked loop chip can receive the original clock output by the FPGA module of the main control board for input, or use the local TCXO for original clock generation, or use an external clock input as the clock source of the phase-locked loop chip.

6. A test machine control and inter-board communication processing system as claimed in claim 5, characterized in that: LVDS differential routing is used from the output of the phase-locked loop chip to the input of the main control board FPGA module of the function board.

7. A test machine control and inter-board communication processing system as claimed in claim 1, characterized in that: The one-way point-to-point synchronization module is a synchronization requirement initiated by the main control board FPGA module or after an external synchronization signal is input to the main control board FPGA module, and is used for some or all functional boards to synchronously test a certain function; or simultaneously output a synchronization signal to other parallel test hosts for synchronous testing of multiple test hosts; The bidirectional point-to-point synchronization module is initiated by the test function board, transmitted to the main control board FPGA module for processing, and then sent to a certain function board or all function boards to perform the synchronization function.

8. A test machine control and inter-board communication processing system as claimed in claim 1, characterized in that: The unidirectional point-to-point synchronization module and the bidirectional point-to-point synchronization module can both be initiated by an external synchronization signal input to the main control board FPGA module, and the main control board FPGA module can also output a synchronization signal to any functional board or output it to other parallel test machines or test units for use.

9. A test machine control and inter-board communication processing system as claimed in claim 1, characterized in that: The one-way trigger module receives an external trigger signal from the main control board FPGA module for processing and then sends it to a certain function board or all function boards to realize the trigger function required for external testing; or receives an internal test program from the main control board FPGA module for processing and then sends it to a certain function board or all function boards to realize the trigger function required for internal testing; The bidirectional trigger module executes the test program by a certain function board, which is used when the function board needs cooperation from other function boards. The function board can directly trigger other function boards or the function board can send the trigger signal to the main control board FPGA module, which is processed by the main control board FPGA module and then sent to other function boards or all function boards that need cooperation to realize the trigger function required for the test.

10. A test machine control and inter-board communication processing system as claimed in claim 1, characterized in that: A separate power supply system is used to ensure the power supply of the IIC circuit, which includes the ADC configured in the function board to collect the main system power supply voltage. The FPGA of each function board connects the IIC to the system main control board. When necessary, the main control board can issue commands to query the power status, working status, temperature status, and protection circuit status of each function board, and preset different alarm steps. When certain fatal errors or protection status occur, the normal state of the test is interrupted and an alarm message is prompted.

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