Modular multilevel converter valve control device and wave recording method thereof

Abstract

The invention discloses a modular multilevel converter valve control device and a wave recording method thereof, which are suitable for various modular multilevel converter valve control devices. The integrated wave recording function of the valve control device plays an important role in observing the operation state of the converter and analyzing the fault transient process of the sub-module. The valve control device is a core control device of the whole valve control system and interactively communicates with each sub-module. The sub-modules upload capacitor voltage, IGBT switching state and fault information to the valve control device, the valve control device needs to gather mass data sent by the sub-modules, and the original recording data is gathered through the programmable logic array FPGA, so that the processing time consumption of the control CPU is effectively reduced, and the output data transmission quantity of the control CPU is reduced. The wave recording method for the modular multilevel converter valve control device has the advantages of being universal in architecture, flexible in configuration, convenient to transplant and the like, and can be suitable for various modular multilevel converter valve control systems.

Description

Technical Field

[0001] The present application relates to the field of power electronics technology, and in particular to a modular multilevel converter valve control device and a wave recording method thereof, wherein the method is applicable to various types of modular multilevel converter control systems. Background Art

[0002] Modular multilevel converter systems are widely used in flexible DC transmission projects, UHV hybrid DC and other DC power electronic systems. The valve control device is the core device for converter system control. The submodule consists of multiple devices such as IGBT module, driver board, DC capacitor voltage and bypass switch. The submodule operation conditions are relatively complex and require high operation reliability. The recording function of the valve control device plays an important role in observing the submodule operation status, analyzing the transient process of submodule failures and troubleshooting valve control failures.

[0003] The recording capability required by the valve control device is very high: the total number of submodules is large, and many recording channels are required; the control cycle of the valve control device is short (for example, 50us), and the recording frequency must meet 20KHz or even higher. At present, the valve control system is generally equipped with a separate centralized recording device, which is connected to the valve control device through optical fiber and transmits related recording data. However, the use of a centralized recording device will increase the complexity of the valve control system and occupy additional cabinet space. Summary of the invention

[0004] The purpose of the present application is to provide a modular multi-level converter valve control device and a wave recording method thereof.

[0005] The present invention adopts the following technical solutions. In a first aspect, the present invention provides a modular multilevel converter valve control device, wherein the modular multilevel converter includes a plurality of bridge arms, each bridge arm includes N submodules, the valve control device is connected to each submodule, each submodule includes an IGBT device and a DC capacitor; the valve control device has an internal recording function, and does not need to be configured with a separate centralized recording device, thereby reducing the space occupied by optical fiber connections and cabinets;

[0006] The valve control device includes: a management CPU, a control CPU, an FPGA and a DDR cache;

[0007] The FPGA is connected to the control CPU, DDR cache and each submodule; the FPGA includes a summarizing module for summarizing the uplink data of each submodule and the output data of the control CPU, and pushing them to the DDR cache as the original recording data;

[0008] The management CPU is connected to the DDR buffer to read the original wave recording data; the management CPU includes a conversion module for converting the original wave recording data to generate a COMTRADE format wave recording file.

[0009] Preferably, the uplink data of the submodule includes: capacitor voltage sampling value, IGBT switch state and fault state.

[0010] Preferably, the summarizing module comprises a first summarizing unit and a second summarizing unit connected to each other;

[0011] The first aggregation unit is used to aggregate uplink data of each submodule to generate first aggregated data;

[0012] The second summarizing unit is used to summarize the first summary data and the output data of the control CPU to generate second summary data;

[0013] Preferably, the FPGA sends the first summary data to the control CPU by connecting to the control CPU. The control CPU receives the first summary data, and the instruction calculation unit of the control CPU calculates and generates control signals for each sub-module, and sends output data containing the sub-module control signals to the FPGA.

[0014] Preferably, the management CPU includes a channel configuration module for configuring recording channel data in an initialization phase.

[0015] The FPGA pushes the recorded original data to the DDR buffer area according to a first set period, and the management CPU centrally processes a plurality of recorded original data according to a second set period, wherein the first set period is shorter than the second set period.

[0016] Preferably, the first setting period is 50 μs, and the second setting period is 1 ms.

[0017] A second aspect of the present invention provides a method for recording waveforms of a modular multilevel converter valve control device, comprising the following steps:

[0018] The step of receiving and summarizing uplink data: the valve control device receives uplink data of each submodule, and the FPGA of the valve control device summarizes the uplink data of each submodule to generate first summary data;

[0019] Steps for generating CPU output data: calculating and generating submodule control signals, generating output data including the submodule control signals, and sending the data to the FPGA, and the FPGA sends the output data including the submodule control signals to each submodule;

[0020] Step of generating raw wave recording data: FPGA aggregates the first summary data and the output data of the control CPU to generate second summary data, and sends the second summary data to the DDR cache as raw wave recording data;

[0021] Steps for generating a standard waveform recording format file: the management CPU reads the original waveform recording data from the DDR buffer, and converts the original waveform recording data into a COMTRADE format waveform recording file.

[0022] Preferably, the step of receiving and summarizing the uplink data includes: the valve control device receives the capacitor voltage sampling value, IGBT switch state and fault state of each submodule as the uplink data.

[0023] Preferably, the management CPU configures the recording channel data in the initialization phase, and treats the uplink data of the submodule as a part of the output data for the control CPU.

[0024] Preferably, the FPGA pushes the recorded original data to the DDR cache area according to a first set period, and the management CPU centrally processes multiple recorded original data according to a second set period; the first set period is shorter than the second set period.

[0025] Compared with the prior art, the beneficial technical effects of the present invention at least include: solving the technical problem that the use of a centralized wave recording device will increase the complexity of the valve control system and occupy additional cabinet space, realizing the wave recording function inside the valve control device, and no need to configure a separate centralized wave recording device, thereby reducing the optical fiber connection and the space occupied by the cabinet; the submodule sends the capacitor voltage, IGBT switch state and fault information to the valve control device, and the valve control device needs to summarize the massive data sent by each submodule, and summarize the original wave recording data through the programmable logic array FPGA, effectively reducing the control CPU processing time and reducing the control CPU output data transmission volume. The present invention has the advantages of universal architecture, flexible configuration, and convenient transplantation, and can be adapted to valve control systems of various modular multi-level converters. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Schematic diagram of a bridge arm of a modular multilevel converter according to an exemplary embodiment of the present application.

[0027] Figure 2 Schematic diagram of a modular multilevel converter control system architecture and a valve control device according to an exemplary embodiment of the present application.

[0028] Figure 3 4 is a schematic diagram of downlink communication of a modular multilevel converter control system architecture according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0029] To further explain the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are only for reference and description and are not intended to limit the present invention.

[0030] Embodiment 1 of the present invention provides a modular multi-level converter valve control device, the valve control device has an internal recording function, and does not need to be configured with a separate centralized recording device, thereby reducing the space occupied by optical fiber connections and cabinets; the valve control device aggregates and receives uplink data from each submodule, calculates and generates submodule control signals and sends them to each submodule, and the valve control device includes: a management CPU (Central Processing Unit), a control CPU, an FPGA (Field Programmable Gate Array) and a DDR (Double Data Rate) cache.

[0031] The modular multilevel converter comprises a plurality of bridge arms. Figure 1 It is a schematic diagram of a bridge arm of a modular multilevel converter according to an exemplary embodiment of the present application, and each bridge arm includes N submodules, namely submodule No. 1, submodule No. 2 to submodule No. N. Those skilled in the art can use a half-bridge submodule or a full-bridge submodule as a submodule, but both include an IGBT (Insulate-Gate Bipolar Transistor) device and a DC capacitor. During operation, the DC capacitor voltage is sampled to obtain a capacitor voltage sampling value.

[0032] The FPGA is connected to each submodule of the modular multilevel converter and receives uplink data of each submodule; the FPGA includes a summarizing module, which includes a first summarizing unit and a second summarizing unit connected to each other; wherein the first summarizing unit is used to summarize the uplink data of each submodule to generate first summary data.

[0033] The FPGA is also connected to the control CPU, sends the first summary data to the control CPU, and receives output data of the control CPU;

[0034] The second summarizing unit of the summarizing module is used to summarize the first summary data and the output data of the control CPU to generate second summary data.

[0035] The FPGA is also connected to the DDR cache and sends the second summary data to the DDR cache.

[0036] Preferably but not restrictively, the uplink data of the submodule includes: capacitor voltage sampling value, IGBT switch state, fault state and other related information.

[0037] The DDR buffer is connected to the FPGA, receives the second summary data from the FPGA, and uses the second summary data as the original wave recording data.

[0038] The control CPU is connected to the FPGA to receive the first summary data; the control CPU includes an instruction calculation unit for calculating and generating control signals for each sub-module; the control CPU sends the output data containing the sub-module control signals to the FPGA, and the FPGA sends the output data to each sub-module.

[0039] The management CPU is connected to the DDR buffer, and obtains the original wave recording data from the DDR buffer. The management CPU includes a conversion module for converting the original wave recording data into a COMTRADE format wave recording file. The management CPU includes a channel configuration module for configuring the wave recording channel data.

[0040] It is worth noting that, as one of the outstanding essential features of the present invention, the raw recorded data of the management CPU is generated by summarizing the uplink data of each sub-module by the summary module of the FPGA chip, which brings significant improvements to the prior art, including at least: reducing the processing time of the control CPU and reducing the output data transmission volume of the control CPU.

[0041] During the initialization phase, the management CPU configures the recording channel data through the configuration module, and uses the submodule uplink data as part of the control CPU output data. That is, from the management CPU side, the submodule uplink data is equivalent to the control CPU. Figure 2 , 3 Shown

[0042] FPGA pushes the recorded original data to the DDR buffer area according to the first set period, and the management CPU centrally processes multiple recorded original data according to the second set period. The first set period is shorter than the second set period, preferably but not limited to, the first set period is 50μs and the second set period is 1ms.

[0043] Embodiment 2 of the present invention provides a modular multilevel converter valve control device recording method, the valve control device integrates an internal recording function, and does not need to configure a separate centralized recording device, thereby reducing the space occupied by optical fiber connections and panel cabinets. Specifically, the method includes the following steps:

[0044] The step of receiving and summarizing the uplink data: the valve control device receives the uplink data of each submodule, the FPGA of the valve control device summarizes the uplink data of each submodule, generates first summary data, and sends the first summary data to the control CPU.

[0045] Preferably but not restrictively, the uplink data of the submodule includes: capacitor voltage sampling value, IGBT switch state and fault state and other related information

[0046] The step of generating CPU output data: controlling the CPU to receive the first summary data, calculating and generating the sub-module control signal, generating the output data including the sub-module control signal, and sending it to the FPGA, and the FPGA sends the output data including the sub-module control signal to each sub-module.

[0047] Steps for generating raw wave recording data: FPGA aggregates the first summary data and the output data of the control CPU to generate second summary data, and sends the second summary data to the DDR cache as the raw wave recording data.

[0048] It is worth noting that the raw recorded data of the management CPU is summarized by the FPGA to reduce the processing time of the control CPU and reduce the amount of data transmission output by the control CPU.

[0049] Preferably but not restrictively, the management CPU configures the recording channel data in the initialization phase and uses the submodule uplink data as part of the control CPU output data. That is, from the management CPU side, the submodule uplink data is equivalent to the control CPU.

[0050] Steps for generating a standard waveform recording format file: the management CPU reads the original waveform recording data from the DDR buffer, and converts the original waveform recording data into a COMTRADE format waveform recording file.

[0051] FPGA pushes the recorded original data to the DDR buffer area according to the first set period, and the management CPU centrally processes multiple recorded original data according to the second set period. The first set period is shorter than the second set period, preferably but not limited to, the first set period is 50μs and the second set period is 1ms.

[0052] Compared with the prior art, the beneficial technical effects of the present invention at least include: solving the technical problem that the use of a centralized wave recording device will increase the complexity of the valve control system and occupy additional cabinet space, realizing the wave recording function inside the valve control device, and no need to configure a separate centralized wave recording device, thereby reducing the optical fiber connection and the space occupied by the cabinet; the submodule sends the capacitor voltage, IGBT switch state and fault information to the valve control device, and the valve control device needs to summarize the massive data sent by each submodule, and summarize the original wave recording data through the programmable logic array FPGA, effectively reducing the control CPU processing time and reducing the control CPU output data transmission volume. The present invention has the advantages of universal architecture, flexible configuration, and convenient transplantation, and can be adapted to valve control systems of various modular multi-level converters.

[0053] The above is only to illustrate the technical idea of ​​the present application, and cannot be used to limit the protection scope of the present application. Any changes made on the basis of the technical solution in accordance with the technical idea proposed in the present application shall fall within the protection scope of the present application.

Claims

1. A modular multilevel converter valve control device, the modular multilevel converter comprises a plurality of bridge arms, each bridge arm comprises N submodules, the valve control device is connected to each submodule, each submodule comprises an IGBT device and a DC capacitor; the valve control device is characterized in that it has an internal wave recording function; The valve control device comprises: Manage CPU, control CPU, FPGA and DDR cache; The FPGA is connected to the control CPU, DDR cache and each submodule; the FPGA includes a summarizing module for summarizing the uplink data of each submodule and the output data of the control CPU, and pushing them to the DDR cache as the original recording data; The management CPU is connected to the DDR buffer to read the original wave recording data; the management CPU includes a conversion module for converting the original wave recording data to generate a COMTRADE format wave recording file.

2. A modular multilevel converter valve control device according to claim 1, characterized in that: The uplink data of the submodule includes: capacitor voltage sampling value, IGBT switch status and fault status.

3. A modular multilevel converter valve control device according to claim 1 or 2, characterized in that: The summarizing module includes a first summarizing unit and a second summarizing unit connected to each other; The first aggregation unit is used to aggregate uplink data of each submodule to generate first aggregated data; The second summarizing unit is used to summarize the first summary data and the output data of the control CPU to generate second summary data.

4. The modular multilevel converter valve control device according to claim 3, characterized in that: The FPGA sends the first summary data to the control CPU by connecting to the control CPU. The control CPU receives the first summary data. The instruction calculation unit of the control CPU calculates and generates control signals for each submodule, and sends output data containing the submodule control signals to the FPGA.

5. The modular multilevel converter valve control device according to claim 3, characterized in that: The management CPU includes a channel configuration module for configuring recording channel data in an initialization phase. The FPGA pushes the recorded original data to the DDR buffer area according to a first set period, and the management CPU centrally processes a plurality of recorded original data according to a second set period, wherein the first set period is shorter than the second set period.

6. A modular multilevel converter valve control device according to claim 5, characterized in that: The first setting period is 50 μs, and the second setting period is 1 ms.

7. A method for recording waveforms of a modular multi-level converter valve control device, characterized in that: The following steps are involved: The step of receiving and summarizing uplink data: the valve control device receives uplink data of each submodule, and the FPGA of the valve control device summarizes the uplink data of each submodule to generate first summary data; Steps for generating CPU output data: calculating and generating submodule control signals, generating output data including the submodule control signals, and sending the data to the FPGA, and the FPGA sends the output data including the submodule control signals to each submodule; Step of generating raw wave recording data: FPGA aggregates the first summary data and the output data of the control CPU to generate second summary data, and sends the second summary data to the DDR cache as raw wave recording data; Steps for generating a standard waveform recording format file: the management CPU reads the original waveform recording data from the DDR buffer, and converts the original waveform recording data into a COMTRADE format waveform recording file.

8. A method for recording waveforms of a modular multilevel converter valve control device according to claim 7, characterized in that: The step of receiving and summarizing the uplink data includes: the valve control device receives the capacitor voltage sampling value, IGBT switch state and fault state of each submodule as the uplink data.

9. A method for recording waveforms of a modular multilevel converter valve control device according to claim 7, characterized in that: The management CPU configures the recording channel data in the initialization phase, and equates the uplink data of the submodule to a part of the output data for the control CPU.

10. The method for recording waveforms of a modular multilevel converter valve control device according to claim 7, characterized in that: The FPGA pushes the recorded original data to the DDR buffer area according to a first set period, and the management CPU centrally processes a plurality of recorded original data according to a second set period; the first set period is shorter than the second set period.

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