Multiplier implementation mode preferential method, system, equipment and medium

Abstract

The invention relates to a preferential method, system and device of a multiplier implementation mode and a medium. The invention provides a prioritizing method for implementation modes of a multiplier. The method comprises the following steps: collecting parameter information of the multiplier; according to the multiplier parameter information, calling a default multiplier implementation mode and a multiplier implementation mode added by at least one user, and respectively generating a universal multiplier code and a multiplier code implemented by at least one user; performing logic comprehensive analysis on the universal multiplier code and the multiplier code realized by at least one user to obtain first area information of a default multiplier realization mode and second area information of a multiplier realization mode added by at least one user; and comparing the first area information with the second area information, and selecting a multiplier implementation mode with the minimum area.

Description

Technical Field

[0001] The present invention relates to the field of chip design, and more specifically, to a method, system, device and medium for optimizing a multiplier implementation. Background Art

[0002] In recent years, with the rapid development of technologies such as big data, the Internet of Things, cloud computing, and edge computing, the application scope of computer systems has become increasingly wide, and people have put forward higher and higher requirements for the data processing capabilities of chips. Not only should we pursue higher circuit performance, but we should also reduce the area of ​​the circuit as much as possible. Among them, multipliers, as important computing components, are widely used in chips such as microprocessors, general-purpose processors, and digital signal processors.

[0003] In the chip design process, multiplier resources are an important resource in logical operations, especially in chips in the image field, where a large number of multipliers are used to implement multiplication-related operations. Therefore, in order to reduce the chip area, optimizing multiplier resources becomes a key task. Usually, algorithm engineers will reduce the number of multipliers at the algorithm level from the perspective of algorithm logic through formula transformation or equivalent substitution, but they cannot provide much help for necessary multiplication operations.

[0004] Therefore, there is a need for a method and system for optimizing multiplier resources during chip design. Summary of the invention

[0005] According to a first aspect of the present disclosure, a method for selecting a multiplier implementation is provided, the method comprising: collecting multiplier parameter information; calling a default multiplier implementation and at least one multiplier implementation added by a user according to the multiplier parameter information, and generating a general multiplier code and at least one user-implemented multiplier code respectively; performing a logic synthesis analysis on the general multiplier code and at least one user-implemented multiplier code to obtain first area information of the default multiplier implementation and second area information of at least one user-added multiplier implementation; and comparing the first area information and the second area information to select a multiplier implementation with the smallest area.

[0006] According to a second aspect of the present disclosure, a system for selecting a multiplier implementation is provided, comprising: a multiplier parameter information collection module, configured to collect multiplier parameter information; a multiplier code generation module, configured to call a system default multiplier implementation and at least one user-added multiplier implementation according to the multiplier parameter information, and generate a general multiplier code and at least one user-implemented multiplier code respectively; a logic synthesis analysis module, configured to obtain first area information of a system default multiplier implementation and second area information of at least one user-added multiplier implementation based on the general multiplier code and at least one user-implemented multiplier code; and a multiplier selection module, comparing the first area information and the second area information, and selecting a multiplier implementation with the smallest area.

[0007] According to a third aspect of the present disclosure, a computer device is provided, comprising: at least one processor; and a memory storing computer instructions that can be executed on the processor, wherein the instructions implement the steps of any one of the above methods when executed by the processor.

[0008] Other features and advantages of the present disclosure will become apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings, which constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0010] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0011] Figure 1 A schematic diagram of an embodiment of a method for optimizing a multiplier implementation provided by the present invention;

[0012] Figure 2 A schematic diagram of an embodiment of a multiplier implementation method for multiplying a signed number by an unsigned number provided by the present invention;

[0013] Figure 3 A schematic diagram of another embodiment of a multiplier implementation method for multiplying a signed number by an unsigned number provided by the present invention;

[0014] Figure 4 A schematic diagram of an embodiment of a system for selecting the best multiplier implementation provided by the present invention;

[0015] Figure 5 A schematic diagram of the hardware structure of an embodiment of a computer device for preferential processing of a multiplier implementation provided by the present invention; and

[0016] Figure 6 A schematic diagram of an embodiment of a non-transitory computer-readable storage medium for preferential processing of multiplier implementations provided by the present invention.

[0017] Note that in the embodiments described below, the same reference numerals are sometimes used in common between different drawings to represent the same parts or parts with the same functions, and their repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to represent similar items, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0018] For ease of understanding, the positions, sizes, and ranges of various structures shown in the drawings and the like sometimes do not represent actual positions, sizes, and ranges, etc. Therefore, the disclosed invention is not limited to the positions, sizes, and ranges, etc. disclosed in the drawings and the like. In addition, the drawings are not necessarily drawn to scale, and some features may be exaggerated to show details of specific components. DETAILED DESCRIPTION

[0019] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless otherwise specifically stated.

[0020] The following description of at least one exemplary embodiment is merely illustrative and is not intended to limit the present disclosure and its application or use. That is, the preferred methods and systems for implementing multipliers herein are shown in an exemplary manner to illustrate different embodiments of the circuits or methods in the present disclosure, and are not intended to be limiting. Those skilled in the art will appreciate that they merely illustrate exemplary ways that can be used to implement the present invention, rather than an exhaustive way.

[0021] Technologies, methods, and apparatus known to ordinary technicians in the relevant field may not be discussed in detail, but where appropriate, such technologies, methods, and apparatus should be considered part of the authorization specification.

[0022] In the chip design process, usually, in the multiplier design, the Verilog hardware description language is used for design; then the standard cell library is used, and the software is used to synthesize the multiplication operation in the code with the synthesis tool to obtain the gate-level netlist, so that the multiplication operation in the code is automatically replaced with the corresponding hardware resources. However, the matching hardware resources are not necessarily optimal, and users will also develop the implementation of the multiplier to achieve the purpose of optimizing the area. But this brings a problem. The optimal solution for the area is not unique. Under different process conditions, such as different frequencies, different chip process critical dimensions, and component libraries provided by different manufacturers, for multipliers corresponding to different data bit widths, according to the synthesis results of the synthesis tool, the self-developed multiplier implementation may be better than the components selected by the tool, but it may also be worse than the latter.

[0023] Therefore, the present invention provides a system that can automatically optimize the logic implementation of the multiplier according to the size of the multiplier area during the chip design process. Through this system, the area of ​​multiplier-related resources in chip design can be effectively reduced, reducing the trouble caused by multiplier selection.

[0024] In a first aspect of an embodiment of the present invention, a method for optimizing a multiplier implementation is proposed. Figure 1 The present invention is a schematic diagram of an embodiment of a method for optimizing the multiplier implementation mode provided by the present invention. Figure 1 The overall block diagram of the method is shown, and the embodiment of the present invention includes the following steps:

[0025] Step S1: Collecting multiplier parameter information. In the multiplier parameter information collection stage, that is, in the multiplier information aggregation stage, firstly, the multiplier information required by the module needs to be collected.

[0026] Specifically, the following table 1 shows a schematic diagram of multiplier parameter information collection. In step S1, in the multiplier parameter information collection stage, the parameter information that needs to be filled in by the user is first the multiplier name (corresponding to the "name" column). The name is used as a kind of indexing method of the multiplier, and at the same time, in the library file finally generated, it will also be used as the function name of the calling function. Assuming that the left and right variable names of the multiplication implementation are A and B (i.e., multiplier A and multiplicand B), the user needs to mark whether A is a signed number, corresponding to the A_signbit column, s means that A is a signed number, u means that A is an unsigned number, and A_BW represents the bit width of A data (including the sign bit). For example, the total bit width of the A variable in raw2y_mult_0 is 8 bits, and the definition related to parameter B is similar. These multiplier parameter information can be summarized in an excel table, for example, and called in the next step.

[0027] Table 1

[0028] name A_signbit(s / u) A_BW B_signbit(s / u) B_BW raw2y_mult_0 s 8 s 8 raw2y_mult_1 s 8 s 8 md_gm_mult_0 u 16 u 16 md_gm_mult_1 u 16 u 16 md_sad_mult_0 s 8 u 8 md_sad_mult_1 s 8 u 8 md_sad_mult_2 s 8 u 8

[0029] Step S2: according to the multiplier parameter information, the default multiplier implementation and at least one multiplier implementation added by the user are called to generate a general multiplier code and at least one multiplier code implemented by the user, respectively. In one embodiment, specifically, in step S2, at the multiplier code generation stage, the user first needs to establish a template library of the multiplier, which usually includes a component library provided by the manufacturer, which includes the default multiplier implementation. In such a multiplier code generation stage, according to the multiplier parameter information, the system will call the component library provided by the manufacturer to automatically generate a general multiplier code that meets the requirements.

[0030] In addition, the user will also add some other types of multiplier implementations to achieve the purpose of optimizing the multiplier area. There are usually three situations when the multiplier is in use, namely, a signed number multiplied by a signed number, an unsigned number multiplied by an unsigned number, and a signed number multiplied by an unsigned number. For example, for an unsigned number multiplied by an unsigned number, there can be at least two multiplier implementations: for example, a chip manufacturer will provide a general implementation, that is, a multiplier implementation in a component library provided by the manufacturer; or an implementation added by the user, such as a braun multiplier implementation or a modified version of a booth multiplier implementation. In step S2, in the method, the codes of these two implementations are generated, and the same multiplier parameter information is configured, and the code information is stored in the dest file finally generated. The dest file is, for example, a verilog file. When these multipliers are in use, they only need to be configured to the multiplier template according to the multiplier parameter information provided by the previous stage.

[0031] For example, for multiplying a signed number by a signed number, there may be at least two multiplier implementations: for example, the chip manufacturer may provide a general implementation, that is, a multiplier implementation in the component library provided by the manufacturer; or a user-added implementation, such as a booth multiplier implementation or a combined multiplier implementation.

[0032] In the process of chip design, sometimes there will be a situation where it is necessary to process a signed number multiplied by an unsigned number. Normally, if this form of operation is handed over to a comprehensive tool for selection, the tool will add a sign bit to the unsigned number, convert it into a signed number, and call the component library file of the two signed numbers multiplied in the tool component library for implementation. For example, a signed 8-bit data is multiplied by an unsigned 8-bit data. The tool will call an 8-bit by 9-bit component of two signed numbers multiplied, which will bring a certain area increase. For this reason, the present invention designs two implementation methods with smaller areas than traditional implementation methods, and retains the possibility of handing over to the tool for selection, that is, a total of three optional implementation methods, which can be selected by users, increasing the flexibility of the system. Through this system, the area of ​​hardware implementation when processing signed numbers multiplied by unsigned numbers can be effectively reduced.

[0033] Therefore, in this method, for the case of multiplying a signed number by an unsigned number, there are three implementation options, namely, Scheme 0, Scheme 1, and Scheme 2; among them, Scheme 0 is the default mode, that is, no extra processing is done, and the synthesis tool is left to select the corresponding components. Schemes 1 and 2 are the implementation methods designed by this system for multiplying a signed number by an unsigned number.

[0034] Figure 2 The present invention provides a schematic diagram of an embodiment of a multiplier implementation method for multiplying a signed number by an unsigned number. Specifically, Figure 2 The multiplier implementation of scheme 1 for multiplying signed numbers by unsigned numbers is shown.

[0035] In solution 1, it is assumed that the multiplier A is a signed number with a bit width of A_DW, and the multiplicand B is an unsigned number with a data bit width of B_DW.

[0036] The implementation process is as follows:

[0037] First, in step 201, it is determined whether the multiplier A is a positive number or 0. If the multiplier A is a positive number or 0, the low (A_DW-1) bits of the multiplier A are retained in step 202; if the multiplier A is a negative number, the low (A_DW-1) bits of the multiplier A are taken in step 203, and all data bits are inverted and added 1. In step 204, the variable A_abs is finally obtained, with a bit width of (A_DW-1), and the formula is implemented as follows:

[0038] A_abs=A[A_DW-1]? (~A[A_DW-2:0]+1):A[A_DW-2:0]; (1)

[0039] Next, in step 205, the variable A_abs is multiplied by the multiplicand B, and in step 206, a variable p_abs is obtained, and the bit width is (A_DW+B_DW-1);

[0040] Next, in step 207, an overflow condition is determined, and an intermediate value p_int is obtained in step 210: if in step 207, the multiplier A reaches the lower limit of the value range (for example, in the case where the data bit width is 8 bits, the value range is -128 to 127, the lower limit is -128, and the upper limit is 127), then in step 209, the intermediate value p_int is equal to the multiplicand B shifted left by (A_DW-1), that is, p_int=B<<(A_DW-1); otherwise, if in step 207, the multiplier A does not reach the lower limit of the value range, then in step 208, the intermediate value p_int is equal to the variable p_abs obtained in the previous step;

[0041] Next, in step 211, it is determined whether the multiplier A is a positive number or 0. If the multiplier A is a positive number or 0, then in step 212, the final result (i.e., the product of the multiplier A and the multiplicand B) product is equal to p_int; otherwise, if the multiplier A is a negative number, then in step 213, the result of the product is the highest bit of the intermediate value p_int plus a 0, then the bit is inverted, and then 1 is added, the formula is as follows:

[0042] product=A[A_DW-1]? (~{1'b0,p_int}+1):p_int (2)

[0043] Product is the final result of the multiplication operation. Compared with the traditional solution, the bit width of each multiplier of the multiplier can be reduced by 1 bit. That is, the original multiplier of (A_DW) bits by (B_DW+1) bits is now a multiplier of (A_DW-1) bits by (B_DW) bits.

[0044] Figure 3 A schematic diagram of another embodiment of a multiplier implementation method for multiplying a signed number by an unsigned number provided by the present invention. Specifically, Figure 3 The multiplier implementation of scheme 2 for multiplying signed numbers by unsigned numbers is shown.

[0045] In scheme 2, it is assumed that the multiplier A is a signed number with a bit width of A_DW, and the multiplicand B is an unsigned number with a data bit width of B_DW.

[0046] The solution 2 is based on the following basic characteristics: for signed data A, the bit width is n, then A can be expanded into the following formula:

[0047]

[0048] Among them, a n-1 It is the sign bit of A.

[0049] When the multiplier A is positive, a n-1If it is 0, the multiplier A is converted to other bits except the sign bit. For example, the representation of 4-bit 3 is 0011, and the sign bit is removed to 011.

[0050] When the multiplier A is negative, a n-1 It is 1, that is, the sign bit is 1. Taking -3 as an example, the representation of the multiplier A is 1101. At this time, the other bits of A except the sign bit are 101, and the data corresponding to 101 is 5. The corresponding formula is -3=-8+5.

[0051] Specifically, in the above formula (3), ai represents the i-th bit in data A, then A*B can be transformed as follows:

[0052]

[0053]

[0054] This can be broken down into a set of subtraction operations, where the minuend is two unsigned numbers subtracted, and the subtrahend can be seen as a shift operation.

[0055] The specific operation steps are as follows:

[0056] like Figure 3 As shown in FIG. 3 , in step 301, the low A_DW-1 bit of the multiplier A is taken, which is defined as A Then in step 302, A Multiply it with the multiplicand B, and then obtain the result variable p_lsb in step 303;

[0057] In step 304, the sign bit of the multiplier A, i.e., the highest bit A[A_DW] of the multiplier A, is ANDed with each bit of the multiplicand B, and then the result p_msb is obtained in step 305;

[0058] In step 306, p_msb is shifted left by (A_DW-1) bits, and then in step 307, the variable p_msb ;

[0059] Next, in step 308, p_lsb is subtracted from p_msb , the final result (ie, the product of the multiplier A and the multiplicand B) product can be obtained in step 309.

[0060] Compared with the traditional solution, the bit width of a multiplier of the multiplier can also be reduced by 1 bit, that is, the original multiplier of (A_DW) bits by (B_DW+1) bits is now a multiplier of (A_DW-1) bits by (B_DW) bits.

[0061] In the present invention, these two hardware implementation methods for multiplying signed numbers by unsigned numbers are designed, which can effectively reduce the actual area and increase the diversity of selection.

[0062] Step S3: Logic synthesis analyzes the general multiplier code and at least one user-implemented multiplier code to obtain the first area information of the default multiplier implementation and the second area information of at least one user-added multiplier implementation. In the operation synthesis analysis stage, the dest file generated in the previous step, that is, the code generated in step S2, is uniformly sent to the synthesis tool (such as the DC synthesis tool provided by the manufacturer) for processing to obtain the area information of various multipliers. Specifically, in the logic synthesis step, the register transfer level hardware description language code (high-level hardware description written in Verilog or VHDL (VHSIC Hardware Description Language)) is converted into a logic gate level netlist for a specific process, and the logic gate level netlist is a description that matches the FPGA hardware resources, and the logic gate level netlist includes a comprehensive area report of the multiplier. The gate level netlist is composed of process library devices, wherein the process library device can be a component library provided by the manufacturer or a component library of the multiplier implementation added by the user in step S2.

[0063] Step S4: Compare the first area information and the second area information, and select the multiplier implementation with the smallest area. In the multiplier selection stage, the comprehensive report generated in the previous step is read through the script, and for each different implementation of the multiplier, the area size of the multiplier with the same parameters under different implementations is compared, and the multiplier design method with the smallest area is selected, and all the multiplier design methods with the best area are summarized, and a library file containing code implementation is automatically generated. The chip engineer can directly call the multiplier in the file during use. For example, for a multiplier named md_sad_mult_0 that multiplies a signed number by an unsigned number, this system provides 3 implementation methods. The system compares the area size of the three implementation methods after synthesis, selects the implementation method with the smallest area, and outputs the code of the implementation method in the final lib library file (verilog language file).

[0064] The present invention utilizes code to realize the process of automatic operation, can automatically compare the area, and generate the required multiplier implementation. On the other hand, the method has the characteristics of easy maintenance and easy upgrade. If there is a new multiplier design method, the template can be directly added to the library file, which is convenient for system upgrade and maintenance. In addition, usually chip engineers will select the multiplier based on previous experience, but in the case of different processes, different frequencies, and different voltages, the pros and cons of various implementations may not be fixed. The system can fully realize automatic processing, and the comparison of the multiplier area is analyzed by using the data obtained by the comprehensive tool, and the report generated by the more accurate tool is used instead of the experience, and the actual simulation data is used instead of the experience for selection, which can ensure more accuracy.

[0065] Based on the above purpose, in a second aspect of an embodiment of the present invention, a system for optimizing multiplier implementations is proposed. Figure 4 A schematic diagram of an embodiment of a system for selecting a multiplier implementation provided by the present invention. In one embodiment, the system 400 comprises: a multiplier parameter information collection module 401, configured to collect multiplier parameter information; a multiplier code generation module 402, configured to call a system default multiplier implementation and at least one user-added multiplier implementation according to the multiplier parameter information, and respectively generate a general multiplier code and at least one user-implemented multiplier code; a logic synthesis analysis module 403, configured to obtain first area information of a system default multiplier implementation and second area information of at least one user-added multiplier implementation based on the general multiplier code and at least one user-implemented multiplier code; and a multiplier selection module 404, comparing the first area information and the second area information, and selecting a multiplier implementation with the smallest area.

[0066] In addition, in a third aspect of an embodiment of the present invention, a computer device is proposed, comprising: at least one processor; and a memory, the memory storing computer instructions that can be run on the processor, the instructions being executed by the processor to implement the following steps: S1, collecting multiplier parameter information; S2, calling a default multiplier implementation and at least one user-added multiplier implementation according to the multiplier parameter information, and generating a general multiplier code and at least one user-implemented multiplier code respectively; S3, performing logic synthesis analysis on the general multiplier code and at least one user-implemented multiplier code to obtain first area information of the default multiplier implementation and second area information of at least one user-added multiplier implementation; and S4, comparing the first area information and the second area information, and selecting a multiplier implementation with the smallest area.

[0067] like Figure 5, which is a schematic diagram of the hardware structure of an embodiment of a computer device for preferential processing of a multiplier implementation provided by the present invention.

[0068] As Figure 5 Taking the device shown as an example, the computer device includes a processor 501 and a memory 502 , and may also include: an input device 503 and an output device 504 .

[0069] The processor 501, the memory 502, the input device 503 and the output device 504 may be connected via a bus or other means. Figure 5 The example of connecting through bus is taken in the following.

[0070] The memory 502 is a non-volatile computer-readable storage medium that can be used to store non-volatile software programs, non-volatile computer executable programs and modules, such as program instructions / modules corresponding to the preferred method of implementing the multiplier in the embodiment of the present application. The processor 501 executes various functional applications and data processing of the server by running the non-volatile software programs, instructions and modules stored in the memory 502, that is, implementing the preferred method of implementing the multiplier in the above method embodiment.

[0071] The memory 502 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required by at least one function; the data storage area may store data created by using a preferred method according to a multiplier implementation method, etc. In addition, the memory 502 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 502 may optionally include a memory remotely arranged relative to the processor 501, and these remote memories may be connected to the local module via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0072] The input device 503 may receive input multiplier parameter information, etc. The output device 504 may include a display device such as a display screen.

[0073] The program instructions / modules corresponding to the optimal method of implementing one or more multipliers are stored in the memory 502, and when executed by the processor 501, the optimal method of implementing the multiplier in any of the above method embodiments is executed.

[0074] Any embodiment of a computer device that executes the above-mentioned method for selecting the best way to implement the multiplier can achieve the same or similar effect as any corresponding embodiment of the above-mentioned method.

[0075] The present invention also provides a non-transitory computer-readable storage medium, which stores a computer program that performs the above method when executed by a processor.

[0076] like Figure 6 FIG. 1 is a schematic diagram of an embodiment of a non-transitory computer storage medium for preferential processing of a multiplier implementation provided by the present invention. Figure 6 Taking the computer storage medium shown as an example, the computer readable storage medium 6 stores a computer program 61 that executes the above method when executed by the processor. The computer readable storage medium can be a tangible device that can retain and store instructions used by the instruction execution device. The computer readable storage medium can be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer readable storage media includes the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device (such as a punch card or a raised structure in a groove with instructions recorded thereon), and any suitable combination of the foregoing. The computer readable storage medium as used herein should not be interpreted as a temporary signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated through a waveguide or other transmission medium (for example, a light pulse through an optical fiber cable), or an electrical signal transmitted through a wire.

[0077] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network can include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network, and forwards the computer-readable program instructions to be stored in a computer-readable storage medium in the corresponding computing / processing device.

[0078] The computer-readable program instructions for performing the operation of the embodiments of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" programming language or similar programming languages. The computer-readable program instructions may be executed completely on the user's computer, partially on the user's computer, executed as an independent software package, partially on the user's computer and partially on a remote computer, or completely on a remote computer or server. In the case of the latter, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider through the Internet). In some embodiments, an electronic circuit (including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) may be executed by utilizing the state information of the computer-readable program instructions to personalize the electronic circuit, to perform the various aspects of the embodiments of the present disclosure.

[0079] Finally, it should be noted that a person skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program, and the program of the preferred method for implementing the multiplier can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned methods.

[0080] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0081] A person skilled in the art should understand that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the disclosure of the embodiments of the present invention (including the claims) is limited to these examples; under the concept of the embodiments of the present invention, the technical features in the above embodiments or different embodiments can also be combined, and there are many other changes in different aspects of the embodiments of the present invention as above, which are not provided in detail for the sake of simplicity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present invention should be included in the protection scope of the embodiments of the present invention.

[0082] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0083] Those skilled in the art will appreciate that the boundaries between the above operations are merely illustrative. Multiple operations can be combined into a single operation, a single operation can be distributed in additional operations, and operations can be performed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of specific operations, and the order of operations may be changed in other various embodiments. However, other modifications, variations, and replacements are equally possible. Therefore, this specification and accompanying drawings should be considered illustrative, not restrictive.

[0084] References in the specification to "one embodiment" or "an embodiment" and other variations of the present principles mean that a particular feature, structure, characteristic, etc. described in connection with the embodiment is included in at least one embodiment of the present principles. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" and any other variations in various places throughout the specification do not necessarily all refer to the same embodiment.

[0085] Those skilled in the art will appreciate that the boundaries between the operations (or steps) described in the above-described embodiments are merely illustrative. Multiple operations can be combined into a single operation, which can be distributed in additional operations, and the operations can be performed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of specific operations, and the order of operations may be changed in other various embodiments. However, other modifications, variations, and replacements are equally possible. Therefore, this specification and accompanying drawings should be considered illustrative, not restrictive.

[0086] The above are exemplary embodiments disclosed in the present invention, but it should be noted that various changes and modifications may be made without departing from the scope of the embodiments disclosed in the claims. The functions, steps and / or actions of the method claims according to the disclosed embodiments described herein do not need to be performed in any particular order. In addition, although the elements disclosed in the embodiments of the present invention may be described or claimed in individual form, they may also be understood as plural unless explicitly limited to the singular.

[0087] It should be understood that, as used herein, the singular forms "a", "an" are intended to include the plural forms as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations including one or more of the associated listed items.

[0088] The serial numbers of the embodiments disclosed in the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0089] Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any manner without departing from the spirit and scope of the present disclosure. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A method for selecting the best implementation of a multiplier, characterized in that: The method comprises: Collect multiplier parameter information; According to the multiplier parameter information, a default multiplier implementation and at least one multiplier implementation added by a user are called to generate a general multiplier code and at least one multiplier code implemented by the user respectively; Logic synthesis analyzes the general multiplier code and the at least one user-implemented multiplier code to obtain first area information of a default multiplier implementation and second area information of at least one user-added multiplier implementation; and The first area information and the second area information are compared, and a multiplier implementation method with the smallest area is selected.

2. The optimal method for implementing a multiplier according to claim 1, characterized in that: The multiplier parameter information includes the first bit width A_DW of the multiplier A, whether the multiplier A is a signed number, the second bit width B_DW of the multiplicand B, and whether the multiplicand B is a signed number.

3. The optimal method for implementing a multiplier according to claim 2, characterized in that: In the case where the multiplier A is a signed number and the multiplicand B is an unsigned number or in the case where the multiplier A is an unsigned number and the multiplicand B is a signed number, the at least one user-added multiplier implementation comprises the following steps: Determine whether the multiplier A is positive or 0. If the multiplier A is positive or 0, keep the low (A_DW-1) bits of the multiplier A. If the multiplier A is negative, take the low (A_DW-1) bits of the multiplier A, invert all data bits, and add 1 to finally get the variable A_abs with a bit width of (A_DW-1). The formula is as follows: A_abs=A[A_DW-1]? (~A[A_DW-2:0]+1):A[A_DW-2:0]; Multiply the variable A_abs by the multiplicand B to obtain the variable p_abs, with a bit width of (A_DW+B_DW-1); The overflow is judged to obtain the intermediate value p_int: if the multiplier A reaches the lower limit of the value range, the intermediate value p_int is equal to the multiplicand B shifted left by (A_DW-1), that is, p_int=B<<(A_DW-1); otherwise, the intermediate value p_int is equal to p_abs obtained in the previous step; Determine whether the multiplier A is positive or 0. If the multiplier A is positive or 0, the product of the multiplier A and the multiplicand B is equal to p_int; otherwise, if the multiplier A is negative, the product is the middle value p_int with a 0 added to the highest bit, then the bit is inverted and then 1 is added. The formula is as follows: product=A[A_DW-1]? (~{1'b0,p_int}+1):p_int.

4. The optimal method for implementing a multiplier according to claim 2, characterized in that: In the case where the multiplier A is a signed number and the multiplicand B is an unsigned number or in the case where the multiplier A is an unsigned number and the multiplicand B is a signed number, the at least one user-added multiplier implementation comprises the following steps: Take the lower A_DW-1 bits of the multiplier A, defined as A ; Will A Multiply it with the multiplicand B to get the result p_lsb; Perform an AND operation on the sign bit of the multiplier A, i.e. the highest bit A[A_DW] of the multiplier A, and each bit of the multiplicand B to obtain the result p_msb; Shift p_msb left by (A_DW-1) bits to get the variable p_msb ; Subtract p_lsb from p_msb , and we get the product of the multiplier A and the multiplicand B.

5. The method for selecting the best multiplier implementation according to claim 2, characterized in that: In the case where both the multiplier A and the multiplicand B are unsigned numbers, the at least one user-added multiplier implementation is a braun multiplier implementation or a modified booth multiplier implementation; or In the case where both the multiplier A and the multiplicand B are signed numbers, the at least one user-added multiplier implementation is a booth multiplier implementation or a combined multiplier implementation.

6. A system for selecting the best multiplier implementation, characterized in that: The system comprises: A multiplier parameter information collection module, configured to collect multiplier parameter information; A multiplier code generation module is configured to call a system default multiplier implementation and at least one user-added multiplier implementation according to the multiplier parameter information to generate a general multiplier code and at least one user-implemented multiplier code respectively; a logic synthesis analysis module configured to obtain first area information of a system default multiplier implementation and second area information of at least one user-added multiplier implementation based on a general multiplier code and at least one user-implemented multiplier code; and The multiplier selection module compares the first area information and the second area information and selects a multiplier implementation with the smallest area.

7. The optimal system for selecting a multiplier implementation according to claim 6, characterized in that: The multiplier parameter information includes the first bit width A_DW of the multiplier A, whether the multiplier A is a signed number, the second bit width B_DW of the multiplicand B, and whether the multiplicand B is a signed number.

8. The optimal system for selecting a multiplier implementation according to claim 7, characterized in that: In the case where the multiplier A is a signed number and the multiplicand B is an unsigned number or in the case where the multiplier A is an unsigned number and the multiplicand B is a signed number, the at least one user-added multiplier implementation comprises the following steps: Determine whether the multiplier A is positive or 0. If the multiplier A is positive or 0, keep the low (A_DW-1) bits of the multiplier A. If the multiplier A is negative, take the low (A_DW-1) bits of the multiplier A, invert all data bits, and add 1 to finally get the variable A_abs with a bit width of (A_DW-1). The formula is as follows: A_abs=A[A_DW-1]? (~A[A_DW-2:0]+1):A[A_DW-2:0]; Multiply the variable A_abs by the multiplicand B to obtain the variable p_abs, with a bit width of (A_DW+B_DW-1); The overflow is judged to obtain the intermediate value p_int: if the multiplier A reaches the lower limit of the value range, the intermediate value p_int is equal to the multiplicand B shifted left by (A_DW-1), that is, p_int=B<<(A_DW-1); otherwise, the intermediate value p_int is equal to p_abs obtained in the previous step; Determine whether the multiplier A is positive or 0. If the multiplier A is positive or 0, the product of the multiplier A and the multiplicand B is equal to p_int; otherwise, if the multiplier A is negative, the result of the product is the highest bit of the intermediate value p_int plus a 0, then the bit is inverted, and then 1 is added. The formula is as follows: product=A[A_DW-1]? (~{1'b0,p_int}+1):p_int.

9. The optimal system for selecting a multiplier implementation according to claim 7, characterized in that: In the case where the multiplier A is a signed number and the multiplicand B is an unsigned number or in the case where the multiplier A is an unsigned number and the multiplicand B is a signed number, the at least one user-added multiplier implementation comprises the following steps: Take the lower A_DW-1 bits of the multiplier A, defined as A ; Will A Multiply it with the multiplicand B to get the result p_lsb; Perform an AND operation on the sign bit of the multiplier A, i.e. the highest bit A[A_DW] of the multiplier A, and each bit of the multiplicand B to obtain the result p_msb; Shift p_msb left by (A_DW-1) bits to get the variable p_msb ; Subtract p_lsb from p_msb , and we get the product of the multiplier A and the multiplicand B.

10. The optimal system for selecting a multiplier implementation according to claim 7, characterized in that: In the case where both the multiplier A and the multiplicand B are unsigned numbers, the at least one user-added multiplier implementation is a braun multiplier implementation or a modified booth multiplier implementation; or In the case where both the multiplier A and the multiplicand B are signed numbers, the at least one user-added multiplier implementation is a booth multiplier implementation or a combined multiplier implementation.

11. A computer device, characterized in that: The device comprises: at least one processor; and A memory storing computer instructions that can be run on the processor, wherein the instructions are executed by the processor to implement the steps of the method according to any one of claims 1 to 5.

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