Chip verification system and method

Abstract

The invention provides a chip verification system and method. The chip verification system comprises a switching chip, a plurality of device connectors and a plurality of PCIe devices, the plurality of device connectors are connected with the switching chip, the plurality of PCIe devices are connected with the switching chip through the corresponding device connectors, the PCIe devices are further used for being connected with an external control terminal, and the external control terminal is connected with the switching chip. The PCIe device is used as an excitation initiating end and an excitation receiving end. According to the chip verification method and device, the excitation data are received and transmitted through the PCIe device to verify the reasonability of the excitation data, so that the verification result of the chip can be rapidly obtained, the PCIe device, the exchange chip and the device connector are mainly used in a hardware architecture for chip verification, hardware resources needed by verification can be effectively saved, related parameters of the device connector and the PCIe device can be flexibly set, and the verification efficiency is improved. The requirements of different verification scenes are matched, and the verification efficiency of the different verification scenes is effectively improved.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a chip verification system and method. Background Art

[0002] Chip prototype verification and system testing are crucial in the chip design process to ensure the design of high-quality and reliable chip products. Among them, prototype verification refers to simulating the actual working environment of the chip before tape-out to verify the chip function and reduce tape-out risks. The common method is to burn the chip netlist (logic design) into the FPGA to use the FPGA as the object to be verified; system testing refers to the functional testing of the chip in the real working environment after tape-out, analyzing and solving the actual problems encountered in the test, and improving the chip yield.

[0003] PCIe switch chip is a high-speed digital-analog hybrid chip with large gate-level scale and complex functions, so it places great demands on prototype verification and system testing. The R&D cost of switch chips is high, and a large part of it is concentrated on prototype verification and system testing. This is because chip verification has many prototype verification and system test points, which takes a long time and requires many software and hardware resources. Summary of the invention

[0004] The main purpose of the present application is to provide a chip verification system and method, which can at least solve the problems of low efficiency and large number of test resources required for chip verification in related technologies.

[0005] To achieve the above-mentioned purpose, the first aspect of the present application provides a chip verification system, including: a switching chip, multiple device connectors and multiple PCIe devices, multiple device connectors are connected to the switching chip, multiple PCIe devices are respectively connected to the switching chip through corresponding device connectors, and the PCIe device is used as an excitation initiator and an excitation receiver; the first PCIe device serving as the excitation initiator is used to generate excitation data and transmit it to the corresponding first device connector; the first device connector is used to transmit the excitation data to the switching chip; the switching chip is used to transmit the excitation data to the second PCIe device through the corresponding second device connector; wherein the second PCIe device serves as the excitation receiver; the second PCIe device is used to verify the rationality of the excitation data, and when the rationality verification passes, the switching chip verification is successful.

[0006] The second aspect of the present application provides a chip verification method, including: a first PCIe device as an excitation initiator generates excitation data and transmits it to a corresponding first device connector; the first device connector transmits the excitation data to a switching chip; the switching chip transmits the excitation data to a second PCIe device through a corresponding second device connector; wherein the second PCIe device serves as an excitation receiving end; the second PCIe device performs rationality verification on the excitation data, and when the rationality verification passes, the switching chip verification is successful.

[0007] As can be seen from the above, in the chip verification system provided by the present application scheme, the hardware architecture of chip verification mainly uses PCIe devices, switching chips, and device connectors, which can effectively save the resources required for verification. PCIe devices can select the corresponding type according to the verification needs, and the PCIe device type connected to the device connector can also be set according to the verification needs, so that it can flexibly match the needs of different verification scenarios and improve the verification efficiency. The first PCIe device serving as the excitation initiator sends the excitation data, which is transmitted to the switching chip through the device connector corresponding to the first PCIe device, and then transmitted to the second PCIe device serving as the excitation receiving end through the corresponding device connector by the switching chip. The second PCIe device parses the received excitation data to determine the rationality of the excitation data, thereby determining whether the chip is successfully verified. There can be multiple verification links, and the PCIe devices at the excitation initiator and the excitation receiving end can be selected according to the verification needs, thereby obtaining the verification results of different verification links and improving the accuracy of verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0009] Figure 1 A schematic diagram of the structure of a first chip verification system provided in an embodiment of the present application; Figure 2 A schematic diagram of the structure of a second chip verification system provided in an embodiment of the present application; Figure 3 A schematic diagram of the structure of a third chip verification system provided in an embodiment of the present application; Figure 4 A schematic diagram of the first PCIe link topology provided in an embodiment of the present application; Figure 5 A schematic diagram of a second PCIe link topology provided in an embodiment of the present application; Figure 6 A schematic diagram of a third PCIe link topology provided in an embodiment of the present application; Figure 7 A schematic diagram of the structure of a PCIe device simulator provided in an embodiment of the present application; Figure 8 A schematic diagram of a simulator parameter configuration instruction provided in an embodiment of the present application; Fig. 9 A schematic diagram of a test sequence configuration instruction provided in an embodiment of the present application; Fig.10 A schematic diagram of a test pattern transmission path provided in an embodiment of the present application; Fig.11 A schematic diagram of a test pattern configuration instruction provided in an embodiment of the present application; Fig.12 A schematic diagram of the basic flow of a chip verification method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0010] In order to make the purpose, features, and advantages of the invention of this application more obvious and easy to understand, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0011] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0012] In order to solve the problem of low efficiency and large number of test resources required for chip verification in the related art, an embodiment of the present application provides a chip verification system, such as Figure 1 FIG. 1 is a schematic diagram of the structure of the first chip verification system provided in this embodiment. Figure 1 The chip verification system includes: a switching chip, multiple device connectors and multiple PCIe devices. The multiple device connectors are all connected to the switching chip. The multiple PCIe devices are connected to the switching chip through corresponding device connectors respectively. The PCIe devices are used as an excitation initiator and an excitation receiver.

[0013] Among them, the first PCIe device as the excitation initiator is used to: generate excitation data and transmit it to the corresponding first device connector; the first device connector is used to: transmit the excitation data to the switching chip; the switching chip is used to: transmit the excitation data to the second PCIe device through the corresponding second device connector; wherein the second PCIe device serves as the excitation receiver; the second PCIe device is used to: verify the rationality of the excitation data, and when the rationality verification passes, the switching chip verification is successful.

[0014] Specifically, in this embodiment, the hardware architecture of chip verification mainly uses PCIe devices, switching chips, and device connectors, wherein the switching chip can be connected to multiple device connectors at the same time, and each device connector can choose to connect or not connect to the PCIe device. The PCIe device can select the corresponding type according to the verification needs, and the PCIe device type connected to the device connector can also be set according to the verification needs, so as to flexibly match the needs of different verification scenarios and improve the verification efficiency; the first PCIe device as the excitation initiator sends the excitation data, which is transmitted to the switching chip through the device connector corresponding to the first PCIe device, and then transmitted to the second PCIe device by the switching chip through the device connector corresponding to the second PCIe device as the excitation receiving end. The second PCIe device parses the received excitation data to determine the rationality of the excitation data according to the excitation configuration instructions, thereby determining whether the chip is successfully verified. There can be multiple verification links, which can improve the efficiency of verification. The PCIe devices at the excitation initiator and the excitation receiving end can be selected according to the verification needs, so as to obtain the verification results of different verification links and improve the accuracy of verification.

[0015] Furthermore, if Figure 2 , Figure 3 The diagrams are respectively a schematic diagram of the structure of the second chip verification system and a schematic diagram of the structure of the third chip verification system provided in this embodiment. Figure 2 , 3 , the device type of the PCIe device includes any of the following: RC device, EP device, NT device and Fabric device. These device types can be simulated by the PCIe device simulator in the PCIe device, and the device connector can be connected to any type of PCIe device among RC device, EP device, NT device and Fabric device, or the device connector is connected to any type of PCIe device among RC device, EP device and NT device, or the device connector is connected to any type of PCIe device among RC device, EP device and Fabric device, or the device connector is connected to any type of PCIe device among RC device and EP device.

[0016] Specifically, take the common PCIe link topology as an example. Figure 4As shown in the figure, the PCIe link adopts an end-to-end data transmission method, that is, there is only one link between two devices, and data flows between upstream and downstream through the link to serve the RC device (Root Complex) and the EP device (End Point), that is, to serve the master and slave devices. Switch is a switching chip, referred to as SW. SW plays the role of expanding the link topology and completing data exchange. The port of the switching chip connected to the upstream is called USP (Upstream Port), and the port connected to the downstream is called DSP (Downstream Port).

[0017] In this embodiment, the number of connected PCIe devices, the data transmission link width of PCIe devices, and the location of PCIe devices can be configured. It is also possible to configure whether the device connector is an NT port or a Fabric port, so as to quickly configure a hardware architecture that meets the requirements of the required verification scenario. Among them, the number of connected PCIe devices should be less than or equal to the total number of device connectors of the system (that is, the total number of external interfaces of the switching chip), and the total link width of the connected PCIe devices should be less than or equal to the total number of channel resources of the switching chip; the positions of n device connectors are numbered from 1 to n, so the position L∈{1, n} of a certain connected PCIe device, that is, the PCIe device can access any existing physical interface resource; the NT port and the Fabric port need to be configured according to whether the device connector has NT and Fabric support capabilities; according to different device capabilities, the link width of the PCIe link, that is, the number of negotiated channels, can be X1, X2, X4, X8, X16, X32 and other widths. NT port refers to a non-transparent port. This port belongs to another system domain and can only transmit partial data with the switch chip in the local domain. It cannot transmit data freely like the devices in the local domain. The corresponding transmission link is Figure 5 As shown in the figure, Fabric ports are generally used for network-like topology interconnection of switch chips in the same or different system domains, which can break through the traditional tree topology. The corresponding transmission links are as follows: Figure 6 Each device connector in this embodiment can be connected to or not connected to EP devices and RC devices, and can be configured or not configured as NT ports and Fabric ports, so that it can be connected to or not connected to NT devices and Fabric devices, and can be connected to PCIe devices of different widths according to the path resources of the switching chip, so as to conveniently and quickly build different switching chip application scenarios as a prototype verification and system test environment. For example Figure 2As shown, the first device connector is connected to the EP1 device, and the link width is X1; the second device connector interface is connected to the NT device, and the link width is X2; the fourth device connector is connected to the Fabric device, and the link width is X8; the n-1th device connector is connected to the RC device, and the link width is X16; the nth device connector is connected to the EP2 device, and the link width is X4; other device connectors are not connected to the device. Figure 3 In the chip verification system shown, the first device connector is connected to the RC device, and the link width is X32; the fourth device connector is connected to the EP1 device, and the link width is X16; the n-1th device connector is connected to the NT device, and the link width is X2; the system is not connected to the fabric device; and the other ports are not connected to the device. Therefore, the device connector in this embodiment can freely configure the type of connected device, the number of devices connected to the system, the data transmission link width of the device, and the device access position can all be freely configured, that is, the relevant variables of the device connector in this embodiment can be reconstructed. In addition, Figure 2 The DUT (Design Under Test) is a switching chip (for prototype verification, it is an FPGA with a chip netlist burned in it; for system testing, it is the chip after the actual tape-out), that is, the chip verification system of this embodiment can be applied to prototype verification scenarios and system testing scenarios.

[0018] Furthermore, the PCIe device includes a PCIe device simulator and a conventional PCIe device. The PCIe device simulator is also connected to an external control terminal. The excitation data includes first sub-excitation data and second sub-excitation data. The PCIe device simulator in the first PCIe device is used to: generate corresponding first sub-excitation data according to the excitation configuration instruction sent by the control terminal, and transmit it to the corresponding first device connector; the conventional PCIe device in the first PCIe device is used to: generate corresponding second sub-excitation data according to a preset PCIe protocol, and transmit it to the corresponding first device connector.

[0019] Furthermore, the conventional PCIe device is specifically used to: generate a corresponding transaction message according to the PCIe protocol, and generate the second sub-stimulation data according to the transaction message.

[0020] Specifically, in this embodiment, the incentive data generated by the PCIe device is mainly generated by the PCIe device simulator and the conventional PCIe device, wherein the PCIe device simulator is used to generate the first sub-incentive data according to the incentive configuration instruction transmitted by the control terminal, and the conventional PCIe device is used to generate the second sub-incentive data according to the preset PCIe protocol, that is, the incentive data sent by the PCIe device includes the first sub-incentive data and the second sub-incentive data; wherein, the second sub-incentive data is mainly a conventional transaction message generated by the conventional PCIe device, and the transaction message is generated by the logic circuit and controller inside the PCIe device, and the logic circuit and controller inside the PCIe device can realize the processing of the protocol stack of the PCIe bus to generate and / or parse the PCIe transaction message. The transaction message in the PCIe protocol can be divided into read transactions, write transactions, configuration transactions, etc. according to the function, and the format of the transaction message includes fields such as the start mark, address, data, and verification information, which are used to determine the type of transaction, the target address, and the data carried.

[0021] Furthermore, if Figure 7 The structure diagram of a PCIe device simulator provided by this embodiment is shown in FIG. Figure 7 The PCIe device simulator includes a debugging interface, an instruction parser and a device behavior simulator; the debugging interface is used to: receive stimulus configuration instructions and transmit them to the instruction parser; the instruction parser is used to: parse the stimulus configuration instructions, and transmit the parsed configuration information to the device behavior simulator; the device behavior simulator is used to: generate corresponding first sub-stimulus data according to the configuration information and transmit it to the first device connector.

[0022] Specifically, in this embodiment, the PCIe device simulator is mainly composed of a debugging interface, an instruction parser and a device behavior simulator, wherein the debugging interface is used to receive the stimulus configuration instructions sent by the control terminal and transmit them to the instruction parser, and the debugging interface can adopt an interface such as a serial port or JTAG; the instruction parser is used to parse the stimulus configuration instructions and transmit the stimulus configuration information obtained by the analysis to the device behavior simulator, and the device behavior simulator is used to generate the first sub-stimulus data and transmit it to the corresponding first device connector.

[0023] Furthermore, the configuration information includes test sequence configuration information, test pattern configuration information and simulator parameter configuration information; the device behavior simulator is specifically used to: set the corresponding parameters of the PCIe device simulator according to the simulator parameter configuration information, and then generate a test sequence and a test pattern according to the test sequence configuration information and the test pattern configuration information, and generate a first sub-stimulus data according to the test sequence and the test pattern and transmit it to the first device connector.

[0024] Furthermore, in one embodiment, a test sequence and a test pattern are generated according to the test sequence configuration information and the test pattern configuration information, including: generating a test sequence according to the test sequence configuration information; wherein the test sequence includes multiple transactions whose transaction headers are arranged in a preset order, and the transactions include standard transactions and / or abnormal transactions; generating a test pattern according to the test pattern configuration information; wherein the test pattern includes target transactions of multiple target transaction types, initiation location information of the pattern, destination information of the pattern, algorithm type and number of target transactions, and the algorithm is used to control the multiple target transactions to make corresponding changes, and the algorithm is preprogrammed in the device behavior simulator.

[0025] Specifically, in this embodiment, the stimulus configuration instruction sent by the control terminal includes a test sequence configuration instruction, a test pattern configuration instruction and a simulator parameter configuration information. After receiving the stimulus configuration information transmitted by the instruction parser, the device behavior simulator first configures the PCIe device simulator according to the simulator parameter configuration information, wherein the simulator parameter configuration instruction includes the parameter to be configured and the value of the parameter, the parameter is represented by a preset number of bits, and the expected setting value of the parameter is input in the instruction, all of which take 5 bits as an example. The form of the simulator parameter configuration instruction is as follows: Figure 8 As shown. The parameters of the simulator in this embodiment may be the data transmission link width, electrical parameters, link behavior to be negotiated (such as rate, whether balanced, etc.), type of simulated device (RC / EP), etc. of the simulator, so that the PCIe device simulator can be used as a PCIe device to access the device connector; the parameter value can be set according to the requirements of prototype verification and system testing, so as to perform prototype verification and system testing in extreme and non-extreme scenarios, abnormal and non-abnormal scenarios. After the relevant parameters are configured, the PCIe device simulator generates corresponding test sequences and test patterns according to the test sequence configuration information and the test pattern configuration information. Among them, the test sequence includes multiple transactions, and the packet headers of multiple transactions are arranged in a preset order. The transaction type in the test sequence can be a single type or a combination type, for example, all standard transactions or abnormal transactions, or a combination of standard transactions and abnormal transactions. Standard transactions refer to transactions that comply with the protocol provisions, and abnormal transactions refer to transactions that do not comply with the protocol standards. The PCIe protocol has corresponding provisions for the header and payload of standard transactions, which include memory transactions, configuration transactions, IO transactions, message transactions, completion transactions, etc. As shown in Table 1 below, these transactions are distinguished by the fmt field and type field in the header. In addition, other fields in the header must also meet the protocol requirements.

[0026] Table 1

[0027] The transaction type that does not comply with the protocol is called abnormal type. By building abnormal incentives through abnormal types, the functional robustness of the switching chip can be confirmed in prototype verification and system testing. The abnormal type is subdivided into fmt / type field abnormalities and other packet header field abnormalities, for example, abnormal transactions with type field 0b11111; abnormal transactions with data payload length field inconsistent with actual payload length, etc. When multiple transactions form a sequence, the corresponding transaction sequence can be in the form of T={T1, T2, T3, ..., Ti, ..., Tn}, where Ti can be a standard transaction or an abnormal transaction, and the number and order of transactions can be arbitrary. For example, sequence 1: {MRd32, IORd, Msg1, Msg2, CAS64, T_abn}, which consists of six transactions, namely: 32-bit memory read request, IO read request, message transaction 1, message transaction 2, 64-bit CAS atomic operation, abnormal transaction T_abn; sequence 2: {CfgRd0_1, CfgRd0_2, CfgRd0_3, CfgRd0_4, CfgRd0_5, T_abn_1, T_abn_2}, which consists of seven transactions, namely: Type 0 configuration read requests 1 to 5, abnormal transactions T_abn_1 to 2. The form of the test sequence configuration instruction is as follows: Fig. 9 As shown, the test sequence configuration instruction includes the transaction type, quantity, and arrangement order of the transaction header (128 bits) that constitute the sequence, so as to instruct the device behavior simulator to generate the corresponding test sequence. That is, the test sequence in this embodiment can flexibly reconstruct and define the transaction type and transaction sequence of the stimulus to be generated.

[0028] The test pattern in this embodiment is composed of a series of special transaction sets with agreed transaction origins and transaction destinations. The characteristics of this set are a large number of transactions, a single transaction type, little change in transaction content, and algorithmic rules, so that the originator can be quickly generated and the destination can be quickly parsed, thereby performing fast and complete prototype verification and system testing. Figure 3Taking the chip verification system structure shown as an example, the test pattern is transmitted from the initiator (e.g., the device corresponding to the first device connector) to the destination (e.g., the device corresponding to the fourth device connector) via the DUT. The test pattern can be a large number (e.g., more than 10,000) of single CfgRd0 transactions. The target register address fields (or other fields required for verification) of these transactions change according to a certain algorithmic rule (e.g., increasing or decreasing by a step of 4, or other function change rules). Before starting verification, the algorithmic rule is notified to the sending place and the destination, so that the sending place can quickly generate the pattern according to the rule, and the destination can quickly parse the pattern according to the rule. The speed here is mainly reflected in that it is only necessary to check whether the change of the transaction follows the pre-agreed algorithmic rule, without checking whether the transaction is standard or abnormal. The transmission path of these test patterns can be reconstructed, that is, the transaction initiator and the destination can be arbitrarily combined to maximize the completeness of verification and testing.

[0029] In this embodiment, the types of transmission paths of the test pattern mainly include: DSP→DSP, USP→DSP, DSP→USP, for example Fig.10 As shown, each type of transmission path takes three paths as an example. Since the number of DSPs in the switching chip is often greater than 1, the type of DSP→DSP includes unidirectional transmission (such as DSP4→DSPn) and bidirectional transmission between two DSPs (such as the transmission path corresponding to DSP2 and DSP3), that is, the origin and destination of different transmission paths in the DSP→DSP transmission path type can be different, and the same origin can correspond to multiple destinations; USP→DSP and DSP→USP include transmission between USP and different DSPs.

[0030] The test pattern configuration instruction in this embodiment includes the transaction type code, origination code, destination code, algorithm type code, and transaction number code of the test pattern. These codes can be several bits. Fig.11 In the form of the test pattern configuration instruction shown, the number of bits of each code is 8bit, 16bit, 16bit, 8bit, and 32bit respectively. The algorithm type is pre-programmed in the device behavior simulator of the PCIe device simulator, and different types can be selected according to the configuration command. Fig.11The test pattern configuration instruction shown indicates that the test pattern is sent from the device corresponding to 0x0100, and the test pattern reaches the device corresponding to 0x0502. The transaction type used by the test pattern is 0x04 (assuming it is a CfgRd0 transaction), and the algorithm used by the test pattern is 0x05 (assuming that the address is incremented by 4 steps). The number of transactions of the test pattern is 0x2710, that is, 10000. After the instruction is input to the initiator, the initiator starts to generate and send the pattern; at the same time, the instruction is also input to the destination, and the destination checks the address in the received test pattern according to the instruction to determine whether it conforms to the expected algorithm rules.

[0031] Furthermore, the conventional PCIe device in the second PCIe device serving as the stimulus receiving end is used to parse the second sub-stimulus data and detect whether the transaction message obtained by parsing meets the preset protocol requirements; the PCIe device simulator in the second PCIe device is used to parse the first sub-stimulus data and the test pattern configuration instruction sent by the control terminal, and detect the test pattern obtained by parsing according to the algorithm type in the test pattern configuration information obtained by parsing to determine whether the test pattern changes according to the algorithm type; the PCIe device simulator in the second PCIe device is also used to parse the first sub-stimulus data and detect whether the test sequence obtained by parsing meets the protocol requirements. When the transaction message, the test pattern and the test sequence all meet the corresponding requirements, the switching chip verification is successful.

[0032] Specifically, detecting whether the test sequence obtained by parsing meets the protocol requirements includes: detecting whether the characteristic fields of each transaction in the test sequence meet the protocol requirements, and, when the test sequence contains abnormal transactions, determining whether the abnormal transactions have completed preset processing.

[0033] In this embodiment, when the second PCIe device as the stimulus receiving end receives the stimulus data, the conventional PCIe device in the second PCIe device is used to parse the transaction message and determine whether the transaction message meets the preset protocol requirements to determine whether the switching chip can normally send and receive the transaction message; the PCIe device simulator in the second PCIe device parses the stimulus configuration instruction sent by the control terminal, and parses the test pattern and test sequence to determine whether the received test pattern meets the preset algorithm rules according to the test pattern configuration instruction in the stimulus configuration instruction. For the test sequence, it is necessary to check the characteristic field of its transaction to determine whether the transaction and transaction sequence are complete and correct. For the test sequence containing abnormal transactions, it is also necessary to determine whether the abnormal transaction is preset (for example, marking, discarding, etc.). By verifying the rationality of the received transaction message, test sequence, test pattern, and abnormal transaction, when each verification is passed, the correctness of the switching chip performance can be determined.

[0034] The present application also provides a chip verification method, such as Fig.12 The following is a basic flow chart of a chip verification method provided by an embodiment. Fig.12 , the chip verification method includes: Step 1201: A first PCIe device serving as a stimulus initiator generates stimulus data and transmits the stimulus data to a corresponding first device connector; Step 1202: The first device connector transmits the excitation data to the switching chip; Step 1203: The switching chip transmits the stimulus data to the second PCIe device serving as the stimulus receiving end through the corresponding second device connector; Step 1204: The second PCIe device performs rationality verification on the stimulus data. When the rationality verification passes, the switching chip verification succeeds.

[0035] Specifically, the chip verification method in this embodiment can be used to perform prototype verification of the chip and system testing of the chip. The verification of the chip is based on the hardware platform resources of the aforementioned chip verification system, and the verification is completed through the stimulus data generated by the reconfigurable PCIe device. The reconfigurable PCIe device includes a conventional PCIe device and a PCIe device simulator. The stimulus data includes transaction messages, test sequences and test patterns. The conventional PCIe device is used to send and receive transaction messages, and the PCIe device simulator is used to send and receive test sequences and test patterns. By parsing the stimulus data transmitted by the stimulus sending end, it is determined whether the transaction message in the stimulus data meets the preset protocol, whether the test sequence meets the preset protocol, and whether the test pattern is transformed according to the preset algorithm, so as to determine whether the exchange chip can normally send, receive and process the stimulus data, and then verify the correctness and stability of its performance.

[0036] It should be noted that, for the above-mentioned embodiments, for the sake of simplicity of description, they are all described as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described action sequence, because according to the present application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0037] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0038] The above is a description of the chip verification system and method provided in this application. For technicians in this field, according to the ideas of the embodiments of this application, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on this application.

Claims

1. A chip verification system, characterized in that: include: A switching chip, a plurality of device connectors and a plurality of PCIe devices, wherein the plurality of device connectors are connected to the switching chip, the plurality of PCIe devices are connected to the switching chip through corresponding device connectors, and the PCIe devices are used as an excitation initiator and an excitation receiver; The first PCIe device as the stimulus initiator is used to: generate stimulus data and transmit it to the corresponding first device connector; The first device connector is used to: transmit the excitation data to the switching chip; The switching chip is used to: transmit the excitation data to a second PCIe device through a corresponding second device connector; wherein the second PCIe device serves as the excitation receiving end; The second PCIe device is used to perform rationality verification on the stimulus data, and when the rationality verification passes, the switching chip verification succeeds.

2. The chip verification system according to claim 1, characterized in that: The PCIe device includes a PCIe device simulator and a conventional PCIe device, the PCIe device simulator is also connected to an external control terminal, and the excitation data includes first sub-excitation data and second sub-excitation data; The PCIe device simulator in the first PCIe device is used to: generate corresponding first sub-stimulation data according to the stimulation configuration instruction sent by the control terminal, and transmit the data to the corresponding first device connector; The conventional PCIe device in the first PCIe device is used to generate corresponding second sub-stimulation data according to a preset PCIe protocol and transmit the second sub-stimulation data to the corresponding first device connector.

3. The chip verification system according to claim 2, characterized in that: The PCIe device simulator includes a debugging interface, an instruction parser and a device behavior simulator; The debugging interface is used to: receive the stimulus configuration instruction and transmit it to the instruction parser; The instruction parser is used to: parse the stimulus configuration instruction and transmit the parsed configuration information to the device behavior simulator; The device behavior simulator is used to generate corresponding first sub-stimulation data according to the configuration information and transmit the data to the first device connector.

4. The chip verification system according to claim 3, characterized in that: The configuration information includes test sequence configuration information, test pattern configuration information and simulator parameter configuration information; The device behavior simulator is specifically used to: set the corresponding parameters of the PCIe device simulator according to the simulator parameter configuration information, then generate a test sequence and a test pattern according to the test sequence configuration information and the test pattern configuration information, generate the first sub-stimulus data according to the test sequence and the test pattern and transmit it to the first device connector.

5. The chip verification system according to claim 4, characterized in that: The generating a test sequence and a test pattern according to the test sequence configuration information and the test pattern configuration information includes: Generate a test sequence according to the test sequence configuration information; wherein the test sequence includes a plurality of transactions whose transaction headers are arranged in a preset order, and the transactions include standard transactions and / or abnormal transactions; A test pattern is generated according to the test pattern configuration information; wherein the test pattern includes target transactions of multiple target transaction types, pattern initiation location information, pattern destination information, algorithm type and target transaction quantity, and the algorithm is used to control the corresponding changes of the multiple target transactions, and the algorithm is preprogrammed in the device behavior simulator.

6. The chip verification system according to claim 2, characterized in that: The conventional PCIe device is specifically used to: generate a corresponding transaction message according to the PCIe protocol, and generate the second sub-stimulation data according to the transaction message.

7. The chip authentication system according to claim 2, characterized in that: The conventional PCIe device in the second PCIe device is used to: parse the second sub-stimulation data, and detect whether the transaction message obtained by parsing meets the preset protocol requirements; The PCIe device simulator in the second PCIe device is used to: parse the first sub-stimulus data and the test pattern configuration instruction sent by the control terminal, and detect the test pattern obtained by the parsing according to the algorithm type in the test pattern configuration information obtained by the parsing, so as to determine whether the test pattern is changed according to the algorithm type; The PCIe device simulator in the second PCIe device is also used to: parse the first sub-stimulus data, and detect whether the test sequence obtained by parsing meets the protocol requirements. When the transaction message, the test pattern and the test sequence all meet the corresponding requirements, the switching chip verification is successful.

8. The chip authentication system according to claim 7, characterized in that: The detecting and analyzing whether the test sequence obtained meets the protocol requirements includes: Detecting whether the characteristic fields of each transaction in the test sequence meet the protocol requirements, and, when the test sequence includes an abnormal transaction, determining whether the abnormal transaction has completed a preset process.

9. The chip authentication system according to claim 1, characterized in that: The device type of the PCIe device includes any one of the following: RC device, EP device, NT device and Fabric device.

10. A chip verification method, characterized in that: include: A first PCIe device as a stimulus initiator generates stimulus data and transmits it to a corresponding first device connector; The first device connector transmits the excitation data to the switching chip; The switching chip transmits the excitation data to a second PCIe device through a corresponding second device connector; wherein the second PCIe device serves as an excitation receiving end; The second PCIe device performs rationality verification on the stimulus data, and when the rationality verification passes, the switching chip verification succeeds.

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