A pixel data processing method, system, electronic device and storage medium

Abstract

The present application discloses a pixel data processing method, system, electronic device and storage medium, and relates to the field of data processing. The system obtains the total number of cache levels based on the ratio of the pixel row interval to the pixel and the number of light sources, and in each row pixel reading cycle, the data in the cache flows downward step by step, and the cache of the last level is stored in the intermediate cache. After the TDI sensor outputs a row of data, it is superimposed with the data in the intermediate cache, and the superimposed data is input into the next cache module, and each data cache module corresponds to a pixel row one by one. Thus, in each row pixel reading cycle, after the data is superimposed, input into the data cache module, and flows out step by step and input into the intermediate cache module in a fixed order, the superposition of the data in the TDI can be realized, without calculating the spatial position corresponding to the cache, thereby improving the efficiency of TDI superposition.

Description

Technical Field

[0001] The present invention belongs to the field of data processing, and in particular relates to a pixel data processing method, system, electronic device and storage medium. Background Art

[0002] As the requirements for detection accuracy and efficiency in the field of machine vision continue to increase, multi-line TDI cameras are increasingly being used. Compared to ordinary line array cameras that generally have only one row of photosensitive pixels, a typical feature of a multi-line TDI camera is that its image sensor (i.e., TDI sensor) has multiple rows of photosensitive pixels. For example, multi-line TDI cameras with 2 or 4 rows of photosensitive pixels are already quite common, and there are even more multi-line TDI cameras with 12 or even 16 rows of photosensitive pixels.

[0003] Compared with multi-line TDI cameras with a higher number of rows (for example, 256 rows), multi-line TDI cameras with low-order pixel rows are characterized in that their image sensors themselves usually do not have the TDI overlay function. It is necessary to read the pixel data corresponding to all rows of pixels from the TDI sensor and then complete the TDI overlay in the back-end processor, which places high demands on the cache space of the back-end processor.

[0004] In order to reduce the cache space of the back-end processor, the Chinese patent "CN118784994A A TDI data caching method, system, electronic device and storage medium" proposes a solution. During the TDI data superposition process, by reusing the same buffer, the image data to be superimposed (i.e., the pixel data of this application) is read, superimposed and rewritten at the same time. Compared with the traditional multi-line cache parallel superposition method, the RAM cache resources in the back-end processor can be reduced by more than half.

[0005] However, the above-mentioned TDI data caching scheme needs to calculate the cache address of each row of pixel data based on factors such as the reading cycle, the total number of sensor rows, and the total number of light sources during each overlay process. When the number of TDI sensor lines (i.e., the number of pixel rows) and the number of light source partitions increase, the cache address calculation process will become complicated and the consumption of logical resources will also increase significantly. Therefore, on the basis of reducing the TDI cache space, there is still room for improvement in the overlay efficiency of TDI data. Summary of the invention

[0006] The present application proposes a pixel data processing method, system, electronic device and storage medium, which are used to further improve the efficiency of TDI data superposition on the basis of reducing TDI cache space.

[0007] To achieve the above objectives, this application proposes the following technical solutions:

[0008] In a first aspect of the present application, a pixel data processing system is provided, comprising:

[0009] An adder, used for superimposing the data of a single row of pixels outputted successively by the image sensor and the data of the intermediate buffer module;

[0010] A data selector, used to input the superimposed data in the adder into the first-level cache area in the corresponding data cache module; wherein the data cache module corresponds one-to-one to the pixel rows in the image sensor except the end;

[0011] N-1 data cache modules, each of which contains M-level cache areas, for receiving cached superimposed data as cached data; and in the process of receiving, the cached data in each level of cache area is sequentially moved to the next level of cache area, and the cached data in the last level of cache area is input into the intermediate cache module; wherein N represents the total number of rows of the image sensor, and N≥2; M=A×B, A represents the ratio of the pixel row interval to the pixel in the image sensor, rounded to the integer plus one, and B represents the number of light sources;

[0012] The intermediate cache module is used to input the internal data into the adder when the data of a single row of pixels is input into the adder; wherein, after the data of the last pixel row in the image sensor is superimposed with the data of the intermediate cache module, the data of the completed TDI superposition is obtained; before running the pixel data processing system, the data of the data cache module and the intermediate cache module are cleared.

[0013] Optionally, the data cache module is composed of one or more data caches;

[0014] A data buffer is used as a first-level buffer area; or, the buffer space in a data buffer is divided to form a multi-level buffer area.

[0015] Optionally, each level of cache caches data of one row of pixels.

[0016] Optionally, the intermediate cache module includes only one cache area.

[0017] Optionally, the data selector includes N-1 output terminals; wherein the final output terminal directly outputs the data superimposed in the adder, and the remaining output terminals are connected one-to-one with the data cache module, and are used to output the data superimposed in the adder to the first-level cache area of ​​the data cache module.

[0018] In a second aspect of the present application, a pixel data processing method is provided, which is applied to any pixel data processing system described in the first aspect, and the pixel data processing method includes:

[0019] In each row pixel reading cycle, the data of a single row of pixels in the image sensor and the data in the intermediate buffer module are obtained and superimposed in the adder;

[0020] Based on the data selector, the superimposed data is input into the corresponding data cache module and cached into the first-level cache area of ​​the data cache module; wherein each data cache module corresponds to a row of pixels in the image sensor, and the data generated by the last pixel row in the image sensor is superimposed with the data in the middle cache module to serve as the data after TDI superposition is completed;

[0021] In the process of inputting the superimposed data into the corresponding data buffer module, the pixel data processing method further includes:

[0022] In each row pixel reading cycle, the data in each level of the cache area in the corresponding data cache module is input into the next level of the cache area, and the data in the last level of the cache area is input into the intermediate cache module.

[0023] Optionally, the total number of the data cache modules is N-1, and according to the order of acquiring data in each row of pixels in the image sensor, based on the data selector, the superimposed data are input into the corresponding data cache modules in turn.

[0024] Optionally, the pixel data processing method further includes:

[0025] Before acquiring the data of a single row of pixels in the image sensor, the data in the data buffer module and the intermediate buffer module are cleared.

[0026] In a third aspect of the present application, an electronic device is provided, comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus;

[0027] Memory, used to store computer programs;

[0028] The processor is used to implement the pixel data processing method described in any one of the second aspects when executing the program stored in the memory.

[0029] In a fourth aspect of the present application, a computer-readable storage medium is provided, in which a computer program is stored. When the computer program is executed by a processor, the pixel data processing method described in any one of the second aspects is implemented.

[0030] The beneficial effects of this application are as follows:

[0031] The present application provides a pixel data processing system, comprising: an adder, used to superimpose the data of a single row of pixels outputted successively by an image sensor and the data of an intermediate cache module; a data selector, used to input the superimposed data in the adder into a first-level cache area in a corresponding data cache module; wherein the data cache module corresponds one-to-one to the pixel rows in the image sensor except the end; N-1 data cache modules, each of which contains M-level cache areas, used to receive the superimposed cached data as cached data; and in the process of receiving, the cached data in each level of cache area is sequentially moved to the next level of cache area The cached data in the last level cache area is input into the middle cache module; wherein N represents the total number of rows of the image sensor, and N≥2; M=A×B, A represents the ratio of the pixel row interval to the pixel in the image sensor, which is rounded up and added to one, and B represents the number of light sources; the middle cache module is used to input the internal data into the adder when the data of a single row of pixels is input into the adder; wherein, the data of the last pixel row in the image sensor is superimposed with the data of the middle cache module to obtain the data that completes the TDI superposition; before running the pixel data processing system, the data of the data cache module and the middle cache module are cleared.

[0032] Based on the above processing, the present application provides a hardware structure that can be used for TDI data superposition, using the ratio of the pixel row interval to the pixel in the image sensor and the numerical value calculated by the number of light sources as the total number of cache levels in the data cache module; in each row pixel reading cycle, the data in the cache area flows downward step by step, and the cache area of ​​the last level is stored in the intermediate cache area; and, after the image sensor outputs a row of data, it is superimposed with the data in the intermediate cache area, and the superimposed data is input into the next cache module, and each cache module corresponds one-to-one to different pixel rows.

[0033] Therefore, under the above hardware structure, in each row pixel reading cycle, after completing the data superposition, input into the data cache module, step-by-step outflow and input into the intermediate cache module in a fixed order, the data superposition in TDI can be realized without calculating the spatial position corresponding to the cache area, thereby improving the efficiency of TDI superposition. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0035] Figure 1 is a structural diagram of a pixel data processing system provided by the present application;

[0036] Figure 2is a structural diagram of another pixel data processing system provided by the present application;

[0037] Figure 3 It is a structural diagram of an electronic device provided by this application. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0039] Linear array photometric stereo methods basically use a linear array camera with multiple light sources placed in different positions. By collecting images of the object under different light sources and combining them with the fusion algorithm deployed in the back-end processor, key information such as the surface normal of the object is calculated, and then an image that can reflect the height of the object surface is generated.

[0040] The quality of the original image collected under each light source will directly affect the normal vector calculation and fusion results. Furthermore, when the camera line frequency is high (limited exposure time is small) or the light source brightness is low, the signal-to-noise ratio of the system original image decreases, and the corresponding fused image quality will also decrease accordingly.

[0041] TDI (Time Delay Integration) technology can take advantage of the multi-row pixel in the DI sensor. By matching the relationship between the object's motion speed and the line frequency, the same position of the object to be measured can be imaged on different rows of pixels of the sensor at different times. By superimposing the imaging results of different rows of pixels, a higher image signal-to-noise ratio can be achieved.

[0042] Existing multi-line TDI sensors usually read out the graphic data corresponding to all rows of pixels and then complete the TDI data superposition in the back-end processor, which takes up a lot of cache space. In order to reduce the cache space of the back-end processor, the Chinese patent "CN118784994A A TDI data cache method, system, electronic device and storage medium" proposes a solution. In the TDI data superposition process, by reusing the same buffer and reading, superimposing and rewriting the data to be superimposed, compared with the traditional multi-line cache parallel superposition method, the RAM cache resources are reduced by more than half.

[0043] However, in the above-mentioned TDI data caching scheme, in each superposition process, it is necessary to calculate the cache address of each row of pixel data (i.e., the data of this application) based on factors such as the reading cycle, the total number of sensor rows, the total number of light sources, etc. When the number of sensor lines and the number of light source partitions increase, the calculation process of the cache address will become complicated, and the corresponding logic resource consumption will also increase greatly, thereby reducing the superposition efficiency of TDI data.

[0044] In order to solve the above problems, Figure 1 As shown, the present application proposes a pixel data processing system, comprising:

[0045] The adder is used to superimpose the data of a single row of pixels output successively by the image sensor and the data of the intermediate buffer module.

[0046] The data selector is used to input the superimposed data in the adder into the first-level cache area in the corresponding data cache module. The data cache module corresponds to the pixel rows in the image sensor except the end.

[0047] N-1 data cache modules, each of which contains M-level cache areas, are used to receive the cached superimposed data as cached data. During the receiving process, the cached data in each level of cache area is moved to the next level of cache area in sequence, and the cached data in the last level of cache area is input into the intermediate cache module. Wherein, N represents the total number of rows of the image sensor, and N≥2; M=A×B, A represents the ratio of the pixel row interval to the pixel in the image sensor, rounded to the integer plus one, and B represents the number of light sources.

[0048] The intermediate cache module is used to input the internal data into the adder when the data of a single row of pixels is input into the adder. The data of the last pixel row in the image sensor is superimposed with the data of the intermediate cache module to obtain the data that completes the TDI superposition. Before running the pixel data processing system, the data of the data cache module and the intermediate cache module are cleared.

[0049] Based on the above processing, the present application provides a hardware structure that can be used for TDI data superposition, using the ratio of the pixel row interval to the pixel in the image sensor and the numerical value calculated by the number of light sources as the total number of cache levels in the data cache module; in each row pixel reading cycle, the data in the cache area flows downward step by step, and the cache area of ​​the last level is stored in the intermediate cache area; and, after the image sensor outputs a row of data, it is superimposed with the data in the intermediate cache area, and the superimposed data is input into the next cache module, and each cache module corresponds one-to-one to different pixel rows.

[0050] Therefore, under the above hardware structure, in each row pixel reading cycle, after completing the data superposition, input into the data cache module, step-by-step outflow and input into the intermediate cache module in a fixed order, the data superposition in TDI can be realized without calculating the spatial position corresponding to the cache area, thereby improving the efficiency of TDI superposition.

[0051] In actual work, after one exposure, all pixels in the multi-line TDI sensor generate pixel values ​​(i.e., data of this application) to form a frame of image data. The back-end processor successively obtains the data of a row of pixels in the above frame of image data in each row pixel reading cycle. Among them, a row pixel reading cycle refers to the time period spent on reading the data in a row of pixels, and successive acquisition refers to obtaining the data of a row of pixels in sequence based on the arrangement order of the pixel rows.

[0052] In one implementation, the adder represents an electronic device that can perform data superposition, and a lookup table may also be used instead.

[0053] The data selector may be a MUX (multiplexer) for connecting the adder to different data cache modules, so that the superimposed data in the adder can be successively input to different data cache modules or directly output according to the order of the row pixel reading cycle.

[0054] In some embodiments, the data selector includes N-1 output terminals; among them, the final output terminal directly outputs the superimposed data in the adder to the processor, and the remaining output terminals are connected one-to-one with the data cache module, and are used to output the superimposed data in the adder to the first-level cache area of ​​the data cache module.

[0055] In the present application, after each exposure, data of different pixel rows in the TDI sensor are acquired one by one according to the arrangement order of the pixel rows. At the same time, the pixel data processing system provided by the present application includes N-1 pixel cache modules, and each pixel cache module corresponds to the first N-1 pixel rows in the TDI sensor.

[0056] For example, the TDI sensor has four pixel rows, L1, L2, L3 and L4, and the corresponding three data cache modules are divided into A1, A2 and A3. L1 is the first pixel row, which means that in the TDI data superposition process, the first pixel row generates the data to be superimposed, or in the process of generating the TDI image, the first pixel row to capture the measured area. Similarly, according to the arrangement order of the pixel rows, the last pixel row represents the last pixel row to capture the measured area in the process of generating the TDI image. Among them, pixel row L1 corresponds to data cache module A1, pixel row L2 corresponds to data cache module A2, and pixel row L3 corresponds to data cache module A3.

[0057] Specifically, when acquiring the data of pixel row L1, the data selector connects the adder to the data cache module A1, superimposes the data of L1 with the data in the intermediate cache module and inputs it into the data cache module A1. In the next row pixel reading cycle, when acquiring the data of pixel row L2, the data selector connects the adder to the data cache module A2 according to the arrangement order of the pixel rows, superimposes the data of L2 with the data in the intermediate cache module and inputs it into the data cache module A2. Similarly, when acquiring the data of pixel row L3, the data selector connects the adder to the data cache module A3 according to the arrangement order of the pixel rows, superimposes the data of L3 with the data in the intermediate cache module and inputs it into the data cache module A3. In the next row pixel reading cycle, when acquiring the data of the last pixel row in the TDI sensor, superimpose it with the data in the intermediate cache module as the data after TDI superposition is completed, and directly outputs it. Among them, it can be directly output to the next processor for processing the data after TDI superposition is completed.

[0058] Each data cache module contains M-level cache areas, and the total number of levels M is obtained by rounding the ratio of the pixel row interval to the pixel in the TDI sensor plus one, and multiplying it by the number of light sources. Among them, the ratio rounding means that when the ratio is an integer, it is rounded to its own value; when the ratio is a non-integer, the ratio value can be rounded up or down according to needs.

[0059] In addition, the number of light sources can be used to represent the number of exposures when the TDI sensor moves a single row of pixels. For example, in single-light mode, the ratio of the line rate of the TDI sensor to the object movement rate is 1:1; in multi-light mode with multi-angle lighting, the number of light sources is M, and at this time, the ratio of the line rate to the object movement rate is M:1.

[0060] In the application scenario where the ratio of the pixel row interval to the pixel is 1 and the number of light sources is 2 (that is, the ratio of the line frequency to the object movement rate is 2), the number of levels of the cache area in each data cache module is 4. Combined with the TDI superposition principle, it can be seen that in this application scenario, the data of the first pixel row at the first exposure is superimposed with the data of the second row of pixel rows under the fifth exposure. According to the aforementioned solution, in each row pixel reading cycle, the data in the cache area in the corresponding data cache module flows to the next cache area, and the data in the last level of the cache area flows to the intermediate cache module. Therefore, according to the structural setting of this superposition system and the direction of data superposition flow, the data of the first pixel row at the first exposure can be superimposed with the data of the second row of pixel rows under the fifth exposure, which conforms to the TDI superposition process.

[0061] In some embodiments, the data cache module is composed of one or more data caches. For example, one data cache is used as a first-level cache area, that is, one data cache module is composed of M caches.

[0062] Alternatively, the data cache module may be composed of a data cache, such as a FIFO cache, by dividing the cache space in the data cache to form an M-level cache area. Based on the above processing, the utilization rate of the cache resources in the cache can be improved.

[0063] In one implementation, each level of buffer caches data of a row of pixels, wherein the data of the row of pixels includes data before superposition and data after superposition.

[0064] In some embodiments, only one buffer area may be provided in the intermediate buffer module. Based on the above processing, it can be known that in the working scenario of an image sensor with 4 pixel rows, a ratio of pixel row interval to pixel size of 1, and a light source number of 3, the total number of corresponding buffer areas in the pixel data processing system provided by the present application is 19, which is the same as the total amount of buffer space (i.e., buffer area) in the solution provided by the Chinese patent "CN118784994A A TDI data caching method, system, electronic device and storage medium". It can be seen that the pixel data processing solution provided by the present application can also achieve the purpose of reducing the TDI buffer space.

[0065] It should be noted that before the pixel data processing system provided by the present application is run, the data in the data cache module and the intermediate cache module are all cleared. That is, in the initial state, the pixel values ​​of the data in the data cache module and the intermediate cache module are all 0. Based on this, not only the influence of the original pixel values ​​in the data cache module and the intermediate cache module on the TDI superposition process is avoided, but also the data generated by the pixel rows that have not captured the measured area does not need to be discarded, which further ensures that during the TDI superposition process, there is no need to calculate the data of the discarded pixel rows, and ensures that during the operation of the TDI superposition system provided by the present application, no logical operation is required.

[0066] Based on the same inventive concept, the present application also provides a pixel data processing method, which is applied to the aforementioned pixel data processing system. The pixel data processing method includes the following steps:

[0067] S1. In each row pixel reading cycle, the data of a single row of pixels in the image sensor and the data in the intermediate buffer module are obtained, and superposition is completed in the adder.

[0068] S2. Based on the data selector, the superimposed data is input into the corresponding data cache module and cached into the first-level cache area of ​​the data cache module.

[0069] Each data buffer module corresponds to a row of pixels in the image sensor, and the data generated by the last pixel row in the image sensor is superimposed with the data in the middle buffer module to serve as row data after TDI superposition is completed.

[0070] In the process of inputting the superimposed data into the corresponding data buffer module, the pixel data processing method further includes the following steps:

[0071] S3. In each row pixel reading cycle, the data in each level of the cache area in the corresponding data cache module is input into the next level of the cache area, and the data in the last level of the cache area is input into the intermediate cache module.

[0072] In one implementation, the total number of data cache modules is N-1, and according to the order of acquiring data of each row of pixels in the TDI sensor, based on the data selector, the superimposed data is input into the corresponding data cache module in turn.

[0073] In one implementation, before acquiring the data of a single row of pixels in the image sensor, the data in the data buffer module and the intermediate buffer module in the pixel data processing system are cleared.

[0074] Based on the above settings, combined with the structural settings in the pixel data processing system, according to the reading order of data in different pixel rows, the data after superimposing pixels in different rows are input into different data cache spaces according to the arrangement order of pixel rows (or the reading order of pixel rows, that is, the preset selection order) using a data selector. At the same time, the number of cache areas and the setting of data flow in the data cache module are used to ensure that the data superimposed in the adder conform to the TDI superposition principle. In addition, when the data after superimposing the last pixel row also belongs to the data after completing TDI superposition, and it is directly output, the logical operation in the TDI superposition process is greatly reduced, and the efficiency of TDI superposition is further improved.

[0075] This solution is explained by taking the application scenario where the total number of rows of sensors is 4, the ratio of pixel row interval to pixel is 1, and the number of light sources is 2 (the ratio of row frequency to object motion speed is 2 at this time) as an example. Figure 2 As shown, Figure 2 A schematic diagram of the structure of another pixel data processing system provided in this application.

[0076] After each exposure, the TDI sensor generates data for 4 rows of pixels. During the data reading process, only one row of pixel data is read in each row pixel reading cycle, and the reading is performed in the order of L1, L2, L3 and L4. The data selector is a 4-to-1 data selector, and the data cache module includes A1, A2 and A3. Among them, each data cache module includes 4 cache areas, namely cache areas 10 to 13, cache areas 20 to 23, and cache areas 30 to 33, and the middle cache module includes only one cache area, namely middle cache area B.

[0077] First, before the TDI superposition system is run, the data in the data cache modules A1, A2 and A3, and the intermediate cache area B are cleared, that is, in the initial state, the data in each cache area is 0.

[0078] After the first exposure, the data generated by the pixel row L1 is valid data L11. In the first row pixel reading cycle, the pixel value in the buffer area 13 is input into the intermediate buffer area B, and the valid data L1 is superimposed with the data of 0 in the intermediate buffer area B and then input into the buffer area 10. The following content of the embodiment is explained by taking the valid data L11 as an example, and the rest of the row data can be understood by referring to this process. Among them, L11 represents the data generated by the pixel row L1 during the first exposure.

[0079] Similarly, in the next three pixel reading cycles, the data of pixel rows L2 and L3 are superimposed with data 0 and input into buffers 20 and 30 respectively, and the data of L4 is superimposed with data 0 and output. Among them, the data of L1 is only valid data, so before the TDI superposition of L1 data is completed during the first exposure, the back-end processor does not need to process the directly output data.

[0080] It should be noted that after each exposure, when the data of the last row of pixels is superimposed with the data in the intermediate buffer area (i.e., the intermediate buffer module), the data in the intermediate buffer area is cleared (i.e., the data in the intermediate buffer area is set to 0). Therefore, after the next exposure, it can be ensured that the result after the data of the first row of pixels is superimposed with the data in the intermediate buffer area is still the original data generated by the first row of pixels, that is, it effectively avoids the error in the superposition process of the first row of pixel data in the next exposure due to the fact that the remaining data in the intermediate buffer area is not 0 after superposition.

[0081] After the second exposure, the data generated by the pixel row L1 is valid data L12, which is input to the buffer area 10, and the valid data L11 is transferred to the buffer area 11. The data of the remaining pixel rows are invalid data, which will not be described in detail.

[0082] After the third exposure, the data 0 in the original buffer area 11 is transferred to the intermediate buffer area B, the data generated by the pixel row L1 is the valid data L13, which is input to the buffer area 10, while the valid data L12 flows to the buffer area 11, and the valid data L11 flows to the buffer area 12.

[0083] After the fourth exposure, the data 0 in the original buffer area 10 is transferred to the intermediate buffer area, and the data generated by the pixel row L1 is the valid data L14, which is input into the buffer area 10, while the valid data L13 flows to the buffer area 11, the valid data L12 flows to the buffer area 12, and the valid data L11 flows to the buffer area 13.

[0084] After the fifth exposure, in the first row pixel reading cycle, the data L11 in the original buffer area 10 is transferred to the intermediate buffer area B, and the data generated by the pixel row L1 is the valid data L15, which is input into the buffer area 10, while the valid data L14 flows to the buffer area 11, the valid data L13 flows to the buffer area 12, and the valid data L12 flows to the buffer area 13.

[0085] During the second row pixel reading cycle, the data L25 generated by the second row of pixels is superimposed with the data L11 in the intermediate buffer area, and then the data in each buffer area in the data buffer module A2 is transferred one by one to the next buffer area, and the data after the superposition of L25 and L11 is cached in the buffer area 20.

[0086] Similarly, after the 9th exposure, the superimposed data of L25 and L11 has been cached in the intermediate cache area B. In the reading process of the data generated after the 9th exposure, in the third row pixel reading cycle, the data L39 generated by the pixel row L3 is superimposed again with the superimposed data of L25 and L11, and then the data in each cache area in the data cache module A2 is transferred one by one to the next cache area, and the superimposed data of L39, L25 and L11 is cached in the cache area 30.

[0087] Similarly, after the 13th exposure, the data after the superposition of L39, L25 and L11 has been cached in the intermediate cache area B. In the reading process of the data generated after the 13th exposure, in the fourth row pixel reading cycle, the data L413 generated by the pixel row L4 is superimposed again with the data after the superposition of L39, L25 and L11, thereby obtaining the data after the TDI superposition is completed and directly output to the next processor. In addition, the TDI superposition corresponding to the remaining rows of pixels can be understood by referring to the above process.

[0088] The present application also provides an electronic device, such as Figure 3 As shown, it includes a processor 301, a communication interface 302, a memory 303 and a communication bus 304, wherein the processor 301, the communication interface 302, and the memory 303 communicate with each other through the communication bus 304.

[0089] Memory 303, used for storing computer programs;

[0090] The processor 301 is used to implement any of the above-mentioned pixel data processing methods when executing the program stored in the memory 303.

[0091] The communication bus mentioned in the above electronic device can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0092] The communication interface is used for communication between the above electronic device and other devices.

[0093] The memory may include a random access memory (RAM) or a non-volatile memory (NVM), such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

[0094] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0095] In another embodiment provided in the present application, a computer-readable storage medium is provided, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned pixel data processing methods are implemented.

[0096] In another embodiment provided in the present application, a computer program product including instructions is also provided, which, when executed on a computer, enables the computer to execute the steps of any pixel data processing method in the above embodiments.

[0097] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A pixel data processing system, characterized in that: include: An adder, used for superimposing the data of a single row of pixels outputted successively by the image sensor and the data of the intermediate buffer module; A data selector, used to input the superimposed data in the adder into the first-level cache area in the corresponding data cache module; wherein the data cache module corresponds one-to-one to the pixel rows in the image sensor except the end; the final output end of the data selector directly outputs the superimposed data in the adder, and the remaining output ends of the data selector are connected one-to-one with the data cache module, and are used to output the superimposed data in the adder to the first-level cache area of ​​the data cache module; N-1 data cache modules, each of which contains M-level cache areas, for receiving cached superimposed data as cached data; and in the process of receiving, the cached data in each level of cache area is sequentially moved to the next level of cache area, and the cached data in the last level of cache area is input into the intermediate cache module; wherein N represents the total number of rows of the image sensor, and N≥2; M=A×B, A represents the ratio of the pixel row interval to the pixel in the image sensor, rounded to the integer plus one, and B represents the number of light sources; The intermediate cache module is used to input the internal data into the adder when the data of a single row of pixels is input into the adder; wherein, after the data of the last pixel row in the image sensor is superimposed with the data of the intermediate cache module, the data of the completed TDI superposition is obtained; before running the pixel data processing system, the data of the data cache module and the intermediate cache module are cleared.

2. The system according to claim 1, characterized in that The data cache module is composed of one or more data caches; A data buffer is used as a first-level buffer area; or, the buffer space in a data buffer is divided to form a multi-level buffer area.

3. The system according to claim 1, characterized in that Each level of buffer caches data for one row of pixels.

4. The system according to claim 1, characterized in that The intermediate cache module only includes one cache area.

5. A pixel data processing method, characterized in that: Applied to the system according to any one of claims 1 to 4, the pixel data processing method comprises: In each row pixel reading cycle, the data of a single row of pixels in the image sensor and the data in the intermediate buffer module are obtained and superimposed in the adder; Based on the data selector, the superimposed data is input into the corresponding data cache module and cached into the first-level cache area of ​​the data cache module; wherein each data cache module corresponds to a row of pixels in the image sensor, and the data generated by the last pixel row in the image sensor is superimposed with the data in the middle cache module to serve as the data after TDI superposition is completed; In the process of inputting the superimposed data into the corresponding data buffer module, the pixel data processing method further includes: The data in each level of cache area in the corresponding data cache module is input into the next level of cache area, and the data in the last level of cache area is input into the intermediate cache module.

6. The method according to claim 5, characterized in that The total number of the data cache modules is N-1. According to the order of acquiring data in each row of pixels of the image sensor, based on the data selector, the superimposed data is input into the corresponding data cache modules in turn.

7. The method according to claim 5, characterized in that The pixel data processing method further includes: Before acquiring the data of a single row of pixels in the image sensor, the data in the data buffer module and the intermediate buffer module are cleared.

8. An electronic device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; Memory, used to store computer programs; The processor is used to implement the pixel data processing method described in any one of claims 5 to 7 when executing the program stored in the memory.

9. A computer-readable storage medium, characterized in that: A computer program is stored in the computer-readable storage medium, and when the computer program is executed by the processor, the pixel data processing method described in any one of claims 5 to 7 is implemented.

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