Display panel and display device

Abstract

The invention provides a display panel and a display device. The problem that in the prior art, the frame size of a display panel is large is solved. The display panel is provided with a display area and a frame area at least partially surrounding the display area, the frame area comprises a first frame area, an arc angle frame area and a second frame area which are connected in sequence, and the display panel comprises a first gate drive circuit located in the frame area; the first gate drive circuit comprises a plurality of first gate drive units, and the distance between every two adjacent first gate drive units in the second frame area and the arc angle frame area is larger than the distance between every two adjacent first gate drive units in the arc angle frame area.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Currently, display screens usually adopt an arc-corner design. Due to the layout of the circuit structure, the arc-corner border area needs to occupy a larger area than the straight border area, resulting in the arc-corner border area being wider than the straight border area, which is not conducive to the realization of a narrow border. Summary of the invention

[0003] In view of this, embodiments of the present application provide a display panel and a display device, which solve the problem of large display panel frame size in the prior art.

[0004] In a first aspect, the present application provides a display panel, comprising a display area and a border area at least partially surrounding the display area, wherein the border area comprises a first border area, an arc-angle border area, and a second border area connected in sequence; the display panel comprises: a first gate driving circuit, located in the border area; the first gate driving circuit comprises a plurality of first gate driving units, and a distance between two adjacent first gate driving units in the second border area and in the arc-angle border area is greater than a distance between two adjacent first gate driving units in the arc-angle border area.

[0005] In combination with the first aspect, in some possible implementations, the first border area and the second border area are both straight borders; preferably, the number of first gate driving units in the second border area is less than the number of first gate driving units in the arc-angle border area; preferably, along the circumference of the display area, multiple first gate driving units are cascaded in sequence; preferably, the first gate driving circuit includes any one of a light-emitting driving circuit and a scanning driving circuit.

[0006] In combination with the first aspect, in some possible implementations, the display panel also includes a second gate driving circuit, which is located in the border area and on the side of the first gate driving circuit close to or away from the display area; preferably, the second gate driving circuit includes a plurality of second gate driving units arranged in sequence along the circumference of the display area; preferably, the arc-angle border area includes a first sub-area close to the first border area and a second sub-area close to the second border area; in the circumference of the display area, the second gate driving units of the first sub-area and the second gate driving units of the second sub-area are staggered; preferably, the number of the second gate driving units in the second sub-area is equal to the number of the first gate driving units in the second border area; preferably, along the circumference of the display area, the plurality of second gate driving units are cascaded in sequence; preferably, the second gate driving circuit includes any one of a light-emitting driving circuit and a scanning driving circuit; preferably, the second gate driving circuit includes a first scanning driving circuit.

[0007] In combination with the first aspect, in some possible implementations, the display panel also includes a third gate driving circuit, which is located in the border area and on the side of the second gate driving circuit away from the first gate driving circuit; preferably, the third gate driving circuit includes a plurality of third gate driving units arranged in sequence along the circumference of the display area; preferably, the arc-angle border area includes a first sub-area close to the first border area and a second sub-area close to the second border area; in the circumference of the display area, the third gate driving units of the first sub-area and the third gate driving units of the second sub-area are staggered; preferably, the number of third gate driving units in the second sub-area is equal to the number of first gate driving units in the second border area; or, the sum of the numbers of third gate driving units in the second border area and the third gate driving units in the second sub-area is equal to the number of first gate driving units in the second border area; preferably, along the circumference of the display area, a plurality of third gate driving units are cascaded in sequence; preferably, the third gate driving circuit includes any one of a light-emitting driving circuit and a scanning driving circuit; preferably, the third gate driving circuit includes a second scanning driving circuit.

[0008] In combination with the first aspect, in some possible implementations, the first gate driving circuit also includes at least one redundant first gate driving unit; the display panel also includes sub-pixels located in the display area, the first gate driving unit is electrically connected to the sub-pixels, and the redundant first gate driving unit is not electrically connected to the sub-pixels; at least part of the redundant first gate driving unit is located in the second border area and on at least one side of the first gate driving unit in the circumferential direction of the display area; preferably, the part of the redundant first gate driving unit is located in the arc angle border area and on the side of the first gate driving unit close to the second border area.

[0009] In combination with the first aspect, in some possible implementations, the display panel also includes a second gate driving circuit, which is located on a side of the first gate driving circuit close to or away from the display area; the second gate driving circuit includes a plurality of second gate driving units and at least one redundant second gate driving unit arranged in sequence along the circumference of the display area, the second gate driving unit is electrically connected to the sub-pixel, and the redundant second gate driving unit is not electrically connected to the sub-pixel; at least one redundant second gate driving unit is located in the arc angle border area, and is located on a side of the second gate driving unit close to the second border area; preferably, the arc angle border area includes a first sub-area close to the first border area and a second sub-area close to the second border area; in the circumference of the display area, the second gate driving unit of the first sub-area and the second gate driving unit of the second sub-area are staggered; preferably, the second border area is provided with at least one redundant second gate driving unit; preferably, in the second border area, the number of redundant second gate driving units is equal to the sum of the number of first gate driving units and redundant first gate driving units.

[0010] In combination with the first aspect, in some possible implementations, the display panel further includes a third gate driving circuit, which is located on a side of the second gate driving circuit close to or far from the first gate driving circuit; the third gate driving circuit includes a plurality of third gate driving units arranged in sequence along the circumference of the display area and at least one redundant third gate driving unit; the redundant third gate driving unit is not electrically connected to the sub-pixel, and the third gate driving unit is electrically connected to the sub-pixel; at least one redundant third gate driving unit is located in the arc angle border area, and is located on a side of the third gate driving unit close to the second border area; preferably, in the arc angle border area, the second gate driving unit and the third gate driving unit are The number of the second gate driving units in the arc-angle border area is equal; or the sum of the number of the second gate driving units in the arc-angle border area and the second gate driving units in the second border area is equal to the number of the third gate driving units in the arc-angle border area; preferably, the arc-angle border area includes a first sub-area close to the first border area and a second sub-area close to the second border area; in the circumferential direction of the display area, the third gate driving units in the first sub-area and the third gate driving units in the second sub-area are staggered; preferably, in the second straight border area, the sum of the number of the first gate driving unit and the redundant first gate driving unit, the sum of the number of the second gate driving unit and the redundant second gate driving unit, and the number of the redundant third gate driving units are equal.

[0011] In combination with the first aspect, in some possible implementations, the display panel further includes a first gate line and a gate connection line; the first gate line is located in the display area, and the gate connection line connects the first gate line and the first gate driving unit in the second frame area; the gate connection line includes a first sub-connection line, a portion of the first sub-connection line located in the display area extends in the same direction as the first gate line, and an orthographic projection of the first sub-connection line on the substrate is located between an orthographic projection of the first gate line on the substrate and an orthographic projection of the first gate driving unit on the substrate; preferably, a portion of the first sub-connection line located in the frame area is electrically connected to the first gate line through at least one line-changing hole; preferably The display panel further includes a second gate line and a third gate line located in the display area, and the orthographic projections of the portion of the first sub-connection line located in the display area, the second gate line, the first gate line, and the third gate line on the substrate are arranged in sequence; preferably, the first gate line, the second gate line, and the third gate line are arranged in the same layer; preferably, the first sub-connection line and the first gate line are arranged in different layers; preferably, the display panel further includes a second initialization signal line, and at least part of the second initialization signal line and the first sub-connection line are colinear; preferably, the first gate line includes a light-emitting line, the second gate line includes a fourth scanning line, and the third gate line includes a second scanning line.

[0012] In combination with the first aspect, in some possible implementations, the display panel also includes a shielding line, which is located on the side of the first sub-connection line close to the substrate; the orthographic projection of the first sub-connection line on the substrate and the orthographic projection of the shielding line on the substrate at least partially overlap; preferably, the shielding line is multiplexed as a first initialization signal line.

[0013] In combination with the first aspect, in some possible implementations, a first sub-connection line of the plurality of gate connection lines is located at a first end of the display area corresponding to a sub-pixel, an orthographic projection of the first end on the substrate overlaps with an orthographic projection of the corresponding sub-pixel on the substrate, and the sub-pixels corresponding to the first ends of adjacent first sub-connection lines are located in adjacent rows and adjacent columns; or, an orthographic projection of the first sub-connection line on the substrate passes through an orthographic projection of at least one sub-pixel on the substrate; the number of sub-pixels through which the orthographic projections of at least some of the first sub-connection lines pass is equal; preferably, the number of sub-pixels through which the orthographic projections of at least some of the adjacent odd and even first sub-connection lines pass is equal.

[0014] In combination with the first aspect, in some possible implementations, the gate connection line also includes a second sub-connection line, and the second sub-connection line is electrically connected to an end of the first sub-connection line away from the first gate line; the extension directions of the second sub-connection line and the first sub-connection line intersect; preferably, an end of the second sub-connection line away from the first sub-connection line is electrically connected to the first gate driving unit; preferably, the second sub-connection line and the first sub-connection line are arranged in different layers; preferably, the second sub-connection line and the first gate line are arranged in different layers; preferably, the display panel also includes a low-voltage power supply line, at least part of the low-voltage power supply line and the second sub-connection line are colinear; preferably, the display panel also includes multiple data lines, and the second sub-connection line is located between adjacent data lines; preferably, the second sub-connection lines of adjacent odd and even positions are connected to the same first gate driving unit.

[0015] In combination with the first aspect, in some possible implementations, a second sub-connection line of the multiple gate connection lines is located at the second end of the display area and corresponds to a sub-pixel, the orthographic projection of the second end on the substrate overlaps with the orthographic projection of the corresponding sub-pixel on the substrate, and the sub-pixels corresponding to adjacent second sub-connection lines are located in adjacent rows and adjacent columns; or, the orthographic projection of the second sub-connection line on the substrate passes through the orthographic projection of at least one sub-pixel on the substrate; the number of sub-pixels through which the orthographic projections of at least some of the second sub-connection lines pass is equal; preferably, the number of sub-pixels through which the orthographic projections of at least some of the adjacent odd and even second sub-connection lines pass is equal.

[0016] In combination with the first aspect, in some possible implementations, the arc-angle border area includes a first sub-area close to the first border area and a second sub-area close to the second border area, and the first gate driving units of the arc-angle border area are all located in the first sub-area; preferably, the display panel also includes a second gate driving circuit and a third gate driving circuit, and part of the second gate driving circuit and part of the third gate driving circuit are located in the second sub-area; the first gate driving circuit also includes a plurality of signal lines, and the signal lines are connected to the first gate driving unit; the orthographic projection of the signal line on the substrate and the orthographic projection of the second gate driving circuit and the third gate driving circuit of the second sub-area on the substrate do not overlap; preferably, the plurality of signal lines include a plurality of clock signal lines; the display panel also includes a low-voltage power supply line, and the low-voltage power supply line is located on the side of the clock signal line away from the substrate; the pressure power supply line includes a plurality of vias, and the overlapping area of ​​the orthographic projections of different clock signal lines on the substrate and the orthographic projections of the multiple vias on the substrate is the same.

[0017] In combination with the first aspect, in some possible implementations, the display panel further has a bonding area, which is located on the side of the border area away from the display area; the first gate drive circuit also includes a plurality of signal lines, the signal lines include input signal lines, the input signal lines include a first sub-input line, a second sub-input line and a third sub-input line; the first sub-input line extends from the bonding area to the second sub-area, the second sub-input line connects one end of the first sub-input line located in the second sub-area and the first gate drive unit in the first sub-area, and the third sub-input line connects one end of the first sub-input line located in the second sub-area and the first gate drive unit in the first border area; preferably, the orthographic projection of the third sub-input line on the substrate and the orthographic projection of the first sub-input line on the substrate at least partially do not overlap.

[0018] In combination with the first aspect, in some possible implementations, the widths of the border area at different positions are equal.

[0019] According to a second aspect of the present application, another display panel is provided, comprising a display area and a border area surrounding the display area, wherein the border area comprises a first border area and a second border area, and the first border area and the second border area are arranged at intervals; the display panel comprises: a first gate driving circuit, located in the border area; the first gate driving circuit comprises a plurality of first gate driving units and at least one redundant first gate driving unit; at least some of the redundant first gate driving units are arranged on at least one side of the first gate driving unit in the first border area; and sub-pixels, located in the display area; the redundant first gate driving units are not electrically connected to the sub-pixels, and the first gate driving units are all electrically connected to the sub-pixels.

[0020] In combination with the second aspect, in some possible implementations, a redundant first gate driving unit is set on at least one side of the first gate driving unit in the second border area; preferably, the first border area and the second border area are connected through the arc-angle border area; preferably, a redundant first gate driving unit is set on at least one side of the first gate driving unit in the arc-angle border area.

[0021] A third aspect of the present application provides a display device, comprising a display panel provided by any of the above embodiments.

[0022] According to the display panel and display device provided by the embodiment of the present application, part of the first gate driving unit in the arc-angle border area is placed outside the second border area. In this way, the area occupied by the arc-angle border area can be reduced, which is conducive to reducing the size of the arc-angle border area, and further conducive to the realization of a narrow border. At the same time, the display panel provided by this embodiment only places part of the first gate driving circuit in the arc-angle border area outside the second border area, rather than placing all the first gate driving circuits in the arc-angle border area outside. In comparison, the former can ensure that the space utilization of the border area is more optimized and avoid space waste under the premise of achieving consistent width in all parts of the border area. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of the top structure of a display panel provided in one embodiment of the present application.

[0024] Figure 2 The first embodiment provides Figure 1 An enlarged view of a first partial area of ​​the display panel is shown.

[0025] Figure 3 1 is a circuit diagram of a first gate driving circuit in the display panel.

[0026] Figure 4 A circuit diagram of a sub-pixel provided in accordance with an embodiment of the present application.

[0027] Figure 5 The second embodiment provides Figure 1 An enlarged view of a local area of ​​the display panel is shown.

[0028] Figure 6 The third embodiment provides Figure 1 An enlarged view of a local area of ​​the display panel is shown.

[0029] Figure 7 The fourth embodiment provides Figure 1 An enlarged view of a local area of ​​the display panel is shown.

[0030] Figure 8 The fifth embodiment provides Figure 1 An enlarged view of a local area of ​​the display panel is shown.

[0031] Fig. 9 The sixth embodiment provides Figure 1 An enlarged view of a local area of ​​the display panel is shown.

[0032] Fig.10 The seventh embodiment provides Figure 1 An enlarged view of a local area of ​​the display panel is shown.

[0033] Fig.11 A circuit diagram of a first gate driving circuit provided in another embodiment.

[0034] Fig.12 The eighth embodiment provides Figure 1 An enlarged view of a local area of ​​the display panel is shown.

[0035] Fig.13 The ninth embodiment provides Figure 1 An enlarged view of a local area of ​​the display panel is shown.

[0036] Fig.14 The tenth embodiment provides Figure 1 An enlarged view of a local area of ​​the display panel is shown.

[0037] Fig.15 The eleventh embodiment provided Figure 1 An enlarged view of a local area of ​​the display panel is shown.

[0038] Fig.16 The twelfth embodiment provided Figure 1 An enlarged view of a local area of ​​the display panel is shown.

[0039] Fig.17 The thirteenth embodiment provided Figure 1 An enlarged view of a local area of ​​the display panel is shown.

[0040] Fig.18 The fourteenth embodiment provided Figure 1 An enlarged view of a local area of ​​the display panel is shown.

[0041] Fig.19 The fifteenth embodiment of the present application provides Figure 1 The diagram shows the wiring layout of a local area of ​​the display panel.

[0042] Fig. 20 for Fig.19 An enlarged view of a first partial area of ​​the display panel is shown.

[0043] Fig.21 for Fig.19 An enlarged view of a second partial area of ​​the display panel is shown.

[0044] Fig. 22 for Fig.19 An enlarged view of a third partial area of ​​the display panel is shown.

[0045] Fig.23 The sixteenth embodiment of the present application provides Figure 1 The diagram shows the wiring layout of a local area of ​​the display panel.

[0046] Fig.24 The seventeenth embodiment of the present application provides Figure 1 The diagram shows the wiring layout of a local area of ​​the display panel.

[0047] Fig.25 Provided for the eighteenth embodiment of the present application Figure 1 The diagram shows the wiring layout of a local area of ​​the display panel.

[0048] Fig.26 for Figure 1 An enlarged view of a second partial area of ​​the display panel is shown.

[0049] Fig. 27 for Fig.26 An enlarged view of a first partial area of ​​the display panel is shown.

[0050] Fig.28 for Fig.26 An enlarged view of a second partial area of ​​the display panel is shown.

[0051] Fig.29 A schematic diagram of the structure of a display device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0052] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0053] In the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is understood that when a structure is referred to as being "on or under" another structure, the structure may be directly on or under the other structure, or there may be intermediate structures. The same reference numerals always indicate the same structure. The structures mentioned herein include any of a film layer, an element, a device, a component, and an assembly.

[0054] When a structure is referred to as being “connected” to another structure, the structure may be directly connected to the other structure or indirectly connected to the other structure with one or more intervening structures interposed therebetween.

[0055] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0056] In this specification, the term “same-layer arrangement” refers to a structure in which two (or more) structures are formed by the same patterning process, and their materials may be the same or different.

[0057] With the development of OLED display technology, the demand for narrow borders is getting higher and higher. The display area boundary includes an arc-shaped boundary, and the border area includes an arc-angle border area located outside the arc-shaped boundary. The circuit structure in the arc-angle border area is arranged in an arc shape, which occupies a large space, making it impossible for display products to achieve narrow borders.

[0058] In order to further achieve a narrow border, an embodiment of the present application provides a display panel and a display device, which reduces the area occupied by the arc-angle border area by transferring part of the gate driving units in the arc-angle border area to the straight border area, which is conducive to achieving a narrow border.

[0059] Figure 1 A schematic diagram of the top structure of a display panel provided in one embodiment of the present application. Figure 2 The first embodiment provides Figure 1 An enlarged view of a first partial area of ​​the display panel is shown. Figure 2 Shows Figure 1 An enlarged view of the first local area P1 in FIG. Figure 1 and Figure 2 As shown, the display panel has a display area AA and a frame area NA surrounding the display area AA. The frame area NA includes a first frame area L1A, an arc-angle frame area SA, and a second frame area L2A connected in sequence. Exemplarily, the first frame area L1A and the second frame area L2A are both straight frames, and the display area AA includes a first straight boundary L1, an arc-shaped boundary S, and a second straight boundary L2 connected. The first frame area L1A is located outside the first straight boundary L1, the arc-angle frame area SA is located outside the arc-shaped boundary S, and the second frame area L2A is located outside the second straight boundary L2.

[0060] The display panel includes: a first gate driving circuit G1. The first gate driving circuit G1 is located in the border area NA. The first gate driving circuit G1 includes a plurality of first gate driving units G1i, i=1, 2, 3...n, and n is any positive integer. The distance between two adjacent first gate driving units G1i between the second border area L2A and the arc angle border area SA is greater than the distance between two adjacent first gate driving units G1i in the arc angle border area SA.

[0061] Exemplarily, the multiple first gate drive units G1i in the first gate drive circuit G1 are arranged in sequence along the circumference of the display area AA. The arc angle border area SA includes a first sub-area SA1 close to the first border area L1A and a second sub-area SA2 close to the second border area L2A. The first part of the first gate drive unit G1i is located in the first sub-area SA1, and the second part of the first gate drive unit G1i is located in the second border area L2A. The length of the second sub-area SA2 in the circumferential direction of the display area AA is greater than the spacing between adjacent first gate drive units G1i in the second border area L2A and the spacing between adjacent first gate drive units G1i in the first sub-area SA1. It is equivalent to placing the terminal first gate drive units G1i of the first gate drive circuit G1 corresponding to the second sub-area SA2 outside the second border area L2A.

[0062] In this way, the area occupied by the second sub-area SA2 can be reduced, so as to reduce the size of the arc-angle frame area SA, and further facilitate the realization of a narrow frame. At the same time, the display panel provided in this embodiment only places part of the first gate drive circuit G1 of the arc-angle frame area SA outside the second frame area L2A, rather than placing all the first gate drive circuits G1 of the arc-angle frame area SA outside. In comparison, the former can ensure that the space utilization of the frame area NA is more optimized and avoid space waste under the premise of achieving a consistent width at all locations of the frame area NA.

[0063] In one embodiment, Figure 2 As shown, the number of the first gate driving units G1i in the second border area L2A is less than the number of the first gate driving units G1i in the arc angle border area SA.

[0064] In one embodiment, Figure 2 As shown, the third portion of the first gate driving circuit G1 is located in the first border area L1A.

[0065] Figure 3 FIG. 1 is a circuit diagram of a first gate driving circuit in the display panel. Figure 3As shown, a plurality of first gate driving units G1i in the first gate driving circuit G1 are sequentially cascaded and connected in the circumferential direction of the display area AA. The first gate driving circuit G1 can generate a scanning signal and / or a light-emitting signal by receiving a clock signal (e.g., a first clock signal transmitted by the first clock signal line CLK1 and a second clock signal transmitted by the second clock signal line CLK2), a start signal SSP, etc. from a timing controller, and can generate a scanning signal and / or a light-emitting signal by sequentially transmitting the start signal to the next stage circuit under the control of the clock signal. Exemplarily, the first gate driving unit G1i includes a shift register.

[0066] like Figure 2 As shown, the display panel further includes a sub-pixel 20 located in the display area AA. The first gate driving circuit G1 is electrically connected to the sub-pixel 20 to provide the generated scanning signal and / or light emitting signal to the sub-pixel 20.

[0067] Figure 4 A circuit diagram of a sub-pixel provided in an embodiment of the present application. Figure 2 and Figure 4 As shown, the sub-pixel 20 includes an electrically connected pixel circuit 21 and a light-emitting device 22. The pixel circuit is, for example, 7T1C, 8T1C, etc. The light-emitting device 22 can be an organic light-emitting diode (OLED), a micro light-emitting diode (Micro LED), a quantum dot light-emitting diode (QLED), etc. The light-emitting device 22 can be a light-emitting device of various colors, such as a red light-emitting device R, a green light-emitting device G, a blue light-emitting device B, etc.

[0068] Take the 8T1C pixel circuit as an example. Figure 4As shown, the pixel circuit 21 includes eight transistors and 1 capacitor C. The first electrode of the first transistor T1 is connected to the second electrode of the fifth transistor T5, the second electrode of the first transistor T1 is connected to the first electrode of the sixth transistor T6, and the control electrode of the first transistor T1 is connected to the first electrode of the capacitor C. The first electrode of the second transistor T2 is connected to the data line Data, the second electrode of the second transistor T2 is connected to the first electrode of the first transistor T1, and the control electrode of the second transistor T2 is connected to the second scan line S2. The first electrode of the third transistor T3 is connected to the control electrode of the first transistor T1, the second electrode of the third transistor T3 is connected to the second electrode of the first transistor T1, and the control electrode of the third transistor T3 is connected to the third scan line S3. The first electrode of the fourth transistor T4 is connected to the second electrode of the first transistor T1, the second electrode of the fourth transistor T4 is connected to the first initialization signal line Vref1, and the control electrode of the fourth transistor T4 is connected to the first scan line S1. The first electrode of the fifth transistor T5 is connected to the high-voltage power line Elvdd, the second electrode of the fifth transistor T5 is connected to the first electrode of the first transistor T1, and the control electrode of the fifth transistor T5 is connected to the luminous line Em. The first electrode of the sixth transistor T6 is connected to the second electrode of the first transistor T1, the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device 22, and the control electrode of the sixth transistor T6 is connected to the light emitting line Em. The first electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device 22, the second electrode of the seventh transistor T7 is connected to the second initialization signal line Vref2, and the control electrode of the seventh transistor T7 is connected to the fourth scan line S4. The first electrode of the eighth transistor T8 is connected to the second electrode of the first transistor T1, the second electrode of the eighth transistor T8 is connected to the third initialization signal line Vref3, and the control electrode of the eighth transistor T8 is connected to the fourth scan line S4. The second electrode of the capacitor C is connected to the high voltage power line Elvdd. The second electrode of the light emitting device 22 is connected to the low voltage power line Elvss.

[0069] Exemplarily, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are P-type transistors, and the third transistor T3 and the fourth transistor T4 are N-type transistors.

[0070] The first gate driving circuit G1 includes any one of a light emitting driving circuit and a scanning driving circuit.

[0071] In one embodiment, the first gate driving circuit G1 may be a light emitting driving circuit. In this case, the first gate driving circuit G1 is connected to the light emitting line Em to generate a light emitting signal and provide it to the sub-pixel.

[0072] In one embodiment, the first gate driving circuit G1 may be a first scanning driving circuit. The first scanning driving circuit is used to provide a scanning signal to the N-type transistor. Figure 4For the pixel circuit shown, the first gate driving circuit G1 is connected to the first scanning line S1 and the third scanning line S3.

[0073] In one embodiment, the first gate driving circuit G1 may be a second scanning driving circuit. The second scanning driving circuit is used to provide a scanning signal for the P-type transistor. Figure 4 For the pixel circuit shown, the first gate driving circuit G1 is connected to the second scan line S2 and the fourth scan line S4.

[0074] The substrate 10 is a substrate substrate. In some embodiments, the substrate substrate may include an organic resin material such as epoxy resin, triazine, silicone resin or polyimide. For example, the substrate substrate may be a FR4 type printed circuit board (PCB), or may be a flexible PCB that is easily deformed. In some embodiments, the substrate substrate may include a ceramic material such as silicon nitride, aluminum nitride or aluminum oxide, or may include a metal or a metal compound. For example, the substrate substrate may be a metal core printed circuit board (MCPCB) or a metal-base copper-clad laminate (MCCL).

[0075] Figure 5 The second embodiment provides Figure 1 The figure shows an enlarged view of a local area of ​​the display panel. Figure 5 As shown, the display panel and Figure 2 The difference of the display panel shown is that, in this embodiment, the display panel further includes a second gate driving circuit G2, which is located in the frame area NA and on a side of the first gate driving circuit G1 close to or away from the display area AA.

[0076] In one embodiment, the second gate driving circuit G2 includes a plurality of second gate driving units G2j arranged in sequence along the circumference of the display area AA. A first portion of the second gate driving units G2j is located in the second sub-area SA2.

[0077] In one embodiment, the second portion of the second gate driving units G2j is located in the first sub-area SA1.

[0078] In one embodiment, the third portion of the second gate driving units G2j is located in the first border area L1A.

[0079] In one embodiment, the number of the second gate driving units G2j in the second sub-area SA2 is equal to the number of the first gate driving units G1i in the second border area L2A.

[0080] In one embodiment, along the circumference of the display area AA, a plurality of second gate driving units G2j are sequentially connected in cascade.

[0081] In one embodiment, the second gate driving circuit includes any one of a light emitting driving circuit and a scanning driving circuit. Exemplarily, the first gate driving circuit G1 includes a light emitting driving circuit, and the first gate driving circuit G1 is connected to the light emitting line Em. The second gate driving circuit G2 includes a first scanning driving circuit, and the second gate driving circuit G2 is connected to the first scanning line S1 and the third scanning line S3.

[0082] Figure 6 The third embodiment provides Figure 1 The figure shows an enlarged view of a local area of ​​the display panel. Figure 5 As shown, the display panel and Figure 5 The difference between the display panels shown is that, in the present embodiment, in the circumferential direction of the display area AA, the second gate driving unit G2j of the first sub-area SA1 and the second gate driving unit G2j of the second sub-area SA2 are arranged in a staggered manner.

[0083] For example, multiple virtual concentric rings centered at the centroid of the display area AA are located in the frame area NA. The second gate drive unit G2j of the second frame area L2A is located on one concentric ring, and the second gate drive unit G2j of the second sub-area SA2 is located on another concentric ring. It should be noted that the shape of the virtual concentric rings mentioned here is adapted to the edge shape of the display area AA, for example, a rounded rectangle.

[0084] In one embodiment, the plurality of virtual concentric rings include a first concentric ring, a second concentric ring, and a third concentric ring arranged in sequence in a direction away from the display area AA. The second gate driving unit G2j of the first sub-area SA1 is arranged along the first concentric ring, the second gate driving unit G2j of the second sub-area SA2 is arranged along the second concentric ring, and the first gate driving unit G1i of the first sub-area SA1 is arranged along the third concentric ring.

[0085] According to the display panel provided in this embodiment, the second gate driving unit G2j of the first sub-area SA1 and the second gate driving unit G2j of the second sub-area SA2 are staggered in the circumferential direction of the display area AA, which is beneficial to improving the uniformity of the circuit structure.

[0086] Figure 7 The fourth embodiment provides Figure 1 The figure shows an enlarged view of a local area of ​​the display panel. Figure 7 The display panel and Figure 6The difference of the display panel shown is that, in this embodiment, the display panel further includes a third gate driving circuit G3. The third gate driving circuit G3 is located in the frame area NA and is located on the side of the second gate driving circuit G2 close to or away from the first gate driving circuit G1. Exemplarily, in the direction close to the display area AA, the first gate driving circuit G1, the second gate driving circuit G2, and the third gate driving circuit G3 are arranged in sequence.

[0087] In one embodiment, the third gate driving circuit G3 includes a plurality of third gate driving units G3m sequentially arranged along the circumference of the display area AA, and a first portion of the third gate driving units G3m are located in the second sub-area SA2.

[0088] In one embodiment, the second portion of the third gate driving units G3m is located in the first sub-area SA1.

[0089] In one embodiment, the third portion of the third gate driving unit G3m is located in the first border area L1A.

[0090] In one embodiment, the number of the third gate driving units G3 m of the second sub-area SA2 is equal to the number of the first gate driving units G1 i of the second border area L2A.

[0091] In one embodiment, the third gate driving circuit G3 includes any one of a light emitting driving circuit and a scanning driving circuit. Exemplarily, the first gate driving circuit G1 includes a light emitting driving circuit, and the first gate driving circuit G1 is connected to the light emitting line Em. The second gate driving circuit G2 includes a first scanning driving circuit, and the second gate driving circuit G2 is connected to the first scanning line S1 and the third scanning line S3. The third gate driving circuit G3 includes a second scanning driving circuit, and the third gate driving circuit G3 is connected to the second scanning line S2 and the fourth scanning line S4.

[0092] Figure 8 The fifth embodiment provides Figure 1 The figure shows an enlarged view of a local area of ​​the display panel. Figure 8 The display panel and Figure 7 The difference between the display panels shown is that, in the present embodiment, in the circumferential direction of the display area AA, the third gate driving unit G3m of the first sub-area SA1 and the third gate driving unit G3m of the second sub-area SA2 are staggered.

[0093] In one embodiment, a plurality of virtual concentric rings centered at the centroid of the display area AA are located in the frame area NA. The plurality of virtual concentric rings include a fifth concentric ring, a fourth concentric ring, a first concentric ring, a second concentric ring, and a third concentric ring arranged in sequence in a direction away from the display area AA. The second gate drive unit G2j of the second frame area L2A is arranged along the fifth concentric ring, and the second gate drive unit G2j of the second sub-area SA2 is arranged along the fourth concentric ring. The second gate drive unit G2j of the first sub-area SA1 is arranged along the first concentric ring, the second gate drive unit G2j of the second sub-area SA2 is arranged along the second concentric ring, and the first gate drive unit G1i of the first sub-area SA1 is arranged along the third concentric ring.

[0094] Fig. 9 The sixth embodiment provides Figure 1 The figure shows an enlarged view of a local area of ​​the display panel. Fig. 9 The display panel and Figure 7 , Figure 8 The difference between the display panels shown is that, in this embodiment, Figure 8 Taking the display panel shown as an example, the third gate driving unit G3m of the fourth part is located in the second border area L2A, and the sum of the number of the third gate driving unit G3m of the second border area L2A and the third gate driving unit G3m of the second sub-area SA2 is equal to the number of the first gate driving unit G1i of the second border area L2A. In this case, in the direction from the second sub-area SA2 to the second border area L2A, the number of circuit structures gradually decreases, thereby better adapting to the transition from the arc-angle border area SA to the second border area L2A, and further improving the space utilization of the arc-angle border area SA.

[0095] Fig.10 The seventh embodiment provides Figure 1 The figure shows an enlarged view of a local area of ​​the display panel. Fig.10 The display panel and Figure 2 The difference of the display panel shown is that, in the present embodiment, the first gate driving circuit G1 further includes at least one redundant first gate driving unit G10. The difference between the first gate driving unit G1i and the redundant first gate driving unit G10 is that the first gate driving unit G1i is electrically connected to the sub-pixel 20, and the redundant first gate driving unit G10 is not electrically connected to the sub-pixel 20. At least part of the redundant first gate driving unit G10 is located in the second border area L2A and is located on at least one side of the first gate driving unit G1i in the circumferential direction of the display area AA.

[0096] For example, the second border area L2A is provided with a plurality of first gate driving units G1i, and at least one redundant first gate driving unit G10 is provided on a side of the plurality of first gate driving units G1i close to the arc-angle border area SA; and / or, at least one redundant first gate driving unit G10 is provided on a side of the plurality of first gate driving units G1i away from the arc-angle border area SA.

[0097] In one embodiment, the partially redundant first gate driving unit G10 is located in the arc-angle border area SA and is located on a side of the first gate driving unit G1i close to the second border area L2A.

[0098] According to the display panel provided in this embodiment, by setting a redundant first gate driving unit G10, it is ensured that the circuit structures on both sides of any first gate driving unit G1i are consistent, thereby avoiding circuit structure differences caused by inconsistent etching degrees in the process due to inconsistent circuit structures, improving the structural uniformity of the first gate driving unit G1i, and further improving the display effect.

[0099] Fig.11 FIG. 1 is a circuit diagram of a first gate driving circuit provided in another embodiment. Fig.11 As shown, among the plurality of first gate driving units G1i sequentially arranged in the circumferential direction of the display area AA, the previous first gate driving unit G1i and the next first gate driving unit G1i of the redundant first gate driving unit G10 are cascade connected. The redundant first gate driving unit G10 is not connected to the input signal line, such as the first clock signal line CLK1, the second clock signal line CLK2, and the output end of the previous stage. The redundant first gate driving unit G10 is also not connected to the output signal line, such as the scan line, and is thus not electrically connected to the sub-pixel 20.

[0100] Fig.12 The eighth embodiment provides Figure 1 The figure shows an enlarged view of a local area of ​​the display panel. Fig.12 The display panel and Fig.10 The difference of the display panel shown is that, in the present embodiment, the display panel further includes a second gate driving circuit G2. The second gate driving circuit G2 is located on the side of the first gate driving circuit G1 close to or away from the display area AA. The second gate driving circuit G2 includes a plurality of second gate driving units G2j and at least one redundant second gate driving unit G20 arranged in sequence along the circumference of the display area AA. The difference between the redundant second gate driving unit G20 and the second gate driving unit G2j is that the redundant second gate driving unit G20 is not electrically connected to the sub-pixel 20, and the second gate driving unit G2j is electrically connected to the sub-pixel 20. At least one redundant second gate driving unit G20 is located in the arc angle border area SA, and is located on the side of the second gate driving unit G2j close to the second border area L2A.

[0101] According to the display panel provided in this embodiment, by setting a redundant second gate driving unit G20, it is ensured that the circuit structures on both sides of any second gate driving unit G2j are consistent, thereby avoiding circuit structure differences caused by inconsistent etching degrees in the process due to inconsistent circuit structures, improving the structural uniformity of the second gate driving unit G2j, and further improving the display effect.

[0102] Fig.13 The ninth embodiment provides Figure 1 The figure shows an enlarged view of a local area of ​​the display panel. Fig.13 The display panel and Fig.12 The difference between the display panels shown is that, in the present embodiment, in the circumferential direction of the display area AA, the first gate driving unit G1i of the first sub-area SA1 and the first gate driving unit G1i of the second sub-area SA2 are arranged in a staggered manner.

[0103] Fig.14 The tenth embodiment provides Figure 1 The figure shows an enlarged view of a local area of ​​the display panel. Fig.14 The display panel and Fig.12 , Fig.13 The difference between the display panels shown is that, in this embodiment, Fig.13 Taking the display panel shown as an example, the second border area L2A is provided with at least one redundant second gate driving unit G20.

[0104] In one embodiment, in the second border area L2A, the number of the redundant second gate driving units G20 is equal to the sum of the number of the first gate driving units G1i and the redundant first gate driving units G10.

[0105] Fig.15 The eleventh embodiment provided Figure 1 The figure shows an enlarged view of a local area of ​​the display panel. Fig.15 The display panel and Fig.12 The difference of the display panel shown is that, in the present embodiment, the display panel further includes a third gate driving circuit G3. The third gate driving circuit G3 includes a plurality of third gate driving units G3m and at least one redundant third gate driving unit G30 sequentially arranged along the circumference of the display area AA. The difference between the third gate driving unit G3m and the redundant third gate driving unit G30 is that the third gate driving unit G3m is electrically connected to the sub-pixel 20, and the redundant third gate driving unit G30 is not electrically connected to the sub-pixel 20. At least one redundant third gate driving unit G30 is located in the arc angle border area SA, and is located on the side of the third gate driving unit G3m close to the second border area L2A.

[0106] In one embodiment, in the arc angle border area SA, the number of the second gate driving units G2j and the number of the third gate driving units G3m are equal, and the number of the redundant second gate driving units G20 and the number of the redundant third gate driving units G30 are equal.

[0107] Fig.16 The twelfth embodiment provided Figure 1 The figure shows an enlarged view of a local area of ​​the display panel. Fig.16 The display panel and Fig.15 The difference of the display panel shown is that, in this embodiment, the sum of the number of the second gate driving units G2j in the arc angle border area SA and the second gate driving units G2j in the second border area L2A is equal to the number of the third gate driving units G3m in the arc angle border area SA.

[0108] Fig.17 The thirteenth embodiment provided Figure 1 The figure shows an enlarged view of a local area of ​​the display panel. Fig.17 The display panel and Fig.15 , Fig.16 The difference between the display panels shown is that, in this embodiment, Fig.16 Taking the display panel shown in FIG. 1 as an example, in the circumferential direction of the display area AA, the third gate driving unit G3m of the first sub-area SA1 and the third gate driving unit G3m of the second sub-area SA2 are arranged in a staggered manner.

[0109] Fig.18 The fourteenth embodiment provided Figure 1 The figure shows an enlarged view of a local area of ​​the display panel. Fig.18 The display panel and Figure 15-17 The difference between the display panel shown in any of the embodiments is that, in this embodiment, Fig.17 Taking the display panel shown as an example, in the second border area L2A, the sum of the number of the first gate driving units G1i and the redundant first gate driving units G10, the sum of the number of the second gate driving units G2j and the redundant second gate driving units G20, and the number of the redundant third gate driving units G30 are equal.

[0110] Fig.19 The fifteenth embodiment of the present application provides Figure 1 The wiring layout of a local area of ​​the display panel is shown in FIG. Fig.19As shown, the display panel also includes a first gate line 31 and a gate connection line 40. The first gate line 31 is located in the display area AA, and the gate connection line 40 connects the first gate line 31 and the first gate driving unit G1i of the second frame area L2A. The gate connection line 40 includes a first sub-connection line 41, and the portion of the first sub-connection line 41 located in the display area AA extends in the same direction as the first gate line 31, and the orthographic projection of the first sub-connection line 41 on the substrate 10 is located between the orthographic projection of the first gate line 30 on the substrate 10 and the orthographic projection of the first gate driving unit G1i on the substrate 10. The portion of the first sub-connection line 41 located in the frame area NA is electrically connected to the first gate line 31 through at least one line change hole O.

[0111] In one embodiment, the gate connection line 40 further includes a second sub-connection line 42, which is electrically connected to an end of the first sub-connection line 41 away from the first gate line 31; the extension directions of the second sub-connection line 42 and the first sub-connection line 41 intersect. Exemplarily, the extension directions of the second sub-connection line 42 and the first sub-connection line 41 are perpendicular.

[0112] Fig. 20 for Fig.19 An enlarged view of the first sub-partial area of ​​the display panel is shown. Fig.21 for Fig.19 An enlarged view of a second sub-partial area of ​​the display panel is shown. Fig. 20 An enlarged view of the first sub-local area P11 is shown. Fig.21 FIG. 2 shows an enlarged view of the second sub-region P12. Fig.19 , Fig. 20 and Fig.21 As shown, the display panel also includes a second gate line 32 and a third gate line 33 located in the display area AA, and the first sub-connection line 41 is located in the display area AA, and the orthographic projections of the second gate line 32, the first gate line 31 and the third gate line 33 on the substrate 10 are arranged in sequence.

[0113] In one embodiment, the first gate line 31 includes a light emitting signal line Em, the second gate line 32 includes a fourth scan line S4, and the third gate line 33 includes a second scan line S2.

[0114] In one embodiment, the first gate line 31, the second gate line 32 and the third gate line 33 are arranged in the same layer. For example, the display panel includes a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer stacked in sequence in a direction away from the substrate 10. The first gate line 31, the second gate line 32 and the third gate line 33 are all located in the first metal layer.

[0115] In one embodiment, the first sub-connection line 41 and the first gate line 31 are disposed in different layers. Continuing with the above example, the first sub-connection line 41 is located in the fourth metal layer.

[0116] In one embodiment, the display panel further includes a second initialization signal line Vref2, and at least a portion of the second initialization signal line Vref2 is colinear with the first sub-connection line 41. The second initialization signal line Vref2 and the first sub-connection line 41 are colinear, which means that the second initialization signal line Vref2 and the first sub-connection line 41 are located in the same metal layer, and the two are located in the same straight line. Continuing with the above example, when the first sub-connection line 41 is located in the fourth metal layer, at least a portion of the second initialization signal line Vref2 is also located in the fourth metal layer.

[0117] In one embodiment, the display panel further includes a shielding line, which is located on the side of the first sub-connection line 41 close to the substrate 10. The orthographic projection of the first sub-connection line 41 on the substrate 10 and the orthographic projection of the shielding line on the substrate 10 at least partially overlap. Exemplarily, the shielding line includes part of the first initialization signal line Vref1, that is, part of the first initialization signal line Vref1 is used as a shielding line. Continuing with the above example, the shielding line is located in the third metal layer. Another part of the first initialization signal line Vref1 is located in the first metal layer, and the first initialization signal line Vref1 of the first metal layer and the first initialization signal line Vref1 of the third metal layer multiplexed as a shielding line cross in a mesh shape. The shielding line can shield the interference between the first sub-connection line 41 and the signal lines in the first metal layer and the second metal layer.

[0118] In one embodiment, the second sub-connection line 42 is disposed in a different layer from the first gate line 31. Continuing from the above example, the second sub-connection line 42 is located in the fifth metal layer.

[0119] In one embodiment, the display panel further includes a low-voltage power line Elvss, and at least a portion of the low-voltage power line Elvss is co-linear with the second sub-connection line 42. The co-linearity of the low-voltage power line Elvss and the second sub-connection line 42 means that the low-voltage power line Elvss and the second sub-connection line 42 are located in the same metal layer, and the two are located in the same straight line. Continuing with the above example, when the second sub-connection line 42 is located in the fifth metal layer, at least a portion of the low-voltage power line Elvss is also located in the fifth metal layer.

[0120] In one embodiment, the display panel further includes a plurality of data lines Data, and the second sub-connection lines 42 are located between adjacent data lines Data. Continuing with the above example, the data lines Data are also located in the fifth metal layer.

[0121] In one embodiment, the display panel further includes a high-voltage power line Elvdd, and at least part of the high-voltage power line Elvdd is located between adjacent data lines Data. The part of the high-voltage power line Elvdd and the second sub-connection line 42 are alternately arranged. Following the above example, at least part of the high-voltage power line Elvdd is located in the fifth metal layer. In one embodiment, part of the high-voltage power line Elvdd is also located in the fourth metal layer, and the high-voltage power line Elvdd of the fourth metal layer and the high-voltage power line Elvdd of the fifth metal layer cross in a mesh shape.

[0122] In one embodiment, the second sub-connection lines of adjacent odd-numbered bits and adjacent even-numbered bits are connected to the same first gate driving unit G1i.

[0123] In one embodiment, Fig.21 As shown, the first sub-connection line 41 is connected to the first gate line 31 through three conductive vias O. Exemplarily, the first gate line 31 is located in the first metal layer, and the first sub-connection line 41 is located in the fourth metal layer. The three conductive vias O include a first conductive via O1, a second conductive via O2, and a third conductive via O3. The first sub-connection line 41 switches to the third metal layer through the first conductive via O1, switches to the second metal layer through the second conductive via O2, switches to the first metal layer through the third conductive via O3, and is electrically connected to the first gate line 31 in the first metal layer.

[0124] Fig. 22 for Fig.19 An enlarged view of the third sub-partial area of ​​the display panel is shown. Fig. 22 An enlarged view of the third sub-region P13 is shown. Fig.19 and Fig. 22 As shown, the first gate driving circuit G1 further includes a plurality of signal lines 50, and the signal lines 50 are connected to the first gate driving unit G1i. The plurality of signal lines include external input signal lines and cascade signal lines between adjacent first gate driving units G1i. The orthographic projections of the plurality of signal lines on the substrate 10 and the orthographic projections of the second gate driving unit G2j of the second sub-area SA2 and / or the third gate driving unit G3m of the second sub-area SA2 on the substrate 10 do not overlap. That is, the signal lines 50 avoid the circuit structure of the second sub-area SA2.

[0125] In one embodiment, the plurality of signal lines 50 include a plurality of clock signal lines CLK. The display panel further includes a low-voltage power supply line 60, which is located on the side of the clock signal line CLK away from the substrate 10. The low-voltage power supply line 60 is electrically connected to the low-voltage power supply line Elvss of the display area AA. The low-voltage power supply line 60 includes a plurality of vias H, and the orthographic projections of different clock signal lines CLK on the substrate 10 overlap with the orthographic projections of the vias H on the substrate 10 in the same area.

[0126] An organic layer is provided between the clock signal line CLK and the low voltage power supply line 60, and water vapor in the organic layer can be released by providing a via H. At the same time, by setting the overlap area of ​​the orthographic projection of different clock signal lines CLK on the substrate 10 and the orthographic projection of the via H on the substrate 10 to be the same, it can be ensured that the loads on different clock signal lines CLK are consistent.

[0127] Fig.23 The sixteenth embodiment of the present application provides Figure 1 The wiring layout of a local area of ​​the display panel is shown in FIG. Fig.23 As shown, in this embodiment, the first end D1 of the first sub-connection line 41 is located in the display area AA and corresponds to the sub-pixel 20, and the orthographic projection of the first end D1 on the substrate overlaps with the orthographic projection of the corresponding sub-pixel 20 on the substrate. The sub-pixels 20 corresponding to the first end D1 of the adjacent first sub-connection line 41 are located in adjacent rows and adjacent columns. And / or, the second sub-connection line 42 is located in the display area AA and corresponds to the sub-pixel 20, and the orthographic projection of the second end D2 on the substrate overlaps with the orthographic projection of the corresponding sub-pixel 20 on the substrate. The sub-pixels 20 corresponding to the second end D2 of the adjacent second sub-connection line 42 are located in adjacent rows and adjacent columns.

[0128] In one embodiment, the first gate driving unit G1i is connected to two adjacent second sub-connection lines 42 .

[0129] Fig.24 The seventeenth embodiment of the present application provides Figure 1 The wiring layout of a local area of ​​the display panel is shown in FIG. Fig.24 As shown, in this embodiment, the orthographic projection of the first sub-connection line 41 on the substrate passes through the orthographic projection of at least one sub-pixel 20. The number of sub-pixels 20 passed through by the orthographic projections of at least some of the first sub-connection lines 41 is equal.

[0130] In one embodiment, the orthographic projections of at least some of the adjacent odd-numbered and even-numbered first sub-connection lines 41 pass through an equal number of sub-pixels 20. For example, the orthographic projections of the adjacent odd-numbered first sub-connection lines 41 and the adjacent even-numbered first sub-connection lines 41 connected to the same first gate driving unit G1i pass through an equal number of sub-pixels 20.

[0131] According to the display panel provided in this embodiment, by setting the number of orthographic projections of sub-pixels 20 through which the orthographic projections of at least some of the first sub-connection lines 41 pass to be equal, a capacitance balancing effect can be achieved, so that the loads on different first sub-connection lines 41 remain consistent, thereby improving the display effect.

[0132] Fig.25 Provided for the eighteenth embodiment of the present application Figure 1The wiring layout of a local area of ​​the display panel is shown in FIG. Fig.25 In the display panel shown, in this embodiment, the orthographic projection of the second sub-connection line 42 on the substrate passes through the orthographic projection of at least one sub-pixel 20. The number of sub-pixels 20 passed by the orthographic projections of at least part of the second sub-connection line 42 is equal.

[0133] In one embodiment, the orthographic projections of at least some of the adjacent odd-numbered and even-numbered second sub-connection lines 42 pass through an equal number of sub-pixels 20. For example, the orthographic projections of the adjacent odd-numbered second sub-connection lines 42 and the even-numbered second sub-connection lines 42 connected to the same first gate driving unit G1i pass through an equal number of sub-pixels 20.

[0134] According to the display panel provided in this embodiment, by setting the number of orthographic projections of sub-pixels 20 through which the orthographic projections of at least some of the second sub-connection lines 42 pass to be equal, a capacitance balancing effect can be achieved, so that the loads on different second sub-connection lines 42 remain consistent, thereby improving the display effect.

[0135] The arc-angle frame area SA mentioned in the display panel provided in any of the above embodiments is applicable to any arc-angle frame area SA of the display panel. For example, for a rounded rectangular display panel, the structure of the arc-angle frame area SA is applicable to any of the four arc-angle frame areas. For the lower arc-angle frame area SA, due to the proximity to the pad area, there is a different design in the circuit structure. The unique structure of the arc-angle frame area SA adjacent to the pad area is specifically described below.

[0136] Fig.26 for Figure 1 An enlarged view of a second partial area of ​​the display panel is shown. Fig.26 Shows Figure 1 An enlarged view of the second local area P2 in FIG. Fig. 27 for Fig.26 An enlarged view of the fourth sub-partial area of ​​the display panel is shown. Fig.28 for Fig.26 An enlarged view of the fifth sub-partial area of ​​the display panel is shown. Fig. 27 An enlarged view of the fourth sub-local area P21 is shown. Fig.28 An enlarged view of the fifth sub-partial region P22 is shown.

[0137] Combination Figure 1 , Figure 26-Figure 28As shown, the display panel also has a bonding area BA, and the bonding area BA is located on the side of the frame area NA away from the display area AA. The first gate drive circuit G1 also includes a plurality of signal lines 50, and the signal lines 50 are connected to the first gate drive unit G1i. The plurality of signal lines include an input signal line IL and a cascade signal line between adjacent first gate drive units G1i. At least part of the input signal line IL includes a first sub-input line IL1, a second sub-input line IL2, and a third sub-input line IL3. The first sub-input line IL1 extends from the bonding area BA to the second sub-area SA2, the second sub-input line IL2 connects one end of the first sub-input line IL1 located in the second sub-area SA2 and the first gate drive unit G1i of the first sub-area SA1, and the third sub-input line IL3 connects one end of the first sub-input line IL1 located in the second sub-area SA2 and the first gate drive unit G1i of the first frame area L1A.

[0138] In one embodiment, the orthographic projection of the third sub-input line IL3 on the substrate 10 and the orthographic projection of the first sub-input line IL1 on the substrate 10 at least partially do not overlap. In this way, signal interference can be avoided.

[0139] In one embodiment, the width of the arc angle frame area SA is greater than or equal to 700 micrometers and less than or equal to 1000 micrometers. Exemplarily, the width of the arc angle frame area SA is 800 micrometers, 850 micrometers, 900 micrometers, 950 micrometers, etc.

[0140] In one embodiment, the width of the border area NA is equal at different positions. Exemplarily, the width of the first border area L1A is consistent at all positions, the width of the arc angle border area SA is consistent at all positions, and the width of the second border area L2A is consistent at all positions. The first border area L1A, the arc angle border area SA, and the second border area L2A are equal in width.

[0141] The present application also provides another display panel. Figure 1 ,as well as Figure 10-Figure 28 The display panel shown in any embodiment of the present invention comprises a display area AA and a frame area NA surrounding the display area AA, the frame area NA comprises a first frame area and a second frame area, and the first frame area and the second frame area are arranged at intervals.

[0142] Exemplarily, the first border area includes Figure 10-Figure 28 The second border area L2A shown includes Figure 1-Figure 25 The arc-angle frame area SA is shown. It should be noted that the first frame area and the second frame area can also be two areas set at any interval in the frame area NA.

[0143] The display panel includes a first gate driving circuit G1. The first gate driving circuit G1 is located in the border area NA. The first gate driving circuit G1 includes a plurality of first gate driving units G1i and at least one redundant first gate driving unit G10, and at least part of the redundant first gate driving unit G10 is arranged on at least one side of the first gate driving unit G1i in the first border area. Similarly, the second border area and the arc corner border area can also be designed in this way.

[0144] The present application also provides a display device. Fig.29 This is a schematic diagram of the structure of a display device provided in one embodiment of the present application. Fig.29 As shown, the display device includes the display panel 100 provided by any of the above embodiments.

[0145] A display device is a product with an image display function. For example, a display device can be used to display static images, such as pictures or photos. A display device can also be used to display dynamic images, such as videos.

[0146] The display device can be a laptop computer, a mobile phone, a handheld or portable computer, a camera, a camcorder, a vehicle-mounted intelligent central control screen, a calculator, a smart watch, a GPS navigator, an electronic photo, an electronic billboard or sign, a projector, etc.

[0147] In addition, the display device may also have functions such as taking photos, recording videos, fingerprint recognition, and face recognition. Accordingly, the display device also includes at least one functional module for realizing the above functions, such as an under-screen camera, an under-screen fingerprint recognition sensor, and the like.

[0148] The basic principles of the present application are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present application. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, not for limitation, and the above details do not limit the present application to being implemented by adopting the above specific details.

[0149] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present application to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A display panel, characterized in that: A display panel having a display area and a frame area at least partially surrounding the display area, wherein the frame area includes a first frame area, an arc-angle frame area, and a second frame area connected in sequence, and the display panel includes: A first gate driving circuit is located in the border area; the first gate driving circuit includes multiple first gate driving units, and the distance between two adjacent first gate driving units in the second border area and the arc angle border area is greater than the distance between two adjacent first gate driving units in the arc angle border area.

2. The display panel according to claim 1, characterized in that: The first border area and the second border area both include straight borders; Preferably, the number of the first gate driving units in the second border area is less than the number of the first gate driving units in the arc-angle border area; Preferably, along the circumference of the display area, a plurality of the first gate driving units are sequentially cascade-connected; Preferably, the first gate driving circuit includes any one of a light emitting driving circuit and a scanning driving circuit.

3. The display panel according to claim 1 or 2, characterized in that: Also included is a second gate driving circuit, the second gate driving circuit is located in the frame area and located on a side of the first gate driving circuit close to or away from the display area; Preferably, the second gate driving circuit comprises a plurality of second gate driving units sequentially arranged along the circumference of the display area; Preferably, the arc-angle frame area includes a first sub-area close to the first frame area and a second sub-area close to the second frame area; in the circumferential direction of the display area, the second gate driving unit of the first sub-area and the second gate driving unit of the second sub-area are staggeredly arranged; Preferably, the number of the second gate driving units in the second sub-area is equal to the number of the first gate driving units in the second border area; Preferably, along the circumference of the display area, a plurality of the second gate driving units are sequentially cascade-connected; Preferably, the second gate driving circuit includes any one of a light emitting driving circuit and a scanning driving circuit; Preferably, the second gate driving circuit includes a first scanning driving circuit.

4. The display panel according to claim 3, characterized in that: Also included is a third gate driving circuit, the third gate driving circuit is located in the border area and located on a side of the second gate driving circuit away from the first gate driving circuit; Preferably, the third gate driving circuit comprises a plurality of third gate driving units sequentially arranged along the circumference of the display area; Preferably, the arc-angle frame area includes a first sub-area close to the first frame area and a second sub-area close to the second frame area; in the circumferential direction of the display area, the third gate driving unit of the first sub-area and the third gate driving unit of the second sub-area are staggeredly arranged; Preferably, the number of the third gate driving units in the second sub-area is equal to the number of the first gate driving units in the second border area; or, The sum of the number of the third gate driving units in the second border area and the number of the third gate driving units in the second sub-area is equal to the number of the first gate driving units in the second border area; Preferably, along the circumference of the display area, a plurality of the third gate driving units are sequentially cascade-connected; Preferably, the third gate driving circuit includes any one of a light emitting driving circuit and a scanning driving circuit; Preferably, the third gate driving circuit includes a second scanning driving circuit.

5. The display panel according to claim 1, characterized in that: The first gate driving circuit further includes at least one redundant first gate driving unit; the display panel further includes a sub-pixel located in the display area, the first gate driving unit is electrically connected to the sub-pixel, and the redundant first gate driving unit is not electrically connected to the sub-pixel; at least part of the redundant first gate driving unit is located in the second border area and is located on at least one side of the first gate driving unit in the circumferential direction of the display area; Preferably, part of the redundant first gate driving units are located in the arc-angle border area, and are located on a side of the first gate driving unit close to the second border area.

6. The display panel according to claim 5, characterized in that: It also includes a second gate driving circuit, which is located at a side of the first gate driving circuit close to or far from the display area; the second gate driving circuit includes a plurality of second gate driving units and at least one redundant second gate driving unit arranged in sequence along the circumference of the display area, the second gate driving unit is electrically connected to the sub-pixel, and the redundant second gate driving unit is not electrically connected to the sub-pixel; at least one of the redundant second gate driving units is located in the arc angle border area, and is located at a side of the second gate driving unit close to the second border area; Preferably, the arc-angle frame area includes a first sub-area close to the first frame area and a second sub-area close to the second frame area; in the circumferential direction of the display area, the second gate driving unit of the first sub-area and the second gate driving unit of the second sub-area are staggeredly arranged; Preferably, the second border area is provided with at least one redundant second gate driving unit; Preferably, in the second border area, the number of the redundant second gate driving units is equal to the sum of the number of the first gate driving units and the redundant first gate driving units.

7. The display panel according to claim 6, characterized in that: It also includes a third gate driving circuit, which is located on a side of the second gate driving circuit close to or far from the first gate driving circuit; the third gate driving circuit includes a plurality of third gate driving units and at least one redundant third gate driving unit arranged in sequence along the circumference of the display area; the redundant third gate driving unit is not electrically connected to the sub-pixel, and the third gate driving unit is electrically connected to the sub-pixel; at least one of the redundant third gate driving units is located in the arc angle frame area, and is located on a side of the third gate driving unit close to the second frame area; Preferably, in the arc-angle border area, the number of the second gate driving units is equal to the number of the third gate driving units; or The sum of the number of the second gate driving units in the arc-angle border area and the number of the second gate driving units in the second border area is equal to the number of the third gate driving units in the arc-angle border area; Preferably, the arc-angle frame area includes a first sub-area close to the first frame area and a second sub-area close to the second frame area; in the circumferential direction of the display area, the third gate driving unit of the first sub-area and the third gate driving unit of the second sub-area are staggeredly arranged; Preferably, in the second border area, the sum of the number of the first gate driving units and the redundant first gate driving units, the sum of the number of the second gate driving units and the redundant second gate driving units, and the number of the redundant third gate driving units are equal.

8. The display panel according to claim 1, characterized in that: It also includes a first gate line and a gate connection line; the first gate line is located in the display area, the gate connection line connects the first gate line and the first gate driving unit in the second frame area; the gate connection line includes a first sub-connection line, a portion of the first sub-connection line located in the display area extends in the same direction as the first gate line, and an orthographic projection of the first sub-connection line on the substrate is located between an orthographic projection of the first gate line on the substrate and an orthographic projection of the first gate driving unit on the substrate; Preferably, the portion of the first sub-connection line located in the frame area is electrically connected to the first gate line through at least one line-changing hole; Preferably, the display panel further comprises a second gate line and a third gate line located in the display area, and the orthographic projections of the portion of the first sub-connection line located in the display area, the second gate line, the first gate line, and the third gate line on the substrate are arranged in sequence; Preferably, the first gate line, the second gate line and the third gate line are arranged in the same layer; Preferably, the first sub-connection line and the first gate line are arranged in different layers; Preferably, the display panel further comprises second initialization signal lines, and at least a portion of the second initialization signal lines and the first sub-connection lines are co-linear; Preferably, the first gate line includes a light emitting line, the second gate line includes a fourth scanning line, and the third gate line includes a second scanning line.

9. The display panel according to claim 8, characterized in that: The display panel further includes a shielding line located on a side of the first sub-connecting line close to the substrate; an orthographic projection of the first sub-connecting line on the substrate and an orthographic projection of the shielding line on the substrate at least partially overlap; Preferably, the shielding line is multiplexed as a first initialization signal line.

10. The display panel according to claim 8 or 9, characterized in that: The first end of the first sub-connection line is located in the display area and corresponds to a sub-pixel, the orthographic projection of the first end on the substrate overlaps with the orthographic projection of the corresponding sub-pixel on the substrate, and the sub-pixels corresponding to the first ends of adjacent first sub-connection lines are located in adjacent rows and adjacent columns; or, The orthographic projection of the first sub-connection line on the substrate passes through the orthographic projection of at least one of the sub-pixels on the substrate; The orthographic projections of at least some of the first sub-connection lines pass through an equal number of orthographic projections of the sub-pixels; Preferably, the number of the sub-pixels through which the orthogonal projections of at least some of the adjacent odd-numbered bits and even-numbered bits of the first sub-connection lines pass is equal.

11. The display panel according to claim 8, characterized in that: The gate connection line further includes a second sub-connection line, the second sub-connection line is electrically connected to an end of the first sub-connection line away from the first gate line; and the extension directions of the second sub-connection line and the first sub-connection line intersect; Preferably, one end of the second sub-connection line away from the first sub-connection line is electrically connected to the first gate driving unit; Preferably, the second sub-connection line and the first sub-connection line are arranged in different layers; Preferably, the second sub-connection line and the first gate line are arranged in different layers; Preferably, the display panel further comprises a low-voltage power line, and at least part of the low-voltage power line and the second sub-connection line are co-linear; Preferably, the display panel further comprises a plurality of data lines, and the second sub-connection lines are located between adjacent data lines; Preferably, the second sub-connection lines of adjacent odd-numbered bits and adjacent even-numbered bits are connected to the same first gate driving unit.

12. The display panel according to claim 11, characterized in that: The second sub-connection line is located at a second end of the display area and corresponds to a sub-pixel, an orthographic projection of the second end on the substrate overlaps with an orthographic projection of the corresponding sub-pixel on the substrate, and the sub-pixels corresponding to adjacent second sub-connection lines are located in adjacent rows and adjacent columns; or, The orthographic projection of the second sub-connection line on the substrate passes through the orthographic projection of at least one sub-pixel on the substrate; the orthographic projections of at least some of the second sub-connection lines pass through an equal number of sub-pixels; Preferably, the number of the sub-pixels through which the orthogonal projections of at least some of the adjacent odd-numbered bits and even-numbered bits of the second sub-connection lines pass is equal.

13. The display panel according to claim 1, characterized in that: The arc-angle border area includes a first sub-area close to the first border area and a second sub-area close to the second border area, and the first gate driving units of the arc-angle border area are all located in the first sub-area; Preferably, the display panel further includes a second gate driving circuit and a third gate driving circuit, and part of the second gate driving circuit and part of the third gate driving circuit are located in the second sub-area; The first gate driving circuit further comprises a plurality of signal lines, the signal lines being connected to the first gate driving unit; the orthographic projections of the signal lines on the substrate do not overlap with the orthographic projections of the second gate driving circuit and the third gate driving circuit of the second sub-area on the substrate; Preferably, the plurality of signal lines include a plurality of clock signal lines; the display panel also includes a low-voltage power supply line, and the low-voltage power supply line is located on the side of the clock signal line away from the substrate; the pressure power supply line includes a plurality of vias, and the overlapping areas of the orthographic projections of different clock signal lines on the substrate and the orthographic projections of the multiple holes on the substrate are the same.

14. The display panel according to claim 1, characterized in that: The first gate driving circuit further comprises a bonding area, wherein the bonding area is located on a side of the frame area away from the display area; the first gate driving circuit further comprises a plurality of signal lines, wherein the signal lines comprise input signal lines, wherein the input signal lines comprise a first sub-input line, a second sub-input line and a third sub-input line; the first sub-input line extends from the bonding area to the second sub-area, the second sub-input line connects one end of the first sub-input line located in the second sub-area and the first gate driving unit in the first sub-area, and the third sub-input line connects one end of the first sub-input line located in the second sub-area and the first gate driving unit in the first frame area; Preferably, an orthographic projection of the third sub-input line on the substrate and an orthographic projection of the first sub-input line on the substrate at least partially do not overlap.

15. The display panel according to claim 1, characterized in that: The width of the border area at different positions is equal.

16. A display panel, characterized in that: A display panel having a display area and a frame area at least partially surrounding the display area, wherein the frame area includes a first frame area and a second frame area, and the first frame area and the second frame area are arranged at intervals; the display panel comprises: A first gate driving circuit is located in the border area; the first gate driving circuit includes a plurality of first gate driving units and at least one redundant first gate driving unit; at least part of the redundant first gate driving units are arranged on at least one side of the first gate driving unit in the first border area; and The sub-pixel is located in the display area; the redundant first gate driving unit is not electrically connected to the sub-pixel, and the first gate driving unit is electrically connected to the sub-pixel.

17. The display panel according to claim 16, characterized in that: The redundant first gate driving unit is disposed on at least one side of the first gate driving unit in the second border area; Preferably, the first border area and the second border area are connected via an arc-angle border area; Preferably, the redundant first gate driving unit is arranged on at least one side of the first gate driving unit in the arc-angle border area.

18. A display device, characterized in that: A display panel comprising any one of claims 1-17.

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