Gate drive circuit

Abstract

The invention relates to a gate drive circuit, which comprises a plurality of cascaded gate drive units, and is characterized in that the Nth gate drive unit comprises a pull-up transistor, an input module, a pull-down module, a boost module and a third transistor, and the input module is connected with a pull-up node and charges the pull-up node; the pull-down module is connected with the pull-up node, the reverse node and a low potential line, and pulls down the potential of the pull-up node to a low level; the boost module is connected with the reverse node and pulls up the potential of the reverse node to a high level; the first electrode of the third transistor is connected with the reverse node, the second electrode is connected with the low potential line, and the grid electrode is connected with the N-4 level pull-up signal. By adding the third transistor and the fourth transistor, the potential of the reverse node can be pulled down before the pre-charging stage of the pull-up node, the effect of the pre-charging stage can be effectively improved, the pre-charging time of the pull-up node and the pre-charged voltage are both higher than those of an original circuit, and therefore the working capacity at the low temperature is enhanced.

Description

Technical Field

[0001] The present invention relates to the technical field of drive circuits, and in particular to a gate drive circuit. Background Art

[0002] The gate driving circuit is used to provide corresponding scanning signals to each scanning line, and includes a plurality of gate driving units. The pull-up node of each gate driving unit requires corresponding potentials at different stages to achieve the required functions.

[0003] The 8T1C circuit currently used in the market does not perform well at low temperatures. The reverse node drop is reduced during the pre-charge phase, and the pull-up node rise time is prolonged. This circuit attenuates as the temperature decreases and the number of transfer levels increases. The pre-charge time of the pull-up node will become shorter and shorter, resulting in the pull-up node being unable to charge to a higher potential and unable to maintain it, ultimately leading to failure to transmit normally.

[0004] Therefore, it is necessary to provide a gate drive circuit that can effectively improve the effect of the pre-charge stage and enhance the ability to work at low temperatures. Summary of the invention

[0005] In order to overcome the deficiencies of the prior art, the present invention provides a gate driving circuit.

[0006] The technical solution of the present invention is as follows:

[0007] A gate driving circuit includes a plurality of cascaded gate driving units, wherein the Nth gate driving unit includes:

[0008] A pull-up transistor, wherein a first electrode of the pull-up transistor is connected to the first clock signal line, a second electrode of the pull-up transistor is connected to the Nth level scan line, and a gate of the pull-up transistor is connected to the pull-up node;

[0009] an input module, the input module being connected to the pull-up node and charging the pull-up node;

[0010] A pull-down module, wherein the pull-down module is connected to the pull-up node, the reverse node, and the low potential line respectively, and the pull-down module is started after the potential of the reverse node rises, and the pull-down module pulls the potential of the pull-up node down to a low level;

[0011] A boost module, the boost module is connected to the reverse node, and the boost module pulls up the potential of the reverse node to a high level according to a boost start signal;

[0012] A third transistor, wherein a first electrode of the third transistor is connected to the reverse node, a second electrode of the third transistor is connected to the low potential line, and a gate of the third transistor is connected to the N-4th level pull-up signal.

[0013] As a further improvement of the present invention, the pull-down module includes a first transistor, a first electrode of the first transistor is connected to the pull-up node, a second electrode of the first transistor is connected to the low potential line, and a gate of the first transistor is connected to the reverse node.

[0014] As a further improvement of the present invention, the boost module includes a second transistor and a first high potential line, the first electrode of the second transistor is connected to the first high potential line, the second electrode of the second transistor is connected to the reverse node, the gate of the second transistor is connected to the first control line, and the first control line is connected to the first clock signal line.

[0015] As a further improvement of the present invention, the Nth level gate driving unit further includes a fourth transistor, the first electrode of the fourth transistor is connected to the reverse node, the second electrode of the fourth transistor is connected to the low potential line, and the gate of the fourth transistor is connected to the N+4th level pull-up signal. As a further improvement of the present invention, the input module includes a fifth transistor and a sixth transistor, the first electrode of the fifth transistor is connected to the second high potential line, the second electrode of the fifth transistor is connected to the pull-up node, and the gate of the fifth transistor is connected to the second control line; the first electrode of the sixth transistor is connected to the low potential line, the second electrode of the sixth transistor is connected to the pull-up node, and the gate of the sixth transistor is connected to the third control line.

[0016] As a further improvement of the present invention, the second control line transmits the N-4th level scanning signal; and the third control line transmits the N+4th level scanning signal.

[0017] As a further improvement of the present invention, the Nth level gate driving unit also includes a seventh transistor, a first electrode of the seventh transistor is connected to the reverse node, a second electrode of the seventh transistor is connected to the low potential line, and a gate of the seventh transistor is connected to the pull-up node.

[0018] As a further improvement of the present invention, the N-th level gate driving unit also includes an eighth transistor, the first electrode of the eighth transistor is connected to the N-th level scan line, the second electrode of the eighth transistor is connected to the low potential line, and the gate of the eighth transistor is connected to the reverse node.

[0019] As a further improvement of the present invention, the Nth-level gate driving unit also includes a ninth transistor, a first electrode of the ninth transistor is connected to the Nth-level scan line, a second electrode of the ninth transistor is connected to the low-potential line, and a gate of the ninth transistor is connected to the second clock signal line.

[0020] As a further improvement of the present invention, the phase of the signal transmitted by the first clock signal line is opposite to that of the signal transmitted by the second clock signal line.

[0021] According to the present invention of the above scheme, the beneficial effects of the present invention are:

[0022] The present invention provides a gate drive circuit, which can achieve the potential of the reverse node being pulled down before the pre-charging stage of the pull-up node by adding a third transistor and a fourth transistor, and can effectively improve the effect of the pre-charging stage. The pre-charging time of the pull-up node and the pre-charged voltage are both higher than those of the original circuit, thereby enhancing the working ability at low temperatures. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of the circuit structure of an existing gate driving unit;

[0024] Figure 2 It is a potential change curve diagram of an existing gate drive unit;

[0025] Figure 3 It is a schematic diagram of the structure of the present invention;

[0026] Figure 4 The potential change curve of the present invention is Figure 1 ;

[0027] Figure 5 The potential change curve of the present invention is Figure 2 . DETAILED DESCRIPTION

[0028] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0030] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances. In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0031] See also Figure 1 and Figure 2 , Figure 1 It is a schematic diagram of the circuit structure of an existing gate driving unit; Figure 2 yes Figure 1 The potential change curve diagram of the gate driving unit shown in the figure, wherein the first curve is the potential change curve of the pull-up node Q at 27°C, the second curve is the potential change curve of the reverse node QB at 27°C, the third curve is the potential change curve of the pull-up node Q at 0°C, the second curve is the potential change curve of the reverse node QB at 0°C, Figure 1 The gate drive circuit shown has the following problems:

[0032] Figure 2 After the potential of the pull-up node Q shown in the figure increases, the potential of the reverse node QB begins to decrease. When the temperature is 27°C, the pre-charge time of the pull-up node Q is 35.67us, and the pre-charge voltage is 24.296V. ​​When the temperature is 0°C, the pre-charge time of the pull-up node Q is 34.702us, and the pre-charge voltage is 22.214V. The expected pre-charge effect cannot be achieved. However, this circuit attenuation will decrease with the decrease of temperature and the increase of the number of transmission levels, and the pre-charge time of the pull-up node Q will become shorter and shorter.

[0033] See also Figure 3 The present invention provides a gate driving circuit, comprising a plurality of cascaded gate driving units, wherein the Nth stage gate driving unit comprises:

[0034] A pull-up transistor T0, wherein a first electrode of the pull-up transistor T0 is connected to the first clock signal line CLK1, a second electrode of the pull-up transistor T0 is connected to the Nth level scan line G(n), and a gate of the pull-up transistor T0 is connected to the pull-up node Q, wherein N and n are both integers greater than 4;

[0035] An input module 1, the input module 1 is connected to the pull-up node Q and charges the pull-up node Q;

[0036] The pull-down module 2 is connected to the pull-up node Q, the reverse node QB, and the low potential line DCL respectively. When the potential of the reverse node QB rises, the pull-down module is started, and the pull-down module 2 pulls the potential of the pull-up node Q down to a low level.

[0037] A boost module 3, the boost module 3 is connected to the reverse node QB, and the boost module 3 pulls up the potential of the reverse node QB to a high level according to a boost start signal;

[0038] The third transistor T3, the first electrode of the third transistor T3 is connected to the reverse node QB, the second electrode of the third transistor T3 is connected to the low potential line DCL, and the gate of the third transistor T3 is connected to the N-4th level pull-up signal Q(n-4), that is, when the N-4th level pull-up signal Q(n-4) controls the third transistor T3 to be turned on, the reverse node QB is connected to the low potential line DCL, and the potential of the reverse node QB can be pulled down to a low level. Conversely, when the N-4th level pull-up signal Q(n-4) controls the third transistor T3 to be turned off, the reverse node QB is disconnected from the low potential line DCL, which has no effect on the potential of the reverse node QB.

[0039] The present invention adds a third transistor T3 and controls the conduction and cutoff of the third transistor T3 through the N-4th level pull-up signal Q(n-4), so as to independently control the potential of the reverse node QB. Before the circuit enters the pre-charging stage, that is, the input module 1 charges the pull-up node Q and before the potential of the pull-up node Q rises, the third transistor T3 is preferentially controlled to be turned on through the N-4th level pull-up signal Q(n-4), so that the potential of the reverse node QB can be pulled down to a low level, that is, the potential of the reverse node QB can be pulled down before the pre-charging stage of the pull-up node Q, and the effect of the pre-charging stage can be effectively improved, so that the pre-charging time of the pull-up node Q and the voltage that the pull-up node Q can be pre-charged to are higher than those of the original circuit, thereby enhancing the working ability at low temperatures.

[0040] Similarly, the driving signal of the third transistor T3 can be reasonably selected and adjusted according to specific usage requirements, such as using the N-3th level pull-up signal Q(n-3), or the N-2th level pull-up signal Q(n-2), or using other control signals. It is only necessary to control the third transistor T3 to be turned on before the pre-charge stage of the pull-up node Q, so as to pull the potential of the reverse node QB down to a low level.

[0041] As an embodiment of the present invention, the pull-down module 2 includes a first transistor T1, a first electrode of the first transistor T1 is connected to the pull-up node Q, a second electrode of the first transistor T1 is connected to the low potential line DCL, and a gate of the first transistor T1 is connected to the reverse node QB. The potential of the reverse node QB controls the on or off of the first transistor T1, that is, when the reverse node QB is at a high level, the first transistor T1 is turned on, and the pull-up node Q is connected to the low potential line DCL, thereby lowering the potential of the pull-up node Q. Conversely, when the reverse node QB is at a low level, the first transistor T1 is turned off, and the pull-up node Q is disconnected from the low potential line DCL, thereby It will not affect the potential of the pull-up node Q. Therefore, when the N-4th level pull-up signal Q(n-4) controls the third transistor T3 to turn on, the potential of the reverse node QB is pulled down to a low level, and the first transistor T1 is in an off state, and the pull-up node Q is disconnected from the low potential line DCL. When the pull-up node Q enters the pre-charging stage, as long as the N-4th level pull-up signal Q(n-4) is at a high level, the potential of the reverse node QB will continue to be lowered, causing the first transistor T1 to continue to be in an off state, and the potential of the pull-up node Q cannot be affected, thereby effectively improving the effect of the pre-charging stage and enhancing the working ability under low temperature conditions.

[0042] As an embodiment of the present invention, the boost module 3 includes a second transistor T2 and a first high potential line DCH1, the first electrode of the second transistor T2 is connected to the first high potential line DCH1, preferably, the voltage of the first high potential line DCH1 is adjustable, and is used to adjust the low voltage stabilization state of the gate to adapt to the difference in high and low temperatures, the second electrode of the second transistor T2 is connected to the reverse node QB, and the gate of the second transistor T2 is connected to the first control line, when it is necessary to raise the potential of the reverse node QB, the first control line sends a control signal to control the second transistor T2 to turn on, and the first high potential line DCH1 is connected to the reverse node QB, so that the potential of the reverse node QB can be raised to a high level, when it is not necessary to raise the potential of the reverse node QB, the first control line sends a control signal to control the second transistor T2 to turn off, and the first high potential line DCH1 is disconnected from the reverse node QB, and cannot affect the potential of the reverse node QB.

[0043] Pre-charging stage: input module 1 charges the pull-up node Q, the potential of the pull-up node Q increases, the second transistor T2 is turned on under the control of the first control line, the first high potential DCH1 is connected to the reverse node QB, the first high potential DCH1 pulls up the potential of the reverse node QB, turns on the first transistor T1, and the pull-up node Q is connected to the low potential line DCL, thereby lowering the potential of the pull-up node Q. It can be seen that the potential of the pull-up node Q is opposite to the potential of the reverse node QB, the potential of the reverse node QB increases, and the potential of the pull-up node Q decreases. Similarly, the potential of the reverse node QB decreases, and the potential of the pull-up node Q increases. The N-4th level pull-up signal Q(n-4) is input to the third transistor T3 to turn on the third transistor T3, so that the reverse node QB is connected to the low potential line DCL, and the potential of the reverse node QB is lowered, thereby avoiding the potential reduction of the pull-up potential Q, thereby improving the pre-charging effect.

[0044] When the set time is reached, the N-4th level pull-up signal Q(n-4) is converted to a low level, and the third transistor T3 cannot be turned on, and the reverse node QB is disconnected from the low potential line DCL, so the potential of the reverse node QB is no longer pulled down. Since the second transistor T2 is in the on state at this time, the reverse node QB is connected to the first high potential line DCH1. Under the action of the first high potential line DCH1, the potential of the reverse node QB continues to rise and reaches a high level, turning on the first transistor T1, so that the pull-up node Q is connected to the low potential line DCL, and the potential of the pull-up node Q is pulled down.

[0045] See also Figure 5 , the first curve is the potential change curve of the N-4th level pull-up signal Q(n-4), the second curve is the potential change curve of the Nth level pull-up signal Q(n), and the third curve is the potential change curve of the Nth level reverse signal QB(n). It can be seen that before the Nth level pull-up signal Q(n) rises, the Nth level reverse signal QB(n) has begun to decrease, that is, the reverse node QB has already reduced its voltage before the pre-charge stage of the pull-up node Q, instead of reducing its voltage after the pre-charge stage of the pull-up node Q begins, see Figure 4, wherein the first curve is the potential change curve of the pull-up node Q at 27°C, the second curve is the potential change curve of the reverse node QB at 27°C, the third curve is the potential change curve of the pull-up node Q at 0°C, the second curve is the potential change curve of the reverse node QB at 0°C, when the temperature is 27°C, the pre-charge time of the pull-up node Q is 36.64us, and the pre-charge voltage is 27.135V, when the temperature is 0°C, the pre-charge time of the pull-up node Q is 36.034us, and the pre-charge voltage is 26.419V. By comparing the potential change curve diagram of the present invention with the potential change curve diagram of the original circuit, it can be seen that the pre-charge time of the pull-up node Q in the pre-charge stage and the pre-charge voltage when the pre-charge stage is completed in the circuit of the present invention are higher than those of the original circuit, and with the increase of transmission, this benefit will gradually increase, which can effectively improve the ability of the circuit at low temperatures.

[0046] As an embodiment of the present invention, the N-th level gate driving unit also includes a fourth transistor T4, a first electrode of the fourth transistor T4 is connected to the reverse node QB, a second electrode of the fourth transistor T4 is connected to the low potential line DCL, and a gate of the fourth transistor T4 is connected to the N+4-th level pull-up signal Q(n+4), that is, when the N+4-th level pull-up signal Q(n+4) controls the fourth transistor T4 to be turned on, the reverse node QB is connected to the low potential line DCL, and the potential of the reverse node QB can be pulled down to a low level. Conversely, when the N+4-th level pull-up signal Q(n+4) controls the fourth transistor T4 to be turned off, the reverse node QB is disconnected from the low potential line DCL, and the potential of the reverse node QB is not affected. Similarly, the driving signal of the fourth transistor T4 can be reasonably selected and adjusted according to specific usage requirements, such as By using the N+3th level pull-up signal Q(n+3), or the N+2th level pull-up signal Q(n+2), or other control signals, it is only necessary to control the fourth transistor T4 to be turned on before the pre-charging stage of the pull-up node Q, so as to pull the potential of the reverse node QB down to a low level. The function of the fourth transistor T4 is the same as that of the third transistor T3, and both are used to reduce the potential of the reverse node QB before the pre-charging stage. The difference lies in that the two transistors act in different occasions. The third transistor T3 acts on forward scanning, and the fourth transistor T4 acts on reverse scanning. The third transistor T3 or the fourth transistor T4 can be selected according to the specific usage situation, and both forward scanning and reverse scanning can reduce the potential of the reverse node QB before the pre-charging stage, thereby improving the overall scope of application, effectively improving the overall compatibility, and saving costs.

[0047] Preferably, the control signals used by the third transistor T3 and the fourth transistor T4 correspond to each other. For example, if the control signal used by the third transistor T3 is the N-4th level pull-up signal Q(n-4), the control signal used by the fourth transistor T4 is the N+4th level pull-up signal Q(n+4); if the control signal used by the third transistor T3 is the N-3th level pull-up signal Q(n-3), the control signal used by the fourth transistor T4 is the N+3th level pull-up signal Q(n+3), which can ensure the relativity during forward scanning and reverse scanning, avoid unnecessary influences caused by differences between the control signals of forward scanning and reverse scanning, and improve the overall stability and reliability of use.

[0048] See also Figure 5 During forward scanning, the first curve is the potential change curve of the N-4th pull-up signal Q(n-4), the second curve is the potential change curve of the N-level pull-up signal Q(n), the third curve is the potential change curve of the N-level reverse signal QB(n), and the fourth curve is the potential change curve of the N+4th pull-up signal Q(n+4). During reverse scanning, the first curve is the potential change curve of the N+4th pull-up signal Q(n+4), the second curve is the potential change curve of the N-level pull-up signal Q(n), the third curve is the potential change curve of the N-level reverse signal QB(n), and the fourth curve is the potential change curve of the N-4th pull-up signal Q(n-4). During the forward scan, the N-4th level pull-up signal Q(n-4) is selected to control the on or off of the third transistor T3. During the reverse scan, the N+4th level pull-up signal Q(n+4) is selected to control the on or off of the fourth transistor T4. Through the cooperation between the third transistor T3 and the fourth transistor T4, the present invention can reduce the potential of the reverse node QB before the pre-charging stage regardless of the forward scan or reverse scan conditions, thereby improving the overall scope of application.

[0049] As an embodiment of the present invention, the first control line is connected to the first clock signal line CLK1, that is, the first clock signal line CLK1 is used as the gate signal of the second transistor T2 to control the conduction or shutdown of the second transistor T2, which can effectively control the second transistor T2 and reduce energy loss, and can effectively reduce the number of control signals.

[0050] As an embodiment of the present invention, the input module 1 includes a fifth transistor T5 and a sixth transistor T6, the first electrode of the fifth transistor T5 is connected to the second high potential line DCH2, the second electrode of the fifth transistor T5 is connected to the pull-up node Q, and the gate of the fifth transistor T5 is connected to the second control line, that is, when the second control line outputs a control signal to control the fifth transistor T5 to be turned on, the pull-up node Q is connected to the second high potential line DCH2, and the second high potential line DCH2 charges the pull-up node Q, when the second control line outputs a control signal to control the fifth transistor T5 to be turned off, the pull-up node Q is disconnected from the second high potential line DCH2, and the second high potential line DCH2 stops charging the pull-up node Q, preferably, the voltage of the second high potential line DCH2 is adjustable; The first electrode of the sixth transistor T6 is connected to the low potential line DCL, the second electrode of the sixth transistor T6 is connected to the pull-up node Q, and the gate of the sixth transistor T6 is connected to the third control line. Similarly, the third control line outputs a control signal to control the conduction or shutdown of the sixth transistor T6, thereby realizing the charging or stopping of the pull-up node Q. The fifth transistor T5 and the sixth transistor T6 also have the same function, but different working environments. The fifth transistor T5 is used for forward scanning, and the sixth transistor T6 is used for reverse scanning. Taking the forward scanning as an example, in the pre-charging stage, the potential of the second high potential line DCH2 is greater than or equal to the potential of the pull-up node Q, which can prevent the charge of the pull-up node Q from leaking through the fifth transistor T5, thereby further stabilizing the potential of the pull-up node Q. The principle is the same during reverse scanning. Preferably, the second control line transmits the N-4th level scanning signal G(n-4); the third control line transmits the N+4th level scanning signal G(n+4); of course, both the second control line and the third control line can use other levels of scanning signals, such as the second control line transmits the N-3th level scanning signal G(n-3), or transmits the N-2th level scanning signal G(n-2), or other scanning signals; the third control line transmits the N+3th level scanning signal G(n+3), or transmits the N+2th level scanning signal G(n+2), or other scanning signals, which can be selected according to specific usage requirements.

[0051] Preferably, the control signal of the second control line corresponds to the control signal of the third control line. For example, if the second control line transmits the N-3th level scanning signal G(n-3), the third control line transmits the N+3th level scanning signal G(n+3); if the second control line transmits the N-2th level scanning signal G(n-2), the third control line transmits the N+2th level scanning signal G(n+2). This ensures the relativity during forward scanning and reverse scanning, avoids unnecessary influences caused by differences between the control signals of forward scanning and reverse scanning, and improves the overall stability and reliability of use.

[0052] As an embodiment of the present invention, the N-th level gate driving unit also includes a seventh transistor T7, a first electrode of the seventh transistor T7 is connected to the reverse node QB, a second electrode of the seventh transistor T7 is connected to the low potential line DCL, and a gate of the seventh transistor T7 is connected to the pull-up node Q, that is, when the pull-up node Q is at a high potential, the seventh transistor T7 is turned on, the reverse node QB is connected to the low potential line DCL, and the low potential line DCL pulls down the potential of the reverse node QB; conversely, when the pull-up node Q is at a low potential, the seventh transistor T7 is turned off, the reverse node QB is disconnected from the low potential line DCL, and the position of the reverse node QB is not affected. During the pre-charging stage, the potential of the pull-up node Q rises, thereby turning on the seventh transistor T7 and pulling down the potential of the reverse node QB, which can ensure the low potential of the reverse node QB when the pull-up node Q is at a high potential, thereby further improving the potential stability of the pull-up node Q.

[0053] As an embodiment of the present invention, the N-th gate driving unit also includes an eighth transistor T8, a first electrode of the eighth transistor T8 is connected to the N-th scan line G(n), a second electrode of the eighth transistor T8 is connected to the low potential line DCL, and a gate of the eighth transistor T8 is connected to the reverse node QB, that is, when the reverse node QB is at a high potential, the eighth transistor T8 is turned on, the N-th scan line G(n) is connected to the low potential line DCL, and the low potential line DCL pulls down the potential of the N-th scan line G(n); conversely, when the reverse node QB is at a low potential, the eighth transistor T8 is turned off, the N-th scan line G(n) is disconnected from the low potential line DCL, and the potential of the N-th scan line G(n) is not affected, that is, when the reverse node QB rises, the eighth transistor T8 is turned on to achieve reset.

[0054] As an embodiment of the present invention, the N-th gate driving unit further includes a ninth transistor T9, a first electrode of the ninth transistor T9 is connected to the N-th scan line G(n), a second electrode of the ninth transistor T9 is connected to the low potential line DCL, and a gate of the ninth transistor T9 is connected to the second clock signal line CLK2, that is, when the second clock signal line CLK2 outputs a control signal to control the ninth transistor T9 to be turned on, the N-th scan line G(n) is connected to the low potential line DCL, and the low potential line DCL pulls down the potential of the N-th scan line G(n), and vice versa, when the second clock signal line CLK2 outputs a control signal to control the ninth transistor T9 to be turned on. After the N-th scan line G(n) is disconnected from the low potential line DCL, and the potential of the N-th scan line G(n) is not affected, that is, the conduction or shutdown of the ninth transistor T9 is controlled by the second clock signal line CLK2, thereby realizing reset control. Preferably, the signal transmitted by the first clock signal line CLK1 is opposite in phase to the signal transmitted by the second clock signal line CLK2, that is, when the first clock signal line CLK1 is outputting a signal, the second clock signal line CLK2 will not output a signal for reset, thereby improving the control over the reset signal, avoiding the abnormal phenomenon of false reset, and reducing the number of control signals and reducing costs.

[0055] As an embodiment of the present invention, the Nth stage gate driving unit further includes a bootstrap capacitor C, one end of the bootstrap capacitor C is connected to the pull-up node Q, and the other end of the bootstrap capacitor C is connected to the Nth stage scan line G(n).

[0056] In summary, the present invention provides a gate drive circuit, which can realize the potential of the reverse node QB being pulled down before the pre-charging stage of the pull-up node Q point by adding a third transistor T3 and a fourth transistor T4, and can effectively improve the effect of the pre-charging stage; the pre-charging time of the pull-up node Q in the pre-charging stage and the pre-charging voltage when the pre-charging stage is completed in the circuit of the present invention are higher than those of the original circuit, and this benefit will gradually increase with the increase of transmission, and can effectively improve the ability of the circuit at low temperatures; through the mutual cooperation of the third transistor T3 and the fourth transistor T4, the present invention can realize the reduction of the potential of the reverse node QB before the pre-charging stage regardless of the forward scanning or reverse scanning conditions, thereby improving the overall scope of application; the first clock signal line CLK1 is used as the gate signal line of the second transistor T2 The seventh transistor T7 can ensure the low potential of the reverse node QB when the pull-up node Q is at a high potential, and further improve the potential stability of the pull-up node Q; the eighth transistor T8 and the ninth transistor T9 realize the reset function; the signal transmitted by the first clock signal line CLK1 is opposite in phase to the signal transmitted by the second clock signal line CLK2, which can achieve that when the first clock signal line CLK1 is outputting a signal, the second clock signal line CLK2 will not output a signal for reset, thereby improving the control over the reset signal and avoiding the abnormal phenomenon of false reset, while reducing the number of control signals and reducing costs.

[0057] It should be emphasized that the above are only preferred embodiments of the present invention and do not limit the present invention in any form. Any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A gate drive circuit, characterized in that: The invention comprises a plurality of cascaded gate driving units, wherein the Nth stage gate driving unit comprises: A pull-up transistor, wherein a first electrode of the pull-up transistor is connected to the first clock signal line, a second electrode of the pull-up transistor is connected to the Nth level scan line, and a gate of the pull-up transistor is connected to the pull-up node; an input module, the input module being connected to the pull-up node and charging the pull-up node; A pull-down module, wherein the pull-down module is connected to the pull-up node, the reverse node, and the low potential line respectively, and the pull-down module is started after the potential of the reverse node rises, and the pull-down module pulls the potential of the pull-up node down to a low level; A boost module, the boost module is connected to the reverse node, and the boost module pulls up the potential of the reverse node to a high level according to a boost start signal; A third transistor, wherein a first electrode of the third transistor is connected to the reverse node, a second electrode of the third transistor is connected to the low potential line, and a gate of the third transistor is connected to the N-4th level pull-up signal.

2. The gate driving circuit according to claim 1, characterized in that: The pull-down module includes a first transistor, a first electrode of the first transistor is connected to the pull-up node, a second electrode of the first transistor is connected to the low potential line, and a gate of the first transistor is connected to the reverse node.

3. The gate driving circuit according to claim 1, characterized in that: The boost module includes a second transistor and a first high potential line, the first electrode of the second transistor is connected to the first high potential line, the second electrode of the second transistor is connected to the reverse node, the gate of the second transistor is connected to the first control line, and the first control line is connected to the first clock signal line.

4. The gate driving circuit according to claim 1, characterized in that: The Nth level gate driving unit also includes a fourth transistor, a first electrode of the fourth transistor is connected to the reverse node, a second electrode of the fourth transistor is connected to the low potential line, and a gate of the fourth transistor is connected to the N+4th level pull-up signal.

5. The gate driving circuit according to claim 1, characterized in that: The input module includes a fifth transistor and a sixth transistor, wherein the first electrode of the fifth transistor is connected to the second high potential line, the second electrode of the fifth transistor is connected to the pull-up node, and the gate of the fifth transistor is connected to the second control line; the first electrode of the sixth transistor is connected to the low potential line, the second electrode of the sixth transistor is connected to the pull-up node, and the gate of the sixth transistor is connected to the third control line.

6. The gate driving circuit according to claim 5, characterized in that: The second control line transmits the N-4th level scanning signal; the third control line transmits the N+4th level scanning signal.

7. The gate driving circuit according to claim 1, characterized in that: The N-th stage gate driving unit further includes a seventh transistor, a first electrode of the seventh transistor is connected to the reverse node, a second electrode of the seventh transistor is connected to the low potential line, and a gate of the seventh transistor is connected to the pull-up node.

8. The gate driving circuit according to claim 1, characterized in that: The N-th level gate driving unit further includes an eighth transistor, a first electrode of the eighth transistor is connected to the N-th level scanning line, a second electrode of the eighth transistor is connected to the low potential line, and a gate of the eighth transistor is connected to the reverse node.

9. The gate driving circuit according to claim 1, characterized in that: The Nth-stage gate driving unit further includes a ninth transistor, a first electrode of the ninth transistor is connected to the Nth-stage scanning line, a second electrode of the ninth transistor is connected to the low potential line, and a gate of the ninth transistor is connected to the second clock signal line.

10. The gate driving circuit according to claim 9, characterized in that: The phase of the signal transmitted by the first clock signal line is opposite to that of the signal transmitted by the second clock signal line.

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