Array substrate, display panel and spliced display screen

Abstract

The invention discloses an array substrate, a display panel and a spliced display screen. The array substrate comprises a substrate; a display area; the display area comprises a shift register circuit setting area and a pixel driving circuit; the pixel driving circuits are arranged in an array; the shift register circuit setting area comprises a plurality of shift register units which are cascaded along a first direction; at least part of the shift register units are correspondingly provided with first bonding pads and second bonding pads; the shift register circuit setting region comprises a grid starting wire and a cascade wire which extend along a first direction; the grid starting wire is electrically connected with the first bonding pad; the cascade lines are used for connecting two adjacent shift register units; and the second bonding pad is electrically connected with the cascade wiring. According to the technical scheme provided by the invention, the array substrate capable of being cut in multiple sizes is provided, and a large-size display screen can be conveniently formed through splicing.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate, a display panel and a spliced ​​display screen. Background Art

[0002] In recent years, in order to maximize the screen size, narrow-framed display panels are increasingly used in various devices. In order to realize large-size display devices, the concept and application of splicing multiple display panels are gradually emerging.

[0003] Due to some special application scenarios, it is often necessary to use substrates of different sizes to form different display panels. Therefore, the existing technology often requires opening substrates of different sizes to produce display panels. However, the mask design of the display array of the display panel is relatively complex, and the array substrate tape-out cost is relatively high, which limits the application and development of spliced ​​screens. Summary of the invention

[0004] The embodiments of the present invention provide an array substrate, a display panel and a spliced ​​display screen, so as to provide an array substrate that can be cut into multiple sizes, so as to facilitate splicing to form a large-size display screen.

[0005] In a first aspect, an embodiment of the present invention provides an array substrate, comprising: a substrate;

[0006] Display area; the display area includes a shift register circuit setting area and a pixel driving circuit;

[0007] The pixel driving circuit is arranged in an array; the shift register circuit setting area includes a plurality of shift register units cascaded along a first direction; at least part of the shift register units are correspondingly provided with a first pad and a second pad;

[0008] The shift register circuit setting area includes a gate start line and a cascade line extending along the first direction; the gate start line is electrically connected to the first pad; the cascade line is used to connect two adjacent shift register units; the second pad is electrically connected to the cascade line.

[0009] In a second aspect, an embodiment of the present invention provides a display panel, comprising: a first array substrate; the first array substrate is cut and made by cutting the array substrate provided by any embodiment of the present invention;

[0010] The first array substrate comprises: a substrate; along a first direction, the first array substrate comprises a first side and a display area; the first side is provided with a side wiring; the display area comprises a shift register circuit setting area and a pixel driving circuit; the pixel driving circuit is arranged in an array; the shift register circuit setting area comprises a plurality of shift register units cascaded along the first direction; at least part of the shift register units are correspondingly provided with a first pad and a second pad; the shift register circuit setting area comprises a gate start wiring and a cascade wiring extending along the first direction; the gate start wiring is electrically connected to the first pad; the cascade wiring is used to connect two adjacent shift register units; the second pad is electrically connected to the cascade wiring;

[0011] A first spacing area including a first cutting gap is provided on a side of the first array substrate away from the first side; the first cutting gap extends along a second direction; the first direction intersects with the second direction and is parallel to the substrate; a first solder pad and a second solder pad on a side of the first cutting gap close to the first side are electrically connected.

[0012] In a third aspect, an embodiment of the present invention further provides a spliced ​​display screen, including: a display panel provided by any embodiment of the present invention;

[0013] A plurality of display panels are spliced ​​together; a first side edge of a first array substrate of the display panel serves as an edge of the spliced ​​display screen.

[0014] In the present invention, the display area of ​​the array substrate includes a shift register circuit setting area and a pixel driving circuit, and the shift register circuit setting area is provided with shift register units cascaded along a first direction, wherein some of the shift register units are correspondingly provided with a first pad and a second pad. The shift register circuit setting area includes a gate start-up line and a cascade line extending along the first direction, the first pad is electrically connected to the gate start-up line, and the second pad is electrically connected to the cascade line. Then the array substrate provided in this embodiment can be cut along a direction perpendicular to the first direction, specifically at the position where the shift register unit provided with the first pad and the second pad is located, so that after the array substrate is cut, the first pad and the second pad are electrically connected, so that the start signal output by the gate start-up line is transmitted to the shift register unit corresponding to the first pad and the second pad, so as to avoid the situation that the electrical connection between the gate start-up line and the cascaded shift register unit is disconnected due to cutting, and avoid the failure of the array substrate. Furthermore, there may be a plurality of shift register units in the shift register circuit setting area, and the first solder pad and the second solder pad are correspondingly provided. Then, this embodiment can be cut at a plurality of positions along the first direction to form array substrates of different sizes, thereby realizing array substrates of a plurality of specifications without reopening the substrate, so as to meet the needs of splicing screens in different scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic structural diagram of an array substrate provided by an embodiment of the present invention;

[0016] Figure 2 for Figure 1 A schematic diagram of a partial enlarged structure of a region B1 of a middle array substrate;

[0017] Figure 3 A schematic diagram of a partially enlarged structure of another array substrate provided by an embodiment of the present invention;

[0018] Figure 4 A schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0019] Figure 5 for Figure 4 A schematic diagram of a partial cross-sectional structure of a middle array substrate;

[0020] Figure 6 for Figure 4 A schematic diagram of the structure of the array substrate after cutting;

[0021] Figure 7 Another schematic diagram of a partial cross-sectional structure provided by an embodiment of the present invention;

[0022] Figure 8 A schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0023] Fig. 9 A schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0024] Fig.10 A schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0025] Fig.11 A schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0026] Fig.12 A schematic structural diagram of a pixel circuit provided by an embodiment of the present invention;

[0027] Fig.13 for Fig.11 A schematic diagram of the local structure of region B2 of the middle array substrate;

[0028] Fig.14 A schematic diagram of a local layout of an array substrate provided by any embodiment of the present invention;

[0029] Fig.15 for Fig.14A schematic diagram of the enlarged structure of the area B2 of the array substrate;

[0030] Fig.16 A schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0031] Fig.17 A schematic structural diagram of a first array substrate provided by an embodiment of the present invention;

[0032] Fig.18 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0033] Fig.19 A schematic structural diagram of a spliced ​​display screen provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0034] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0035] For borderless spliced ​​displays such as OLED, LED, MiniLED and MicroLED, due to some special application scenarios, substrates of multiple sizes are often required. However, the complex mask design of the array substrate and the high tape-out cost of the array substrate limit the application and expansion of the spliced ​​screen. Accordingly, the present invention proposes an array substrate that can be freely cut horizontally, which can achieve multi-size array substrates without reopening the substrate (new size motherboard), thereby meeting the needs of spliced ​​screens of various sizes. And there is no need to open new substrates, matching masks and matching production lines, saving preparation costs. Figure 1 and Figure 2 As shown, Figure 1 A schematic diagram of the structure of an array substrate provided by an embodiment of the present invention, Figure 2 for Figure 1 A partial enlarged structural diagram of a region B1 of the array substrate in FIG. 1 is a schematic diagram of a partial enlarged structural diagram of a region B1 of the array substrate in FIG.

[0036] Display area AA; the display area AA includes a shift register circuit setting area AA1 and a pixel driving circuit 12;

[0037] The pixel driving circuit 12 is arranged in an array; the shift register circuit setting area AA1 includes a plurality of shift register units 131 arranged in cascade along the first direction Y; at least part of the shift register units 131 are correspondingly provided with a first pad 141 and a second pad 142;

[0038] The shift register circuit setting area AA1 includes a gate enable line 151 and a cascade line 152 extending along the first direction Y; the gate enable line 151 is electrically connected to the first pad 141; the cascade line 152 is used to connect two adjacent shift register units 131; and the second pad 142 is electrically connected to the cascade line 152.

[0039] In an embodiment of the present invention, the display area of ​​the array substrate includes a shift register circuit setting area and a pixel driving circuit, and the shift register circuit setting area is provided with shift register units cascaded along a first direction, wherein some of the shift register units are correspondingly provided with a first pad and a second pad. The shift register circuit setting area includes a gate start line and a cascade line extending along the first direction, the first pad is electrically connected to the gate start line, and the second pad is electrically connected to the cascade line. Then the array substrate provided in this embodiment can be cut along a direction perpendicular to the first direction, specifically at the position where the shift register unit provided with the first pad and the second pad is located, so that after the array substrate is cut, the first pad and the second pad are electrically connected, so that the start signal output by the gate start line is transmitted to the shift register unit corresponding to the first pad and the second pad, so as to avoid the situation that the electrical connection between the gate start line and the cascaded shift register unit is disconnected due to cutting, and avoid the failure of the array substrate. Furthermore, there may be a plurality of shift register units in the shift register circuit setting area, and the first solder pad and the second solder pad are correspondingly provided. Then, this embodiment can be cut at a plurality of positions along the first direction to form array substrates of different sizes, thereby realizing array substrates of a plurality of specifications without reopening the substrate, so as to meet the needs of splicing screens in different scenarios.

[0040] The above is the core idea of ​​the present invention. The technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] The display panel formed by the array substrate in this embodiment is used to form a spliced ​​screen. In this embodiment, the array substrate may include a display area AA, and no non-display area is provided, so as to avoid black edges appearing at the edges of two adjacent display panels in the spliced ​​screen, thereby improving the display effect of the spliced ​​screen. In this embodiment, the shift register unit is provided in the display area AA. Specifically, Figure 1As shown, the display area AA may include a shift register circuit setting area AA1 and a pixel driving circuit 12. The register circuit setting area AA1 includes a plurality of shift register units 131 cascaded along a first direction Y, and the first direction Y is a direction parallel to the substrate 11 of the array substrate. The pixel driving circuit 12 is arranged in an array in the display area AA. The shift register unit 131 is used to generate a scanning signal or a light emitting control signal for driving the pixel driving circuit 12. The pixel driving circuit 12 is used to generate a driving light emitting element ( Figure 1 The driving current is not shown in FIG. Figure 1 As shown, the display area AA may include a plurality of shift register circuit setting areas AA1, and the shift register units 131 of different shift register circuit setting areas AA1 are used to generate different signals. Figure 1 As shown, the display area AA may include two shift register circuit setting areas AA1, wherein the shift register unit 131 of one shift register circuit setting area AA1 is used to generate a scan signal SCAN, and the shift register unit 131 of the other shift register circuit setting area AA1 is used to generate a light emitting control signal EMIT, then the pixel driving circuit 12 may be a 7T1C (7 transistors and 1 capacitor) circuit or an 8T1C circuit, and this embodiment does not specifically limit the specific structure of the pixel driving circuit. It should be noted that the number of shift register circuit setting areas AA1 can be set according to the specific structure of the pixel driving circuit, Figure 1 In the figure, only two shift register circuit setting areas AA1 are taken as an example for illustration. This embodiment includes but is not limited to setting two shift register circuit setting areas AA1.

[0042] The shift register circuit setting area AA1 includes a plurality of shift register units 131 cascaded along a first direction Y. In this embodiment, at least some of the cascaded shift register units 131 may be selected to set corresponding pads: a first pad 141 and a second pad 142. Optionally, in this embodiment, a corresponding first pad 141 and a second pad 142 may be set for each shift register unit 131, that is, the shift register unit 131 is set in a one-to-one correspondence with the first pad 141, and the shift register unit 131 is set in a one-to-one correspondence with the second pad 142. Alternatively, some of the shift register units 131 are selected in the shift register circuit setting area AA1 to set corresponding pads, such as Figure 1 As shown, the selected part of the shift register units 131 is set in a one-to-one correspondence with the first pads 141, and the selected part of the shift register units 131 is set in a one-to-one correspondence with the second pads 142.

[0043] The shift register circuit setting area AA1 further includes a gate start line 151 and a cascade line 152 extending along the first direction Y. The gate start line 151 is used to output a gate start signal STV to the cascaded shift register units 131 in the shift register circuit setting area AA1. The cascade line 152 is used to connect two adjacent shift register units 131 in the cascaded shift register units 131, and is used to drive the shift register units 131 step by step. Figure 1 and Figure 2 As shown, the first pad 141 is electrically connected to the gate enable wiring 151 , and the second pad 142 is electrically connected to the cascade wiring 152 .

[0044] like Figure 1 As shown, the gate start line 151 extends along the first direction Y, and the STV signal output by the gate start line 151 enters the shift register unit 131 from the top of the array substrate (the end of the array substrate away from the signal terminal outputting the gate start signal, that is, the far end of the array substrate), and the scanning process of the array substrate is a positive direction scanning design. When the display panel cuts the array substrate in a direction perpendicular to the first direction Y, the connection line 11' between the gate start line 151 and the first shift register unit 131 at the top of the array substrate will be removed. The position of the shift register unit 131 provided with the first pad 141 and the second pad 142 can be used as the preset cutting position of the array substrate. When the array substrate is cut from a preset cutting position in a direction perpendicular to the first direction Y, the preset cutting position is the actual cutting position. For example, Figure 1As shown, the actual cutting position can be a position extending along the straight line L0, the first pad 141 and the second pad 142 of the shift register unit 131 at the actual cutting position are electrically connected, and the gate start wiring 151 of the array substrate after cutting is electrically connected to the shift register unit 131 at the preset cutting position (the first shift register unit 131 in the cascaded shift register unit 131 after cutting), then the array substrate after cutting can continue to be scanned in the positive direction, and the driving process of the array substrate is completed, effectively avoiding the problem that the array substrate fails due to the part of the actual cutting position close to the far end being cut off. The array substrate can also include multiple preset cutting positions, each preset cutting position can be used as the actual cutting position. After the cutting is completed, the part of the actual cutting position of the array substrate close to the far end is discarded, and the part of the side of the actual cutting position away from the far end is retained as the array substrate after cutting, so as to form array substrates of different sizes. In the prior art, there are many sizes of display panels, and array substrates of display panels of different sizes are usually prepared using different mask plates. In order to reduce the number of mask plates and reduce the array substrate tape-out, this embodiment manufactures an array substrate through a set of mask plates, and then cuts the array substrate to realize the manufacture of display panels of various sizes, which is convenient for preparing spliced ​​screens for various scenes.

[0045] Continue to refer Figure 1 and Figure 2Optionally, along the first direction Y, a spacing area 132 is provided between two adjacent shift register units 131; the spacing area 132 includes at least one first spacing area 133; the first pad 141 and the second pad 142 are provided in the first spacing area 133. In this embodiment, the shift register circuit setting area AA1 includes shift register units 131 cascaded along the first direction Y, and a spacing area 132 is provided between adjacent shift register units 131, and the spacing area 132 is used to set a scan signal line for transmitting a scan signal SCAN, and a light control signal line for transmitting a light control signal EMIT. Optionally, in the display area AA, a plurality of pixel driving circuits 12 are arranged in sequence along the second direction X to form a row of pixel driving circuits 12, and a plurality of rows of pixel driving circuits 12 are arranged in sequence along the first direction Y. The second direction X intersects with the first direction Y, and the area between two adjacent rows of pixel driving circuits 12 is the spacing area 132. Of course, in another example of the present embodiment, a plurality of light-emitting elements are arranged in sequence along the second direction X to form a row of light-emitting elements, and a plurality of rows of light-emitting elements are arranged in sequence along the first direction Y, and the spacing region 132 may also be a region between two adjacent rows of light-emitting elements 12. In the present embodiment, the spacing region 132 extends along the second direction X. In addition, the spacing region 132 may also be provided with a first solder pad 141 and a second solder pad 142. In the present embodiment, the spacing region 132 provided with the first solder pad 141 and the second solder pad 142 is referred to as a first spacing region 133. The number of the first spacing regions 133 may be multiple, and the first spacing regions 133 may correspond one-to-one to the shift register units 131 provided with the first solder pad 141 and the second solder pad 142, and the first spacing region 133 is provided on the side of the corresponding shift register unit 131 close to the far end of the array substrate. In the present embodiment, the first solder pad 141 and the second solder pad 142 may be provided in the first spacing region 133 between two adjacent shift register units 131. In addition, as Figure 3 As shown, Figure 3 A schematic diagram of a partially enlarged structure of another array substrate provided by an embodiment of the present invention. In addition to being arranged in the spacing area 132, the first pad 141 and the second pad 142 can also be arranged on the side of the shift register unit 131, that is, in the direction perpendicular to the first direction Y, the first pad 141 and the second pad 142 are arranged in the gap between the pixel driving circuit 12 and the shift register unit 131. Optionally, in order to further reduce the gap space occupied by the first pad 141 and the second pad 142, in the direction perpendicular to the substrate 11, the first pad 141 can be controlled to at least partially overlap with the gate start wiring 151, and the second pad 142 can be controlled to at least partially overlap with the cascade wiring 152, so as to increase the local space of the pixel driving circuit 12 and the shift register unit 131, thereby increasing the arrangement density of the pixel driving circuit 12 of the array substrate, improving the PPI of the formed display panel, and improving the display effect of the display panel.

[0046] Figure 4 A schematic diagram of the structure of another array substrate provided by an embodiment of the present invention, Figure 5 for Figure 4 Schematic diagram of the local cross-sectional structure of the middle array substrate. Optionally, along the first direction Y, the display area AA may include a first side L1 and at least two sub-display areas 16 arranged in sequence away from the first side L1; the first side L1 is provided with a side wiring 17; a first spacing area 133 is included between two adjacent sub-display areas 16; the first spacing area 133 includes a preset cutting gap 18 extending along the second direction X; the first direction Y intersects with the second direction X and is parallel to the substrate 11; the first pad 141 and the second pad 142 are arranged on the side of the preset cutting gap 18 close to the side wiring 17.

[0047] The second direction X is parallel to the substrate 11, and the first direction Y intersects the second direction X. Optionally, as Figure 4 As shown, the first direction Y is perpendicular to the second direction X. The shift register circuit setting area AA1 includes shift register units 131 cascaded along the first direction Y, and the display area AA also includes pixel driving circuits 12 arranged in sequence along the second direction X. Exemplarily, each shift register unit 131 corresponds to a row of pixel driving circuits 12 extending along the second direction X. Figure 4 As shown, along the first direction Y, the display area AA may include at least two sub-display areas 16. In this embodiment, a first spacing area 133 may be set between two adjacent sub-display areas 16 to set a first pad 141 and a second pad 142. Specifically, in this embodiment, a preset cutting gap 18 extending along the second direction X is formed in each first spacing area 133. The preset cutting gap 18 is an area where the array substrate can be cut. This area may be marked during the preparation of the array substrate, so as to facilitate the operator to perform lateral cutting of the array substrate along the preset cutting gap 18. It should be noted that in this embodiment, the edge of the array substrate at one end close to the signal terminal for outputting the gate start signal is referred to as the first side L1. The first side L1 is provided with a side trace 17, such as Figure 5As shown, the side wiring 17 extends along the first side L1 of the array substrate, and is used to electrically connect the signal lines such as the gate start wiring 151 to the corresponding signal terminals. The signal terminals can be arranged on the side of the substrate 11 of the array substrate away from the pixel driving circuit 12. Optionally, a binding area 171 is arranged on the side of the substrate 11 away from the shift register unit 131, and the binding area 171 includes a plurality of signal terminals. Optionally, the side wiring 17 can extend to the side of the substrate 11 away from the shift register unit 131; the side wiring 17 is electrically connected to the corresponding binding pad (signal terminal) of the binding area 171. The driver chip can be bound on the binding area 171, and the driver chip transmits each signal to each signal line of the display area AA through the binding pad and the side wiring 17. In this embodiment, the binding area 171 of the array substrate is arranged on the non-display side of the substrate 11, so that the binding area does not occupy the space on the display side of the display panel, realizing the borderless design of the display panel, and facilitating the splicing of multiple display panels to form a spliced ​​screen.

[0048] In order to realize the individual control of each array substrate, after the cutting is completed along the preset cutting gap 18, the present embodiment needs to retain the array substrate including the first side L1 and the signal terminal. In order to avoid the failure of the array substrate, in the present embodiment, in the first spacing area 133, the first pad 141 and the second pad 142 are arranged on the side of the preset cutting gap 18 close to the side trace 17, so that after the cutting is completed, the first pad 141 and the second pad 142 close to the actual cutting position are left in the array substrate including the first side L1, avoiding the problem of the array substrate failing due to the part close to the far end of the actual cutting position being cut off. Along the first direction Y, the array substrate is provided with a plurality of preset cutting gaps 18, each of which can be cut, so the user can select the corresponding preset cutting gap 18 for cutting according to the required size of the target array substrate, so that array substrates of multiple sizes can be obtained without reopening the substrate.

[0049] Continue to refer Figure 4Optionally, the sub-display area 16 may include N shift register units 131 cascaded along the first direction Y; N is an integer greater than 1; the preset cutting gap 18 between any two sub-display areas 16 may be used as the first cutting gap 181. In this embodiment, the array substrate forms a plurality of sub-display areas 16 along the first direction Y, and each sub-display area 16 may include N shift register units 131 cascaded along the first direction Y, that is, the size of each sub-display area 16 along the first direction Y is the same and fixed, so that it is convenient for the user to select the corresponding preset cutting gap 18 as the first cutting gap 181 for cutting according to the size of the target array substrate. In this embodiment, the value of N can be selected according to the cutting requirements. For example, if the target array substrate requires a large number of specifications, N can be set to a smaller value to facilitate the realization of a large number of target array substrates of different sizes. If the target array substrate requires a smaller number of specifications, N can be set larger to reduce the number of first spacing regions 133, thereby reducing the number of first pads 141 and second pads 142, so as to further increase the layout space of the pixel driving circuit 12 and enhance the display effect of the display panel. Figure 4 As shown, each sub-display area 16 may include two shift register units 131 cascaded along the first direction Y. Of course, the value of N includes but is not limited to 2, and N can be set according to the size of the first array substrate 100.

[0050] Figure 6 for Figure 4 Schematic diagram of the structure of the array substrate after cutting, refer to Figure 4 and Figure 6 Optionally, the preset cutting gap 18 may include a first cutting gap 181; after the cutting process is completed along the first cutting gap 181, the array substrate forms a first array substrate 100 and a second array substrate 101; the first array substrate 100 includes a side wiring 17; the first pad 141 and the second pad 142 of the first array substrate 100 disposed near the first cutting gap 181 are electrically connected. In this embodiment, the preset cutting gap 18 that needs to be cut is referred to as the first cutting gap 181. Figure 6 As shown, after the array substrate is cut along the first cutting gap 181, a first array substrate 100 and a second array substrate 101 are formed. The first array substrate 100 includes the side wiring 17, and the second array substrate 101 is the portion of the array substrate away from the first cutting gap 181 and the side wiring 17. It should be noted that Figure 6As shown, the first spacing area 133 where the first cutting gap 181 is located is also provided with a first pad 141 and a second pad 142. After the array substrate is cut, the first pad 141 and the second pad 142 on the side of the first cutting gap 181 near the side wiring 17 in the first spacing area 133 are left on the first array substrate 100. Because the electrical connection between the gate start wiring 151 and the shift register unit 131 of the first array substrate 100 is disconnected after the array substrate is cut, after the cutting is completed, the first pad 141 and the second pad 142 of the shift register unit 131 near the first cutting gap 181 need to be connected, so that the gate start wiring 151 transmits the gate start signal to the first shift register unit 131 in the cascaded shift register units 131, so as to realize the forward direction scanning of the first array substrate 100. The first array substrate 100 is used as a target array substrate of the corresponding specification required by the user, and the target array substrate is subsequently formed into a display panel to facilitate the preparation of the spliced ​​screen. Optionally, the first pad 141 and the second pad 142 can be electrically connected through a connection layer 195 formed by silver paste or conductive ink. The first pad 141 and the second pad 142 can expose the metal structure layer, so that the operator can electrically connect the metal structure layers of the two through silver paste or conductive ink. Exemplarily, in this embodiment, the silver paste method can be used to dispense glue between the first pad 141 and the second pad 142 for short circuit, ensuring that the STV signal after cutting is introduced from the top of the first array substrate 100 (the first shift register unit 131).

[0051] Figure 7 Another partial cross-sectional structural schematic diagram provided for an embodiment of the present invention, optionally, in a direction perpendicular to the substrate 11, the first pad 141 and the second pad 142 may include multiple structural layers 19; adjacent structural layers 19 are electrically connected; the structural layer 19 farthest from the substrate 11 among the multiple structural layers 19 is an exposed structural layer 191; the exposed structural layer 191 of the first pad 141 disposed near the first cutting gap 181 of the first array substrate 100 is electrically connected to the exposed structural layer 191 of the second pad 142. Figure 7 As shown, multiple structural layers 19 may be provided on the substrate 11, and the first pad 141 and the second pad 142 include multiple structural layers 19. The multiple structural layers 19 can reduce the resistance of the pad, and the multiple structural layers 19 include an exposed structural layer 191. After the array substrate is cut, the exposed structural layer 191 in the first pad 141 and the second pad 142 can be electrically connected through a connection layer 195 of silver paste or conductive ink material. An organic or inorganic insulating layer is provided between adjacent structural layers 19 to achieve insulation. Figure 7Optionally, in the direction away from the substrate 11, the area of ​​the structural layer 19 can be successively increased to further reduce the pad resistance, and the exposed structural layer 191 is the layer with the largest area among the multiple structural layers 19. When the operator connects the exposed structural layer 191 of the first pad 141 and the second pad 142, the larger exposed structural layer 191 facilitates the electrical connection operation, effectively avoiding the problem of difficult coating process of the connecting layer 195 due to the small area of ​​the exposed structural layer 191.

[0052] Continue to refer Figure 5 and Figure 7 Optionally, the array substrate may include: a first metal layer 21, which is arranged on the substrate 11; the first metal layer 21 includes a first structure layer 192 of a first pad 141 and a second pad 142; a second metal layer 22, which is arranged on a side of the first metal layer 21 away from the substrate 11; the second metal layer 22 includes a second structure layer 193 of the first pad 141 and the second pad 142; a third metal layer 23, which is arranged on a side of the second metal layer 22 away from the substrate 11; the third metal layer 23 includes a third structure layer 194 of the first pad 141 and the second pad 142; a fourth metal layer 24, which is arranged on a side of the third metal layer 23 away from the substrate 11; the fourth metal layer 24 includes an exposed structure layer 191 of the first pad 141 and the second pad 142; wherein the first structure layer 192, the second structure layer 193, the third structure layer 194 and the exposed structure layer 191 are electrically connected in sequence. The substrate 11 of the array substrate includes a first metal layer 21, a second metal layer 22, a third metal layer 23 and a fourth metal layer 24 which are sequentially arranged away from the substrate 1. Each metal layer is provided with a structural layer 19, and the first pad 141 and the second pad 142 can form a stacked structure including four structural layers 19. Specifically, the first metal layer 21 forms a first structural layer 192 of the pad, the second metal layer 22 forms a second structural layer 193 of the pad, the third metal layer 23 forms a third structural layer 194 of the pad, and the fourth metal layer 24 forms an exposed structural layer 191 of the pad. The first structural layer 192, the second structural layer 193, the third structural layer 194 and the exposed structural layer 191 are sequentially electrically connected through through holes to increase the volume of the pad, reduce the impedance value of the pad, and improve the driving display effect of the display panel.

[0053] Continue to refer Figure 7, Optionally, in a plane parallel to the substrate 11, the exposed structure layer 191 may cover the projection of the third structure layer 194, the third structure layer 194 may cover the projection of the second structure layer 193; the second structure layer 193 may cover the projection of the first structure layer 192. In the direction away from the substrate 11, the arrangement area of ​​the structure layer 19 increases successively. If the structure layer 19 includes the first structure layer 192, the second structure layer 193, the third structure layer 194 and the exposed structure layer 191 in sequence, in the direction perpendicular to the substrate 11, the second structure layer 193 covers the first structure layer 192, the third structure layer 194 covers the second structure layer 193, and the exposed structure layer 191 covers the third structure layer 194. In this embodiment, while increasing the volume of the pad and reducing the impedance, the occupied area of ​​each structure layer 19 of the pad in the plane where the substrate 11 is located is reduced as much as possible, thereby increasing the local space of the pixel driving circuit or the shift register unit 131 and other circuits.

[0054] Continue to refer Figure 7 Optionally, the shift register unit 131 and the pixel driving circuit 12 may include a plurality of thin film transistors TFT; the first metal layer 21 further includes a gate layer 211 of the thin film transistor TFT; the second metal layer 22 further includes a source-drain layer 212, a gate start wiring 151 and a cascade wiring 152 of the thin film transistor TFT. In this embodiment, a driving circuit layer is formed on the substrate 11, and the driving circuit layer includes a shift register unit 131 and a pixel driving circuit 12, and the shift register unit 131 and the pixel driving circuit 12 are both composed of a plurality of thin film transistors TFT. The thin film transistor TFT includes an active layer 210, a gate layer 211 and a source-drain layer 212 which are sequentially away from the substrate 11. The gate layer 211 can be arranged on the first metal layer 21, and the source-drain layer 212 can be arranged on the second metal layer 22. In addition, the second metal layer 22 may also be provided with a gate start line 151 and a cascade line 152. The gate start line 151 may be electrically connected to the second structure layer 193 of the first pad 141 through the second metal layer 22, and the cascade line 152 may be electrically connected to the second structure layer 193 of the second pad 142 through the second metal layer 22. In addition, the array substrate may be provided with a light-emitting element to form a display panel. For example, Figure 7 As shown, the thin film transistor TFT of the array substrate can be electrically connected to the light emitting element 31 through the connection wires on the third metal layer 23 and the fourth metal layer 24. Figure 7 The light emitting element 31 is illustrated by taking a MicroLED chip as an example, but in this embodiment, the light emitting element 31 includes but is not limited to a MicroLED chip, and may also be an OLED, an LED, or a MicroLED.

[0055] Figure 8A schematic diagram of the structure of another array substrate provided by an embodiment of the present invention, optionally, along the second direction X, the cascade wiring 152 can be arranged between the gate start wiring 151 and the shift register unit 131. The cascade wiring 152 needs to connect two adjacent shift register units 131 along the first direction Y, and the gate start wiring 151 only needs to be electrically connected to the first shift register unit 131 of the cascaded shift register units 131. In order to reduce the cross-line setting, the cascade wiring 152 is arranged between the gate start wiring 151 and the shift register unit 131. On the basis of the above embodiment, if the first pad 141 and the second pad 142 are arranged in the first spacing area 133, optionally, the second pad 142 can be arranged on the side of the first pad 141 away from the gate start line 151; along the first direction Y, the shift register unit 131 on the first side of the first spacing area 133 is connected to the shift register unit 131 on the second side of the first spacing area 133 through the first cascade line 152; the first cascade line 152 includes an extension structure 1521 extending to the first spacing area 133; the extension structure 1521 is electrically connected to the second pad 142. Along the second direction X, the first pad 141 is arranged between the gate start line 151 and the second pad 142, the first pad 141 is arranged close to the gate start line 151, and the second pad 142 is arranged close to the first cascade line 152, so as to reduce the setting of the crossover line and the connecting lead to save the circuit layout space. In addition, the first cascade wiring 152 includes an extension structure 1521 extending to the first spacing region 133, and the extension structure 1521 of the first spacing region 133 can form a pad accommodation space between the gate enable wiring 151 and the cascade wiring 152. Figure 8 As shown, along the second direction X, the gate start wiring 151, the first pad 141, the second pad 142 and the extension structure 1521 are arranged in sequence, or as Fig. 9 As shown, Fig. 9 A schematic structural diagram of another array substrate provided by an embodiment of the present invention, in which along the second direction X, the gate start trace 151, the first pad 141, the extension structure 1521 and the second pad 142 are arranged in sequence. Figure 8 and Fig. 9 The arrangement can reduce the complexity of wiring in the first spacing area 133 while forming a space for accommodating the pad. Figure 8 and Fig. 9 Optionally, the extension structure 1521 may include a first branch 1522 extending along the second direction X, a second branch 1523 along the first direction Y, and a third branch 1524 extending along the second direction X; the first branch 1522, the second branch 1523 and the third branch 1524 are connected in sequence; the second branch 1523 is electrically connected to the second pad 142.

[0056] Fig.10 A schematic diagram of the structure of another array substrate provided in an embodiment of the present invention, optionally, in a plane parallel to the substrate 11, the second pad 142 and the extension structure 1521 may at least partially overlap. In order to further reduce the complexity of wiring in the first spacing area 133, in a direction perpendicular to the substrate 11, the second pad 142 and the extension structure 1521 overlap. Exemplarily, if the second pad 142 includes a first structure layer, a second structure layer, a third structure layer and an exposed structure layer that are sequentially away from the substrate 11, if the extension structure 1521 is arranged in the same layer as the second structure layer, then part of the branches of the extension structure 1521 can be reused as the second structure layer to reduce the wiring arrangement of the metal structure, so as to minimize the area of ​​the first spacing area 133 and improve the arrangement density of the shift register unit 131 and the pixel driving circuit 12.

[0057] Fig.11 A schematic diagram of the structure of another array substrate provided in an embodiment of the present invention, optionally, the display area AA may include a plurality of shift register circuit setting areas AA1 and a plurality of pixel drive circuit setting areas AA2; along the second direction X, the shift register circuit setting areas and the pixel drive circuit setting areas AA2 are alternately arranged. The shift register circuit setting area AA1 includes shift register units 131 cascaded along the first direction Y, and the pixel drive circuit setting area AA2 includes a pixel drive circuit 12 arranged in an array. The pixel drive circuit 12 requires a plurality of scan signals or light-emitting control signals. In this embodiment, a plurality of shift register circuit setting areas AA1 may be arranged, and different shift register circuit setting areas AA1 are used to generate different scan signals or light-emitting control signals. A plurality of shift register circuit setting areas AA1 may be evenly arranged in the display area AA, so as to facilitate the close arrangement of the corresponding pixel drive circuit 12 for the light-emitting element of the display panel, avoid the situation where the light-emitting element and the corresponding pixel drive circuit 12 need to be electrically connected through a longer connecting lead, and effectively reduce the wiring complexity of the display panel. Specifically, the display area AA may include a plurality of shift register circuit setting areas AA1 and a plurality of pixel driving circuit setting areas AA2. Along the second direction X, the shift register circuit setting areas and the pixel driving circuit setting areas AA2 are alternately arranged.

[0058] Fig.12 A schematic diagram of a pixel circuit structure provided by an embodiment of the present invention, optionally, the pixel driving circuit 12 includes: an amplitude modulation module 121 and a pulse width modulation module 122; the amplitude modulation module 121 and the pulse width modulation module 122 are electrically connected; the amplitude modulation module 121 is used to control the amplitude of the driving current; the pulse width modulation module 122 is used to adjust the pulse width of the driving voltage; Fig.13 for Fig.11 The local structure diagram of the area B2 of the array substrate is shown in FIG. Figures 11 to 13, the shift register circuit setting area AA1 includes: a first shift register circuit setting area AA11, including a first shift register unit 1311 arranged in cascade; the first shift register unit 1311 is used to provide a sweep signal SWEEP for the pulse width modulation module 122; a second shift register circuit setting area AA12, including a second shift register unit 1312 arranged in cascade; the second shift register unit 1312 is used to provide a first scan signal PWM_SCAN1 for the pulse width modulation module 122; a third shift register circuit setting area AA13, including a third shift register unit 1313 arranged in cascade; the third shift register unit 1313 is used to provide a second scan signal PWM_SCAN2 for the pulse width modulation module 122; a fourth shift register circuit setting area AA14, including a fourth shift register unit 1314 arranged in cascade ; The fourth shift register unit 1314 is used to provide the first light-emitting control signal PWM_EMIT for the pulse width modulation module 122; the fifth shift register circuit setting area AA15 includes a fifth shift register unit 1315 arranged in cascade; the fifth shift register unit 1315 is used to provide the third scan signal PAM_SCAN1 for the amplitude modulation module 121; the sixth shift register circuit setting area AA16 includes a sixth shift register unit 1316 arranged in cascade; the sixth shift register unit 1316 is used to provide the fourth scan signal PAM_SCAN2 for the amplitude modulation module 121; the seventh shift register circuit setting area AA17 includes a seventh shift register unit 1317 arranged in cascade; the seventh shift register unit 1317 is used to provide the second light-emitting control signal PAM_EMIT for the amplitude modulation module 121. Fig.12This is an example of a pixel driving circuit in the present embodiment. The pixel driving circuit 12 includes an amplitude modulation module 121 and a pulse width modulation module 122. It needs to input at least 7 control signals including a scanning signal SWEEP, a first scanning signal PWM_SCAN1, a second scanning signal PWM_SCAN2, a first light-emitting control signal PWM_EMIT, a third scanning signal PAM_SCAN1, a fourth scanning signal PAM_SCAN2 and a second light-emitting control signal PAM_EMIT. Then, 7 groups of shift register circuit setting areas AA1 can be set accordingly to generate the above-mentioned control signals respectively. In addition, the pixel driving circuit also requires signals such as the first data signal PWM_DATA, the second data signal PAM_DATA, the reset signal VREF, and the first level VDD1. For example, in this embodiment, a reset signal line extending along the second direction X can be formed in the spacing area to provide the reset signal VREF, a first level line to provide the first level VDD1, and a first data line extending along the first direction Y can be formed between adjacent pixel driving circuits 12 to provide PWM_DATA and a second data line to provide PAM_DATA. In addition, a first grid for outputting a PVDD signal and a second grid for outputting a PVEE signal can be arranged on the entire surface, thereby providing a working signal for the pixel driving circuit to enable the pixel driving circuit to output a driving current.

[0059] Optional, such as Fig.11 As shown, the array substrate of this embodiment can be symmetrically arranged, and two shift register circuit setting areas AA1 are arranged for each group and are symmetrically arranged. Exemplarily, two first shift register circuit setting areas AA11 for providing the sweep signal SWEEP can be arranged and are symmetrically arranged about the array substrate. It should be noted that when there are multiple shift register circuit setting areas AA1 on the array substrate, the first pad 141 and the second pad 142 of each shift register circuit setting area AA1 are arranged in the first spacing area 133 containing a preset cutting gap, so as to facilitate cutting the entire array substrate along the second direction X, thereby forming first array substrates of different specifications, so as to prepare splicing screens for various scenes.

[0060] Fig.14 A schematic diagram of a local layout of an array substrate provided by any embodiment of the present invention. Fig.15 for Fig.14Schematic diagram of the enlarged structure of the area B2 of the array substrate in FIG. Optionally, the array substrate may include: a plurality of first signal lines 15 extending along the first direction Y; the first signal lines 15 are electrically connected to the shift register unit 131; at least one first signal line 15 has a hollow or opening in the preset cutting gap 18, and the first signal line 15 is used to provide the shift register unit 131 with the required working signal, including but not limited to the first signal line 15 gate start line 151 and the cascade line 152. There is a first signal line 15 with a hollow or opening in the preset cutting gap 18, for example, Fig.15 As shown, some of the first signal lines 15 are provided with openings 153. When laser cutting is performed along the preset cutting gap 18, the difficulty of cutting the array substrate is reduced, and the first signal line 15 is conveniently disconnected at the preset cutting gap 18. Moreover, the hollowing out or opening pre-forms a partial disconnection design. Therefore, during the cutting process of the array substrate, the first signal line 15 and the insulating layer near it are not easy to form cracks extending to the sub-display area, thereby improving the reliability of the array substrate and facilitating the array substrate to be cut in multiple specifications. Optionally, the first signal line 15 may include at least one of the following: a first level signal line VGH, a second level signal line VGL, a first clock signal line CK, a second clock signal line XCK, a gate start line 151, and a cascade line 152. Any of the above-mentioned first signal lines 15 may be designed with the above-mentioned hollowing out or opening, and this embodiment does not specifically limit this. Optionally, in a plane parallel to the substrate 11, the shape of the hollowing out or opening may be circular, elliptical, rectangular, triangular, rhombus, regular pentagonal, or regular hexagonal, such as Fig.15 As shown, this embodiment is illustrated by taking a rectangular opening 153 as an example. The shapes of the hollow or openings in this embodiment include but are not limited to the shapes listed above.

[0061] Fig.16A schematic diagram of the structure of another array substrate provided in an embodiment of the present invention, optionally, the array substrate may further include: a data line 25 extending along a first direction Y; the data line 25 is electrically connected to a corresponding side wiring 17; the array substrate may further include: an electrostatic protection unit 26, which is arranged on a side of the display area AA close to the side wiring 17; the electrostatic protection unit 26 is used to transfer static electricity on the data line 25. In this embodiment, the display area AA includes a data line 25 extending along the first direction Y, the data line 25 is electrically connected to a corresponding side wiring 17, and the data signal provided by the signal terminal on the non-display side of the array substrate can be obtained through the side wiring 17. In order to improve the accuracy of the data signal and prevent the data signal from being affected by other film layers, it is necessary to provide an electrostatic protection unit 26 for the data line 25 to release and transfer the static electricity of the data line 25. In the prior art, the electrostatic protection unit is arranged at the distal end of the array substrate. In this embodiment, because the distal end of the array substrate away from the side wiring 17 needs to be cut off, the electrostatic protection unit 26 is arranged on the side of the array substrate close to the side wiring 17. After the cutting process is completed, the electrostatic protection unit 26 will not be cut off, so as to avoid the electrostatic failure problem of the target array substrate after cutting, thereby improving the reliability of the target array substrate. For example, Fig.16 As shown, the electrostatic protection unit 26 can be an electrode plate extending along the second direction X, and the electrode plate and the data line 25 are located in different metal structures, thereby generating coupling with the data line 25 and transferring the static electricity on the data line 25. In addition, the electrostatic protection unit 26 can also be an electrostatic protection circuit electrically connected to the data line 25 to export the static electricity on the data line 25. This embodiment does not limit the specific form of the electrostatic protection unit 26.

[0062] Based on the same concept, an embodiment of the present invention further provides a display panel. Fig.17 A schematic diagram of the structure of a first array substrate provided by an embodiment of the present invention is shown in FIG. Fig.17 As shown, the display panel includes: a first array substrate 100; the first array substrate 100 is cut and made by the array substrate provided by any embodiment of the present invention;

[0063] The first array substrate 100 includes: a substrate 11; along the first direction Y, the first array substrate 100 includes a first side L1 and a display area AA; the first side L1 is provided with a side wiring 17; the display area AA includes a shift register circuit setting area AA1 and a pixel driving circuit 12; the pixel driving circuit 12 is arranged in an array; the shift register circuit setting area AA1 includes a plurality of shift register units 131 cascaded along the first direction Y; at least part of the shift register units 131 are correspondingly provided with a first pad 141 and a second pad 142; the shift register circuit setting area AA1 includes a gate start wiring 151 and a cascade wiring 152 extending along the first direction Y; the gate start wiring 151 is electrically connected to the first pad 141; the cascade wiring 152 is used to connect two adjacent shift register units 131; the second pad 142 is electrically connected to the cascade wiring 152;

[0064] A first spacing region 133 including a first cutting gap 181 is disposed on a side of the first array substrate 100 away from the first side L1; the first spacing region 133 extends along the second direction X; the first direction Y intersects with the second direction X and is parallel to the substrate 11; the first pad 141 and the second pad 142 on a side of the first cutting gap 181 close to the first side L1 are electrically connected. Optionally, the first pad 141 and the second pad 142 on a side of the first cutting gap 181 close to the first side L1 may be electrically connected through a connection layer 195 of silver paste or conductive ink material.

[0065] Based on the above embodiments, continue to refer to Fig.17 Optionally, along the first direction Y, a spacing area 132 may be provided between two adjacent shift register units 131; the spacing area 132 includes at least one first spacing area 133; the first pad 141 and the second pad 142 are provided in the first spacing area 133. Of course, the first pad 141 and the second pad 142 may also be provided in the gap between the gate enable wiring 151 and the corresponding shift register unit 131, and the present embodiment does not limit the setting positions of the first pad 141 and the second pad 142.

[0066] In an embodiment of the present invention, the display area of ​​the array substrate includes a shift register circuit setting area and a pixel driving circuit, and the shift register circuit setting area is provided with shift register units cascaded along a first direction, wherein some of the shift register units are correspondingly provided with a first pad and a second pad. The shift register circuit setting area includes a gate start line and a cascade line extending along the first direction, the first pad is electrically connected to the gate start line, and the second pad is electrically connected to the cascade line. Then the array substrate provided in this embodiment can be cut along a direction perpendicular to the first direction, specifically at the position where the shift register unit provided with the first pad and the second pad is located, so that after the array substrate is cut, the first pad and the second pad are electrically connected, so that the start signal output by the gate start line is transmitted to the shift register unit corresponding to the first pad and the second pad, so as to avoid the situation that the electrical connection between the gate start line and the cascaded shift register unit is disconnected due to cutting, and avoid the failure of the array substrate. Furthermore, there may be a plurality of shift register units in the shift register circuit setting area, and the first solder pad and the second solder pad are correspondingly provided. Then, this embodiment can be cut at a plurality of positions along the first direction to form array substrates of different sizes, thereby realizing array substrates of a plurality of specifications without reopening the substrate, so as to meet the needs of splicing screens in different scenarios.

[0067] Optional, continue to refer to Fig.17 , along the first direction Y, the first array substrate 100 may include at least two sub-display areas 16; a first spacing area 133 is provided between adjacent sub-display areas 16; a preset cutting gap 18 is provided in the first spacing area 133; a first cutting gap 181 is provided on the side of the sub-display area 16 farthest from the first side L1 away from the first side L1. It should be noted that in this embodiment, the first cutting gap 181 is the cutting gap at the top of the first array substrate 100, which is the actual cutting gap of the initial array substrate. The preset cutting gap 18 between two adjacent sub-display areas 16 in the first array substrate 100 is a gap that can be cut but is not cut. In this embodiment, by setting a plurality of sub-display areas 16, a first array substrate 100 of the required specifications can be formed. Alternatively, along the first direction Y, the first array substrate 100 may also include one sub-display area 16; a first cutting gap 181 is provided on the side of the sub-display area 16 away from the first side L1. In this embodiment, the first array substrate 100 can be formed by cutting the original array substrate according to the target specification size. The first array substrate 100 of the required size is convenient for the subsequent formation of a display panel of the required size, and finally multiple display panels of the required size are spliced ​​together to form a spliced ​​screen.

[0068] Fig.18 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention. Optionally, the display panel may further include: a light emitting element layer ( Fig.18 (not shown), arranged on the side of the array substrate away from the substrate 11; the light-emitting element layer includes light-emitting elements 31 arranged in an array; the light-emitting element 31 is electrically connected to the corresponding pixel driving circuit 12 of the first array substrate; the first array substrate 100 includes a pixel driving circuit setting area AA2; the pixel driving circuit setting area AA2 includes the pixel driving circuit 12 arranged in an array; the light-emitting element 31 includes a first light-emitting element 311 and a second light-emitting element 312; in a plane parallel to the substrate 11, the first light-emitting element 311 is arranged in the shift register circuit setting area AA1; the second light-emitting element 312 is arranged in the pixel driving circuit setting area AA2; the first light-emitting element 311 is electrically connected to the corresponding pixel driving circuit 12 of the pixel driving circuit setting area AA2 through a first connecting line 32. Fig.18 As shown, the display panel includes a first array substrate and a light-emitting element layer, in order to control the uniform display of the shift register circuit setting area AA1 and the pixel drive circuit setting area AA2. Some light-emitting elements 31 need to be set in the shift register circuit setting area AA1. In this embodiment, the light-emitting element 31 located in the shift register circuit setting area AA1 is referred to as the first light-emitting element 311, and the light-emitting element 31 located in the pixel drive circuit setting area AA2 is referred to as the second light-emitting element 312. The first light-emitting element 311 is electrically connected to the corresponding pixel drive circuit 12 of the pixel drive circuit setting area AA2 through the first connecting line 32. It should be noted that the first light-emitting element 311 in each sub-display area 16 is electrically connected to the pixel drive circuit 12 of the same sub-display area 16, so as to avoid the first connecting line 32 appearing in the first spacing area 133 between adjacent sub-display areas 16. In this embodiment, the setting of the first light-emitting element 311 and its first connecting line 32 effectively reduces the wiring setting of the first spacing area 133, and reduces the process difficulty of the display panel in this embodiment. And it avoids the situation that the first connection line 32 is cut off when cutting to form the first array substrate, effectively avoids the display panel failure, and improves the reliability of the display panel. Optionally, the light emitting element 31 may include a red light emitting element R, a green light emitting element G and a blue light emitting element B.

[0069] An embodiment of the present invention further provides a spliced ​​display screen. Fig.19 A schematic diagram of a spliced ​​display screen provided by an embodiment of the present invention is shown in FIG. Fig.19As shown, the spliced ​​display screen provided by the embodiment of the present invention includes: a plurality of display panels 200 of any embodiment of the present invention; a plurality of display panels 200 are spliced ​​together; a first side L1 (provided with a side wiring 17) of the first array substrate 100 of the display panel 200 serves as the edge of the spliced ​​display screen. The spliced ​​display screen can be a large-size advertising screen in public places such as shopping malls, stations, and airports; it can also be a security monitoring screen for monitoring centers, command centers, etc. that need to display a large number of monitoring images in real time; it can also be a video conferencing screen that can provide a larger field of view and a clearer display effect to enhance the conference experience of participants; this is not specifically limited in the present embodiment. In the present embodiment, the array substrate can be cut into multiple sizes as required to form display panels 200 of different specifications, thereby forming special shapes in special application scenarios. For example, Fig.19 As shown, since the advertising screen needs to cover the entire wall, and the wall is an irregular shape, a plurality of display panels 200 in this embodiment can be spliced ​​together to form an advertising screen to cover the entire wall, giving users a better experience.

[0070] In this embodiment, the spliced ​​display screen includes the technical features of the display panel provided in any embodiment of the present invention, and has the beneficial effects of the corresponding technical features, which will not be described in detail here.

[0071] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. An array substrate, characterized in that: include: substrate; Display area; the display area includes a shift register circuit setting area and a pixel driving circuit; The pixel driving circuit is arranged in an array; the shift register circuit setting area includes a plurality of shift register units cascaded along a first direction; at least part of the shift register units are correspondingly provided with a first pad and a second pad; The shift register circuit setting area includes a gate start line and a cascade line extending along the first direction; the gate start line is electrically connected to the first pad; the cascade line is used to connect two adjacent shift register units; the second pad is electrically connected to the cascade line.

2. The array substrate according to claim 1, characterized in that: Along the first direction, a spacing region is arranged between two adjacent shift register units; the spacing region includes at least one first spacing region; and the first pad and the second pad are arranged in the first spacing region.

3. The array substrate according to claim 2, characterized in that: Along the first direction, the display area includes a first side edge and at least two sub-display areas sequentially arranged away from the first side edge; the first side edge is provided with a side edge wiring; The first spacing area is included between two adjacent sub-display areas; the first spacing area includes a preset cutting gap extending along a second direction; the first direction intersects with the second direction and is parallel to the substrate; The first pad and the second pad are arranged on a side of the preset cutting gap close to the side routing line.

4. The array substrate according to claim 3, characterized in that: The preset cutting gap includes a first cutting gap; after the cutting process is completed along the first cutting gap, the array substrate forms a first array substrate and a second array substrate; The first array substrate includes the side wiring; The first pad and the second pad of the first array substrate disposed near the first cutting gap are electrically connected.

5. The array substrate according to claim 4, characterized in that: The sub-display area includes N shift register units cascaded along the first direction; N is an integer greater than 1; Any preset cutting gap between any two of the sub-display areas can serve as the first cutting gap.

6. The array substrate according to claim 4, characterized in that: The first pad and the second pad are electrically connected via silver paste or conductive ink.

7. The array substrate according to claim 3, characterized in that: The side wiring extends to a side of the substrate away from the shift register unit; A binding area is arranged on one side of the substrate away from the shift register unit; and the side wiring is electrically connected to a corresponding binding pad of the binding area.

8. The array substrate according to claim 4, characterized in that: In a direction perpendicular to the substrate, the first pad and the second pad each include a plurality of structural layers; The adjacent structural layers are electrically connected; the structural layer farthest from the substrate among the multiple structural layers is an exposed structural layer; The exposed structure layer of the first pad disposed near the first cutting gap of the first array substrate is electrically connected to the exposed structure layer of the second pad.

9. The array substrate according to claim 8, characterized in that: In a direction away from the substrate, the areas of the structural layers increase successively.

10. The array substrate according to claim 1, characterized in that: The array substrate comprises: A first metal layer is disposed on the substrate; the first metal layer includes a first structure layer of the first pad and the second pad; A second metal layer is disposed on a side of the first metal layer away from the substrate; the second metal layer includes a second structure layer of the first pad and the second pad; A third metal layer is disposed on a side of the second metal layer away from the substrate; the third metal layer includes a third structure layer of the first pad and the second pad; A fourth metal layer is disposed on a side of the third metal layer away from the substrate; the fourth metal layer includes an exposed structure layer of the first pad and the second pad; Wherein, the first structure layer, the second structure layer, the third structure layer and the exposed structure layer are electrically connected in sequence.

11. The array substrate according to claim 10, characterized in that: In a plane parallel to the substrate, the exposed structure layer covers a projection of the third structure layer, the third structure layer covers a projection of the second structure layer; and the second structure layer covers a projection of the first structure layer.

12. The array substrate according to claim 10, characterized in that: The shift register unit and the pixel driving circuit include a plurality of thin film transistors; The first metal layer also includes a gate layer of the thin film transistor; The second metal layer also includes a source and drain layer of the thin film transistor, the gate enable wiring and the cascade wiring.

13. The array substrate according to claim 2, characterized in that: Along the second direction, the cascade wiring is arranged between the gate enable wiring and the shift register unit.

14. The array substrate according to claim 13, characterized in that: The second pad is arranged on a side of the first pad away from the gate start wiring; Along the first direction, the shift register unit on the first side of the first spacing area is connected to the shift register unit on the second side of the first spacing area through a first cascade wiring; The first cascade trace includes an extension structure extending to the first spacing area; the extension structure is electrically connected to the second pad.

15. The array substrate according to claim 14, characterized in that: The extension structure includes a first branch extending along the second direction, a second branch extending along the first direction, and a third branch extending along the second direction; The first branch, the second branch and the third branch are connected in sequence; the second branch is electrically connected to the second pad.

16. The array substrate according to claim 14, characterized in that: In a plane parallel to the substrate, the second pad at least partially overlaps with the extension structure.

17. The array substrate according to claim 1, characterized in that: The display area includes a plurality of shift register circuit setting areas and a plurality of pixel drive circuit setting areas; Along the second direction, the register circuit setting area and the pixel driving circuit setting area are alternately arranged.

18. The array substrate according to claim 17, characterized in that: The pixel driving circuit comprises: an amplitude modulation module and a pulse width modulation module; the amplitude modulation module and the pulse width modulation module are electrically connected; the amplitude modulation module is used to control the amplitude of the driving current; the pulse width modulation module is used to adjust the pulse width of the driving voltage; The shift register circuit setting area includes: A first shift register circuit setting area includes a first shift register unit arranged in cascade; the first shift register unit is used to provide a sweep frequency signal for the pulse width modulation module; A second shift register circuit setting area includes a second shift register unit arranged in cascade; the second shift register unit is used to provide a first scanning signal for the pulse width modulation module; A third shift register circuit setting area includes a third shift register unit arranged in cascade; the third shift register unit is used to provide a second scanning signal for the pulse width modulation module; A fourth shift register circuit setting area includes a fourth shift register unit arranged in cascade; the fourth shift register unit is used to provide a first light-emitting control signal for the pulse width modulation module; A fifth shift register circuit setting area, comprising a fifth shift register unit arranged in cascade; the fifth shift register unit is used to provide a third scanning signal for the amplitude modulation module; A sixth shift register circuit setting area, comprising a sixth shift register unit arranged in cascade; the sixth shift register unit is used to provide a fourth scanning signal for the amplitude modulation module; The seventh shift register circuit setting area includes a seventh shift register unit arranged in cascade; the seventh shift register unit is used to provide a second light-emitting control signal for the amplitude modulation module.

19. The array substrate according to claim 3, characterized in that: include: A plurality of first signal lines extending along the first direction; the first signal lines are electrically connected to the shift register unit; At least one of the first signal lines has a hollow or opening in the preset cutting gap.

20. The array substrate according to claim 19, characterized in that: The first signal line includes at least one of the following: a first level signal line, a second level signal line, a first clock signal line, a second clock signal line, the gate enable line, and the cascade line.

21. The array substrate according to claim 19, characterized in that: In a plane parallel to the substrate, the shape of the hollow or opening is circular, elliptical, rectangular, triangular, rhombus, regular pentagon or regular hexagon.

22. The array substrate according to claim 3, characterized in that: It also includes a data line extending along the first direction; the data line is electrically connected to the corresponding side wiring; The array substrate further includes: an electrostatic protection unit, which is arranged on a side of the display area close to the side wiring; the electrostatic protection unit is used to transfer static electricity on the data line.

23. A display panel, characterized in that: include: a first array substrate; The first array substrate is made by cutting the array substrate according to any one of claims 1 to 22; The first array substrate comprises: a substrate; Along the first direction, the first array substrate includes a first side and a display area; the first side is provided with a side wiring; the display area includes a shift register circuit setting area and a pixel driving circuit; the pixel driving circuit is arranged in an array; the shift register circuit setting area includes a plurality of shift register units cascaded along the first direction; at least part of the shift register units are correspondingly provided with a first pad and a second pad; the shift register circuit setting area includes a gate start wiring and a cascade wiring extending along the first direction; the gate start wiring is electrically connected to the first pad; the cascade wiring is used to connect two adjacent shift register units; the second pad is electrically connected to the cascade wiring; A first spacing area including a first cutting gap is provided on a side of the first array substrate away from the first side; the first cutting gap extends along a second direction; the first direction intersects with the second direction and is parallel to the substrate; a first solder pad and a second solder pad on a side of the first cutting gap close to the first side are electrically connected.

24. The display panel according to claim 23, characterized in that: Along the first direction, a spacing region is arranged between two adjacent shift register units; the spacing region includes at least one first spacing region; and the first pad and the second pad are arranged in the first spacing region.

25. The display panel according to claim 23, characterized in that: Along the first direction, the first array substrate includes a sub-display area; the first cutting gap is arranged on a side of the sub-display area away from the first side edge; or, Along the first direction, the first array substrate includes at least two sub-display areas; the first spacing area is arranged between adjacent sub-display areas; the first spacing area is arranged with a preset cutting gap; the first cutting gap is arranged on the side of the sub-display area farthest from the first side edge away from the first side edge.

26. The display panel according to claim 23, characterized in that: Also includes: A light emitting element layer is arranged on a side of the array substrate away from the substrate; the light emitting element layer includes light emitting elements arranged in an array; The light emitting element is electrically connected to a corresponding pixel driving circuit of the first array substrate; the first array substrate includes a pixel driving circuit setting area; The pixel driving circuit setting area includes the pixel driving circuits arranged in an array; The light-emitting element comprises a first light-emitting element and a second light-emitting element; In a plane parallel to the substrate, the first light emitting element is arranged in the shift register circuit arrangement area; the second light emitting element is arranged in the pixel driving circuit arrangement area; The first light emitting element is electrically connected to a corresponding pixel driving circuit in the pixel driving circuit setting area through a first connecting line.

27. A spliced ​​display screen, characterized in that: include: The display panel according to any one of claims 23 to 26; A plurality of display panels are spliced ​​together; a first side edge of a first array substrate of the display panel serves as an edge of the spliced ​​display screen.

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