Method, electronic system and electronic device for memory signal timing calibration

Abstract

The invention discloses a memory signal timing calibration method, an electronic system and an electronic device. In some embodiments, the electronic system includes a memory input-output circuit including: a first circuit to generate a first data signal; a second circuit for generating a second data signal; and a first phase control circuit, where the first phase control circuit is configured to perform a phase adjustment of a phase of the second data signal.

Description

[0001] This application claims priority to and the benefit of U.S. Provisional Application No. 63 / 535,542, filed on August 30, 2023, entitled “BACKGROUND DATA STROBE TO DATA SIGNAL (DQS2DQ) CALIBRATION METHOD USING DATA SIGNAL (DQ) TIMING STATISTICS,” and U.S. Patent Application No. 18 / 515,094, filed on November 20, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] One or more aspects of embodiments according to the present disclosure relate to memory functionality, and more particularly, to systems and methods for memory signal timing calibration. Background Art

[0003] In a computing system that includes a memory, the memory may require various support circuits for interfacing with the memory. Such circuits may include address decoding circuits, driver circuits for driving a data bus connected to a processor or to a memory management unit, etc. Such support circuits may perform various functions and ensure optimal performance of the memory. Memory input-output circuits may be employed to generate drive signals for the memory.

[0004] Aspects of the present disclosure are related to this general technical environment. Summary of the invention

[0005] According to an embodiment of the present disclosure, a system is provided, comprising: a memory input-output circuit, comprising: a first circuit for generating a first data signal; a second circuit for generating a second data signal; and a first phase control circuit, the first phase control circuit being configured to perform phase adjustment of the phase of the second data signal.

[0006] In some embodiments, the first phase control circuit includes: a phase interpolator configured to generate a first interpolation signal having a phase between the second data signal and the third data signal.

[0007] In some embodiments, the first phase control circuit includes: a phase interpolator configured to generate a first interpolated signal having a phase between the second data signal and a third data signal, and the third data signal has a phase substantially 90 degrees different from that of the second data signal.

[0008] In some embodiments, the first phase control circuit includes: a phase interpolator configured to generate a first interpolation signal; and the first phase control circuit is configured to: perform an operating mode phase adjustment of the phase of the second data signal based on a value of the second data signal at an edge of the first data signal, a value of the first interpolation signal at an edge of the first data signal, and a value of the third data signal at an edge of the first data signal.

[0009] In some embodiments: the first phase control circuit includes: a phase interpolator configured to generate a first interpolated signal having a phase substantially intermediate between the second data signal and the third data signal; and the first phase control circuit is configured to: perform an operating mode phase adjustment of the phase of the second data signal based on a value of the second data signal at an edge of the first data signal, a value of the first interpolated signal at an edge of the first data signal, and a value of the third data signal at an edge of the first data signal.

[0010] In some embodiments: the first phase control circuit includes: a phase interpolator configured to generate a first interpolated signal having a phase substantially intermediate between the second data signal and the third data signal.

[0011] In some embodiments: the first phase control circuit includes: a phase interpolator configured to generate a first interpolation signal; and the first phase control circuit is configured to: determine that the value of the second data signal at an edge of the first data signal is equal to the first value; determine that the value of the first interpolation signal at an edge of the first data signal is equal to the second value; determine that the value of the third data signal at an edge of the first data signal is equal to the third value; determine that the second value is the same as the first value; determine that the third value is different from the second value; and increase the second counter.

[0012] In some embodiments, the system further includes: a memory unit on the same semiconductor chip as the memory input-output circuit.

[0013] According to an embodiment of the present disclosure, a device is provided, the device comprising: a semiconductor chip including a memory unit and a memory input-output circuit. The memory input-output circuit comprises: a first circuit for generating a first data signal; a second circuit for generating a second data signal; and a first phase control circuit, the first phase control circuit being configured to perform an operation mode phase adjustment of the phase of the second data signal.

[0014] In some embodiments: the first phase control circuit includes: a phase interpolator configured to generate a first interpolation signal having a phase between the second data signal and the third data signal.

[0015] In some embodiments: the first phase control circuit includes: a phase interpolator configured to generate a first interpolated signal having a phase between the second data signal and the third data signal, and the third data signal has a phase substantially 90 degrees different from that of the second data signal.

[0016] In some embodiments: the first phase control circuit includes: a phase interpolator configured to generate a first interpolation signal having a phase between the second data signal and the third data signal; and the first phase control circuit is configured to: perform an operating mode phase adjustment of the phase of the second data signal based on a value of the second data signal at an edge of the first data signal, a value of the first interpolation signal at an edge of the first data signal, and a value of the third data signal at an edge of the first data signal.

[0017] In some embodiments: the first phase control circuit includes: a phase interpolator configured to generate a first interpolated signal having a phase substantially intermediate between the second data signal and the third data signal; and the first phase control circuit is configured to: perform an operating mode phase adjustment of the phase of the second data signal based on a value of the second data signal at an edge of the first data signal, a value of the first interpolated signal at an edge of the first data signal, and a value of the third data signal at an edge of the first data signal.

[0018] In some embodiments: the first phase control circuit includes: a phase interpolator configured to generate a first interpolated signal having a phase substantially intermediate between the second data signal and the third data signal.

[0019] In some embodiments: the first phase control circuit includes: a phase interpolator configured to generate a first interpolation signal; and the first phase control circuit is configured to: determine that the value of the second data signal at an edge of the first data signal is equal to the first value; determine that the value of the first interpolation signal at an edge of the first data signal is equal to the second value; determine that the value of the third data signal at an edge of the first data signal is equal to the third value; determine that the second value is the same as the first value; determine that the third value is different from the second value; and increase the second counter.

[0020] According to an embodiment of the present disclosure, a method is provided, the method comprising: performing an operating mode phase adjustment of the phase of a second data signal by a first phase control circuit of a memory input-output circuit, wherein the memory input-output circuit comprises: a first circuit for generating a first data signal; a second circuit for generating a second data signal; and a first phase control circuit.

[0021] In some embodiments: the first phase control circuit includes a phase interpolator; and the method includes: generating, by the phase interpolator, a first interpolated signal having a phase between the second data signal and the third data signal.

[0022] In some embodiments: the first phase control circuit includes a phase interpolator; and the method includes: generating a first interpolated signal having a phase between the second data signal and the third data signal by the phase interpolator, and the third data signal has a phase that is substantially 90 degrees different from the phase of the second data signal.

[0023] In some embodiments, the first phase control circuit includes a phase interpolator configured to generate a first interpolated signal having a phase substantially intermediate between the second data signal and the third data signal.

[0024] In some embodiments, a semiconductor chip includes a memory input-output circuit and a memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] These and other features and advantages of the present disclosure will be appreciated and understood with reference to the specification, claims and drawings.

[0026] Figure 1 is a system-level block diagram according to an embodiment of the present disclosure.

[0027] Figure 2A is a schematic diagram of a portion of a memory input-output circuit without operating mode phase adjustment according to an embodiment of the present disclosure.

[0028] Figure 2B is a graph of waveforms in a half-rate system according to an embodiment of the present disclosure.

[0029] Figure 2C is a graph of an offset waveform in a half-rate system according to an embodiment of the present disclosure.

[0030] Figure 3A is a schematic diagram of a portion of a memory input-output circuit having a first kind of operating mode phase adjustment according to an embodiment of the present disclosure.

[0031] Figure 3B is a graph of a first set of data waveforms and data strobe waveforms according to an embodiment of the present disclosure.

[0032] Figure 4A is a schematic diagram of a portion of a memory input-output circuit having a second kind of operating mode phase adjustment according to an embodiment of the present disclosure.

[0033] Figure 4B is a graph of a second set of data waveforms and data strobe waveforms according to an embodiment of the present disclosure.

[0034] Figure 4C is a schematic diagram of a portion of a memory input-output circuit for determining a phase error delta according to an embodiment of the present disclosure.

[0035] Figure 4D is a schematic diagram of a portion of a memory input-output circuit with a second kind of operating mode phase adjustment showing a feedback path according to an embodiment of the present disclosure.

[0036] Figure 5 is a schematic diagram of a portion of a memory input-output circuit having a third kind of operating mode phase adjustment according to an embodiment of the present disclosure.

[0037] Figure 6 is a flow chart of a method for memory signal calibration according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] The specific embodiments described below in conjunction with the accompanying drawings are intended as a description of exemplary embodiments of the system and method for memory signal timing calibration provided according to the present disclosure, and are not intended to represent the only form in which the present disclosure can be constructed or utilized. The description describes the features of the present disclosure in conjunction with the illustrated embodiments. However, it will be understood that the same or equivalent functions and structures can be implemented by different embodiments that are also intended to be included in the scope of the disclosure. As indicated elsewhere herein, the same element numbers are intended to indicate the same elements or features.

[0039] In a computing system, a memory input-output circuit may generate a drive signal for a memory (e.g., for a dynamic random access memory). Such a drive signal may include a data signal (e.g., carrying data to be written) and a data strobe signal (whose edge may be used to latch the data into the memory (e.g., into a memory cell of the memory)). The data signal and the data strobe signal may follow different signal paths (e.g., propagate on different signal paths).

[0040] Therefore, if the temperature of the memory input-output circuit changes or if the power supply voltage (VDD) of the memory input-output circuit changes, the delay change in the data signal (caused by the temperature change or the change in the power supply voltage) may be different from the delay change in the data strobe signal (caused by the temperature change or the change in the power supply voltage). If the differential delay change is large enough and is not compensated, it may cause a write error in a write operation performed on the memory as a result of, for example, a setup time violation or a hold time violation.

[0041] Therefore, a host including a central processing unit (CPU), a memory, and a memory input-output circuit may periodically (e.g., at startup and periodically thereafter, or when a temperature change or a power supply voltage change is detected by the host) perform calibration. For example, such calibration may be performed in a calibration mode by performing a series of memory write operations while adjusting a delay of a data strobe signal relative to a data signal within a certain delay range, and setting an operation mode delay to a value halfway between the shortest delay for performing a successful write operation and the longest delay for performing a successful write operation.

[0042] However, such an approach may have the following disadvantages: (i) when the memory input-output circuit is in the calibration mode, memory accesses in response to storage instructions executed by the host's central processor may not be performed, (ii) frequent calibration may thereby degrade the performance of the host, or (iii) if the temperature change rate or the power supply voltage change rate is large enough, infrequent calibration may bring the risk of write errors.

[0043] Therefore, it may be advantageous to perform calibration (e.g., phase adjustment of a data strobe signal) in an operating mode. As used herein, an "operating mode" is a mode in which a memory write operation is performed for the purpose of writing data (and not merely for performing calibration). Such phase adjustment of a data strobe signal may be performed by a circuit that may be referred to as a data strobe phase control circuit as follows.

[0044] In a system with a quarter rate clock, four data strobe signals including a first data strobe signal and a second data strobe signal that are 90 degrees out of phase with each other may be used, with the second data strobe signal lagging the first data strobe signal by 90 degrees. For write operations with a low risk of causing write errors, the edges in the data signals may be centered between the edges of the first data strobe signal and the edges of the second data strobe signal.

[0045] An interpolated signal may be generated from the first data selection signal and the second data selection signal (e.g., using a phase interpolator), e.g., the interpolated signal having an edge between the first data selection signal and the second data selection signal (e.g., halfway between the first data selection signal and the second data selection signal) such that a phase of the interpolated signal lags behind a phase of the first data selection signal by 45 degrees.

[0046] If the phases of the first data strobe signal and the second data strobe signal are such that the write operation will have a low risk of causing a write error, the edge of the interpolation signal may coincide with the edge of the data signal. Therefore, if the edge of the interpolation signal leads (e.g., precedes) the corresponding edge of the data signal (indicating that the edge of the interpolation signal occurs too early and therefore the phase of the first data strobe signal and the phase of the second data strobe signal are advanced too far), the data strobe phase control circuit may delay the first data strobe signal and the second data strobe signal; if the edge of the interpolation signal lags behind (e.g., follows) the corresponding edge of the data signal, the data strobe phase control circuit may advance the phase of the first data strobe signal and the phase of the second data strobe signal in response.

[0047] A determination may be made based on sampling of the first data strobe signal, the interpolated signal, and the second data strobe signal with an edge of the data signal (i.e., taken at an edge of the data signal) to determine whether an edge of the interpolated signal precedes or lags a corresponding edge of the data signal. If (i) the sampling of the first data strobe signal with an edge of the data signal has a first value, (ii) the sampling of the first interpolated signal with an edge of the data signal has a second value, (iii) the sampling of the second data strobe signal with an edge of the data signal has a third value, (iv) the second value is different from the first value, and (v) the third value is the same as the second value, the data strobe phase control circuit may infer that the interpolated signal lags (e.g., follows) a corresponding edge of the data signal, and in response, the data strobe phase control circuit may advance a phase of the first data strobe signal and a phase of the second data strobe signal.

[0048] If (i) sampling of the first data strobe signal utilizing an edge of the data signal has a first value, (ii) sampling of the first interpolated signal utilizing an edge of the data signal has a second value, (iii) sampling of the second data strobe signal utilizing an edge of the data signal has a third value, (iv) the second value is the same as the first value, and (v) the third value is different from the second value, the data strobe phase control circuit may infer that the interpolated signal leads (e.g., precedes) the corresponding edge of the data signal, and in response, the data strobe phase control circuit may delay the phase of the first data strobe signal and the phase of the second data strobe signal.

[0049] If (i) sampling of the first data strobe signal utilizing an edge of the data signal has a first value, (ii) sampling of the first interpolation signal utilizing an edge of the data signal has a second value, (iii) sampling of the second data strobe signal utilizing an edge of the data signal has a third value, (iv) the second value is the same as the first value, and (v) the third value is the same as the second value, the data strobe phase control circuit may take no action and leave the phase of the first data strobe signal and the phase of the second data strobe signal unchanged.

[0050] Figure 1 A system-level block diagram of a host 100 is shown, which includes a central processing unit (CPU) 105, a memory management unit 110, and a system memory (or memory) (e.g., dynamic random access memory (DRAM) 120), and the memory management unit 110 includes a memory input-output circuit 115. In some embodiments, the dynamic random access memory 120 is remote from the CPU. In some embodiments, for some applications (e.g., some mobile applications), the dynamic random access memory 120 is close to the CPU.

[0051] like Figure 2A As shown in , the memory input-output circuit 115 may include a first differential amplifier 205-1 (or, amplifier 205-1) and a second differential amplifier 205-2 (or, amplifier 205-2), the first differential amplifier 205-1 receiving clock signals CK and CKB and followed by a first frequency divider (e.g., a first toggle flip-flop (T flip-flop)) 210-1 (or, / 2 210-1) to generate a half-rate clock signal, and the second differential amplifier 205-2 receiving data strobe signals DQS and DQSB and followed by a second frequency divider (e.g., a second toggle flip-flop (T flip-flop)) 210-2 (or, / 2 210-2) to generate two half-rate data strobe signals (in Figure 2A Two half-rate data strobe signals can be used to control two D flip-flops 220 (in Figure 2A In the figure, only one D flip-flop 220 is shown for clock control, and the two D flip-flops 220 receive and latch the data signal DQ1 after the data signal DQ1 is filtered by the continuous time linear equalizer (CTLE), and can output the latched data signal DQ1_out. The circuit that generates the data strobe signal may be referred to as a "data strobe signal generating circuit" or a "second circuit".

[0052] If the edge of the data strobe signal DQS is Figure 2BIf the relative phase of the data signal DQ1 and the data strobe signal DQS is such that the edge of the data strobe signal DQS is such that the edge of the data strobe signal DQS is such that the edge of the data signal DQ1 is such that the edge of the data signal DQ1 is such that the edge of the data signal DQ2 is such that the edge of the data signal DQ3 is such that the edge of the data signal DQ4 is such that the edge of the data signal DQ5 is such that the edge of the data signal DQ6 is such that the edge of the data signal DQ7 is such that the edge of the data signal DQ8 is such that the edge of the data signal DQ9 is such that the edge of the data signal DQ1 ... Figure 2C does not fall in the middle between the edges of the data signal DQ1 (for example, Figure 2C The data strobe signal in Figure 2B The data strobe signal Δt in 1 ,and Figure 2C The data signal in the Figure 2B The data signal Δt in 2 ), errors may occur in latching of the data signal (eg, because a setup time requirement or a hold time requirement may not be met).

[0053] Reference Figure 3A In one embodiment, a first differential amplifier 205-1 followed by a first frequency divider 210-1 generates a quarter rate clock signal, and a second differential amplifier 210-2 followed by a second frequency divider 210-2 generates four quarter rate data strobe signals. Two delay circuits (one following the first frequency divider 210-1 (which may be referred to as delay circuit 305-1 or delay 305-1), and one (which may be referred to as data strobe delay circuit 305-2 or delay 305-2) following the second frequency divider 210-2) adjust the delay of the signals propagating through them. For example, the data strobe delay circuit 305-2 may adjust the common mode delay of the four quarter rate data strobe signals (e.g., it may adjust the phase of each of the four quarter rate data strobe signals by the same amount). The four quarter rate data strobe signals may clock four D flip-flops 220, which receive and latch the data signal after it is filtered by a continuous time linear equalizer (CTLE) 215.

[0054] A phase interpolator (PI) 310 generates an interpolated signal from a first data strobe signal (which may have a phase defined as zero degrees, and which may also be referred to as a "second data signal") and a second data strobe signal (which may have a phase delayed by 90 degrees relative to the first data strobe signal (orthogonal to the first data strobe signal), and which may be referred to as a "third data signal"). The interpolated signal may have a phase that is substantially midway between the phase of the first data strobe signal and the phase of the second data strobe signal (e.g., within a first amount midway between the phase of the first data strobe signal and the phase of the second data strobe signal, where the first amount is between 0 degrees and 35 degrees). In some embodiments, the interpolated signal is within 10 degrees midway between the phase of the first data strobe signal and the phase of the second data strobe signal. In some embodiments, the setup time of the D flip-flop 220 is greater than or less than the hold time of the D flip-flop 220, and the nominal phase of the interpolated signal is selected so that the setup time margin is equal to the hold time margin.

[0055] The sampling trigger 315 (which may be a D flip-flop) is used to sample the interpolation signal using the rising edge of the data signal (at or near the corresponding rising edge of the interpolation signal). As used herein, "using" the edge of the second signal to sample the first signal means obtaining a sample of the first signal at a sampling time defined by the edge of the second signal. As used herein, the value of the first signal at the edge of the second signal means the value of the first signal when the edge appears in the second signal.

[0056] In some embodiments, the data signal (DQ1), the first data strobe signal DQS0, the second data strobe signal DQS90, and the interpolation signal DQS45 are Figure 3B At time t 1 , the interpolation signal is sampled using the data signal. The sampled value obtained in this manner may indicate: (i) if the sampled value is 1, the edge in the interpolation signal leads the edge in the data signal (indicating that the phase of the first data strobe signal and the phase of the second data strobe signal should be delayed), or (ii) if the sampled value is 0, the edge in the interpolation signal lags the edge in the data signal (indicating that the phase of the first data strobe signal and the phase of the second data strobe signal should be advanced). Therefore, in such an embodiment, the data strobe phase control circuit (which may also be referred to as a "phase control circuit") may adjust (e.g., advance or delay) the phase of the first data strobe signal and the second data strobe signal based on the sampled value. As used herein, the data strobe phase control circuit includes a portion of the circuit "for detecting a phase error of the data strobe signal relative to the data signal and providing feedback (e.g., feedback to the data strobe delay circuit 305) to reduce the phase error."

[0057] However, in Figure 3A and 3B In the embodiment of the present invention, other samples (i) obtained by the rising edge (e.g., at t 2 The samples obtained at t may not be helpful for adjusting the phase of the first data strobe signal and the phase of the second data strobe signal, or (ii) (e.g., at t 3 The samples obtained at t 1 The samples obtained are opposite to the results. Therefore, in some embodiments, additional circuits can be used to discard samples that do not coincide with (or almost coincide with) the rising edge in the interpolated signal. Figure 3B In the embodiment, the time at which t 3 Opportunity to measure the relative phase of the data signal and the interpolated signal.

[0058] Figure 4A A portion of a memory input-output circuit in some embodiments is shown. Figure 3A As in the embodiment of , the phase interpolator (PI) 310 generates an interpolation signal from four data strobe signals (e.g., from the first data strobe signal and the second data strobe signal) output by the data strobe delay circuit 305-2. Three sampling flip-flops 315 (which may be D flip-flops) are used to sample each of (i) the first data strobe signal, (ii) the interpolation signal, and (iii) the second data strobe signal using the rising edge of the data signal to form: (i) sampling of the first data strobe signal using the edge of the first data signal, (ii) sampling of the interpolation signal using the edge of the first data signal, and (iii) sampling of the second data strobe signal using the edge of the first data signal. In Figure 4A In the embodiment, the combination of the second differential amplifier 205-2, the second frequency divider 210-2 and the data strobe delay circuit 305-2 may be referred to as a "data strobe signal generating circuit", and the CTLE may be referred to as a "data signal generating circuit" or as a "first circuit".

[0059] Reference Figure 4B , Figure 4C and Figure 4D , then, the data strobe phase control circuit may advance the value of the first counter (which may be referred to as the late counter d_late) or the second counter (which may be referred to as the early counter d_early) according to whether the sampling indicates whether the edge in the interpolation signal is late or early (and therefore whether the edges in the first data strobe signal and the second data strobe signal are late or early). Whether the edge in the interpolation signal and the edges in the first data strobe signal and the second data strobe signal are late or early may be determined based on the sampling, and then the phase of each of the data strobe signals may be adjusted accordingly by the data strobe phase control circuit.

[0060] The determination may be performed as follows. In a first scenario, the data strobe phase control circuit may (i) determine that a sample of the first data strobe signal using an edge of the first data signal has a first value, (ii) determine that a sample of the interpolated signal using an edge of the first data signal has a second value, (iii) determine that a sample of the second data strobe signal using an edge of the first data signal has a third value, (iv) determine that the second value is different from the first value (e.g., determine that DQS0≠DQS45), and (v) determine that the third value is the same as the second value (e.g., determine that DQS45=DQS90). Based on these determinations, the data strobe phase control circuit may increase the value of the first counter (late counter).

[0061] In the second case, the data strobe phase control circuit may (i) determine that the sampling of the first data strobe signal using the edge of the first data signal has a first value, (ii) determine that the sampling of the interpolation signal using the edge of the first data signal has a second value, (iii) determine that the sampling of the second data strobe signal using the edge of the first data signal has a third value, (iv) determine that the second value is the same as the first value (e.g., determine that DQS0=DQS45), and (v) determine that the third value is different from the second value (e.g., determine that DQS45≠DQS90). Based on these determinations, the data strobe phase control circuit may increase the value of the second counter (early counter).

[0062] This method can be effectively Figure 4B Time t 1 and time t 3 Both make the appropriate counter change (eg, increment the value of the first counter or the second counter). If all three samples are identical (as is the case at time t2), the value of the counter may not be incremented. Figure 4C Circuitry is shown that can be used to increment the value of the first counter 405 or the second counter 410 based on the samples. In some embodiments, an OR gate can be used instead of the exclusive-OR gate shown to function similarly. Figure 4D Shown with Figure 4A Similar to the circuit of the phase error detection logic 415 (or detection logic 415) (which may include, for example Figure 4C ) shows that the phase adjustment signal DQ1_pd (eg, DQ1_pd90, DQ1_pd45, and DQ1_pd0) is fed back to the delay circuit 305 (which is Figure 4D ( ) are explicitly shown as adjustable. In some embodiments, Figure 4A , Figure 4C and Figure 4DThe circuit may be generalized (e.g., by including an additional phase interpolator for generating a second interpolated signal that is 90 degrees out of phase with the interpolated signal, and by sampling at both the rising and falling edges of the data signal) to perform phase error measurements at additional time points (e.g., at additional edges in the data signal).

[0063] like Figure 5 As shown in , in order to improve the signal-to-noise ratio of phase error detection, relative phase measurements performed on multiple bits (e.g., 8 bits) can be combined. A majority vote (regarding whether to advance or delay the phase of the data strobe signal) can be determined in the voting circuit 505, and the result can be used to adjust the phase of all delay circuits 305. For example, each of the eight data paths (e.g., DQ1 to DQ8) can count the values ​​d_early and d_late of the counters for each write event, and after each write enable goes low, the delay code controlling the delay circuit 305 can be updated according to the majority vote of whether the phase should be advanced or delayed.

[0064] In some embodiments, the memory input-output circuit is manufactured on the same semiconductor chip as the memory for which the memory input-output circuit generates a drive signal. Some embodiments enable the memory input-output circuit to correct for process, power supply voltage and temperature (PVT) changes online (e.g., in operating mode). Some embodiments may be used with any other standard in which the system uses a clock forwarding scheme, the burst length is short, and the system is not configured to continuously run clock and data recovery (CDR). Such a system has many parallel signal paths that share a clock source, and the system can save power and periodically run such calibration to follow temperature and voltage changes. Some embodiments may be applied to Universal Chiplet Interconnect Express (UCIe), Graphic Double Data Rate Synchronous Dynamic Random Access Memory (GDDR), Low Power Double Data Rate Memory (LPDDR), and High Bandwidth Memory (HBM).

[0065] Figure 6is a flow chart of a method in some embodiments. The method includes: at 610, performing an operation mode phase adjustment of the phase of the second data signal by a first phase control circuit of a memory input-output circuit, wherein the memory input-output circuit includes: a first circuit for generating a first data signal; a second circuit for generating a second data signal; and a first phase control circuit. In some embodiments: the first phase control circuit includes a phase interpolator; and the method includes: generating a first interpolation signal having a phase between the second data signal and the third data signal by the phase interpolator. In some embodiments: the first phase control circuit includes a phase interpolator, and the method includes: generating a first interpolation signal having a phase between the second data signal and the third data signal by the phase interpolator, and the third data signal has a phase substantially 90 degrees different from the phase of the second data signal. In some embodiments, the first phase control circuit includes: a phase interpolator configured to generate a first interpolation signal having a phase substantially intermediate between the second data signal and the third data signal. In some embodiments, the semiconductor chip includes a memory input-output circuit and a memory cell.

[0066] As used herein, "a portion" of something means "at least some" of the thing, and thus may mean less than all of the thing or all of the thing. Thus, "a portion" of a thing includes the entire thing as a special case (i.e., an example where the entire thing is a portion of the thing). As used herein, when a second amount is "within Y" of a first amount X, it means that the second amount is at least XY, and the second amount is at most X+Y. As used herein, when a second quantity is "within Y%" of a first quantity, it means that the second quantity is at least (1-Y / 100) times the first quantity, and the second quantity is at most (1+Y / 100) times the first quantity. As used herein, the term "or" should be interpreted as "and / or", so that, for example, "A or B" means any one of "A", "B", and "A and B".

[0067] The background provided in the Background section of this disclosure is included to set context only, and the contents of this section are not admitted to be prior art. Any component or combination of components described (e.g., in any system diagram included herein) may be used to perform one or more of the operations of any flowchart included herein. In addition, (i) the operations are example operations and may involve various additional steps that are not explicitly covered, and (ii) the chronological order of the operations may vary.

[0068] Each of the terms "processing circuitry" and "means for processing" is used herein to refer to any combination of hardware, firmware, and software employed to process data or digital signals. Processing circuit hardware may include, for example, an application specific integrated circuit (ASIC), a general or dedicated central processing unit (CPU), a digital signal processor (DSP), a graphics processing unit (GPU), and a programmable logic device (such as a field programmable gate array (FPGA)). In a processing circuit, as used herein, each function is performed by hardware that is configured (i.e., hardwired) to perform that function, or by more general hardware (such as a CPU) that is configured to execute instructions stored in a non-transitory storage medium. The processing circuit may be manufactured on a single printed circuit board (PCB) or distributed across several interconnected PCBs. The processing circuit may contain other processing circuits; for example, the processing circuit may include two processing circuits (FPGA and CPU) interconnected on a PCB.

[0069] As used herein, when a method (e.g., an adjustment) or a first quantity (e.g., a first variable) is referred to as being “based on” a second quantity (e.g., a second variable), it means that the second quantity is an input to the method or the second quantity affects the first quantity (e.g., the second quantity may be an input (e.g., the only input or one of several inputs) to a function that calculates the first quantity, or the first quantity may be equal to the second quantity, or the first quantity may be the same as the second quantity (e.g., stored at the same location or locations in memory as the second quantity)).

[0070] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the spirit and scope of the inventive concept, the first element, first component, first region, first layer or first part discussed herein may be referred to as the second element, second component, second region, second layer or second part.

[0071] For ease of description, spatial relative terms (such as "below", "below", "lower", "under", "above", "upper", etc.) may be used herein to describe the relationship between an element or feature and another (one or more) element or (one or more) feature as shown in the figure. It will be understood that such spatial relative terms are intended to cover different directions of the device in use or in operation in addition to the directions depicted in the figure. For example, if the device in the figure is turned over, the elements described as "below" or "below" or "below" of other elements or features will be oriented to be "above" other elements or features. Therefore, the example terms "below" and "below" can cover the orientation above and below. The device can be oriented in other ways (for example, rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intermediate layers may also be present.

[0072] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the inventive concept. As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation rather than terms of degree, and are intended to account for the inherent deviations in measurements or calculations that one of ordinary skill in the art would recognize.

[0073] As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. It will also be understood that the terms "include" and / or "comprising" specify the existence of stated features, wholes, steps, operations, elements and / or components when used in this specification, but do not exclude the existence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Statements such as "at least one of ..." modify the entire column of elements when following a column of elements without modifying the single element in the column. In addition, the use of "may" when describing the embodiment of the inventive concept represents "one or more embodiments of the present disclosure". In addition, the term "exemplary" is intended to represent an example or description. As used herein, the terms "use", "being used", "being used" can be considered to be synonymous with the terms "utilize", "being utilized", "being utilized", respectively.

[0074] It will be understood that when an element or layer is referred to as being “on,” “connected to,” “bound to,” or “adjacent to” another element or layer, it may be directly on, directly connected to, directly bound to, or immediately adjacent to the other element or layer, or one or more intervening elements or layers may be present. In contrast, when an element or layer is referred to as being “directly on,” “directly connected to,” “directly bound to,” or “immediately adjacent to” another element or layer, there are no intervening elements or layers present.

[0075] Any numerical range recited herein is intended to include all subranges within the recited range that fall within the same numerical precision. For example, a range of "1.0 to 10.0" or "between 1.0 and 10.0" is intended to include all subranges between the recited minimum value of 1.0 and the recited maximum value of 10.0 (and including the recited minimum value of 1.0 and the recited maximum value of 10.0), i.e., having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0 (such as, for example, 2.4 to 7.6). Similarly, a range described as "within 35% of 10" is intended to include all subranges between (and including) the recited minimum value of 6.5 (i.e., (1-35 / 100) times 10) and the recited maximum value of 13.5 (i.e., (1+35 / 100) times 10), i.e., having a minimum value equal to or greater than 6.5 and a maximum value equal to or less than 13.5 (such as, for example, 7.4 to 10.6). Any maximum numerical limitation recited herein is intended to include all lower numerical limitations subsumed therein, and any minimum numerical limitation recited in this specification is intended to include all higher numerical limitations subsumed therein.

[0076] Some embodiments may include features of the following numbered statements.

[0077] 1. An electronic system comprising: A memory input-output circuit comprising: A first circuit, configured to generate a first data signal; A second circuit for generating a second data signal; and A first phase control circuit, The first phase control circuit is configured to perform phase adjustment of the phase of the second data signal.

[0078] 2. The electronic system of statement 1, wherein the first phase control circuit comprises: a phase interpolator configured to generate a first interpolated signal having a phase between the second data signal and the third data signal.

[0079] 3. An electronic system as described in statement 1 or statement 2, wherein: The first phase control circuit includes: a phase interpolator configured to generate a first interpolation signal having a phase between the second data signal and the third data signal; and The third data signal has a phase that is ninety degrees different from that of the second data signal.

[0080] 4. An electronic system according to any of the preceding statements, wherein: The first phase control circuit includes: a phase interpolator configured to generate a first interpolation signal; and The first phase control circuit is configured to perform an operating mode phase adjustment of the phase of the second data signal based on a value of the second data signal at an edge of the first data signal, a value of the first interpolated signal at an edge of the first data signal, and a value of the third data signal at an edge of the first data signal.

[0081] 5. An electronic system according to any of the preceding statements, wherein: The first phase control circuit includes: a phase interpolator configured to generate a first interpolation signal having a phase intermediate between the second data signal and the third data signal; and The first phase control circuit is configured to perform an operating mode phase adjustment of the phase of the second data signal based on a value of the second data signal at an edge of the first data signal, a value of the first interpolated signal at an edge of the first data signal, and a value of the third data signal at an edge of the first data signal.

[0082] 6. An electronic system according to any of the preceding statements, wherein: The first phase control circuit includes a phase interpolator configured to generate a first interpolation signal having a phase intermediate between the second data signal and the third data signal.

[0083] 7. An electronic system according to any of the preceding statements, wherein: The first phase control circuit includes: a phase interpolator configured to generate a first interpolation signal; and The first phase control circuit is configured as: determining that a value of the second data signal at an edge of the first data signal is equal to the first value; determining that a value of the first interpolation signal at an edge of the first data signal is equal to a second value; determining that a value of the third data signal at an edge of the first data signal is equal to a third value; determining that the second value is the same as the first value; determining that the third value is different from the second value; and Increase the counter value.

[0084] 8. The electronic system according to any of the preceding statements, further comprising: a memory unit on the same semiconductor chip as the memory input-output circuit.

[0085] 9. An electronic device comprising: Semiconductor chips, including: memory unit, and memory input-output circuit; Wherein, the memory input-output circuit includes: A first circuit, configured to generate a first data signal; A second circuit for generating a second data signal; and A first phase control circuit, The first phase control circuit is configured to perform an operation mode phase adjustment of the phase of the second data signal.

[0086] 10. The electronic device of statement 9, wherein the first phase control circuit comprises: a phase interpolator configured to generate a first interpolated signal having a phase between the second data signal and the third data signal.

[0087] 11. An electronic device according to statement 9 or statement 10, wherein: The first phase control circuit includes: a phase interpolator configured to generate a first interpolation signal having a phase between the second data signal and the third data signal; and The third data signal has a phase that is ninety degrees different from that of the second data signal.

[0088] 12. An electronic device according to any one of statements 9 to 11, wherein: The first phase control circuit includes: a phase interpolator configured to generate a first interpolation signal having a phase between the second data signal and the third data signal; and The first phase control circuit is configured to perform an operating mode phase adjustment of the phase of the second data signal based on a value of the second data signal at an edge of the first data signal, a value of the first interpolated signal at an edge of the first data signal, and a value of the third data signal at an edge of the first data signal.

[0089] 13. An electronic device according to any one of statements 9 to 12, wherein: The first phase control circuit includes: a phase interpolator configured to generate a first interpolation signal having a phase intermediate between the second data signal and the third data signal; and The first phase control circuit is configured to perform an operating mode phase adjustment of the phase of the second data signal based on a value of the second data signal at an edge of the first data signal, a value of the first interpolated signal at an edge of the first data signal, and a value of the third data signal at an edge of the first data signal.

[0090] 14. An electronic device according to any one of statements 9 to 13, wherein: The first phase control circuit includes a phase interpolator configured to generate a first interpolation signal having a phase intermediate between the second data signal and the third data signal.

[0091] 15. An electronic device according to any one of statements 9 to 14, wherein: The first phase control circuit includes: a phase interpolator configured to generate a first interpolation signal; and The first phase control circuit is configured as: determining that a value of the second data signal at an edge of the first data signal is equal to the first value; determining that a value of the first interpolation signal at an edge of the first data signal is equal to a second value; determining that a value of the third data signal at an edge of the first data signal is equal to a third value; determining that the second value is the same as the first value; determining that the third value is different from the second value; and Increase the value of the counter.

[0092] 16. A method for memory signal timing calibration, comprising: an operation mode phase adjustment of the phase of the second data signal performed by a first phase control circuit of the memory input-output circuit, Wherein, the memory input-output circuit includes: A first circuit, configured to generate a first data signal; A second circuit for generating a second data signal; and A first phase control circuit.

[0093] 17. The method of statement 16, wherein: The first phase control circuit includes a phase interpolator; and The method also includes generating, by a phase interpolator, a first interpolated signal having a phase between the second data signal and the third data signal.

[0094] 18. The method of statement 16 or statement 17, wherein: The first phase control circuit includes a phase interpolator; and The method further includes: generating, by a phase interpolator, a first interpolation signal having a phase between the second data signal and the third data signal; and The third data signal has a phase that is ninety degrees different from that of the second data signal.

[0095] 19. A method according to any one of statements 16 to 18, wherein the first phase control circuit comprises: a phase interpolator configured to generate a first interpolated signal having a phase intermediate between the second data signal and the third data signal.

[0096] 20. A method according to any of statements 16 to 19, wherein the semiconductor chip comprises a memory input-output circuit and a memory cell.

[0097] Although exemplary embodiments of systems and methods for memory signal calibration have been specifically described and illustrated herein, many modifications and variations will be apparent to those skilled in the art. Therefore, it should be understood that systems and methods for memory signal calibration constructed in accordance with the principles of the present disclosure may be implemented differently than as specifically described herein. The invention is also defined in the appended claims and their equivalents.

Claims

1. An electronic system comprising: A memory input-output circuit comprising: A first circuit, configured to generate a first data signal; A second circuit for generating a second data signal; and A first phase control circuit, The first phase control circuit is configured to perform phase adjustment of the phase of the second data signal.

2. The electronic system as claimed in claim 1, wherein: The first phase control circuit includes a phase interpolator configured to generate a first interpolation signal having a phase between the second data signal and the third data signal.

3. The electronic system of claim 1, wherein: The first phase control circuit includes: a phase interpolator configured to generate a first interpolation signal having a phase between the second data signal and the third data signal; and The third data signal has a phase that is ninety degrees different from that of the second data signal.

4. The electronic system of claim 1, wherein: The first phase control circuit includes: a phase interpolator configured to generate a first interpolation signal; and The first phase control circuit is configured to perform an operating mode phase adjustment of the phase of the second data signal based on a value of the second data signal at an edge of the first data signal, a value of the first interpolated signal at an edge of the first data signal, and a value of the third data signal at an edge of the first data signal.

5. The electronic system of claim 1, wherein: The first phase control circuit includes: a phase interpolator configured to generate a first interpolation signal having a phase intermediate between the second data signal and the third data signal; and The first phase control circuit is configured to perform an operating mode phase adjustment of the phase of the second data signal based on: a value of the second data signal at an edge of the first data signal, a value of the first interpolated signal at an edge of the first data signal, and a value of the third data signal at an edge of the first data signal.

6. The electronic system of claim 1, wherein: The first phase control circuit includes a phase interpolator configured to generate a first interpolation signal having a phase intermediate between the second data signal and the third data signal.

7. The electronic system according to any one of claims 1 to 6, wherein: The first phase control circuit includes: a phase interpolator configured to generate a first interpolation signal; and The first phase control circuit is configured as: determining that a value of the second data signal at an edge of the first data signal is equal to the first value; determining that a value of the first interpolation signal at an edge of the first data signal is equal to a second value; determining that a value of the third data signal at an edge of the first data signal is equal to a third value; determining that the second value is the same as the first value; determining that the third value is different from the second value; and Increase the value of the counter.

8. The electronic system according to any one of claims 1 to 6, further comprising: A memory cell is on the same semiconductor chip as the memory input-output circuits.

9. An electronic device comprising: Semiconductor chips, including: memory unit, and Memory input-output circuits, Wherein, the memory input-output circuit includes: A first circuit, configured to generate a first data signal; A second circuit for generating a second data signal; and A first phase control circuit, The first phase control circuit is configured to perform an operation mode phase adjustment of the phase of the second data signal.

10. The electronic device according to claim 9, wherein: The first phase control circuit includes a phase interpolator configured to generate a first interpolation signal having a phase between the second data signal and the third data signal.

11. The electronic device of claim 9, wherein: The first phase control circuit includes: a phase interpolator configured to generate a first interpolation signal having a phase between the second data signal and the third data signal; and The third data signal has a phase that is ninety degrees different from that of the second data signal.

12. The apparatus of claim 9, wherein: The first phase control circuit includes: a phase interpolator configured to generate a first interpolation signal having a phase between the second data signal and the third data signal; and The first phase control circuit is configured to perform an operating mode phase adjustment of the phase of the second data signal based on a value of the second data signal at an edge of the first data signal, a value of the first interpolated signal at an edge of the first data signal, and a value of the third data signal at an edge of the first data signal.

13. The electronic device of claim 9, wherein: The first phase control circuit includes: a phase interpolator configured to generate a first interpolation signal having a phase intermediate between the second data signal and the third data signal; and The first phase control circuit is configured to perform an operating mode phase adjustment of the phase of the second data signal based on a value of the second data signal at an edge of the first data signal, a value of the first interpolated signal at an edge of the first data signal, and a value of the third data signal at an edge of the first data signal.

14. The electronic device of claim 9, wherein: The first phase control circuit includes a phase interpolator configured to generate a first interpolation signal having a phase intermediate between the second data signal and the third data signal.

15. The electronic device according to any one of claims 9 to 14, wherein: The first phase control circuit includes: a phase interpolator configured to generate a first interpolation signal; and The first phase control circuit is configured as: determining that a value of the second data signal at an edge of the first data signal is equal to the first value; determining that a value of the first interpolation signal at an edge of the first data signal is equal to a second value; determining that a value of the third data signal at an edge of the first data signal is equal to a third value; determining that the second value is the same as the first value; determining that the third value is different from the second value; and Increase the value of the counter.

16. A method for memory signal timing calibration, comprising: an operation mode phase adjustment of the phase of the second data signal performed by a first phase control circuit of the memory input-output circuit, Wherein, the memory input-output circuit includes: A first circuit, configured to generate a first data signal; A second circuit for generating a second data signal; and A first phase control circuit.

17. The method of claim 16, wherein: The first phase control circuit includes a phase interpolator; and The method also includes generating, by a phase interpolator, a first interpolated signal having a phase between the second data signal and the third data signal.

18. The method of claim 16, wherein: The first phase control circuit includes a phase interpolator; and The method further includes: generating, by a phase interpolator, a first interpolation signal having a phase between the second data signal and the third data signal; and The third data signal has a phase that is ninety degrees different from that of the second data signal.

19. The method according to claim 16, wherein: The first phase control circuit includes a phase interpolator configured to generate a first interpolation signal having a phase intermediate between the second data signal and the third data signal.

20. The method according to any one of claims 16 to 19, wherein: The semiconductor chip includes a memory input-output circuit and a memory cell.

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