Memory device and operating method thereof

Abstract

The invention relates to a memory device and an operating method of the memory device. An example memory device includes a first bank, a second bank, and a cache controller. The cache controller is configured to set a hash function based on a power control signal including an instruction to stop supplying power to the first bank, and map the first address, the second bank, and a first transaction provided by the master device after the power control signal is input based on the hash function.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0115276 filed on August 31, 2023, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2023-0164516 filed on November 23, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a memory device and a method of operating the memory device. Background Art

[0003] Semiconductor memories are widely used to store data in various electronic devices such as computers and wireless communication devices. Among static random access memories (RAMs) (SRAMs) as a type of semiconductor memory, single-port SRAMs and dual-port SRAMs capable of performing read and write operations at higher speeds than single-port SRAMs have been developed. In a typical single-port SRAM, one unit memory cell may include six transistors that perform read and write operations sequentially, while a dual-port SRAM may be configured to perform read and write operations in a dual mode by adding two active transistors to a typical single-port SRAM to be used in an integrated circuit requiring ultra-high speed. Summary of the invention

[0004] The present disclosure relates to an electronic device and an operating method of a memory device for improving operation accuracy, reliability of the electronic device, performance degradation due to cache miss, power outage time, operation time of a flush operation, response time, etc.

[0005] In general, according to some aspects, a memory device includes: a first memory body, configured to: receive power and store at least one cache line corresponding to a first address group; a second memory body, configured to: receive power and store at least one cache line corresponding to a second address group; and a cache controller, configured to: set a hash function based on a power control signal, and map the first address and the second memory body based on the hash function, a first address provided by a master device after the power control signal is input, and a first transaction including a first target indicating the first memory body, the power control signal commands to suspend the supply of power to the first memory body.

[0006] In general, according to some aspects, a memory device includes: a first memory body, configured to receive power in response to a power control signal commanding power to be supplied; a second memory body, configured to store at least one first cache line corresponding to a first address group, and to store at least one second cache line corresponding to a second address group, the first address group being provided before the first memory body receives power; and a cache controller, configured to set a hash function based on the power control signal, and map the first address to the first memory body based on the hash function, a first address provided by a master device after the power control signal is input, and a first transaction including a second target indicating the second memory body.

[0007] In general, according to some aspects, a method for operating a memory device includes: in response to a power control signal commanding whether to supply power to a first memory group, flushing a cache line in a selected memory group among a first memory group and a second memory group; forwarding cache lines to be mapped to an unselected memory group among cache lines stored in the selected memory group to an unselected memory group based on a hash function selected from a plurality of hash functions according to the power control signal and a transaction provided by a master device, the plurality of hash functions being different from each other; and providing a response signal notifying the master device of a change in the hash function of the master device to the master device.

[0008] In general, according to some aspects, an electronic device includes: a power manager configured to generate power and output a power control signal commanding whether to supply power; a memory including a first storage body group, a second storage body group and a cache controller, the cache controller being configured to: set a hash function in response to the power control signal; and map a first address corresponding to the first storage body group to a storage body group selected from the first storage body group and the second storage body group according to the power control signal based on the hash function; and a processor including a first hash function and a second hash function, the first hash function being configured to output a first target indicating the first storage body group from the first address group and a second target indicating the second storage body group from the second address group, the second hash function being configured to output a second target from the second address group, and the processor being configured to provide a transaction including the first address to the memory based on the hash function selected from the first hash function and the second hash function. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0010] Figure 1 is a block diagram of an example of an electronic device.

[0011] Figure 2A , Figure 2B and Figure 2C is an example graph used to describe a hash function.

[0012] Figure 3 and Figure 4 is an example diagram of a transaction provided by a master device.

[0013] Figure 5 , Figure 6 and Figure 7 is a diagram of the operation of an example of an electronic device.

[0014] Figure 8 , Fig. 9 and Fig.10 is a diagram of the operation of an example of an electronic device.

[0015] Fig.11 is a flowchart of an example of a forwarding operation of a memory.

[0016] Fig.12 is a block diagram of an example of a memory bank.

[0017] Fig.13 is a circuit diagram of an example of a memory cell.

[0018] Fig.14 is a flow chart of an example of a method of operating a memory device. DETAILED DESCRIPTION

[0019] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0020] Figure 1 is a block diagram of an example of the electronic device 10 .

[0021] Reference Figure 1 , the electronic device 10 may be included in a mobile device such as a smart phone and a wearable device, and in this case, the electronic device 10 may be implemented as an application processor (AP) or a system on a chip (SoC). However, the embodiment is not limited thereto, and the electronic device 10 may be included in a computing device such as a personal computer (PC), a tablet PC, and a server.

[0022] The electronic device 10 may include a processor 110 , a memory device 120 , and a power manager 130 .

[0023] The processor 110 may include a device capable of processing data (such as a central processing unit (CPU), a neural processing unit (NPU), a graphics processing unit (GPU), and an AP). The processor 110 may execute an operating system (OS) and / or various applications. The processor 110 may send a transaction requesting a specific operation to be performed to the memory device 120. In addition, the processor 110 may receive a response to the transaction from the memory device 120. For example, the processor 110 may send a transaction including a read request and an address to the memory device 120, and the memory device 120 may read data stored in a memory area corresponding to the address. However, the embodiment is not limited thereto. In some embodiments, in order to transmit a transaction to any one of the first memory bank 122_1 to the (n)th memory bank 122_n of the memory device 120, the processor 110 may provide a target and a transaction indicating a specific memory bank to the memory device 120 by using a hash function and a transaction stored in the processor 110. The processor 110 may be referred to as a master device.

[0024] The memory device 120 may perform operations by receiving power from the power manager 130. The memory device 120 may be referred to as a memory. The memory device 120 may include a cache controller 121 and a first memory bank 122_1 to an (n)th memory bank 122_n. The cache controller 121 may receive a transaction from the processor 110. The cache controller 121 may transmit the transaction to a corresponding memory bank to access a memory bank corresponding to an address included in the transaction. In some embodiments, the cache controller 121 may set a hash function in response to a power control signal, and may map a first address corresponding to a first memory bank group to a memory bank group selected from among the first memory bank group and the second memory bank group according to the power control signal based on the hash function. The first memory bank group and the second memory bank group may receive power from the power manager 130 to operate independently. The first memory bank group may include at least one of the first memory bank 122_1 to the (n)th memory bank 122_n. The second memory bank group may include the remaining memory banks except at least one of the first memory bank 122_1 to the (n)th memory bank 122_n of the first memory bank group. In an embodiment, the first memory bank group may include at least one memory bank capable of interrupting power supply when the electronic device 10 is turned on, and the second memory bank group may include at least one memory bank designed to always supply power when the electronic device 10 is turned on. The power control signal may be generated by the power manager 130. The power control signal may indicate whether power is to be supplied to the first memory bank group. The number of the first memory bank 122_1 to the (n)th memory bank 122_n may be n. n may be an integer of 2 or greater. Each of the first memory bank 122_1 to the (n)th memory bank 122_n may receive power generated by the power manager 130 and may operate independently. A memory bank may also be referred to as a slice.

[0025] In some embodiments, the memory device 120 may be implemented as a static random access memory (RAM) (SRAM). The SRAM may be used as a cache in a computing device. In order to increase the throughput of the data throughput per unit time representing the cache, an independently operable memory structure may be applied to the SRAM. The memory structure may be a structure in which a plurality of caches are partitioned so that each partition is accessed simultaneously. When the SRAM of the memory structure requires relatively low performance, the power of some memory banks may be disconnected to save power. On the other hand, when the SRAM of the memory structure requires high performance, power may be supplied to the memory bank in which the power has been disconnected. When the power mode is converted, the cache line mapped to the power-off memory bank may need to be redirected to the power-on memory bank. In addition, in order to ensure normal operation, the operation of the processor 110 may also need to be stopped when the necessary tasks are being completed before the power mode is switched from the previous power mode to the new current power mode. In this way, the time at which the operation of the processor 110 is completed before the power mode is switched may be referred to as the blackout time. When the blackout time increases, because the time for processing the operation of the processor 110 may be delayed, it may be necessary to reduce the blackout time.

[0026] The power manager 130 may generate power. The power generated by the power manager 130 may be supplied to the processor 110 and / or the memory device 120. In some embodiments, the power generated by the power manager 130 may be supplied to at least one of the first memory bank 122_1 to the (n)th memory bank 122_n. The power manager 130 may output a power control signal indicating whether power is supplied to a first memory bank group among the first memory bank 122_1 to the (n)th memory bank 122_n. In some embodiments, the power manager 130 may output a power control signal indicating whether power to be supplied to at least one memory bank is supplied (e.g., disconnected or connected). In some embodiments, the power manager 130 may output a power control signal that points to a first mode, a second mode, or a third mode, in which power is supplied only to a specific memory bank (e.g., the first memory bank 122_1) among the first memory bank 122_1 to the (n)th memory bank 122_n, in which power is supplied only to a preset number (e.g., n / 2) of memory banks among the first memory bank 122_1 to the (n)th memory bank 122_n, and in which power is supplied to the first memory bank 122_1 to the (n)th memory bank 122_n in the third mode. According to some embodiments, the power manager 130 may be implemented as a power management unit (PMU).

[0027] The memory device 120 of the present disclosure can reduce power outage time while improving performance degradation in a system that controls power-performance balance by using dynamic cache size adaptation. The memory device 120 of the present disclosure can be implemented as an L1 cache or an L2 cache of a CPU, or can also be implemented as an L3 cache of a CPU cluster. Optionally, the memory device 120 of the present disclosure can be implemented as a cache embedded in a GPU or NPU and as a last level cache (LLC) present in a bus interconnect. Optionally, the memory device 120 of the present disclosure can be implemented as an L3 cache including four or more memory banks, and the four or more memory banks support multiple master devices via multiple cores and multiple ports in a CPU cluster used in a SoC of a mobile device.

[0028] According to some of the above-mentioned embodiments, in the electronic device 10, the accuracy of the operation of the electronic device 10 can be improved, failures can be prevented, the reliability of the electronic device 10 can be improved, performance degradation due to cache misses can be prevented, power outage time can be reduced, the operation time of the flush operation can be reduced, and the response time of the electronic device 10 can be improved.

[0029] Figure 2A , Figure 2B and Figure 2C is an example graph describing a hash function.

[0030] Reference Figure 1 , Figure 2A , Figure 2B and Figure 2C , each of the processor 110 and the cache controller 121 may set the hash function by selecting any one of the plurality of hash functions 210. In some embodiments, after the cache controller 121 changes the hash function, the processor 110 may change the hash function. For example, the cache controller 121 may change the hash function among the plurality of hash functions 210 according to the power control signal of the power manager 130, the processor 110 may receive a response signal (or confirmation signal) from the cache controller 121, and may change the hash function among the plurality of hash functions 210 according to the response signal of the cache controller 121.

[0031] The cache controller 121 may select any one hash function from the plurality of hash functions 210 according to the power control signal of the power manager 130, the processor 110 may receive a response signal (or confirmation signal) from the cache controller 121, and may select any one hash function from the plurality of hash functions 210 according to the response signal of the cache controller 121. The plurality of memory banks may include first to third memory banks 220_1 to 220_3 (or referred to as memory banks 1 220_1 to 3 220_3), and the plurality of hash functions 210 may include first to third hash functions 211 to 213. However, the embodiment is not limited thereto.

[0032] Each address group may be input to a hash function, and a target indicating a storage body may be output as an output of the hash function. In some embodiments, the address included in each address group may include information required to identify whether a block in the cache is requested by the processor 110, and may include a tag field and an index field, the tag field including a high bit of the address, and the index field including an index value indicating a specific path among multiple paths. The address may also include an offset field, the offset field including an offset value. In this case, the tag field and the index field may be input to the hash function.

[0033] In some embodiments, the power control signal may command that power is supplied to at least one of the plurality of storage bodies. For example, the power control signal may command that power is supplied to only one of the first storage body 220_1 to the third storage body 220_3. As another example, the power control signal may command that power is supplied to only two of the first storage body 220_1 to the third storage body 220_3. As another example, the power control signal may command that power is supplied to all of the first storage body 220_1 to the third storage body 220_3. According to some embodiments, the first storage body group may include the first storage body 220_1 and the second storage body 220_2, and the second storage body group may include the third storage body 220_3. In some embodiments, the power control signal may also command that power is stopped from being supplied to one storage body or two storage bodies among the three storage bodies. In the following, it is assumed that the power control signal commands that power is supplied to at least one storage body.

[0034] Reference Figure 2A, the first hash function 211 may be selected from the plurality of hash functions 210. In some embodiments, when the first to third memory banks 220_1 to 220_3 are all powered on, the processor 110 and the cache controller 121 may select the first hash function 211. The first hash function 211 may receive the first address group ADDa and output the first target TGT1 indicating the first memory bank 220_1 (or representing the first memory bank 220_1) to the first memory bank 220_1. Optionally, the first hash function 211 may receive the second address group ADDb and output the second target TGT2 indicating the second memory bank 220_2 to the second memory bank 220_2. Optionally, the first hash function 211 may receive the third address group ADDc and output the third target TGT3 indicating the third memory bank 220_3 to the third memory bank 220_3.

[0035] Reference Figure 2B , the second hash function 212 may be selected from the plurality of hash functions 210. In some embodiments, one of the first to third memory banks 220_1 to 220_3 may be powered off. For example, the power supplied to the first memory bank 220_1 may be stopped. Because the power supply to the first memory bank 220_1 has been stopped, the first address group ADDa may need to be remapped to the second memory bank 220_2 or the third memory bank 220_3 other than the first memory bank 220_1. For example, the first address group ADDa may include a plurality of first addresses (e.g., ADDa1, ADDa2, ADDa3, and ADDa4), some of the first addresses (e.g., ADDa1 and ADDa2) among the plurality of first addresses (e.g., ADDa1, ADDa2, ADDa3, and ADDa4) may be mapped to the second memory bank 220_2, and other first addresses (e.g., ADDa3 and ADDa4) among the plurality of first addresses (e.g., ADDa1, ADDa2, ADDa3, and ADDa4) may be mapped to the third memory bank 220_3. The embodiment of mapping some addresses to the memory bank is not limited to Figure 2B, and can be designed in various ways. It is shown that the number of first addresses (e.g., ADDa1, ADDa2, ADDa3, and ADDa4) can be four, but this is only an example. In some embodiments, when the first storage body 220_1 is powered off, the processor 110 and the cache controller 121 may select the second hash function 212. Similar to the first hash function 211, the second hash function 212 may receive the second address group ADDb or the third address group ADDc, and output the second target TGT2 or the third target TGT3 to the second storage body 220_2 or the third storage body 220_3, respectively. Optionally, the second hash function 212 may receive each of some of the first addresses ADDa1 and ADDa2, and output the second target TGT2 to the second storage body 220_2. Optionally, the second hash function 212 may receive each of the other of the first addresses ADDa3 and ADDa4, and output the third target TGT3 to the third storage body 220_3.

[0036] Reference Figure 2C , a third hash function 213 may be selected from among the plurality of hash functions 210 .

[0037] In some embodiments, two of the first memory bank 220_1 to the third memory bank 220_3 may be powered off. For example, the power supplied to the first memory bank 220_1 and the second memory bank 220_2 may be stopped, and the power may be supplied only to the third memory bank 220_3. Because the power supplied to the first memory bank 220_1 and the second memory bank 220_2 has been stopped, it may be necessary to remap the first address group ADDa and the second address group ADDb to the third memory bank 220_3. In some embodiments, when the first memory bank 220_1 and the second memory bank 220_2 are powered off, the processor 110 and the cache controller 121 may select the third hash function 213. The third hash function 213 may receive the first address group ADDa, the second address group ADDb, or the third address group ADDc, and output the third target TGT3 to the third memory bank 220_3. In this way, when the power supplied to at least one memory bank is stopped, a specific address group may be remapped to a memory bank different from the previously mapped memory bank.

[0038] Although not shown, the processor 110 and / or the cache controller 121 may further include an arbitrator for delivering an address (or a transaction including an address) to a memory bank according to a target.

[0039] Figure 3 and Figure 4 is an example diagram of a master device 310 providing a transaction to a memory device 320 . Figure 3is a diagram of a path through which a transaction is sent to a memory device 320 when the host device 310 selects the first hash function 211, and Figure 4 2 is a diagram of a path through which a transaction is sent to the memory device 320 when the master device 310 selects the second hash function 212. In the following, for ease of description, it is assumed that the number of hash functions and memory banks is two. Figure 3 and Figure 4 Each implementation method of .

[0040] Reference Figure 3 and Figure 4 , the main device 310 included in the electronic device 30 may correspond to Figure 1 The processor 110 in the main device 310 may include a first hash function (H1) 311 and a second hash function (H2) 312. The memory device 320 included in the electronic device 30 may correspond to Figure 1 The memory device 320 may include a first memory bank (memory bank 1) 330_1 and a second memory bank (memory bank 2) 330_2. Figure 3 and Figure 4 , the memory device 320 is shown as including two memory banks, but is not limited thereto. The first memory bank 330_1 may be included in the first memory bank group as a memory bank capable of stopping power supply, and the second memory bank 330_2 may be included in the second memory bank group as at least one memory bank designed to always supply power when the memory device 320 is turned on. The host device 310 may select any one hash function from a plurality of hash functions, input the address of the transaction into the selected hash function, and determine to which of the first memory bank 330_1 and the second memory bank 330_2 of the memory device 320 the transaction is arbitrated.

[0041] In some embodiments, at least one of the first memory bank 330_1 and the second memory bank 330_2 may include a cache controller. For example, the first memory bank 330_1 may include a cache controller 331_1, and the second memory bank 330_2 may include a cache controller 331_2. Each cache controller may include a first hash function and a second hash function. For example, the cache controller 331_1 may include a first hash function 332_1 and a second hash function 333_1, and the cache controller 331_2 may include a first hash function 332_2 and a second hash function 333_2.

[0042] Each of the first memory bank 330_1 and the second memory bank 330_2 may include a path group. For example, the first memory bank 330_1 may include a path group 334_1, and the second memory bank 330_2 may include a path group 334_2. Each path group may include a plurality of paths. For example, each of the path group 334_1 and the path group 334_2 may include a first path way1 to a fourth path way4 (or referred to as a first path WAY1 to a fourth path WAY4). Figure 3 and Figure 4 , each of the first memory bank 330_1 and the second memory bank 330_2 is shown as including four paths, but is not limited thereto. The paths of the path group 334_1 may include cache lines corresponding to the first addresses included in the first address group ADDa, respectively, and the paths of the path group 334_2 may include cache lines corresponding to the second addresses included in the second address group ADDb, respectively. Tags and data may be stored in each cache line. For example, in the path group 334_1, tags TAG_a1, TAG_a2, and TAG_a3 of the first address group ADDa and data DATA_a1, DATA_a2, and DATA_a3 may be stored. In this case, the tag TAG_a1 may indicate an address (e.g., ADDa1) included in the first address group ADDa, the tag TAG_a2 may indicate an address (e.g., ADDa2) included in the first address group, and the tag TAG_a3 may indicate an address (e.g., ADDa3) included in the first address group. For example, in the way group 334_2, tags TAG_b1, TAG_b2, and TAG_b3 and data DATA_b1, DATA_b2, and DATA_b3 of the second address group ADDb may be stored. The tags TAG_b1, TAG_b2, and TAG_b3 may indicate the second addresses (eg, ADDb1, ADDb2, and ADDb3), respectively.

[0043] Reference Figure 3 , the master device 310 may select the first hash function 311. The master device 310 may arbitrate the first transaction TXNa to the first memory bank 330_1 by using the first hash function 311. In other words, the first transaction TXNa may be transmitted to the first memory bank 330_1, and the first transaction TXNa may include the arbitrated first address ADDai, the request, and the first target TGT1. The master device 310 may arbitrate the second transaction TXNb to the second memory bank 330_2 by using the first hash function 311. In other words, the second transaction TXNb may be transmitted to the second memory bank 330_2, and the second transaction TXNb may include the arbitrated second address ADDbi, the request, and the second target TGT2.

[0044] Reference Figure 4, the master device 310 may select the second hash function 312. The master device 310 may transmit the first transaction TXNa to the second memory bank 330_2 of the memory device 320 by using the second hash function 312. Alternatively, the master device 310 may transmit the second transaction TXNb to the second memory bank 330_2 of the memory device 320 by using the second hash function 312. The path through which the first transaction TXNa is arbitrated to the memory bank may be referred to as an “A path”, and the path through which the second transaction TXNb is arbitrated to the memory bank may be referred to as a “B path”.

[0045] The memory device 320 implemented as a cache memory can determine which memory bank is to be assigned an address (or a cache line) by performing a hash function based on the address of the cache line using a request arbitration logic. Therefore, the memory banks assigned according to the address mode can be classified. To this end, each of the cache controllers 331_1 and 331_2 may include an allocation determination logic configured to determine whether to assign an address to a memory bank, and a forwarding logic configured to forward a cache line stored in a specific memory bank to another memory bank.

[0046] Figure 5 , Figure 6 and Figure 7 is a diagram of the operation of an example of the electronic device 30 .

[0047] Reference Figure 5 , Figure 6 and Figure 7 , the first memory bank 330_1 may be included in the first memory bank group. The first memory bank 330_1 may receive power PWR and store at least one cache line corresponding to the first address group ADDa. The second memory bank 330_2 may be included in the second memory bank group. At least one cache line corresponding to the second address group ADDb may be stored by receiving power PWR. The cache controller 331_1 may set a hash function in response to a power control signal pointing to stop supplying power to the first memory bank 330_1, and map the first address ADDai to the second memory bank 330_2 based on the hash function and the first transaction TXNa. In this case, the first transaction TXNa may be provided from the main device 310 after the above-mentioned power control signal is input, and may include the first address ADDai and the first target TGT1.

[0048] Reference Figure 5, the master device 310 may select the first hash function 311. The master device 310 may output the first transaction TXNa to the memory device 320 based on the first hash function 311, so that the first transaction TXNa is transmitted to the first memory bank 330_1. According to the first hash function 311 of the master device 310, the first transaction TXNa may be transmitted to the first memory bank 330_1 through the A path (A ROUTE), and the second transaction TXNb may be transmitted to the second memory bank 330_2 through the B path (B ROUTE). On the other hand, the first power control signal PCS1 may be input to the memory device 320. The first power control signal PCS1 may be generated by the power manager 130, and may point to stop supplying the power PWR to the first memory bank group. When some memory banks (e.g., the first memory bank 330_1) enter the power-off mode, the hash function may be changed so that tags TAG_a1, TAG_a2, and TAG_a3 and data DATA_a1, DATA_a2, and DATA_a3 stored in the cache lines (e.g., the first path to the third path way1, way2, and way3) previously allocated to the first memory bank 330_1 are allocated to the memory bank (e.g., the second memory bank 330_2) that is powered on. For example, the cache controller 331_1 may select the second hash function 333_1 from the first hash function 332_1 and the second hash function 333_1 in response to the first power control signal PCS1. In another example, the cache controller 331_1 may change the hash function from the first hash function 332_1 to the second hash function 333_1 in response to the first power control signal PCS1. On the other hand, the master device 310 may maintain the first hash function 311 for a specific period of time even after the first power control signal PCS1 is input.

[0049] Reference Figure 6, the cache controller 331_1 may perform a flush operation on the way group 334_1 of the first memory bank 330_1 by using the second hash function 333_1. The cache line stored in the way group 334_1 may be flushed FLH. The flush operation may include an operation of reading a tag of a cache line stored in the memory bank, and an operation of moving and storing data of the cache line stored in the memory bank in a memory or storage device on a layer lower than the memory device 320 by using information included in the tag. The layers of the memory may include a register included in a processor, an L1 cache, an L2 cache, an L3 cache, a main memory, an auxiliary storage device, and the like. For example, when the memory device 320 is an L1 cache, a memory device located at a layer lower than the memory device 320 may include an L2 cache, an L3 cache, or a main memory, and a storage device located at a layer lower than the memory device 320 may include an auxiliary storage device. However, the embodiment is not limited thereto. The main memory may include, for example, double data rate (DDR) synchronous DRAM (SDRAM) (DDR SDRAM), low power DDR (LPDDR) SDRAM (LPDR SDRAM), graphic DDR (GDDR) SDRAM (GDDR SDRAM), rambus DRAM (RDRAM), etc. The auxiliary storage device may correspond to a memory card, a PC card, a compact flash card, a smart media card, a memory stick, a multimedia card, a secure digital (SD) card, a universal flash device, a hard disk drive (HDD), a solid state disk / drive (SSD), etc.

[0050] On the other hand, when the flush operation to the first memory bank 330_1 is being performed, the master device 310 may be running and outputting a transaction to the memory device 320. In other words, the cache controller 331_1 that performs the flush operation may receive a transaction from the master device 310. In this case, because the hash function included in the master device 310 is the first hash function 311, the master device 310 may provide the first transaction TXNa to the first memory bank 330_1. The first address group ADDa included in the first transaction TXNa may not belong to the first memory bank 330_1. In this case, the cache controller 331_1 may map the second memory bank 330_2 to the first address group ADDa based on the second hash function 333_1 and the first address group ADDa, and perform a forwarding FWD operation to the second memory bank 330_2 for the first transaction TXNa. In some embodiments, the forwarding FWD operation may include: an operation of determining whether a transaction including an address group that no longer belongs to a memory bank that is powered off has a cache hit, and an operation of generating a new transaction so that the corresponding address group is forwarded to a memory bank that is powered on. For example, a first transaction TXNa including a first address ADDa3 and a first target TGT1 may be provided to a cache controller 331_1 that performs a flush operation. Because a cache line including a tag TAG_a3 and data DATA_a3 is stored in a way group 334_1, the cache controller 331_1 may determine that the first transaction TXNa has a cache hit. In addition, the cache controller 331_1 may output the data DATA_a3 to the master device 310 in response to the cache hit. In addition, the cache controller 331_1 may input the first address ADDa3 to the second hash function 333_1, and may generate a second target TGT2 indicating the second memory bank 330_2. The cache controller 331_1 may generate a new transaction including a storage request commanding a cache line to be stored, including the first address ADDa3, the second target TGT2, and the tag TAG_a3 and the data DATA_a3. The transaction generated by the cache controller 331_1 may be referred to as an internal transaction. The cache controller 331_1 may provide the internal transaction to the master device 310, or perform a forwarding FWD operation to the second memory bank 330_2 for the internal transaction. On the other hand, the cache controller 331_1 may invalidate a cache line (e.g., tag TAG_a3 and data DATA_a3) stored in the third way way3 of the way group 334_1. As another example, a first transaction TXNa including a first address ADDa4 and a first target TGT1 may be provided to the cache controller 331_1 that performs a flush operation. Because the cache line corresponding to the first address ADDa4 is not stored in the way group 334_1, the cache controller 331_1 may determine that the first transaction TXNa has become a cache miss.In addition, the cache controller 331_1 may input the first address ADDa4 to the second hash function 333_1, and may generate the second target TGT2. The cache controller 331_1 may change the first target TGT1 included in the first transaction TXNa to the second target TGT2. The cache controller 331_1 may provide an internal transaction including the first address ADDa4 and the second target TGT2 to the master device 310, or perform a forwarding FWD operation to the second memory bank 330_2 on the internal transaction, so that the first address ADDa4 and the second memory bank 330_2 are remapped or redirected.

[0051] When the flush operation is completed, the information updated by the cache line stored in the way group 334_1 can be stored in the memory or storage device in the lower layer. When the information included in the tag is not updated due to need, the operation of storing the data of the cache line in the memory or storage device in the lower layer can also be omitted.

[0052] Reference Figure 7 , when the flush operation is completed, the cache controller 331_1 may output a response signal to the host device 310. In this case, the response signal may be a signal notifying that a hash function selected from among a plurality of hash functions included in the host device 310 is changed to another hash function. The host device 310 may receive the response signal from the cache controller 331_1, and may change the hash function from the first hash function 311 to the second hash function 312 in response to the response signal. On the other hand, supply of the power PWR to the first memory bank 330_1 may be stopped.

[0053] In some embodiments, the cache controller 331_2 may be pre-disabled to terminate the forwarding FWD operation before stopping the supply of power PWR to the first memory bank 330_1. In this case, the time of the forwarding FWD operation may be reduced. However, the embodiment is not limited thereto, and the cache controller 331_2 may also be disabled when stopping the supply of power PWR to the first memory bank 330_1.

[0054] On the other hand, when the previously powered-off memory bank 330_1 is powered-on again, the second hash function 312 may be changed (or restored) to the first hash function 311. In this case, normal operation can be ensured only when the cache lines to be allocated to the first memory bank 330_1, which is powered-on again, among the cache lines allocated to the powered-on second memory bank 330_2 are flushed to FLH or migrated to the first memory bank 330_1. Hereinafter, an embodiment of the operation of the electronic device 30 is described for the case where the previously powered-off first memory bank 330_1 is powered-on again.

[0055] Figure 8, Fig. 9 and Fig.10 is a diagram of the operation of an example of the electronic device 30 .

[0056] Reference Figure 8 , Fig. 9 and Fig.10 , the first memory bank 330_1 included in the first memory bank group may receive power PWR in response to a power control signal commanding the supply of power PWR. The second memory bank 330_2 included in the second memory bank group may receive power PWR, and may store at least one first cache line and at least one second cache line. The first cache line may correspond to the first address group ADDa, and the second cache line may correspond to the second address group ADDb. The cache controller 331_2 may set a hash function in response to the power control signal, and may map the first address ADDai to the second memory bank 330_2 based on the hash function and the first transaction TXNa. In this case, the first transaction TXNa may be provided by the main device 310 after the above-mentioned power control signal is input, and may include the first address ADDai and the second target TGT2.

[0057] Reference Figure 7 and Figure 8 , when the first memory bank 330_1 is powered off, the first transaction TXNa or the second transaction TXNb may be transmitted to the second memory bank 330_2 according to the second hash function 312 of the master device 310. The second memory bank 330_2 may include a cache controller 331_2 and a path group 334_2. The path group 334_2 may include a first cache line corresponding to (or mapped to) a first address and a second cache line corresponding to a second address. Each of the first cache line and the second cache line may be one or more. For example, the first cache line may be stored in the fourth path way4 of the path group 334_2. Each of the second cache lines may be stored in each of the first path to the third path way1, way2, and way3 of the path group 334_2. In this case, the tag TAG_ai included in the first cache line may include information about any first address ADDai. Tags TAG_b1 , TAG_b2 , and TAG_b3 included in the second cache line may include information about second addresses (eg, ADDb1 , ADDb2 , and ADDb3 ) included in the second address group ADDb.

[0058] On the other hand, power PWR may be supplied to the first memory bank 330_1 which is powered off. In this case, according to some embodiments, the memory device 320 may be initialized internally. After the initialization is completed, the second power control signal PCS2 may be input to the memory device 320. The second power control signal PCS2 may be generated by the power manager 130 and may point to supplying power PWR to the first memory bank group. The cache controller 331_2 included in the second memory bank 330_2 may select the first hash function 332_2 from the first hash function 332_2 and the second hash function 333_2 in response to the second power control signal PCS2. For example, the cache controller 331_2 may change the hash function from the second hash function 333_2 to the first hash function 332_2 in response to the second power control signal PCS2. On the other hand, even after the second power control signal PCS2 is input, the main device 310 may maintain the second hash function 312 for a specific period of time. Although not shown, the cache controller 331_1 of the first memory bank 330_1 may also change the hash function from the second hash function 333_1 to the first hash function 332_1 .

[0059] Reference Fig. 9 , the cache controller 331_2 may perform a flush operation on the way group 334_1 of the second memory bank 330_2 by using the first hash function 332_2. The cache lines stored in the way group 334_2 may be flushed to FLH. In some embodiments, at least one first cache line stored in the way group 334_2 may be flushed to FLH. In addition, in some embodiments, the cache controller 331_2 may perform a flush operation on only the cache lines having the tag TAG_ai of the first address group ADDa no longer belonging to the second memory bank 330_2 among the cache lines stored in the way group 334_2 by using the first hash function 332_2, but is not limited thereto.

[0060] On the other hand, when the flush operation is being performed on the second memory bank 330_2, the master device 310 may be running and outputting transactions to the memory device 320. In other words, the cache controller 331_2 that performs the flush operation may receive transactions from the master device 310. In this case, the master device 310 may provide the first transaction TXNa to the second memory bank 330_2. The first address group ADDa included in the first transaction TXNa may no longer belong to the second memory bank 330_2. In this case, the cache controller 331_2 may map the first memory bank 330_1 to the first address group ADDai based on the first hash function 332_2 and the first address group ADDa, and perform a forwarding FWD operation to the first memory bank 330_1 on the first transaction TXNa. For example, when the first transaction TXNa provided to the cache controller 331_2 performing the flush operation has a cache hit, the cache controller 331_2 may output data DATA_ai to the master device 310, and the cache controller 331_2 may generate an internal transaction for storing the first cache line in the first memory bank 330_1, and provide the internal transaction to the master device 310. The internal transaction may include a storage request commanding the first address ADDai indicated by the tag TAG_ai, the first target TGT1, and the first cache line. The first target TGT1 may be generated from the first address of the first transaction TXNa and the first hash function 332_2. The cache controller 331_2 may invalidate the first cache line. When the first transaction TXNa is a cache miss, the cache controller 331_2 may generate a first target TGT1 based on the first hash function 332_2 and the first address of the first transaction TXNa, and may provide an internal transaction including the first address and the first target TGT1 to the main device 310, or perform a forwarding FWD operation on the internal transaction to the first storage body 330_1, so that the corresponding first address is redirected to the first storage body 330_1.

[0061] Reference Fig.10 , when the flush operation is completed, the cache controller 331_2 may output a response signal to the master device 310, and the master device 310 may change the hash function from the second hash function 312 to the first hash function 311 in response to the response signal. In some embodiments, when the master device 310 changes the second hash function 312 to the first hash function 311, the cache controller 331_2 may be disabled to terminate the forwarding FWD operation. In this case, the time for the forwarding FWD operation may be reduced. However, the embodiment is not limited thereto, and the cache controller 331_2 may remain enabled even after the master device 310 changes the hash function.

[0062] Fig.11is a flow chart of an example of a forwarding FWD operation of the memory device 320 .

[0063] Reference Fig.11 In operation S100, the memory device 320 may receive a transaction request from the master device 310. In some implementations, the transaction request may include a read request, a target, and an address.

[0064] In operation S110, the memory device 320 may check the target memory bank by using the hash function for the next memory bank on / off mode. For example, the cache controller 331_1 or 331_2 may set the hash function by changing the hash function in response to the power control signal. In addition, the cache controller 331_1 or 331_2 may check the target memory bank by inputting the address to the changed hash function and generating a target indicating a specific memory bank.

[0065] In operation S120, the memory device 320 may check cache hit / miss. For example, the cache controller 331_1 or 331_2 may read a cache line of the way group 334_1 or 344_2 and determine whether the cache is a hit or a miss by using the tag and address of the cache line. In operation S130, the memory device 320 may determine whether the transaction request has a cache hit. Figure 6 For example, the cache controller 331_1 may determine whether a first transaction TXNa with respect to at least one cache line stored in the first memory bank 330_1 has a cache hit, and may respond to the first transaction TXNa according to a result of the determination of the cache hit. Fig. 9 , for example, the cache controller 331_2 may determine whether a first transaction TXNa for at least one first cache line stored in the second memory bank 330_2 has a cache hit, and may respond to the first transaction TXNa according to a result of the determination of the cache hit.

[0066] When the cache hits (Yes in operation S130), in operation S140, the memory device 320 may service the transaction request using the cache line hit. Figure 6 For example, the cache controller 331_1 may output a cache hit cache line (eg, data of the cache line) to the host device 310. Fig. 9 , for example, the cache controller 331_2 may output a cache hit cache line to the master device 310 .

[0067] In operation S150, the memory device 320 determines whether the corresponding request (eg, transaction request) corresponds to a memory bank including the cache controller 331_1 or 331_2. Figure 6 For example, the cache controller 331_1 may determine whether the target generated in operation S110 matches the first reference target. The first reference target may be pre-stored in the cache controller 331_1. In this case, the first reference target may be the first target TGT1. Fig. 9 For example, the cache controller 331_2 may determine whether the target generated in operation S110 matches the second reference target. The second reference target may be pre-stored in the cache controller 331_2. In this case, the first reference target may be the second target TGT2. When the generated target matches the second reference target (yes in operation S150), the operation may be terminated. When the generated target is different from the second reference target (no in operation S150), in operation S151, the memory device 320 may generate a storage transaction for storing the corresponding cache line in the target memory bank. Reference Figure 6 For example, the cache controller 331_1 may output a first internal transaction including a first address ADDai, a second target TGT2, and a storage request to the master device 310 to the master device 310. Fig. 9 For example, the cache controller 331_2 may output a first internal transaction including a first address ADDai, a first target TGT1, and a storage request to the master device 310 to the master device 310. In operation S152, the memory device 320 may invalidate the corresponding cache line. Figure 6 For example, the cache controller 331_1 may invalidate a cache hit cache line (eg, tag TAG_a3 and data DATA_a3). Fig. 9 , for example, the cache controller 331_2 may invalidate a cache hit cache line (eg, tag TAG_ai and data DATA_ai) that is cache hit and stored in the second memory bank 330_2 .

[0068] When a cache miss occurs (No in operation S130), in operation S160, the memory device 320 may determine whether the corresponding request (eg, transaction request) corresponds to a bank including the cache controller 331_1 or 331_2. In other words, the operation in operation S160 may be the same as the operation in operation S150.

[0069] When the generated target matches the second reference target (yes in operation S160), in step S161, the memory device 320 may perform a cache miss procedure. For example, the cache controller 331_1 or 331_2 may select a victim row from all paths. When a cache miss occurs, the victim row may be a cache row for storing data stored in a memory or storage device in a lower layer. The cache controller 331_1 or 331_2 may perform storing the data stored in the memory or storage device in the lower layer in the selected victim row, etc.

[0070] When the generated target is different from the second reference target (No in operation S160), in operation S162, the transaction request may be forwarded to the target storage body. Figure 6 For example, the cache controller 331_1 may change the target from the first target TGT1 to the second target TGT2 by using the second hash function 333_1, and may output a second internal transaction including the changed target (eg, the second target TGT2) and the first address ADDai to the master device 310. Fig. 9 , for example, the cache controller 331_2 may change the target from the second target TGT2 to the first target TGT1 by using the first hash function 332_2 , and may output a second internal transaction including the first target TGT1 and the first address ADDai to the master device 310 .

[0071] Fig.12 is a block diagram of an example of a memory bank 500 .

[0072] Reference Fig.12 , the memory body 500 may receive a command CMD, an address ADDR, a clock CLK, and input data DATA_IN during a write operation. For example, the memory body 500 may receive a command CMD, an address ADDR, and input data DATA_IN indicating a write operation, and store the input data DATA_IN in a memory cell region corresponding to the address ADDR in the memory cell array 510. The memory body 500 may receive a command CMD, an address ADDR, and a clock CLK during a read operation. For example, the memory body 500 may receive a command CMD and an address ADDR indicating a read operation, may read data stored in a memory cell region corresponding to the address ADDR, and may output the read data to the outside as output data DATA_OUT.

[0073] In some embodiments, the memory bank 500 may include a memory cell array 510 , a column decoder 520 , a row decoder 530 , a write driver / sense amplifier 540 , an input / output (I / O) circuit 550 , and control logic 560 .

[0074] The memory cell array 510 may include a plurality of memory cells (MCs) 511. The plurality of MCs 511 may be arranged at points where word lines WL and bit lines BL cross each other. The column decoder 520 may select at least one bit line BL from among the plurality of bit lines BL based on the column address CA. The row decoder 530 may activate at least one word line WL from among the plurality of word lines WL based on the row address RA. In other words, the row decoder 530 may select at least one word line WL from among the plurality of word lines WL.

[0075] The write driver / sense amplifier 540 may transmit input data DATA_IN delivered by the I / O circuit 550 to the column decoder 520 during a write operation. Alternatively, the write driver / sense amplifier 540 may amplify the data transmitted by the column decoder 520 during a read operation and transmit output data DATA_OUT to the I / O circuit 550. The I / O circuit 550 may transmit the input data DATA_IN to the write driver / sense amplifier 540. Alternatively, the I / O circuit 550 may output the output data DATA_OUT transmitted by the write driver / sense amplifier 540.

[0076] The control logic 560 may receive a command CMD, an address ADDR, and a clock CLK, and generate a row address RA, a column address CA, and a control signal CTR. For example, the control logic 560 may identify a read command by decoding the command CMD, and may generate a row address RA, a column address CA, and a control signal CTR in order to read output data DATA_OUT from the memory cell array 510. In addition, the control logic 560 may identify a write command by decoding the command CMD, and may generate a row address RA, a column address CA, and a control signal CTR in order to write input data DATA_IN to the memory cell array 510.

[0077] Fig.13 is a circuit diagram of an example of a memory cell MC.

[0078] Reference Fig.13, when the memory bank 500 is included in the SRAM, the memory cell MC may be an SRAM cell including six transistors. The memory cell MC may be referred to as a 6T SRAM cell. The memory cell MC may include a first p-channel (P) metal oxide semiconductor (MOS) (PMOS) transistor P1 and a second p-channel (P) metal oxide semiconductor (MOS) (PMOS) transistor P2 and a first n-channel (N) metal oxide semiconductor (MOS) (NMOS) transistor N1 to a fourth n-channel (N) metal oxide semiconductor (MOS) (NMOS) transistor N4. The first PMOS transistor P1 and the second PMOS transistor P2 may be connected between a power supply voltage VDD line and a first node A and a second node B, respectively. The first NMOS transistor N1 and the second NMOS transistor N2 may be connected between a ground voltage VSS line and a first node A and a second node B, respectively. The first node A may be connected to a gate of each of the second PMOS transistor P2 and the second NMOS transistor N2. The second node B may be connected to a gate of each of the first PMOS transistor P1 and the first NMOS transistor N1. The first node A and the second node B may be connected to the bit line BL and the complementary bit line / BL via the third NMOS transistor N3 and the fourth NMOS transistor N4, respectively. The gates of the third NMOS transistor N3 and the fourth NMOS transistor N4 may be connected to the word line WL. The third NMOS transistor N3 and the fourth NMOS transistor N4 may be referred to as access transistors or transfer transistors. The memory cell MC may store data and complementary data at the first node A and the second node B, and may maintain their latched states. When the word line WL is enabled in a write operation, the data and complementary data transmitted to the bit line BL and the complementary bit line / BL via the third NMOS transistor N3 and the fourth NMOS transistor N4 may be latched at the first node A and the second node B. On the other hand, in the memory cell MC, when the word line WL is enabled in a read operation, the data latched at the first node A and the second node B may be transmitted to the bit line BL and the complementary bit line / BL via the third NMOS transistor N3 and the fourth NMOS transistor N4. In some embodiments, the memory cell MC may include a first inverter and a second inverter. The first inverter may include a first PMOS transistor P1 and a first NMOS transistor N1. The second inverter may include a second PMOS transistor P2 and a second NMOS transistor N2.

[0079] Fig.14 is a flow chart of an example of a method of operation of the memory device 120 .

[0080] Reference Figure 1 and Fig.14 , the operating method of the memory device 120 may include operations S1000 , S2000 , and S3000 .

[0081] In operation S1000, in response to a power control signal commanding whether to supply power to a first memory bank group (e.g., the first memory bank 122_1), the cache controller 121 may flush a cache line stored in a memory bank group selected from the first memory bank group and a second memory bank group (e.g., the second memory bank 122_2). Implementations of operation S1000 may correspond to Figure 5 and Figure 8 The embodiments shown in each of the.

[0082] In some embodiments of operation S1000 , operation S1000 may include receiving a first power control signal PCS1 , and flashing a first memory bank group as a selected memory bank group in response to the first power control signal PCS1 .

[0083] In some embodiments of operation S1000 , operation S1000 may include receiving a second power control signal commanding whether to supply power to the first memory bank group, and flashing a second memory bank group as a selected memory bank group in response to the second power control signal PCS2 .

[0084] In operation S2000, the cache controller 121 may perform a forwarding FWD operation to the unselected memory bank group on the cache lines to be mapped to the unselected memory bank group among the cache lines stored in the selected memory bank group based on a hash function selected according to the power control signal among the plurality of different hash functions and a transaction provided by the master device. Implementation of operation S2000 may correspond to Figure 6 and Fig. 9 The embodiments shown in each of the.

[0085] In some embodiments of operation S2000, operation S2000 may include: selecting a hash function that outputs a second target indicating a second storage body group from an address of the transaction among a plurality of hash functions, determining whether the transaction is a cache hit relative to a cache line stored in the first storage body group based on the hash function and the address of the transaction, and transmitting the cache hit cache line to the second storage body group.

[0086] In some embodiments of operation S2000, operation S2000 may include: selecting a hash function from a plurality of hash functions that outputs a first target indicating a first storage body group from a first address group and a second target indicating a second storage body group from a second address group, determining whether a transaction is a cache hit relative to a cache line stored in the second storage body group based on the hash function and an address of the transaction, and transmitting the cache hit cache line to the first storage body group.

[0087] In operation S3000 , the cache controller 121 may output a response signal to the master device to notify the master device (eg, the processor 110 ) that a hash function is to be changed.

[0088] In some embodiments of operation S3000 , after the flush operation is completed, the cache controller 121 may output a first response signal notifying that a hash function among a plurality of hash functions included in the host device is to be changed.

[0089] In some embodiments of operation S3000 , after the flush operation is completed, the cache controller 121 may output a second response signal notifying that a hash function among a plurality of hash functions included in the host device is to be changed.

[0090] Those skilled in the art will clearly understand that various modifications or changes may be made to the structure of the present disclosure without departing from the scope or technical ideas of the present disclosure. In view of the description given above, when modifications and changes to the present disclosure fall within the scope of the claims and their equivalents, the present disclosure will be deemed to include modifications and changes to the present disclosure.

[0091] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of any invention or the scope that may be claimed, but rather as descriptions of features that may be specific to a particular implementation of a particular invention. Specific features described in this specification in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented in multiple implementations individually or in any suitable subcombination. In addition, although features may be described above as working in a particular combination, one or more features from a combination may be deleted from the combination in some cases, and the combination may be directed to a subcombination or a variation of a subcombination.

[0092] While the present disclosure has been shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.

Claims

1. A memory device, comprising: A first memory bank configured to: receive power and store at least one cache line corresponding to a first address group; a second memory bank configured to: receive power and store at least one cache line corresponding to a second address group; as well as A cache controller is configured to: set a hash function based on a power control signal, and map a first address to a second storage body based on the hash function, a first address provided by a master device after the power control signal is input, and a first transaction including a first target indicating the first storage body, wherein the power control signal includes an instruction for suspending the supply of power to the first storage body.

2. The memory device according to claim 1, wherein: The cache controller is configured to: change the hash function from the first hash function to the second hash function based on the power control signal, The first hash function is configured to: output a first target based on the first address group, and output a second target indicating a second storage body based on the second address group; and The second hash function is configured to output a second target based on the first address group and the second address group.

3. The memory device according to claim 1, wherein: The cache controller is configured as: determining whether the first transaction is a cache hit with respect to the at least one cache line stored in the first memory bank, and The first transaction is responded to according to the result of the cache hit.

4. The memory device according to claim 3, wherein: The cache controller is configured as: Based on the occurrence of a cache hit, providing a cache line corresponding to the first transaction to the master device, providing a second target indicating a second memory bank, a storage request commanding storage of the cache line, and a first internal transaction including the first address to the master device, or forwarding the second target, the storage request, and the first internal transaction to the second memory bank, and The first memory bank is controlled to invalidate the cache line stored in the first memory bank.

5. The memory device according to claim 1, wherein: The cache controller is configured as: Based on the occurrence of a cache miss, the first target is changed to a second target, the second target indicating a second memory bank, and A second internal transaction is provided to the master device or forwarded to a second memory bank, the second internal transaction including a second target and the first address.

6. The memory device according to claim 1, wherein: The cache controller is configured as: controlling the first memory bank to perform a flush operation of flushing the at least one cache line stored in the first memory bank, and Based on a flush operation being performed on the first memory bank, a first transaction is received.

7. The memory device according to claim 6, wherein: The cache controller is configured as: Upon completion of the flash operation, a response signal notifying that a hash function included in the host device is changed is provided to the host device.

8. The memory device according to any one of claims 1 to 7, wherein: A cache controller is included in the first memory bank.

9. A memory device comprising: A first memory bank configured to: receive power based on a power control signal, the power control signal including an instruction for supplying power; a second memory bank configured to: store at least one first cache line corresponding to a first address group, and store at least one second cache line corresponding to a second address group, the first address group being provided before the first memory bank receives power; as well as A cache controller is configured to: set a hash function based on a power control signal, and map a first address to a first memory bank based on the hash function, a first address provided by a master device after the power control signal is input, and a first transaction including a second target indicating a second memory bank.

10. The memory device according to claim 9, wherein: The cache controller is configured to: change the hash function from the second hash function to the first hash function based on the power control signal, The first hash function is configured to: output a first target indicating a first storage bank based on a first address group, and output a second target based on a second address group; and The second hash function is configured to output a second target based on the first address group and the second address group.

11. The memory device according to claim 9, wherein: The cache controller is configured as: determining whether the first transaction is a cache hit with respect to the at least one first cache line, and The first transaction is responded to according to the result of the cache hit.

12. The memory device according to claim 11, wherein: The cache controller is configured as: Based on the occurrence of a cache hit, providing a first cache line corresponding to the first transaction to the master device, providing a first target indicating a first memory bank, a storage request commanding storage of a first cache line, and a first internal transaction including a first address to a master device, or forwarding the first target, the storage request, and the first internal transaction to the first memory bank, and The second memory bank is controlled to invalidate the first cache line stored in the second memory bank.

13. The memory device according to claim 11, wherein: The cache controller is configured as: Based on the occurrence of a cache miss, the second target is changed to the first target, the first target indicating the first memory bank, and A second internal transaction is provided to the host or forwarded to the first memory bank, the second internal transaction including the first target and the first address.

14. The memory device according to any one of claims 9 to 13, wherein: The cache controller is configured as: controlling the second memory bank to perform a flush operation of flushing the at least one first cache line stored in the second memory bank, and Based on a flush operation being performed on the second memory bank, a first transaction is received.

15. The memory device of claim 14, wherein: The cache controller is configured as: Upon completion of the flash operation, a response signal notifying that a hash function included in the host device is changed is provided to the host device.

16. A method for operating a memory device, the method comprising: flushing a plurality of cache lines stored in a selected memory bank group based on a power control signal commanding whether to supply power to the first memory bank group, the selected memory bank group being selected from the first memory bank group and the second memory bank group; forwarding a cache line of the plurality of cache lines stored in the selected memory bank group to an unselected memory bank group of the first memory bank group and the second memory bank group based on a hash function selected from a plurality of hash functions according to a power control signal and based on a transaction provided by the master device, wherein the cache line of the plurality of cache lines is to be mapped to the unselected memory bank group and the plurality of hash functions are different from each other; as well as A response signal notifying the change of the hash function of the master device is provided to the master device.

17. The operating method according to claim 16, wherein: The step of flushing the plurality of cache lines stored in the selected memory bank group comprises: receiving a first power control signal, the first power control signal including an instruction to suspend supply of power to a first memory bank group; and Based on the first power control signal, the first memory bank group is selected as the memory bank group for flashing, and The step of forwarding a cache line among the plurality of cache lines comprises: selecting, based on the address of the transaction, a hash function that outputs a second target from the plurality of hash functions, the second target indicating a second memory bank group; determining, based on the hash function and the address of the transaction, whether the transaction is a cache hit with respect to a cache line stored in the first memory bank group; and The cache line of the cache hit is transferred to the second memory bank group.

18. The operating method according to claim 17, wherein: The step of providing a response signal to the master device comprises: After flushing the plurality of cache lines, a first response signal notifying that the hash function of the master is changed is output.

19. The operating method according to claim 16, wherein: The step of flushing the plurality of cache lines comprises: receiving a second power control signal including an instruction for supplying power to the first memory bank group; and Based on the second power control signal, the second memory bank group is selected as the memory bank group for flashing, and The step of forwarding a cache line among the plurality of cache lines comprises: selecting a hash function from the plurality of hash functions, the hash function configured to output a first target indicating a first memory bank group from a first address group and to output a second target indicating a second memory bank group from a second address group; determining, based on the hash function and the address of the transaction, whether the transaction is a cache hit with respect to a cache line stored in a second memory bank group; and The cache line of the cache hit is transferred to the first memory bank group.

20. The operating method according to claim 19, wherein: The step of providing a response signal to the master device comprises: After flushing the plurality of cache lines, a second response signal notifying that the hash function of the master is changed is output.

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