Memory device, operating method of memory device, and storage device

Abstract

The invention relates to a memory device, an operating method of the memory device, and a storage device. The memory device includes: a plurality of memory planes, each memory plane including a plurality of memory banks; one or more plane groups, each plane group comprising at least two memory planes sharing at least one peripheral circuit; a plurality of compression circuits, each of which is connected to a respective bank and outputs compressed data by compressing data read from the respective bank; a plurality of merge circuits each receiving the compressed data and at least one output control signal corresponding to a merge group among the plurality of merge groups, each merge circuit outputting merge data obtained by merging the compressed data corresponding to the memory banks grouped in the merge group in response to the at least one output control signal; and an output buffer circuit that latches and outputs the merged data in response to the at least one output control signal. The merged group comprises at least two memory banks in the same plane group.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0112889 filed on August 28, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to a memory device, an operating method of a memory device, and a memory device. Background Art

[0004] The data read from the memory device can be transmitted to the input / output pad via the data line. Due to physical limitations, the number or quantity of data lines can be fixed to a predetermined number. Typically, multiple memory devices or multiple memory areas (memory banks) included in one memory device can share and use a fixed number of data lines.

[0005] Generally speaking, an operation including sharing and using data lines may mean an operation in which a plurality of memory devices or a plurality of memory areas included in one memory device use a fixed number of data lines in a set order at a set time through time division multiplexing or time sharing. Summary of the invention

[0006] According to an embodiment of the present disclosure, a memory device includes: multiple memory planes, each memory plane includes multiple memory bodies; one or more plane groups, each plane group includes at least two memory planes that share at least one peripheral circuit; multiple compression circuits, wherein each compression circuit is connected to a corresponding memory body in the multiple memory bodies, and outputs compressed data by compressing data read from a corresponding memory body in the multiple memory bodies in a compression read operation; multiple merging circuits, each merging circuit receives compressed data and at least one output control signal corresponding to a merging group in a plurality of merging groups among a plurality of output control signals, each merging circuit outputs merged data obtained by merging compressed data corresponding to the memory bodies grouped in the merging group in response to at least one output control signal among the plurality of output control signals; and an output buffer circuit that latches the merged data and outputs the merged data in response to at least one output control signal among the plurality of output control signals; wherein the merging group includes at least two memory bodies included in the same plane group.

[0007] According to another embodiment of the present disclosure, a method of operating a memory device includes: generating compressed data obtained by compressing data read from a plurality of memory bodies included in each of a plurality of memory planes; merging the compressed data corresponding to the memory bodies grouped into a merge group in response to at least one output control signal of a plurality of output control signals corresponding to at least one memory body; and outputting the merged data in response to at least one output control signal of the plurality of output control signals, wherein the plurality of memory planes are grouped into memory plane groups, wherein each memory plane group includes at least two memory planes that share at least one peripheral circuit, and wherein the merged group includes at least some of the memory bodies included in the same plane group.

[0008] According to another embodiment of the present disclosure, a storage device includes: a memory device; and a memory controller configured to provide a read command for requesting data to be read to the memory device; wherein the memory device includes: a plurality of memory planes, each memory plane including a plurality of memory bodies; one or more plane groups, each plane group including at least two memory planes sharing at least one peripheral circuit; a plurality of compression circuits, wherein each compression circuit is connected to a corresponding memory body in the plurality of memory bodies, and outputs compressed data by compressing data read from the plurality of memory bodies in a compression read operation; a plurality of merging circuits, each merging circuit receiving compressed data and at least one output control signal corresponding to a merging group in the plurality of merging groups among a plurality of output control signals, each merging circuit outputting merged data obtained by merging compressed data corresponding to the memory bodies grouped in the merging group in response to at least one output control signal among the plurality of output control signals; and an output buffer circuit latching the merged data and outputting the merged data in response to at least one output control signal among the plurality of output control signals; and wherein the merging group includes at least some of the memory bodies included in the same plane group.

[0009] According to an embodiment of the present disclosure, a memory device includes: a plurality of memory planes, each memory plane including a plurality of memory bodies; a first plane group including at least two memory planes sharing at least one peripheral circuit; a first compression circuit connected to a first memory body among the plurality of memory bodies and configured to output first compressed data by compressing data read from the first memory body, wherein the first memory body is in a first merging group; a second compression circuit connected to a second memory body among the plurality of memory bodies and configured to output second compressed data by compressing data read from the second memory body, wherein the second memory body is in the first merging group; a first merging circuit corresponding to the first merging group and receiving the first compressed data, the second compressed data and at least one output control signal among a plurality of output control signals, the first merging circuit outputting the first merging data obtained by merging the first compressed data and the second compressed data in response to at least one output control signal among the plurality of output control signals; and an output buffer circuit latching the first merging data and outputting the first merging data in response to at least one output control signal among the plurality of output control signals, wherein the first merging group includes at least some of the memory bodies included in the first plane group. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Example embodiments are described more fully below with reference to the accompanying drawings, which may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure conveys the scope of the example embodiments to those skilled in the art.

[0011] In the accompanying drawings, dimensions may be exaggerated or imprecise for ease of illustration. When an element is referred to as being "between" two elements, the element may be the only element between the two elements, or one or more intermediate elements may also be present between the two elements. The same reference numerals represent the same elements throughout the disclosure.

[0012] Figure 1 is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0013] Figure 2 FIG. 1 is a diagram showing an embodiment according to the present disclosure. Figure 1 Schematic diagram of the merging circuit shown in .

[0014] Figure 3 FIG. 1 is a diagram showing an embodiment according to the present disclosure. Figure 1 A diagram of the transmission circuit and output buffer circuit shown.

[0015] Figure 4 FIG. 1 is a diagram showing an embodiment according to the present disclosure. Figure 1 Schematic diagram of the combining circuit and the transmission circuit shown.

[0016] Figure 5 FIG. 1 is a diagram showing an embodiment according to the present disclosure. Figure 4 A diagram of an embodiment of a merging circuit is shown.

[0017] Figure 6 FIG. 1 is a diagram showing an embodiment according to the present disclosure. Figure 5 Schematic diagram of an example implementation of a merging circuit shown in .

[0018] Figure 7 FIG. 1 is a diagram showing an embodiment according to the present disclosure. Figure 4 A diagram of the merging circuit and transfer circuit shown during normal read operation.

[0019] Figure 8 FIG. 1 is a diagram showing another embodiment according to the present disclosure. Figure 4 A diagram of the merging circuit and transfer circuit shown during normal read operation.

[0020] Fig. 9 FIG. 1 is a diagram showing an embodiment according to the present disclosure. Figure 4 A diagram of the merge circuit and the transfer circuit shown during a compressed read operation.

[0021] Fig.10 It is shown that according to the present disclosure Figure 1 A block diagram of another embodiment of a memory controller is shown.

[0022] Fig.11 is a block diagram illustrating a storage device according to an embodiment of the present disclosure.

[0023] Fig.12 It is shown that according to the present disclosure Fig.11 A diagram of another embodiment of a memory controller is shown.

[0024] Fig.13 is a flowchart illustrating an operating method of a memory device according to an embodiment of the present disclosure.

[0025] Fig.14 The present invention is a diagram showing an embodiment of the present invention. Fig.13 Detailed flowchart.

[0026] Fig.15 The present invention is a diagram showing an embodiment of the present invention. Fig.13 Detailed flowchart. DETAILED DESCRIPTION

[0027] The specific structural or functional descriptions disclosed herein are merely illustrative and are used to describe embodiments of the concepts according to the present disclosure. Embodiments of the concepts according to the present disclosure may be implemented in various forms and should not be interpreted as being limited to the embodiments set forth herein.

[0028] The embodiment provides a memory device, a method for operating the memory device, and a memory device, which can reduce or prevent a merging failure that may occur during a merging process of data when performing a compression read operation while having a relatively simple structure.

[0029] In an operation mode such as a compression read operation, data read in each of a plurality of memory devices or a plurality of memory areas included in one memory device can be compressed and output, and the plurality of memory devices or the plurality of memory areas included in one memory device can use a known number of data lines obtained by dividing a fixed number of data lines for each of the plurality of memory areas. Therefore, the plurality of memory devices or the plurality of memory areas included in one memory device can be used simultaneously. For example, when data read in each of four memory devices is compressed by 1 / 4 and the compressed data is output, each of the four memory devices uses two data lines obtained by dividing eight data lines for each of the four memory devices. Therefore, the four memory devices can be used simultaneously.

[0030] Figure 1 is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0031] Reference Figure 1 , the memory device 1000 includes a plurality of memory banks 1100. Each memory bank 1100 includes a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of memory cells. In an embodiment, the plurality of memory cells may be nonvolatile memory cells. The memory cells connected to the same word line may be described as a page. Therefore, a memory block may include a plurality of pages.

[0032] In an embodiment, the memory bank 1100 may be memory regions respectively included in different memory devices. In another embodiment, the memory bank 1100 may be different memory regions divided in one memory device.

[0033] exist Figure 1 In the embodiment, the memory device 1000 includes eight (8) memory banks 1100 BK0 to BK3 and BK0' to BK3'. The number of memory banks 1100 is not limited to eight. For example, the number of memory banks 1100 may be two or more and less than or greater than Figure 1 In another example, the number of memory banks 1100 may be 16 or 32.

[0034] In an embodiment, a plurality of banks 1100 are included in the memory plane 1110. For example, bank 0BK0 and bank 1BK1 may be included in the zeroth memory plane, bank 2BK2 and bank 3BK3 may be included in the first memory plane, bank 0'BK0' and bank 1'BK1' may be included in the second memory plane, and bank 2'BK2' and bank 3'BK3' may be included in the third memory plane.

[0035] Among the memory planes 1110, the memory planes 1110 that share at least one peripheral circuit are grouped to constitute at least one plane group 1130. For example, the zeroth memory plane 1110 including the memory bank 0BK0 and the memory bank 1BK1 and the first memory plane 1110 including the memory bank 2BK2 and the memory bank 3BK3 share a peripheral circuit, and therefore, the zeroth memory plane and the first memory plane may be grouped into the zeroth plane group 1130. In addition, the second memory plane 1110 including the memory bank 0'BK0' and the memory bank 1'BK1' and the third memory plane 1110 including the memory bank 2'BK2' and the memory bank 3'BK3' share a peripheral circuit, and therefore, the second memory plane and the third memory plane may be grouped into the first plane group 1130.

[0036] In an embodiment, memory banks 1100 that are physically adjacent to each other may be grouped to constitute a sub-merge group 1120. In an embodiment, memory banks 1100 included in the same plane group 1130 and included in different memory planes 1110 may be grouped to constitute a sub-merge group 1120. In an embodiment, each of the plane groups 1130 may include a plurality of sub-merge groups 1120.

[0037] In an embodiment, the memory banks 1100 that are physically adjacent to each other may be grouped to constitute a merge group 1140. More specifically, the sub-merge groups 1120 that are physically adjacent to each other may be grouped to constitute a merge group 1140. Data output from the memory banks 1100 included in one merge group 1140 may be merged into merged data M.DATA. In an embodiment, the merge group 1140 may be configured using the memory banks 1100 included in the same plane group 1130, and each of the plane groups 1130 may include at least one merge group 1140. In an embodiment, as shown in FIG. Figure 1 As shown, since one plane group 1130 is included in one merge group 1140, the plane group 1130 and the merge group 1140 may be the same, but the present disclosure is not limited to such an embodiment. In another embodiment, one plane group 1130 may include two or more merge groups 1140. In an embodiment, the memory bodies 1100 included in one sub-merge group 1120 are included in the same merge group 1140, but may be included in different memory planes 1110.

[0038] In the present disclosure, when the memory banks 1100 included in one plane group 1130 are continuously arranged, the memory banks 1100 that are physically adjacent to each other may be determined only based on the relative distances between the memory banks 1100. Figure 1 As shown, compression circuit 1200, merging circuit 1300, etc. are located between memory planes 1110 in one plane group 1130. Since peripheral circuits including compression circuit 1200 and merging circuit 1300 may be located on a plane different from the plane where memory banks 1100 are located, peripheral circuits may not be considered when determining whether memory banks 1100 are adjacent to each other. Figure 1 , the compression circuit 1200 and the merging circuit 1300 between the memory bank 0BK0 and the memory bank 2BK2 may be located on a plane different from the plane where the memory bank 1100 is located. Therefore, when determining whether the memory banks 1100 excluding the compression circuit 1200 and the merging circuit 1300 are adjacent to each other, the memory bank 0BK0 and the memory bank 2BK2 may be adjacent to each other memory banks 1100. Similarly, the memory bank 0'BK0' and the memory bank 2'BK2', the memory bank 1BK1 and the memory bank 3BK3, and the memory bank 1'BK1' and the memory bank 3'BK3' may be adjacent to each other memory banks 1100.

[0039] The compression circuit 1200 is connected to each of the memory banks 1100. The compression circuit 1200 may be enabled when the memory device 1000 performs a compression read operation. In an embodiment, the memory device 1000 may perform a compression read operation based on a command received from outside the memory device 1000. In another embodiment, the memory device 1000 may perform a compression read operation according to its own decision.

[0040] When performing a compressed read operation, first, read data R.DATA may be output from each of the memory banks 1100. The read data R.DATA may be output in response to an output control signal OUTPUT_CTR. The output control signal OUTPUT_CTR may be generated based on a provided clock signal. The clock signal may be provided from outside the memory device 1000 or from a source within the memory device 1000. Although Figure 1 Only output control signals OUTPUT_CTR0 , OUTPUT_CTR1 , OUTPUT_CTR0 ′, and OUTPUT_CTR1 ′ output from bank 0BK0 , bank 1BK1 , bank 0 ′BK0 ′, and bank 1 ′BK1 ′ are illustrated, but the present disclosure is not limited to this example, and each bank 1100 may output the output control signal OUTPUT_CTR.

[0041] Subsequently, read data R.DATA read from each of the memory banks 1100 may be compressed in the compression circuit 1200 connected to each of the memory banks 1100, and thus compressed data C.DATA may be output from each of the compression circuits 1200. The compressed data C.DATA may also be output in response to the output control signal OUTPUT_CTR.

[0042] The compression circuit 1200 may compress the read data R.DATA at a compression ratio of 1:N, thereby generating compressed data C.DATA. N may be a natural number equal to 2 or greater. For example, when it is assumed that N is 4, the compression circuit 1200 may compress the read data R.DATA at a compression ratio of 1:4, i.e., 25%, thereby generating compressed data C.DATA. For example, when the read data R.DATA is 16 bits, 4-bit compressed data C.DATA of N=4 may be output from the compression circuit 1200.

[0043] The compressed data C.DATA output from the compression circuit 1200 may be merged in the merge circuit 1300. The merge circuit 1300 may merge the compressed data C.DATA corresponding to different memory banks 1100. More specifically, the merge circuit 1300 may merge the compressed data C.DATA corresponding to the memory banks 1100 included in the same merge group 1140. For example, Figure 1 As shown, the memory banks 0BK0 to 3BK3 may be included in one merge group 1140, and the compressed data 0C.DATA0 to 3C.DATA3 respectively corresponding to the memory banks 0BK0 to 3BK3 may be merged in the first merge circuit 1300. Similarly, the memory banks 0'BK0' to 3'BK3' may be included in another merge group 1140, and the compressed data 0'C.DATA0' to 3'C.DATA3' respectively corresponding to the memory banks 0'BK0' to 3'BK3' may be merged in the second merge circuit 1300. As shown in the figure, the merge circuit 1300 generates the merge data M.DATA corresponding to each merge group 1140.

[0044] In an embodiment, the merge circuit 1300 receives the compressed data C.DATA corresponding to the memory banks 1100 in the merge group 1140 and the output control signal OUTPUT_CTR, and merges the compressed data C.DATA corresponding to the memory banks 1100 in the merge group 1140 using the output control signal OUTPUT_CTR. In an embodiment, the merge circuit 1300 may latch the compressed data C.DATA corresponding to the memory banks 1100 in the merge group 1140, and output the latched compressed data C.DATA based on or in response to the output control signal OUTPUT_CTR, thereby outputting the merged data M.DATA obtained by merging the compressed data C.DATA corresponding to the memory banks 1100 in the merge group 1140.

[0045] The merging circuit 1300 may select and use any one of the output control signals OUTPUT_CTR output from the memory bank 1100 in the merging group 1140. For example, when the compressed data 0C.DATA0 to the compressed data 3C.DATA3 are merged by the merging circuit 1300, the merging circuit 1300 may select and use the output control signal 0OUTPUT_CTR0 output from the memory bank 0BK0 among the output control signals output from the memory bank 0BK0 to the memory bank 3BK3. Therefore, the merged data 0M.DATA0 may be output in response to the output control signal 0OUTPUT_CTR0. The method of selecting the output control signal OUTPUT_CTR is not limited to the above example.

[0046] In an embodiment, the merge circuit 1300 may output different data based on whether the compression read operation is enabled. In an embodiment, when the compression read operation is enabled or activated, the merge circuit 1300 may output merged data M.DATA obtained by merging compressed data C.DATA obtained by compressing read data R.DATA read from the memory bank 1100. In another embodiment, when the compression read operation is disabled, that is, during a normal read operation, the merge circuit 1300 may output the read data R.DATA read from the memory bank 1100 as normal data N.DATA without merging the data or unmodified data.

[0047] The merged data M.DATA output from the merging circuit 1300 is provided to the transmission circuit 1400. The transmission circuit 1400 is connected to the merging circuit 1300 through a plurality of channels, such as a communication bus or a separate communication line, and selects one or more (some) of the plurality of channels based on a plane group selection signal indicating a plane group to be selected among the plane groups 1130. The transmission circuit 1400 outputs the data input from the merging circuit 1300 through the selected channel.

[0048] In an embodiment, when a channel for transmitting the merged data M.DATA is selected, the transmission circuit 1400 receives the merged data M.DATA from the merge circuit 1400. The transmission circuit 1400 outputs the received merged data M.DATA without performing additional merge.

[0049] The merged data M.DATA output from the transmission circuit 1400 may be latched into the output buffer circuit 1500. The merged data M.DATA latched into the output buffer circuit 1500 may be output based on or in response to the output control signal OUTPUT_CTR. The output buffer circuit 1500 may select any one of the output control signals OUTPUT_CTR corresponding to the memory banks 1100 included in the merge group 1140, and output the merged data M.DATA in response to the selected output control signal OUTPUT_CTR. For example, when the merged data M.DATA0 is obtained by merging the compressed data 0C.DATA0 to the compressed data 3C.DATA3, the output buffer circuit 1500 selects and uses the output control signal 0OUTPUT_CTR0 among the output control signals output from the memory banks 0BK0 to 3BK3. Therefore, in response to the output control signal 0OUTPUT_CTR0, the merged data 0M.DATA0 is output from the output buffer circuit 1500.

[0050] The output control signal OUTPUT_CTR can be output from the memory bank 1100. The output control signal OUTPUT_CTR can be used for the output and merging of data. For example, the memory bank 1100, the compression circuit 1200, etc. can output the read data R.DATA or the compressed data C.DATA in response to the output control signal OUTPUT_CTR. In addition, the merging circuit 1300, the output buffer circuit 1500, etc. can align and output the latched data in response to the output control signal OUTPUT_CTR, so that the output control signal OUTPUT_CTR is used for the merging of data.

[0051] Figure 2 It is shown as Figure 1 A diagram of the merging circuit shown.

[0052] Reference Figure 1 and Figure 2, the memory banks 0BK0 to 3BK3 may be the memory banks 1100 included in the same merging group 1140. The read data 0R.DATA0 read from the memory bank 0BK0 may be compressed by the compression circuit 1200, and the compressed data 0C.DATA0 may be output from the compression circuit 1200. In addition, the read data 1R.DATA1 read from the memory bank 1BK1 may be compressed by the compression circuit 1200, and the compressed data 1C.DATA1 may be output from the compression circuit 1200. The read data 2R.DATA2 read from the memory bank 2BK2 may be compressed by the compression circuit 1200, and the compressed data 2C.DATA2 may be output from the compression circuit 1200. The read data 3R.DATA3 read from the memory bank 3BK3 may be compressed by the compression circuit 1200, and the compressed data 3C.DATA3 may be output from the compression circuit 1200.

[0053] The output control signal OUTPUT_CTR is output together with the read data R.DATA from each of the memory banks 1100, and the read data R.DATA is output from each of the memory banks 1100 in response to the output control signal OUTPUT_CTR. Therefore, the read data 0R.DATA0 to 3R.DATA3 are output in response to the output control signals 0OUTPUT_CTR0 to 3OUTPUT_CTR3, respectively.

[0054] The compressed data 0C.DATA0 to the compressed data 3C.DATA3 are merged by the merge circuit 1300. In an embodiment, the merge circuit 1300 includes a D flip-flop. The compressed data 0C.DATA0 to the compressed data 3C.DATA3 are input to the D flip-flop for latching. In an embodiment, the merge circuit 1300 includes a number of D flip-flops corresponding to the number of data bits read from each memory bank 1100, but the present disclosure is not limited thereto. For example, when 16 bits of data are read from the memory bank 1100, the merge circuit 1300 includes 16 flip-flops. In a normal read operation, 16 bits of data are read from the memory bank 1100 and latched into the 16 flip-flops. For simplicity of the drawings, Figure 2Only one D flip-flop is shown in the figure, but a plurality of D flip-flops may be used, one D flip-flop for each bit of the data C.DATA0, C.DATA1, C.DATA2, and C.DATA3 input to the merging circuit 1300, wherein each data line C.DATA0, C.DATA1, C.DATA2, and C.DATA3 is directly connected to a corresponding D flip-flop, respectively. In the compression read operation, when the read data R.DATA is compressed by the compression circuit 1200 at a compression ratio of 1:4, i.e., 25%, the 4-bit compressed data 0C.DATA0 compressed and outputted in the compression circuit 1200, the 4-bit compressed data 1C.DATA1 compressed and outputted in the compression circuit 1200, the 4-bit compressed data 2C.DATA2 compressed and outputted in the compression circuit 1200, and the 4-bit compressed data 3C.DATA3 compressed and outputted in the compression circuit 1200 may be divided to be latched into 16 flip-flops. When the read data R.DATA is compressed by the compression circuit 1200 at a compression ratio of 1:8, i.e., 12.5%, the 2-bit compressed data 0C.DATA0 compressed and output in the compression circuit 1200, the 2-bit compressed data 1C.DATA1 compressed and output in the compression circuit 1200, the 2-bit compressed data 2C.DATA2 compressed and output in the compression circuit 1200, and the 2-bit compressed data 3C.DATA3 compressed and output in the compression circuit 1200 can be divided to be latched into 8 of the 16 flip-flops, and the other 8 flip-flops may not be used.

[0055] The latched compressed data 0C.DATA0 to the latched compressed data 3C.DATA3 can be aligned and output by the output control signal OUTPUT_CTR input to the D flip-flop, so that the merged data 0M.DATA0 is output. Figure 2 In the embodiment, the output control signal 0OUTPUT_CTR0 is used as a clock signal input to the D flip-flop. The present disclosure is not limited to this example. However, the clock signal input to the D flip-flop can be selected from any one of the output control signal 0OUTPUT_CTR0 to the output control signal 3OUTPUT_CTR3. Therefore, in an embodiment, the merging circuit 1300 can optionally include a signal selector configured to select the clock signal input to the D flip-flop.

[0056] Figure 3 It is shown Figure 1 Schematic diagram of the transmission circuit and output buffer circuit shown.

[0057] Reference Figure 1 and Figure 3 , the transmission circuit 1400 may include a data selector 1410 and a signal selector 1420 .

[0058] The data selector 1410 may receive the merged data M.DATA output from the plurality of merge circuits 1300. In an embodiment, the data selector 1410 includes one or more data selection circuits (not shown), and the data selection circuits may be connected to the merge circuit 1300 through a plurality of channels. The data selection circuit selects one or more (some) channels based on a plane group selection signal indicating a plane to be selected among the plane groups. The data selector 1410 outputs the merged data M.DATA input through the selected channels. In an embodiment, when the data selector 1410 selects some channels, the data selector 1410 may simply output the received data as is. The data selector 1410 may not perform merging of the received data.

[0059] The signal selector 1420 may receive the output control signal OUTPUT_CTR outputted from the memory bank 1100. When the memory device 1000 performs a compression read operation, the signal selector 1420 selects and outputs at least one of the received output control signals OUTPUT_CTR. In an embodiment, the signal selector 1420 selects one of the output control signals OUTPUT_CTR corresponding to the memory bank 1100 included in one merging group 1140.

[0060] For example, Figure 3 As shown, the data selector 1410 receives the merged data 0M.DATA0 obtained by merging the compressed data C.DATA0 to C.DATA3 output from the memory bank 0BK0 to the memory bank 3BK3, and outputs the merged data 0M.DATA0 from the merge circuit 1300 in response to the output control signal 0OUTPUT_CTR0. The data selector 1410 receives the merged data 1M.DATA1 obtained by merging the compressed data C.DATA0' to C.DATA3' output from the memory bank 0'BK0' to the memory bank 3'BK3', and outputs the merged data 1M.DATA1 from the merge circuit 1300 in response to the output control signal 0'OUTPUT_CTR0'.

[0061] The signal selector 1420 may receive the output control signals 0OUTPUT_CTR0 and 0'OUTPUT_CTR0' generated from the memory bank 1100. In an embodiment, in addition to the output control signal output from the merge circuit 1300, the signal selector 1420 may further receive other output control signals output from the memory bank 1100. In an embodiment, the signal selector 1420 may select the output control signal 0OUTPUT_CTR0 as the output control signal corresponding to the merge data 0M.DATA0, and output the selected output control signal.

[0062] When the memory device 1000 performs a normal read operation, the signal selector 1420 receives the output control signal OUTPUT_CTR generated from the memory bank 1100 from which data is read, and outputs the received output control signal OUTPUT_CTR as is. Figure 3 Although not shown, the signal selector 1420 may further receive output control signals OUTPUT_CTR outputted from the bank 1BK1, the bank 1′BK1′, the bank 2BK2, the bank 2′BK2′, the bank 3BK3, and the bank 3′BK3′, respectively.

[0063] The merged data M.DATA output by the data selector 1410 and the output control signal OUTPUT_CTR selected by the signal selector 1420 may be provided to the output buffer circuit 1500. The output buffer circuit 1500 may include an output control circuit 1510 and a latch group 1520.

[0064] The latch group 1520 may include a plurality of latches, and the merged data M.DATA output from the transmission circuit 1400 may be latched into the plurality of latches. The output control circuit 1510 provides the data output control signal DOUT_CTR to the latch group 1520 based on or in response to the output control signal OUTPUT_CTR received from the transmission circuit 1400. More specifically, the output control circuit 1510 provides the data output control signal DOUT_CTR to the latch group 1520 based on or in response to the output control signal OUTPUT_CTR selected or output by the signal selector 1420. The merged data M.DATA latched in the latch group 1520 is output in response to the data output control signal DOUT_CTR.

[0065] Figure 4 It is shown as Figure 1 Schematic diagram of the combining circuit and the transmission circuit shown.

[0066] Reference Figure 1 and Figure 4 , the merging circuits 1300a and 1300b receive the compressed data C.DATA or the read data R.DATA outputted from the memory bank 1100 ( Figure 1 For example, with Figure 1The merging circuit 1300a corresponding to the merging group 1140 included in the zeroth plane group 1130 on the left receives the compressed data C.DATA0 to C.DATA3 or the normal data N.DATA0 to N.DATA3 output from the memory bank 0BK0 to the memory bank 3BK3. In an embodiment, the compressed data C.DATA0 to C.DATA3 can be input through one channel, the normal data N.DATA0 and N.DATA2 can be input through another channel, and the normal data N.DATA1 and N.DATA3 can be input through another channel. The normal data input through one channel can be the normal data output from the memory bank 1100 included in a sub-merging group 1120. For example, the memory bank 0BK0 and the memory bank 2BK2 that output the normal data 0N.DATA0 and 2N.DATA2 are included in the same sub-merging group 1120. The memory bank 1BK1 and the memory bank 3BK3 that respectively output the normal data 1N.DATA1 and 3NDATA3 may be included in the same sub-merging group 1120.

[0067] and Figure 1 The merging circuit 1300b corresponding to the second merging group 1140 included in the first plane group 1130 on the right receives the compressed data C.DATA0' to C.DATA3' or the normal data N.DATA0' to N.DATA3' outputted from the memory bank 0'BK0' to the memory bank 3'BK3' respectively. In an embodiment, the compressed data C.DATA0' to C.DATA3' can be inputted through one channel, the normal data N.DATA0' and N.DATA2' can be inputted through another channel, and the normal data N.DATA1' and N.DATA3' can be inputted through another channel. The normal data inputted through one channel can be the normal data outputted from the memory bank 1100 included in one sub-merging group 1120. For example, the memory bank 0'BK0' and the memory bank 2'BK2' outputting the normal data 0'N.DATA0' and 2'N.DATA2' are included in the same sub-merging group 1120. The memory bank 1 ′ BK1 ′ and the memory bank 3 ′ BK3 ′ outputting normal data 1 ′ N.DATA1 ′ and 3 ′ N.DATA3 ′ may be included in the same sub-merging group 1120 .

[0068] The merging circuits 1300a and 1300b select data to be input based on whether the compression read operation is enabled or activated. In an embodiment, the merging circuits 1300a and 1300b receive a compression read enable signal ESS_EN indicating whether the compression read operation is enabled, and select channels for inputting data to the merging circuits 1300a and 1300b in response to the compression read enable signal ESS_EN. For example, when the compression read enable signal ESS_EN indicates that the compression read operation is enabled, the merging circuit 1300a selects a channel for inputting compressed data C.DATA0 to C.DATA3, and the merging circuit 1300b selects a channel for inputting compressed data C.DATA0' to C.DATA3'. For example, when the compression read enable signal ESS_EN indicates that the compression read operation is disabled, that is, when the compression read enable signal ESS_EN indicates to perform a normal read operation, the merging circuit 1300a selects a channel for inputting normal data N.DATA0 to N.DATA3, and the merging circuit 1300b selects a channel for inputting normal data N.DATA0' to N.DATA3'.

[0069] The merging circuits 1300a and 1300b may output input data through a plurality of channels. In an embodiment, the merging circuit 1300a outputs compressed data C.DATA0 to C.DATA3 or normal data N.DATA0 and N.DATA2 through channel 0CH0, and outputs normal data N.DATA1 and N.DATA3 through channel 1CH1. The number of channels and the kind or type of data output through each channel are not limited to this example. In an embodiment, the merging circuit 1300b may output normal data N.DATA1' and N.DATA3' through channel 2CH2, and output compressed data C.DATA0' to C.DATA3' or normal data N.DATA0' and N.DATA2' through channel 3CH3. The number of channels and the kind or type of data output through each channel are not limited to this example.

[0070] The data selector 1410 includes a plurality of data selection circuits 1411a and 1411b that receive data output from the merging circuits 1300a and 1300b. Each of the data selection circuits 1411a and 1411b can receive data output from different plane groups 1130, and output the received data based on the plane group to be selected. In an embodiment, the data selection circuit 1411 receives a plane group selection signal SEL_PLG indicating a plane group to be selected, and selects the data to be output based on or in response to the plane group selection signal SEL_PLG. For example, when the plane group selection signal SEL_PLG indicates the zeroth plane group 1130, the data selection circuit 1411a outputs the data DATA0 received through the channel 0CH0, and the data selection circuit 1411b outputs the data DATA1 received through the channel 1CH1. For example, when the plane group selection signal indicates the first plane group 1130 , the data selection circuit 1411 a outputs data DATA0 received through the channel 2 CH, and the data selection circuit 1411 b outputs data DATA1 received through the channel 3 CH3 .

[0071] Figure 5 It is shown as Figure 4 A diagram of an embodiment of a merging circuit is shown.

[0072] Reference Figure 5 In the example of , the merging circuit 1300 includes a first multiplexing circuit 1310 , a second multiplexing circuit 1320 , and a latch circuit 1330 .

[0073] The multiplexing circuits 1310 and 1320 receive compressed data or normal data output from the memory bank 1100, and output data based on whether the compression read operation is enabled. In an embodiment, the first multiplexing circuit 1310 receives normal data N.DATA1 and N.DATA3 or compressed data C.DATA1 and C.DATA3 output from the memory bank 1BK0 and the memory bank 3BK3. In an embodiment, the first multiplexing circuit 1310 receives normal data or compressed data output from the memory bank 1100 included in one sub-merging group 1120. The first multiplexing circuit 1310 receives a compression read enable signal ESS_EN indicating whether the compression read operation is enabled, and outputs the input data according to the received compression read enable signal ESS_EN. For example, when the compression read enable signal ESS_EN indicates that the compression read operation is enabled, the first multiplexing circuit 1310 outputs compressed data C.DATA1 and C.DATA3. When the compression read enable signal ESS_EN indicates that the compression read operation is disabled, the first multiplexing circuit 1310 outputs normal data N.DATA1 and N.DATA3. The data output from the first multiplexing circuit 1310 is provided to the transmission circuit 1400 through the channel 1CH1.

[0074] In an embodiment, the second multiplexing circuit 1320 receives normal data N.DATA0 and N.DATA2 output from the memory bank 0BK0 and the memory bank 2BK2 or data output from the memory bank 1BK1 and the memory bank 3BK3 and compressed data C.DATA0 and C.DATA2 output from the memory bank 0BK0 and the memory bank 2BK2 via the first multiplexing circuit 1310. Therefore, the second multiplexing circuit 1320 receives the data output from the first multiplexing circuit 1310. In an embodiment, the second multiplexing circuit 1320 receives normal data output from the memory bank 1100 included in one sub-merging group 1120 or compressed data output from the memory bank 1100 included in two or more sub-merging groups 1120. The second multiplexing circuit 1320 receives a compression read enable signal ESS_EN indicating whether a compression read operation is enabled or activated, and outputs the input data according to the received compression read enable signal ESS_EN. For example, when the compression read enable signal ESS_EN indicates that the compression read operation is enabled, the first multiplexing circuit 1310 outputs the compressed data C.DATA1 and C.DATA3 as described above, and the second multiplexing circuit 1320 receives the compressed data C.DATA1 and C.DATA3 output from the first multiplexing circuit 1310 and the compressed data C.DATA0 and C.DATA2 output from the memory bank 0BK0 and the memory bank 2BK2. Because the compression read enable signal ESS_EN indicates that the compression read operation is enabled, the second multiplexing circuit 1320 outputs the received compressed data C.DATA0 to C.DATA3. When the compression read enable signal ESS_EN indicates that the compression read operation is disabled, the second multiplexing circuit 1320 outputs the normal data N.DATA0 and N.DATA2. The data output by the second multiplexing circuit 1320 is provided to the latch circuit 1330.

[0075] The latch circuit 1330 latches data output from at least one of the multiplexing circuits 1310 and 1320. More specifically, the latch circuit 1330 latches data output through the second multiplexing circuit 1320. The latch circuit 1330 outputs the data latched into the latch circuit 1330 based on or in response to an output control signal corresponding to at least some of the memory banks 1100. When the compressed data C.DATA0 to C.DATA3 output from the second multiplexing circuit 1320 are latched into the latch circuit 1330, the compressed data C.DATA0 to C.DATA3 are aligned and output based on or in response to the output control signal OUTPUT_CTR, thereby outputting the merged data M.DATA. The data output from the latch circuit 1330 may be provided to the transmission circuit 1400 through the channel 0 CH0.

[0076] Figure 6 It is shown as Figure 5 A diagram of an example implementation of a merging circuit is shown.

[0077] Reference Figure 6 , the first multiplexing circuit 1310 may include a D flip-flop and a multiplexer. The D flip-flop may align and output normal data N.DATA1 and N.DATA3 output from the memory bank 1Bk1 and the memory bank 3BK3 included in one sub-merging group 1120 based on or in response to an output control signal 1OUTPUT_CTR1 input to the clock input of the D flip-flop. The multiplexer selects and outputs compressed data C.DATA1 and C.DATA3 output from the memory bank 1BK1 and the memory bank 3BK3 included in one sub-merging group 1120 or normal data N.DATA1 and N.DATA3 based on or in response to a compression read enable signal ESS_EN. In an embodiment, when a compression read operation is performed, the compressed data C.DATA1 and C.DATA3 may be subsequently aligned in time in the latch circuit 1330. The compressed data C.DATA1 and C.DATA3 may not be aligned in time in the first multiplexing circuit 1310. Therefore, the multiplexer can be located after or before the D flip-flop, but the present disclosure is not limited to this connection order. In an embodiment, the first multiplexing circuit 1310 receives normal data output from a memory bank 1100 included in a sub-merging group 1120 or compressed data output from a memory bank 1100 included in a sub-merging group 1120.

[0078] The second multiplexing circuit 1320 includes a multiplexer. The multiplexer receives normal data N.DATA0 and N.DATA2 output from the memory bank 0BK0 and the memory bank 2BK2 included in one sub-merging group 1120 as a first input. The multiplexer receives compressed data C.DATA0 and C.DATA2 output from the memory bank 0BK0 and the memory bank 2BK2 included in one sub-merging group 1120 and data output from the first multiplexing circuit 1310 as a second input. In an embodiment, the second multiplexing circuit 1320 receives normal data output from the memory bank 1100 included in one sub-merging group 1120 or compressed data output from the memory bank 1100 included in two or more sub-merging groups 1120. For example, when the compression read operation is enabled, compressed data 1C.DATA1 and compressed data 3C.DATA3 are output from the first multiplexing circuit 1310. Therefore, the compressed data OC.DATA0 to 3C.DATA3 are input as the second input of the multiplexer included in the second multiplexing circuit 1320. The multiplexer selects and outputs the data input as the first input or the second input based on or in response to the compression read enable signal ESS_EN. In an embodiment, when a compression read operation is performed, the compressed data OC.DATA0 to 3C.DATA3 input as the second input of the multiplexer is output by the multiplexer of the second multiplexing circuit 1320.

[0079] The latch circuit 1330 includes a D flip-flop that latches the data output from the second multiplexing circuit 1320. The D flip-flop receives the output control signal OUTPUT_CTR0 via the clock signal input of the D flip-flop, and outputs the latched data based on or in response to the received output control signal OUTPUT_CTR0. The output control signal OUTPUT_CTR0 input to the D flip-flop is not limited to a specific output control signal. In an embodiment, when a compressed read operation is performed, the compressed data 0C.DATA0 to 3C.DATA3 output from the second multiplexing circuit 1320 are latched into the D flip-flop. The latched compressed data 0C.DATA0 to 3C.DATA3 can be aligned and output by the output control signal OUTPUT_CTR0 input to the D flip-flop, so that the merged data 0M.DATA0 is output.

[0080] Figure 7 It is shown as Figure 4 A diagram of the merging circuit and transfer circuit shown during normal read operation.

[0081] Reference Figure 1 as well as Figures 4 to 7, a merging circuit 1300a corresponding to the merging group 1140 included in the zeroth plane group 1130 and a merging circuit 1300b corresponding to the merging group 1140 included in the first plane group 1130 respectively include multiplexing circuits 1310a, 1310b, 1320a and 1320b and latch circuits 1330a and 1330b.

[0082] Multiplexing circuits 1310a, 1310b, 1320a, and 1320b may correspond to sub-merging group 1120. Figures 7 to 9 In the illustrated embodiment, the first multiplexing circuit 1310a corresponds to the sub-merging group 1120 including the memory bank 1BK1 and the memory bank 3BK3, and the second multiplexing circuit 1320a corresponds to the sub-merging group 1120 including the memory bank 0BK0 and the memory bank 2BK2. The present disclosure is not limited thereto. For example, in another embodiment, the first multiplexing circuit 1310a may correspond to the sub-merging group 1120 including the memory bank 0BK0 and the memory bank 2BK2, and the second multiplexing circuit 1320a may correspond to the sub-merging group 1120 including the memory bank 1BK1 and the memory bank 3BK3. The input / output channels connected to the merging circuit 1300 are changed accordingly.

[0083] exist Figures 7 to 9 In the illustrated embodiment, the first multiplexing circuit 1310b corresponds to the sub-merging group 1120 including the memory bank 0 'BK0' and the memory bank 2 'BK2', and the second multiplexing circuit 1320b corresponds to the sub-merging group 1120 including the memory bank 1 'BK1' and the memory bank 3 'BK3'. The present disclosure is not limited to this example. For example, in another embodiment, the first multiplexing circuit 1310b may correspond to the sub-merging group 1120 including the memory bank 1 'BK1' and the memory bank 3 'BK3', and the second multiplexing circuit 1320b may correspond to the sub-merging group 1120 including the memory bank 0 'BK0' and the memory bank 2 'BK2'. The input / output channels connected to the merging circuit 1300 are changed accordingly. For example, with Figure 7Unlike the example shown in FIG. 1 , when the first multiplexing circuit 1310 b corresponds to the sub-merging group 1120 including the memory bank 0 'BK0' and the memory bank 2 'BK2', and the second multiplexing circuit 1320 b corresponds to the sub-merging group 1120 including the memory bank 1 'BK1' and the memory bank 3 'BK3', the channel 2 CH2 output from the first multiplexing circuit 1310 b is connected to the data selection circuit 1411 b, and the channel 3 CH3 output from the second multiplexing circuit 1320 b is connected to the data selection circuit 1411 a. The memory device 1000 may perform a normal read operation on the zeroth plane group 1130. Therefore, the compression read enable signal ESS_EN may indicate that the compression read operation is disabled, that is, the normal read operation is performed, and the plane group selection signal SEL_PLG may indicate the zeroth plane group 1130. Therefore, the value of the compression read enable signal ESS_EN may be 0, and the value of the plane group selection signal SEL_PLG may be 0.

[0084] When the value of the compression read enable signal ESS_EN is 0, the multiplexer included in the first multiplexing circuit 1310a corresponding to the merging group 1140 included in the zeroth plane group 1130 outputs the normal data N.DATA1 and N.DATA3 output from the memory bank 1BK1 and the memory bank 3BK3 included in the same sub-merging group 1120. Before the normal data N.DATA1 and N.DATA3 are input to the multiplexer, the normal data N.DATA1 and N.DATA3 output from the memory bank 1BK1 and the memory bank 3BK3 may be aligned in response to the output control signal 1OUTPUT_CTR1. The normal data N.DATA1 and N.DATA3 output from the first multiplexing circuit 1310a are input to the data selection circuit 1411b through the channel 1CH1.

[0085] When the value of the compression read enable signal ESS_EN is 0, the multiplexer included in the second multiplexing circuit 1320a corresponding to the merging group 1140 included in the zeroth plane group 1130 outputs the normal data N.DATA0 and N.DATA2 output from the memory bank 0BK0 and the memory bank 2BK2 included in the same sub-merging group 1120. After the normal data N.DATA0 and N.DATA2 are latched into the latch circuit 1330a, the normal data N.DATA0 and N.DATA2 output from the second multiplexing circuit 1320a are output in response to the output control signal 0OUTPUT_CTR0. Therefore, the normal data N.DATA0 and N.DATA2 latched into the latch circuit 1330a are aligned based on or in response to the output control signal 0OUTPUT_CTR0. The aligned normal data N.DATA0 and N.DATA2 output from the latch circuit 1330a are input to the data selection circuit 1411a through the channel 0CH0.

[0086] like Figure 7 As shown in FIG. 1 , when the value of the plane group selection signal SEL_PLG is 0, the data selection circuit 1411a outputs the normal data N.DATA0 and N.DATA2 input through the channel 0 CH0 to the zeroth output line GDL0. Figure 7 As shown, when the value of the plane group selection signal SEL_PLG is 0, the data selection circuit 1411 b outputs the normal data N.DATA1 and N.DATA3 input through the channel 1 CH1 to the first output line GDL1 .

[0087] When the values ​​of the compression read enable signal ESS_EN and the plane group selection signal SEL_PLG are both 0, the normal data N.DATA0 and N.DATA2 input to the second multiplexing circuit 1320a corresponding to the merge group 1140 included in the zeroth plane group 1130 are output to the zeroth output line GDL0, and the normal data N.DATA1 and N.DATA3 input to the first multiplexing circuit 1310a corresponding to the merge group 1140 included in the zeroth plane group 1130 are output to the first output line GDL1.

[0088] Figure 8 It is shown as Figure 4 A diagram of the merging circuit and transfer circuit shown during normal read operation.

[0089] Reference Figure 1 , Figures 4 to 6 and Figure 8, the memory device 1000 performs a normal read operation on the first plane group 1130. Therefore, the compression read enable signal ESS_EN indicates that the compression read operation is disabled, that is, a normal read operation is performed, and the plane group selection signal SEL_PLG indicates the first plane group 1130. Therefore, the value of the compression read enable signal ESS_EN is 0, and the value of the plane group selection signal SEL_PLG is 1.

[0090] When the value of the compression read enable signal ESS_EN is 0, the multiplexer included in the first multiplexing circuit 1310b corresponding to the merging group 1140 included in the first plane group 1130 outputs the normal data N.DATA0' and N.DATA2' output from the memory bank 0 'BK0' and the memory bank 2 'BK2' included in the same sub-merging group 1120. Before the normal data N.DATA0' and N.DATA2' are input to the multiplexer, the normal data N.DATA0' and N.DATA2' output from the memory bank 0 'BK0' and the memory bank 2 'BK2' may be aligned in response to the output control signal 0 'OUTPUT_CTR0'. The normal data N.DATA0' and N.DATA2' output from the first multiplexing circuit 1310b are input to the data selection circuit 1411a through the channel 2CH2.

[0091] When the value of the compression read enable signal ESS_EN is 0, the multiplexer included in the second multiplexing circuit 1320b corresponding to the merging group 1140 included in the first plane group 1130 outputs the normal data N.DATA1' and N.DATA3' output from the memory bank 1'BK1' and the memory bank 3'BK3' included in the same sub-merging group 1120. After the normal data N.DATA1' and N.DATA3' are latched into the latch circuit 1330b, the normal data N.DATA1' and N.DATA3' output from the second multiplexing circuit 1320b are output in response to the output control signal 1'OUTPUT_CTR1'. The normal data N.DATA1' and N.DATA3' latched into the latch circuit 1330b may be aligned based on or in response to the output control signal 1'OUTPUT_CTR1'. The aligned normal data N.DATA1′ and N.DATA3′ output from the latch circuit 1330b are input to the data selection circuit 1411b through the channel 3CH3.

[0092] When the value of the plane group selection signal SEL_PLG is 1, the data selection circuit 1411a outputs the normal data N.DATA0' and N.DATA2' input through the channel 2CH2 to the zeroth output line GDL0. When the value of the plane group selection signal SEL_PLG is 1, the data selection circuit 1411b outputs the normal data N.DATA1' and N.DATA3' input through the channel 3CH3 to the first output line GDL1.

[0093] According to the compression read enable signal ESS_EN and the plane group selection signal SEL_PLG, the normal data N.DATA0' and N.DATA2' input to the first multiplexing circuit 1310b corresponding to the merge group 1140 included in the first plane group 1130 are output to the zeroth output line GDL0, and the normal data N.DATA1' and N.DATA3' input to the second multiplexing circuit 1320b corresponding to the merge group 1140 included in the first plane group 1130 are output to the first output line GDL1.

[0094] Fig. 9 It is shown as Figure 4 A diagram of the merge circuit and the transfer circuit shown during a compressed read operation.

[0095] Reference Figure 1 , Figures 4 to 6 and Fig. 9 , the memory device 1000 performs a compressed read operation. Therefore, the compressed read enable signal ESS_EN indicates that the compressed read operation is enabled, that is, the normal read operation is disabled, and the plane group selection signal SEL_PLG indicates the zeroth plane group 1130 or the first plane group 1130. Therefore, the value of the compressed read enable signal ESS_EN is 1, the value of the plane group selection signal SEL_PLG input to the data selection circuit 1411a is 0, and the value of the plane group selection signal SEL_PLG input to the data selection circuit 1411b is 1.

[0096] When the value of the compression read enable signal ESS_EN is 1, the multiplexer included in the first multiplexing circuit 1310a corresponding to the merging group 1140 included in the zeroth plane group 1130 outputs the compressed data C.DATA1 and C.DATA3 output from the memory bank 1BK1 and the memory bank 3BK3 included in the same sub-merging group 1120. The compressed data C.DATA1 and C.DATA3 output from the first multiplexing circuit 1310a are input to the second multiplexing circuit 1320a.

[0097] When the value of the compression read enable signal ESS_EN is 1, the multiplexer included in the second multiplexing circuit 1320a corresponding to the merging circuit 1140 included in the zeroth plane group 1130 outputs the compressed data C.DATA0 and C.DATA2 output from the memory bank 0BK0 and the memory bank 2BK2 included in the same sub-merging group 1120 and the compressed data C.DATA1 and C.DATA3 input from the first multiplexing circuit 1310a. After the compressed data C.DATA0 to C.DATA3 are latched into the latch circuit 1330a, the compressed data C.DATA0 to C.DATA3 output from the second multiplexing circuit 1320a are output in response to the output control signal 0OUTPUT_CTR0. The compressed data C.DATA0 to C.DATA3 latched into the latch circuit 1330a are aligned based on or in response to the output control signal 0OUTPUT_CTR0. In an embodiment, the aligned and output compressed data C.DATA0 to C.DATA3 are the merged data M.DATA0. The merged data M.DATA0 output from the latch circuit 1330a is input to the data selection circuit 1411a through the channel 0 CH0.

[0098] When the value of the compression read enable signal ESS_EN is 1, the multiplexer included in the first multiplexing circuit 1310b corresponding to the merging group 1140 included in the first plane group 1130 outputs the compressed data C.DATA0' and C.DATA2' output from the memory bank 0 'BK0' and the memory bank 2 'BK2' included in the same sub-merging group 1120. The compressed data C.DATA0' and C.DATA2' output from the first multiplexing circuit 1310b are input to the second multiplexing circuit 1320b.

[0099] When the value of the compression read enable signal ESS_EN is 1, the multiplexer included in the second multiplexing circuit 1320b corresponding to the merging group 1140 included in the first plane group 1130 outputs the compressed data C.DATA1' and C.DATA3' output from the memory bank 1'BK1' and the memory bank 3'BK3' included in the same sub-merging group 1120 and the compressed data C.DATA0' and C.DATA2' output from the first multiplexing circuit 1310b. After the compressed data C.DATA0' to C.DATA3' are latched into the latch circuit 1330b, the compressed data C.DATA0' to C.DATA3' output from the second multiplexing circuit 1320b are output in response to the output control signal 1'OUTPUT_CTR1'. The compressed data C.DATA0' to C.DATA3' latched into the latch circuit 1330b are aligned based on or in response to the output control signal 1'OUTPUT_CTR1'. In an embodiment, the aligned and output compressed data C.DATA0' to C.DATA3' are the merged data M.DATA1. The merged data M.DATA1 output from the latch circuit 1330b is input to the data selection circuit 1411b through the channel 3 CH3.

[0100] When the plane group selection signal SEL_PLG has a value of 0, the data selection circuit 1411a outputs the merged data M.DATA0 input through the channel 0 CH0 to the zeroth output line GDL0. In addition, when the plane group selection signal SEL_PLG has a value of 1, the data selection circuit 1411b outputs the merged data M.DATA1 input through the channel 3 CH3 to the first output line GDL1.

[0101] According to the compression read enable signal ESS_EN and the plane group selection signal SEL_PLG, the compressed data C.DATA1 and C.DATA3 input to the first multiplexing circuit 1310a corresponding to the merging group 1140 included in the zeroth plane group 1130 and the compressed data C.DATA0 and C.DATA2 input to the second multiplexing circuit 1320a corresponding to the merging group 1140 included in the zeroth plane group 1130 are merged as the output of the zeroth output line GDL0. The compressed data C.DATA1′ and C.DATA3′ input to the first multiplexing circuit 1310b corresponding to the merging group 1140 included in the first plane group 1130 and the compressed data C.DATA0′ and C.DATA2′ input to the second multiplexing circuit 1320b corresponding to the merging group 1140 included in the first plane group 1130 are merged as the output of the first output line GDL1.

[0102] In an embodiment, the output buffer circuit 1500 may output the merged data M.DATA latched into the output buffer circuit 1500 based on or in response to the output control signal OUTPUT_CTR corresponding to the second multiplexing circuits 1320a and 1320b among the output control signals OUTPUT_CTR. Figure 7 As shown, the output buffer circuit outputs the merged data M.DATA latched into the output buffer circuit 1500 based on or in response to the output control signal 0 OUTPUT_CTR0 and the output control signal 1 ' OUTPUT_CTR1 '. Figure 7 Different from the example shown, when the first multiplexing circuit 1310b corresponds to the sub-merging group 1120 including the memory bank 1'BK1' and the memory bank 3'BK3', and the second multiplexing circuit 1320b corresponds to the sub-merging group 1120 including the memory bank 0'BK0' and the memory bank 2'BK2', the output buffer circuit 1500 may output the merged data M.DATA latched into the output buffer circuit 1500 based on or in response to the output control signal 1 OUTPUT_CTR1 and the output control signal 0 'OUTPUT_CTR0'.

[0103] Fig.10 It is shown Figure 1 A block diagram of an alternative embodiment of a memory controller is shown.

[0104] Reference Fig.10 , the memory device 100 may include a memory cell array 110 , a voltage generator 120 , an address decoder 130 , an input / output circuit 140 , and a control logic 150 .

[0105] The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz, where z is an integer. The plurality of memory blocks BLK1 to BLKz are connected to the address decoder 130 through row lines RL. The plurality of memory blocks BLK1 to BLKz may be connected to the input / output circuit 140 through column lines CL. In an embodiment, the row lines RL may include word lines, source selection lines, and drain selection lines. In an embodiment, the column lines may include bit lines.

[0106] Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. In an embodiment, the plurality of memory cells may be nonvolatile memory cells.

[0107] In any one of the plurality of memory blocks BLKi (where i is an integer), a plurality of word lines arranged in parallel to each other may be connected between a first selection line and a second selection line. The first selection line may be a source selection line SSL, and the second selection line may be a drain selection line DSL. More specifically, the memory block BLKi may include a plurality of strings ST connected between the bit lines BL1 to BLn and the source line SL, where n is an integer. The bit lines BL1 to BLn may be connected to the string ST, respectively, and the source line SL may be connected to the string ST in common. The strings ST may be configured identically to one another, and the string ST connected to the first bit line BL1 will be described in detail below as an example.

[0108] The string ST may include a source selection transistor SST, a plurality of memory cells MC1 to MC16, and a drain selection transistor DST connected in series between a source line SL and a first bit line BL1. At least one source selection transistor SST and at least one drain selection transistor DST may be included in one string ST. The number of memory cells is greater than the number of memory cells MC1 to MC16 shown in the figure, and one string ST includes memory cells of the number of memory cells MC1 to MC16 shown in the figure.

[0109] The source of the source select transistor SST is connected to the source line SL, and the drain of the drain select transistor DST is connected to the first bit line BL1. The memory cells MC1 to MC16 are connected in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in different strings ST can be connected to the source select line SSL, and the gates of the drain select transistors DST included in different strings ST can be connected to the drain select line DSL. The gates of the memory cells MC1 to MC16 are connected to a plurality of word lines WL1 to WL16. A group of memory cells connected to the same word line among the memory cells included in different strings ST may be referred to as a physical page PPG. Therefore, the number of physical pages PPG corresponds to the number of word lines WL1 to WL16 included in the memory block BLKi.

[0110] Each of the memory cells may be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a triple-level cell (TLC) storing three data bits, or a quad-level cell (QLC) storing four data bits.

[0111] The SLC stores one bit of data. The SLC of one physical page PPG may store one logical page of data. One logical page of data may include a number of data bits corresponding to the number of cells included in one physical page PPG.

[0112] MLC, TLC and QLC can store two or more bits of data. One physical page PPG can store two or more logical pages of data.

[0113] The memory cell array 110 is configured with a plurality of memory banks including a plurality of memory blocks. Figure 1 The described memory banks 1100 are identical. The memory cell array 110 includes a plurality of memory planes, and each of the memory planes includes a plurality of memory banks, as described above.

[0114] In an embodiment, the voltage generator 120, the address decoder 130 and the input / output circuit 140 are collectively designated as a peripheral circuit. The peripheral circuit can drive the memory cell array 110 under the control of the control logic 150. The peripheral circuit drives the memory cell array 110 to perform programming operations, read operations and erase operations. The memory planes sharing the peripheral circuit can be grouped into plane groups. In an embodiment, the plane group includes one or more merge groups configured by adjacent memory bodies, and each of the merge groups includes one or more sub-merge groups configured by adjacent memory bodies. In an embodiment, each of the sub-merge groups includes memory bodies included in different memory planes.

[0115] The voltage generator 120 generates a plurality of operating voltages by using an external power supply voltage supplied to the memory device 100. The voltage generator 120 may operate under the control of the control logic 150.

[0116] In an embodiment, the voltage generator 120 generates an internal power supply voltage by regulating an external power supply voltage. The internal power supply voltage generated by the voltage generator 120 is used as an operating voltage of the memory device 100.

[0117] In an embodiment, the voltage generator 120 generates a plurality of operating voltages by using an external power supply voltage or an internal power supply voltage. The voltage generator 120 may generate various voltages used by the memory device 100. For example, the voltage generator 120 may generate a plurality of erase voltages, a plurality of program voltages, a plurality of pass voltages, a plurality of select read voltages, and a plurality of unselect read voltages.

[0118] In order to generate a plurality of operating voltages having various voltage levels, the voltage generator 120 may include a plurality of clamp capacitors receiving the internal power supply voltage. The voltage generator 120 may generate the plurality of operating voltages by selectively enabling the plurality of clamp capacitors under the control of the control logic 150.

[0119] A plurality of operating voltages generated by the voltage generator 120 may be provided to the memory cell array 110 through the address decoder 130 .

[0120] It is shown that the address decoder 130 is connected to the memory cell array 110 through the row line RL. The address decoder 130 operates under the control of the control logic 150. The address decoder 130 receives the address ADDR from the control logic 150. The address decoder 130 decodes the block address in the received address ADDR. The address decoder 130 selects at least one storage block from a plurality of storage blocks BLK1 to BLKi according to the decoded block address. The address decoder 130 decodes the row address in the received address ADDR. The address decoder 130 selects at least one word line from the word lines of the selected storage block according to the decoded row address. In an embodiment, the address decoder 130 decodes the column address in the received address ADDR. The address decoder 130 connects the input / output circuit 140 and the memory cell array 110 to each other according to the decoded column address.

[0121] For example, the address decoder 130 may include components such as a row decoder, a column decoder, and an address decoder.

[0122] The input / output circuit 140 may include a plurality of page buffers. The plurality of page buffers may be connected to the memory cell array 110 through bit lines. In a programming operation, data may be stored in a selected memory cell according to data stored in the plurality of page buffers. In a read operation, data stored in a selected memory cell may be sensed through a bit line, and the sensed data may be stored in a page buffer.

[0123] The input / output circuit 140 may include a plurality of compression circuits. The compression circuits may be connected to a plurality of page buffers. More specifically, each of the compression circuits may be connected to a page buffer that is connected to a corresponding memory bank. The compression circuits may be connected to a plurality of memory banks. Figure 1 The compression circuit 1200 described above is the same. When a compression read operation is performed under the control of the control logic 150, the compression circuit may compress and output data read from the memory cell array 110.

[0124] The input / output circuit 140 includes a plurality of merging circuits, a transmission circuit, and an output buffer circuit. The merging circuit may be connected to two or more compression circuits, and the transmission circuit may be connected to two or more merging circuits. The merging circuit and the transmission circuit may be connected to the output buffer circuit. Figure 1 The merge circuit 1300 and the transmission circuit 1400 described above are the same. The merge circuit can merge and output the data output from the compression circuit. More specifically, the merge circuit can merge the compressed data corresponding to the memory banks grouped into the above-mentioned merge group. The transmission circuit can transfer the data output from the merge circuit to the output buffer circuit. The output buffer circuit can be connected to the output buffer circuit of the embodiment of the present invention. Figure 1 The output buffer circuit 1500 described is the same.

[0125] The control logic 150 controls the address decoder 130, the voltage generator 120, and the input / output circuit 140. The control logic 150 may operate in response to a command CMD transmitted from an external device. The control logic 150 may control a peripheral circuit by generating a control signal in response to the command CMD and the address ADDR. The control logic 150 controls the peripheral circuit so that the memory device 100 performs a normal read operation or a compressed read operation.

[0126] Fig.11 is a block diagram illustrating a storage device according to an embodiment of the present disclosure.

[0127] Reference Fig.11 , the storage device 50 includes a memory device 100 and a memory controller 200. The storage device 50 may be a device for storing data under the control of a host such as a mobile phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a television, a tablet computer, or an in-vehicle infotainment system. Alternatively, the storage device 50 may be a device for storing data under the control of a host to store large amounts of data in one location (e.g., a server or a data center).

[0128] The memory device 50 may be manufactured as any of various types of memory devices according to a host interface using a communication scheme with a host. The memory device 50 may be manufactured to have any of various package types.

[0129] The memory device 100 stores data. The memory device 100 operates under the control of the memory controller 200. For example, the memory device 100 may be Figure 1 The memory device 1000 or Fig.10 The memory device 100 shown. The memory device 100 may include: a memory cell array 110 including a plurality of memory cells; an input / output (I / O) circuit 140 connected to the memory cell array 110 and outputting data read from the memory cells; and a control logic 150 controlling a peripheral circuit. As described above, the memory cell array 110 may include a plurality of memory banks, each memory bank including a plurality of memory blocks. Each of the memory blocks may include a plurality of pages. In an embodiment, a page may be a unit for storing data in the memory device 100 or reading data stored in the memory device 100. A memory block may be a unit for erasing data.

[0130] In an embodiment, the memory device 100 may be any one of various types of volatile memory or non-volatile memory. In this specification, for ease of description, it is assumed that the memory device 100 is a NAND flash memory, but other types of memory may also be applied.

[0131] The memory device 100 receives a command and an address from the memory controller 200, and accesses an area selected by the address in the memory cell array. The memory device 100 performs an operation indicated by the command on the area selected by the address. For example, the memory device 100 can perform a write operation (programming operation), a read operation, and an erase operation. During a programming operation, the memory device 100 programs data in an area selected by an address. During a read operation, the memory device 100 reads data from an area selected by an address. During an erase operation, the memory device 100 erases data stored in an area selected by an address.

[0132] The memory controller 200 may control the overall operations of the memory device 50 .

[0133] The memory controller 200 executes firmware (FW) when power is applied to the memory device 50. When the memory device 100 is a flash memory device, the memory controller 200 runs FW such as a flash translation layer (FTL) for controlling communication between the host and the memory device 100.

[0134] In an embodiment, the memory controller 200 receives a logical address (LA) input from a host and converts the LA into a physical address (PA) indicating an address of a memory cell in the memory device 100 where data is to be stored or from which data is to be read.

[0135] The memory controller 200 controls the memory device 100 to perform a write operation, a read operation, an erase operation, etc. in response to a request from the host. During a program operation, the memory controller 200 provides a write command, a PA, and data to the memory device 100. During a read operation, the memory controller 200 provides a read command and a PA to the memory device 100. During an erase operation, the memory controller 200 provides an erase command and a PA to the memory device 100.

[0136] In an embodiment, the memory controller 200 autonomously generates commands, addresses, and data regardless of any request from the host, and sends the commands, addresses, and data to the memory device 100. For example, the memory controller 200 provides the memory device 100 with commands, addresses, and data for performing program operations, read operations, and erase operations associated with performing wear leveling, read reclamation, garbage collection, etc.

[0137] In an embodiment, the memory controller 200 may control at least two memory devices 100. The memory controller 200 may control the memory devices according to an interleaving method to improve operation performance. The interleaving scheme may be a scheme for controlling operations of at least two memory devices 100 to overlap with each other.

[0138] In an embodiment, the memory controller 200 includes a read operation manager 210. The read operation manager 210 controls the memory device 100 to perform a compressed read operation or a normal read operation. For example, the read operation manager 210 determines whether the memory device 100 performs a compressed read operation or a normal read operation, and provides a compressed read command or a normal read command to the memory device 100 according to whether the memory device 100 is to perform a compressed read operation or a normal read operation. The control logic 150 controls the peripheral circuit including the I / O circuit 140 to perform a compressed read operation or a normal read operation in response to the received command. Therefore, the data read from the memory cell array 110 is output to the memory controller 200 through the I / O circuit 140. When the memory device 100 receives the compressed read command, the I / O circuit 140 provides the memory controller 200 with the read data compressed by the compression operation. As described above, the compressed read data may be data obtained by compressing data read from a plurality of memory banks and then merging the compressed data in a merging group unit. When the memory device 100 receives a normal read command, the I / O circuit 140 provides normal data that has not been subjected to a compression operation to the memory controller 200. The normal data is data obtained by not performing compression and merging on data read from a memory bank.

[0139] In an embodiment, a compression read operation may be performed using an efficient soft sensing (ESS) scheme. The ESS scheme may be a scheme that simultaneously compresses data of a plurality of regions in the memory cell array 110 and merges and outputs the compressed data together.

[0140] Fig.12 yes Fig.11 A diagram of another embodiment of a memory controller is shown.

[0141] Reference Fig.12 , the memory controller 2000 may include a processor 2010 , an internal memory 2020 , an error checking and correction (ECC) circuit 2030 , a host interface 2040 , a buffer memory interface 2050 , and a memory interface 2060 .

[0142] The processor 2010 may perform various calculations for controlling the memory device 100 or generate various commands. When the processor 2010 receives a request from the host 400, the processor 2010 may generate a command according to the received request and send the generated command to a queue controller (not shown). The processor 2010 may control the next operation of the memory device 100 based on the verification result received by the memory interface 2060 from the memory device 100. In an embodiment, the processor 2010 generates a normal read command or a compressed read command.

[0143] The internal memory 2020 stores various information used during the operation of the memory controller 2000. For example, the internal memory 2020 may include a logical and physical address mapping table.

[0144] The ECC circuit 2030 is configured to detect and correct one or more errors in data received from the memory device 100 by using an error correction code. The processor 2010 may adjust a read voltage and control the memory device 100 to perform a re-read according to an error detection result of the ECC circuit 2030. In an exemplary embodiment, the error correction block may be provided as a component of the memory controller 2000.

[0145] The host interface 2040 may exchange commands, addresses, data, etc. between the memory controller 2000 and the host 400. For example, the host interface 2040 may receive a request, an address, data, etc. from the host 400, and output data read from the memory device 100 to the host 400. The host interface 2040 may communicate with the host 400 using various protocols.

[0146] The buffer memory interface 2050 may transfer data between the processor 2010 and the buffer memory. The buffer memory may be used as a working memory or cache memory of the memory controller 2000 and store data used in the storage device. The buffer memory may be used by the processor 2010 as a read buffer, a write buffer, a mapping buffer, etc.

[0147] The memory interface 2060 may exchange commands, addresses, data, etc. between the memory controller 2000 and the memory device 100. For example, the memory interface 2060 may send commands, addresses, data, etc. to the memory device 100 through a channel, and receive data, etc. from the memory device 100. The memory interface 2060 may provide a compressed read command or a normal read command to the memory device 100 according to an instruction of the processor 2010. Therefore, the memory interface 2060 may receive compressed read data or normal read data from the memory device 100.

[0148] Fig.13 is a flowchart illustrating an operating method of a memory device according to an embodiment of the present disclosure.

[0149] Reference Figure 1 and Fig.13 , the compression circuit 1200 of the memory device 1000 compresses S1301 the read data R.DATA provided from the memory bank 1100 , and thus, the compressed data C.DATA is output from the compression circuit 1200 .

[0150] The merge circuit 1300 of the memory device 1000 merges S1303 the compressed data C.DATA based on or in response to the output control signal OUTPUT_CTR corresponding to at least one of the memory banks 1100. In an embodiment, the compressed data C.DATA corresponding to the memory banks 1100 grouped into the merge group 1140 are merged. In an embodiment, the merge group 1140 is configured with a plurality of memory banks 1100 included in the same plane group 1130, and the plane group 1130 is configured with the memory plane 1110 sharing the peripheral circuit. One plane group 1130 includes one or more merge groups 1140. In an embodiment, the merge group 1140 is configured with the memory banks 1100 that are physically adjacent to each other. More specifically, the merge group 1140 is configured with the sub-merge groups 1120 that are physically adjacent to each other. In an embodiment, the compressed data C.DATA output from the compression circuit 1200 is latched into the merge circuit 1300. When the data latched in response to the output control signal OUTPUT_CTR is output from the merge circuit 1300 , the merge data M.DATA is output.

[0151] Merged data M.DATA output from merge circuit 1300 is latched into output buffer circuit 1500. Data latched into output buffer circuit 1500 of memory device 1000 is output S1305 from output buffer circuit 1500 in response to at least one output control signal OUTPUT_CTR among a plurality of output control signals OUTPUT_CTR output by memory bank 1100.

[0152] Fig.14 It is shown Fig.13 Detailed flowchart.

[0153] Reference Fig.14 , the merge circuit 1300 of the memory device 1000 latches S1401 the compressed data C.DATA corresponding to the memory bank 1100. In an embodiment, the merge circuit 1300 corresponds to the merge group 1140. Therefore, the merge circuit 1300 latches the compressed data C.DATA corresponding to the memory bank 1100 included in the same merge group 1140. The merge circuit 1300 selects at least one (e.g., some) channels of input data based on whether the compression read mode is enabled. Therefore, the merge circuit 1300 selects the data to be output and latches the selected data.

[0154] The merging circuit 1300 of the memory device 1000 outputs the compressed data C.DATA latched at S1403 based on or in response to the output control signal OUTPUT_CTR. In an embodiment, the output control signal OUTPUT_CTR is selected from the output control signals output from the memory banks 1100 included in the same merging group. The latched compressed data C.DATA may be aligned and output in response to the output control signal OUTPUT_CTR, and the output of the aligned compressed data C.DATA may be output as the merged data M.DATA obtained by merging the compressed data C.DATA.

[0155] Fig.15 It is shown Fig.13 Detailed flowchart.

[0156] Reference Fig.15 , the transmission circuit 1400 of the memory device 1000 receives the merged data M.DATA from the merge circuit 1300. The transmission circuit 1400 selects at least one (some) channels of input data based on or in response to a plane group selection signal indicating a plane group 1130 to be selected. Therefore, the transmission circuit 1400 selects data to be output. The transmission circuit 1400 outputs S1501 the merged data M.DATA to the output buffer circuit 1500 according to the plane group selection signal.

[0157] The output buffer circuit 1500 of the memory device 1000 latches S1503 the merged data M.DATA received from the transmission circuit 1400 , and outputs the latched merged data M.DATA based on or in response to the output control signal OUTPUT_CTR.

[0158] According to the present disclosure, a memory device, a method for operating the memory device, and a memory device are provided that can reduce or prevent merging failures that may occur during data merging when performing a compression read operation while having a relatively simple structure.

[0159] Although the present disclosure is shown and described with reference to certain embodiments or examples, it will be understood by those skilled in the art that various changes may be made in form and detail without departing from the spirit and scope of the present disclosure as encompassed by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments, but should be determined not only by the appended claims, but also by their equivalents.

[0160] In the above-described embodiments, all processes may be selectively performed or some of these processes may be omitted. In each embodiment, these processes are not necessarily performed in the order described and may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are only examples for facilitating understanding of the present disclosure, and the present disclosure is not limited to these embodiments or examples. In addition to the embodiments disclosed herein, those skilled in the art may make various modifications based on the technical scope of the present disclosure.

[0161] On the other hand, exemplary embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used herein, these terms are used for the convenience of describing the embodiments of the present disclosure and are not otherwise limited. Therefore, the present disclosure is not limited to the above-described embodiments, and many changes can be made within the spirit and scope of the present disclosure.

Claims

1. A memory device, comprising: a plurality of memory planes, each memory plane comprising a plurality of memory banks; one or more plane groups, each plane group including at least two memory planes sharing at least one peripheral circuit; a plurality of compression circuits, each compression circuit being connected to a corresponding memory bank among the plurality of memory banks and outputting compressed data by compressing data read from a corresponding memory bank among the plurality of memory banks in a compression read operation; a plurality of merging circuits, each merging circuit receiving the compressed data and at least one output control signal corresponding to a merging group among the plurality of merging groups among the plurality of output control signals, each merging circuit outputting merged data obtained by merging the compressed data corresponding to the memory banks grouped in the merging group in response to at least one output control signal among the plurality of output control signals; as well as an output buffer circuit, responsive to at least one output control signal among the plurality of output control signals, to latch the merged data and output the merged data; The merge group includes at least some storage bodies included in the same plane group.

2. The memory device according to claim 1, wherein: Each of the one or more plane groups includes one or more merge groups.

3. The memory device according to claim 2, wherein: The merge group is configured with memory banks that are physically adjacent to each other.

4. The memory device according to claim 3, wherein: The coalescing group includes memory banks included in different memory planes.

5. The memory device according to claim 4, wherein: Four or more memory banks are grouped in the coalescing group.

6. The memory device according to claim 1, wherein: Each of the merging circuits comprises: one or more multiplexing circuits that receive normal data and compressed data from the memory bank, the one or more multiplexing circuits selecting data to be output based on whether the compressed read operation is enabled; and A latch circuit latches data output from at least some of the multiplexing circuits, the latch circuit outputting the latched data based on the output control signal.

7. The memory device according to claim 6, wherein: The one or more multiplexing circuits respectively correspond to a plurality of sub-merging groups included in one merge group, and receive normal data or compressed data output from memory banks included in the corresponding sub-merging groups.

8. The memory device according to claim 7, wherein: Each of the merging circuits comprises: a first multiplexing circuit that outputs the first compressed data or the first normal data output from the memory bank included in the first sub-merging group; and The second multiplexing circuit outputs the second compressed data output from the memory bank included in the second sub-merging group, and the first compressed data or the second normal data output from the memory bank included in the sub-merging group.

9. The memory device according to claim 7, wherein: In the sub-merge group, memory banks included in the same merge group and included in different memory planes are grouped. 10 . The memory device of claim 6 , further comprising a transmission circuit that receives the merged data from the merge circuit, the transmission circuit transmitting the merged data to the output buffer circuit.

11. The memory device according to claim 10, wherein: The transmission circuit is connected to the multiplexing circuit through a plurality of channels, respectively, selects some of the plurality of channels based on a plane group selection signal indicating a plane group to be selected among the plane groups, and outputs data input through the selected channels to the output buffer circuit.

12. A method of operating a memory device, comprising: generating compressed data obtained by compressing data read from a plurality of memory banks included in each of a plurality of memory planes; merging compressed data corresponding to the memory banks grouped into a merging group in response to at least one of a plurality of output control signals corresponding to at least one of the plurality of memory banks; as well as outputting the combined data in response to at least one of the plurality of output control signals, wherein the plurality of memory planes are grouped into memory plane groups, each memory plane group comprising at least two memory planes sharing at least one peripheral circuit, and In the merged group, at least some memory banks included in the same plane group are grouped.

13. The method according to claim 12, wherein: The merge group is configured with memory banks that are physically adjacent to each other.

14. The method according to claim 13, wherein: Each of the one or more plane groups includes one or more merge groups.

15. The method according to claim 12, wherein: Merging the compressed data comprises: latching compressed data corresponding to the memory bank included in the merge group; and The latched data is output based on the output control signal.

16. The method according to claim 12, wherein: Outputting the merged data includes: transmitting the combined data to an output buffer circuit; and The merged data latched into the output buffer circuit is output based on at least some of the output control signals.

17. The method according to claim 16, wherein: The transmitting of the merged data to the output buffer circuit is performed based on a plane group selection signal indicating a plane group to be selected among the plane groups.

18. A storage device, comprising: Memory device; as well as a memory controller that provides a read command to the memory device requesting data to be read; Wherein, the memory device comprises: a plurality of memory planes, each memory plane comprising a plurality of memory banks; one or more plane groups, each plane group including at least two memory planes sharing at least one peripheral circuit; a plurality of compression circuits, each compression circuit being connected to a corresponding memory bank among the plurality of memory banks and outputting compressed data by compressing data read from a corresponding memory bank among the plurality of memory banks in a compression read operation; a plurality of merging circuits, each merging circuit receiving the compressed data and at least one output control signal corresponding to a merging group among the plurality of merging groups among the plurality of output control signals, each merging circuit outputting merged data obtained by merging the compressed data corresponding to the memory banks grouped in the merging group in response to at least one output control signal among the plurality of output control signals; and an output buffer circuit that latches the merged data and outputs the merged data in response to at least one output control signal among the plurality of output control signals; and The merge group includes at least some storage bodies included in the same plane group.

19. The storage device according to claim 18, wherein: When the read command is a compression read command, the data read from the plurality of memory banks are respectively compressed, merged in a merge group unit, and then provided to the memory controller.

20. The storage device according to claim 18, wherein: When the read command is a normal read command, data read from the plurality of memory banks is provided to the memory controller.

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