Method for forming NAND metal gate

Abstract

The invention relates to the technical field of integrated circuits, in particular to a method for forming an NAND metal gate. Comprising the following steps of: 1, growing gate oxide on the surface of a wafer serving as a substrate, and sequentially depositing polycrystalline silicon and a sacrificial layer; the polycrystalline silicon and the sacrificial layer form a grid electrode; an intermediate product A is obtained; 2, performing grid etching on the grid side surface of the intermediate product A to form a side wall; a product B is obtained; 3, growing a hole layer dielectric layer on the gate oxide surface of the etched part in the product B, and grinding and flattening to obtain a product C; step 4, etching the product C to remove the sacrificial layer to obtain a product D with a recess on the polycrystalline silicon surface; 5, sequentially growing low-resistance metal layers on the product D with the recess on the surface of the polycrystalline silicon to obtain a product E; 6, the surface of the product E is flattened, and only the low-resistance metal layer replacing the sacrificial layer in the grid electrode is reserved and exists in the recess in the surface of the polycrystalline silicon; and obtaining the NAND metal gate.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a method for forming a NAND metal gate. Background Art

[0002] With the rapid development of semiconductor technology, especially the continuous advancement of storage technology, NAND flash memory, as the mainstream non-volatile memory, plays a vital role in the field of data storage. In the current 2D NAND manufacturing process, the performance of the gate has become one of the key factors affecting the overall performance of NAND flash memory devices.

[0003] In order to reduce the gate resistance and thus improve the conductive efficiency and stability of NAND flash memory devices, gate metallization has become an indispensable process step. In the prior art, there are two main methods for traditional gate metallization: one is to grow two layers of polysilicon and tungsten silicon when the gate is grown, and the other is to metallize the gate polysilicon before entering the hole layer to produce metal silicide to avoid metal contamination in the middle process. However, the square resistance of tungsten silicon or metal silicide formed by these two methods is still relatively large, so in some special wafer fabs, polysilicon and metal tungsten are grown when the gate is grown, which can further reduce the gate square resistance, but it is necessary to control metal contamination in the middle process, and the compatibility with other integrated circuit process platforms is poor.

[0004] In summary, it is of great significance to develop a NAND metal gate preparation method that can simultaneously overcome multiple problems such as large gate resistance, difficult to control metal contamination in the mid-stage process, and poor compatibility with other process platforms. Summary of the invention

[0005] The object of the present invention is to provide a method for forming a NAND metal gate to solve the problems raised in the prior art.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] A method for forming a NAND metal gate comprises the following steps:

[0008] Step 1: Using a wafer as a substrate, growing gate oxide on its surface, and then depositing polysilicon and a sacrificial layer in sequence; the polysilicon and the sacrificial layer form a gate; and obtaining an intermediate product A;

[0009] Step 2: Etch the gate side of the intermediate product A to form a sidewall to obtain product B;

[0010] Step 3: growing a hole layer dielectric layer on the surface of the gate oxide etched in product B, grinding and flattening, and obtaining product C;

[0011] Step 4: Etching the product C to remove the sacrificial layer, and obtaining the product D with a depression on the polysilicon surface;

[0012] Step 5: sequentially growing low-resistance metal layers on the product D having depressions on the polysilicon surface to obtain product E;

[0013] Step 6: Planarize the surface of product E, leaving only the low-resistance metal layer that replaces the sacrificial layer in the gate and exists in the depression on the polysilicon surface, to obtain a NAND metal gate.

[0014] More optimally, in step 1, the gate oxide material includes silicon dioxide, and the thickness of the gate oxide is

[0016] More optimally, in step 1, the thickness of the polysilicon is

[0017] More optimally, in step 1, the material of the sacrificial layer includes silicon nitride, and the thickness of the sacrificial layer is

[0019] More optimally, in step 2, the material of the sidewalls includes silicon nitride.

[0020] More optimally, in step 3, the material of the porous dielectric layer includes silicon dioxide, and the thickness of the porous dielectric layer is

[0021] More optimally, in step 3, the polishing and planarization is specifically to stop the polishing on the sacrificial layer and expose the sacrificial layer by etching back.

[0022] More optimally, in step 4, the process of etching away the sacrificial layer is specifically: using a wet etching method to remove the sacrificial layer with hot phosphoric acid.

[0023] More optimally, in step 5, the material of the low resistance metal includes metal tungsten, and the thickness of the low resistance metal layer is

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] 1. This method can further reduce the NAND gate sheet resistance.

[0026] 2. This method can effectively avoid the risk of metal contamination caused by the presence of metal tungsten in the middle process when metal tungsten is traditionally used as the gate material, while maintaining good compatibility with other process platforms. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0028] Figure 1 is a structural diagram of step 1 in Example 1;

[0029] Figure 2 This is a structural diagram of step 2 in Example 1;

[0030] Figure 3 This is a structural diagram of step 3 in Example 1;

[0031] Figure 4 This is a structural diagram of step 4 in Example 1;

[0032] Figure 5 is a structural diagram of step 5 in Example 1;

[0033] Figure 6 is a structural diagram of step 6 in Example 1;

[0034] Figure 7 It is the structural diagram of step 1 in comparative example 1;

[0035] Figure 8 It is the structural diagram of step 2 in comparative example 1;

[0036] Fig. 9 It is the structural diagram of step 3 in comparative example 1;

[0037] Fig.10 It is the structural diagram of step 4 in comparative example 1;

[0038] Fig.11 It is the structural diagram of step 1 in comparative example 2;

[0039] Fig.12 It is the structural diagram of step 2 in comparative example 2;

[0040] Fig.13 This is the structural diagram of step 3 in comparative example 2. DETAILED DESCRIPTION

[0041] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] In one embodiment, a method for forming a NAND metal gate comprises the following steps:

[0043] Step 1: Figure 1 As shown, the wafer is used as the substrate, and gate oxide is grown on its surface. The material of the gate oxide is silicon dioxide, and the thickness of the gate oxide is Then polysilicon and sacrificial layer are deposited in sequence. The thickness of polysilicon is The material of the sacrificial layer is silicon nitride, and the thickness of the sacrificial layer is The polysilicon and the sacrificial layer form a gate to obtain an intermediate product A;

[0044] Step 2: If Figure 2 As shown, the gate side of the intermediate product A is etched to form a sidewall, and the material of the sidewall is silicon nitride; and product B is obtained;

[0045] Step 3: If Figure 3 As shown, a hole layer dielectric layer is grown on the surface of the gate oxide etched in product B. The material of the hole layer dielectric layer is silicon dioxide. The thickness of the hole layer dielectric layer is Grinding and flattening, grinding stops on the sacrificial layer, and the sacrificial layer is exposed by etching back to obtain product C;

[0046] Step 4: Figure 4 As shown, the product C is wet-etched with hot phosphoric acid to remove the sacrificial layer, thereby obtaining a product D with a depression on the polysilicon surface;

[0047] Step 5: Figure 5 As shown, the product D with a concave surface of the polysilicon is sequentially grown with a low-resistance metal layer, the material of the low-resistance metal layer is metal tungsten, and the thickness of the low-resistance metal layer is Obtain product E;

[0048] Step 6: Figure 6 As shown, the surface of product E is planarized, leaving only the metal tungsten that replaces the sacrificial layer in the gate and exists in the depression on the polysilicon surface, thereby obtaining a NAND metal gate.

[0049] Embodiment 1: A method for forming a NAND metal gate, comprising the following steps:

[0050] Step 1: Figure 1 As shown, the wafer is used as the substrate, and gate oxide is grown on its surface. The material of the gate oxide is silicon dioxide, and the thickness of the gate oxide is Then polysilicon and sacrificial layer are deposited in sequence. The thickness of polysilicon is The material of the sacrificial layer is silicon nitride, and the thickness of the sacrificial layer is The polysilicon and the sacrificial layer form a gate to obtain an intermediate product A;

[0051] Step 2: If Figure 2As shown, the gate side of the intermediate product A is etched to form a sidewall, and the material of the sidewall is silicon nitride; and product B is obtained;

[0052] Step 3: If Figure 3 As shown, a hole layer dielectric layer is grown on the surface of the gate oxide etched in product B. The material of the hole layer dielectric layer is silicon dioxide. The thickness of the hole layer dielectric layer is Grinding and flattening, grinding stops on the sacrificial layer, and the sacrificial layer is exposed by etching back to obtain product C;

[0053] Step 4: Figure 4 As shown, the product C is wet-etched with hot phosphoric acid to remove the sacrificial layer, thereby obtaining a product D with a depression on the polysilicon surface;

[0054] Step 5: Figure 5 As shown, the product D with a concave surface of the polysilicon is sequentially grown with a low-resistance metal layer, the material of the low-resistance metal layer is metal tungsten, and the thickness of the low-resistance metal layer is Obtain product E;

[0055] Step 6: Figure 6 As shown, the surface of product E is planarized, leaving only the metal tungsten that replaces the sacrificial layer in the gate and exists in the depression on the polysilicon surface, thereby obtaining a NAND metal gate.

[0056] Embodiment 2: A method for forming a NAND metal gate, comprising the following steps:

[0057] Step 1: Figure 1 As shown, the wafer is used as the substrate, and gate oxide is grown on its surface. The material of the gate oxide is silicon dioxide, and the thickness of the gate oxide is Then polysilicon and sacrificial layer are deposited in sequence. The thickness of polysilicon is The material of the sacrificial layer is silicon nitride, and the thickness of the sacrificial layer is The polysilicon and the sacrificial layer form a gate to obtain an intermediate product A;

[0058] Step 2: If Figure 2 As shown, the gate side of the intermediate product A is etched to form a sidewall, and the material of the sidewall is silicon nitride; and product B is obtained;

[0059] Step 3: If Figure 3 As shown, a hole layer dielectric layer is grown on the surface of the gate oxide etched in product B. The material of the hole layer dielectric layer is silicon dioxide. The thickness of the hole layer dielectric layer is Grinding and flattening, grinding stops on the sacrificial layer, and the sacrificial layer is exposed by etching back to obtain product C;

[0060] Step 4: Figure 4As shown, the product C is wet-etched with hot phosphoric acid to remove the sacrificial layer, thereby obtaining a product D with a depression on the polysilicon surface;

[0061] Step 5: Figure 5 As shown, the product D with a concave surface of the polysilicon is sequentially grown with a low-resistance metal layer, the material of the low-resistance metal layer is metal tungsten, and the thickness of the low-resistance metal layer is Obtain product E;

[0062] Step 6: Figure 6 As shown, the surface of product E is planarized, leaving only the metal tungsten that replaces the sacrificial layer in the gate and exists in the depression on the polysilicon surface, thereby obtaining a NAND metal gate.

[0063] Embodiment 3: A method for forming a NAND metal gate, comprising the following steps:

[0064] Step 1: Figure 1 As shown, the wafer is used as the substrate, and gate oxide is grown on its surface. The material of the gate oxide is silicon dioxide, and the thickness of the gate oxide is Then polysilicon and sacrificial layer are deposited in sequence. The thickness of polysilicon is The material of the sacrificial layer is silicon nitride, and the thickness of the sacrificial layer is The polysilicon and the sacrificial layer form a gate to obtain an intermediate product A;

[0065] Step 2: If Figure 2 As shown, the gate side of the intermediate product A is etched to form a sidewall, and the material of the sidewall is silicon nitride; and product B is obtained;

[0066] Step 3: If Figure 3 As shown, a hole layer dielectric layer is grown on the surface of the gate oxide etched in product B. The material of the hole layer dielectric layer is silicon dioxide. The thickness of the hole layer dielectric layer is Grinding and flattening, grinding stops on the sacrificial layer, and the sacrificial layer is exposed by etching back to obtain product C;

[0067] Step 4: Figure 4 As shown, the product C is wet-etched with hot phosphoric acid to remove the sacrificial layer, thereby obtaining a product D with a depression on the polysilicon surface;

[0068] Step 5: Figure 5 As shown, the product D with a concave surface of the polysilicon is sequentially grown with a low-resistance metal layer, the material of the low-resistance metal layer is metal tungsten, and the thickness of the low-resistance metal layer is Obtain product E;

[0069] Step 6: Figure 6As shown, the surface of product E is planarized, leaving only the metal tungsten that replaces the sacrificial layer in the gate and exists in the depression on the polysilicon surface, thereby obtaining a NAND metal gate.

[0070] Comparative Example 1: According to Figure 7 to Figure 10 , a NAND metal gate is prepared using the prior art 1.

[0071] Step 1: Figure 7 As shown, a wafer is used as a substrate, gate oxide is grown on its surface, and polysilicon is deposited on the gate oxide to obtain product A;

[0072] Step 2: If Figure 8 As shown, the side of the polysilicon of product A is etched to form a side wall to obtain product B;

[0073] Step 3: If Fig. 9 As shown, the product B is grown with a hole layer dielectric layer, which is ground and flattened and then etched back to expose the polysilicon top to obtain product C;

[0074] Step 4: Fig.10 As shown, the top of the polysilicon of product C is subjected to polysilicon metallization, and metal silicide is formed thereon to obtain a NAND metal gate.

[0075] Comparative Example 2: According to Figure 11 to Figure 13 , a NAND metal gate is prepared using the prior art 2.

[0076] Step 1: Fig.11 As shown, a wafer is used as a substrate, a gate oxide is grown on its surface, polysilicon and metal tungsten are deposited on the surface of the gate oxide, and the polysilicon and metal tungsten form a gate to obtain product A;

[0077] Step 2: If Fig.12 As shown, the side of the gate of product A is etched to form a sidewall to obtain product B;

[0078] Step 3: If Fig.13 As shown, a hole layer dielectric layer is grown to obtain a NAND metal gate.

[0079] Conclusion: From the data in the above table, we can see that the scheme completes the semiconductor mid-stage process by first forming polysilicon and covering it with a sacrificial layer, then removes the sacrificial layer in the pre-hole stage, and then grows metal tungsten on it, replacing the sacrificial layer on the original gate with metal tungsten, that is, the final gate is composed of polysilicon and metal tungsten, which not only reduces the gate block resistance but also avoids the problem of metal contamination; in the scheme, since the growth of metal tungsten is placed in the pre-hole process stage and the sacrificial layer technology is used to achieve self-alignment, the compatibility and flexibility of the process are significantly improved, making the scheme easier to integrate with other process platforms.

[0080] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A method for forming a NAND metal gate, characterized in that: The steps include: Step 1: Using a wafer as a substrate, growing gate oxide on its surface, and then depositing polysilicon and a sacrificial layer in sequence; the polysilicon and the sacrificial layer form a gate; and obtaining an intermediate product A; Step 2: Etch the gate side of the intermediate product A to form a sidewall; Obtain product B; Step 3: growing a hole layer dielectric layer on the surface of the gate oxide etched in product B, grinding and flattening, and obtaining product C; Step 4: Etching the product C to remove the sacrificial layer, and obtaining the product D with a depression on the polysilicon surface; Step 5: sequentially growing low-resistance metal layers on the product D having depressions on the polysilicon surface to obtain product E; Step 6: Planarize the surface of product E, leaving only the low-resistance metal layer that replaces the sacrificial layer in the gate and exists in the depression on the polysilicon surface, to obtain a NAND metal gate.

2. The method for forming a NAND metal gate according to claim 1, characterized in that: In step 1, the gate oxide material includes silicon dioxide, and the thickness of the gate oxide is 3. The method for forming a NAND metal gate according to claim 1, characterized in that: In step 1, the thickness of the polysilicon is 4. The method for forming a NAND metal gate according to claim 1, characterized in that: In step 1, the material of the sacrificial layer includes silicon nitride, and the thickness of the sacrificial layer is 5. The method for forming a NAND metal gate according to claim 1, characterized in that: In step 2, the material of the sidewall spacer includes silicon nitride.

6. The method for forming a NAND metal gate according to claim 1, characterized in that: In step 3, the material of the porous dielectric layer includes silicon dioxide, and the thickness of the porous dielectric layer is 7. The method for forming a NAND metal gate according to claim 1, characterized in that: In step 3, the polishing and planarization specifically includes polishing to stop on the sacrificial layer and exposing the sacrificial layer by etching back.

8. The method for forming a NAND metal gate according to claim 1, characterized in that: In step 4, the process of etching and removing the sacrificial layer is specifically: using a wet etching method to remove the sacrificial layer with hot phosphoric acid.

9. The method for forming a NAND metal gate according to claim 1, characterized in that: In step 5, the material of the low resistance metal includes metal tungsten, and the thickness of the low resistance metal layer is

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