Manufacturing method of semiconductor device and semiconductor device

Abstract

The invention discloses a manufacturing method of a semiconductor device and the semiconductor device, and the method comprises the steps: providing a wafer stacking structure, forming a plurality of conductive structures in the wafer stacking structure, dividing the wafer stacking structure into a central region and an edge region, and forming a barrier layer and an isolation layer covering the barrier layer in the edge region of the wafer stacking structure, the barrier layer is located in the edge area, and at least part of the at least one conductive structure corresponds to the barrier layer; a device through hole and an edge through hole are formed, the device through hole is located in the central area, the edge through hole is located in the edge area and is formed corresponding to the coverage area of the barrier layer, at least one conductive structure is exposed through the device through hole, and the first depth of the device through hole is larger than the second depth of the edge through hole; the conductive structure is connected with the outside through the device through hole, and the conductive structure in the edge region is not exposed, so that the arc phenomenon caused by the contact of the conductive structure in a silicon through hole process in the device can be effectively reduced, and the performance of the semiconductor device is further improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device and a semiconductor device. Background Art

[0002] In the application process of integrated circuits, the performance of various devices will be affected by the manufacturing process. Because of the different materials between the layers in the manufacturing process, it is easy to cause damage to some materials, which in turn affects the electrical performance of the device.

[0003] In current semiconductor devices, arcing often occurs in wafer stacking structures during the Through Silicon Via (TSV) process, causing damage to the structures of other materials in the TSV, thereby affecting the electrical performance and reliability of the device. The damaged structure may also cause current leakage, increased resistance or signal transmission delay, thereby reducing the overall performance of the semiconductor device. Summary of the invention

[0004] The main technical problem solved by the present invention is to provide a method for manufacturing a semiconductor device and a semiconductor device, which can effectively reduce the arc phenomenon in the device and thus improve the performance of the semiconductor device.

[0005] In order to solve the above technical problems, a technical solution adopted in the present application is: providing a method for manufacturing a semiconductor device, comprising: providing a wafer stacking structure, wherein a plurality of conductive structures are formed in the wafer stacking structure, and the wafer stacking structure is divided into a central area and an edge area, a barrier layer and an isolation layer covering the barrier layer are formed in the edge area of ​​the wafer stacking structure, and the barrier layer is located in the edge area, and at least a portion of at least one of the conductive structures corresponds to the barrier layer; forming a device through hole and an edge through hole, the device through hole is located in the central area, and the edge through hole is located in the edge area and is formed corresponding to the covering area of ​​the barrier layer, wherein at least one of the conductive structures is exposed through the device through hole, and a first depth of the device through hole is greater than a second depth of the edge through hole.

[0006] In one embodiment of the present application, providing a wafer stacking structure includes: providing a first wafer, the first wafer including: a first substrate, a first dielectric layer arranged on the first surface of the first substrate, wherein a first conductive structure is formed in the first dielectric layer; providing a second wafer, the second wafer including: a second substrate, a second dielectric layer arranged on the first surface of the second substrate, wherein a second conductive structure is formed in the second dielectric layer; wherein the first wafer and the second wafer are bonded to form the wafer stacking structure, and the first conductive structure and the second conductive structure are connected to form the conductive structure in the wafer stacking structure.

[0007] In one embodiment of the present application, the forming of the device through hole and the edge through hole includes: performing a first etching using a first etching method to form a first portion of the device through hole and a first portion of the edge through hole, wherein the first portion of the device through hole extends along the isolation layer to the first dielectric layer in the wafer stacking structure and exposes the first dielectric layer; the first portion of the edge through hole extends along the isolation layer to the barrier layer and exposes the barrier layer, and a third depth of the first portion of the device through hole is greater than a fourth depth of the first portion of the edge through hole; performing a second etching using a second etching method to form a second portion of the device through hole and a second portion of the edge through hole, wherein the second portion of the device through hole extends along the first portion of the device through hole to the conductive structure and exposes the conductive structure; the second portion of the edge through hole extends along the first portion of the edge through hole to at least a portion of the barrier layer; wherein the first portion of the device through hole and the second portion of the device through hole constitute the device through hole, and the first portion of the edge through hole and the second portion of the edge through hole constitute the edge through hole.

[0008] In one embodiment of the present application, the first etching using the first etching method to form the first part of the device through hole and the first part of the edge through hole includes: using the first etching method to remove the isolation layer in the central area and the first substrate in the wafer stacking structure to form the first part of the device through hole; and removing the isolation layer in the edge area and exposing the barrier layer to form the first part of the edge through hole; the second etching using the second etching method to form the second part of the device through hole and the second part of the edge through hole includes: using the second etching method to remove at least a part of the first dielectric layer in the wafer stacking structure along the first part of the device through hole and expose the conductive structure to form the second part of the device through hole; and removing at least a part of the barrier layer along the first part of the edge through hole to form the second part of the edge through hole.

[0009] In one embodiment of the present application, a first etching rate of the central area by the first etching method is greater than a second etching rate of the edge area; a third etching rate of the central area by the second etching method is greater than a fourth etching rate of the edge area.

[0010] In one embodiment of the present application, providing the first wafer includes: providing the first substrate; forming the first dielectric layer on the first surface of the first substrate, and forming a first sub-conductive structure and the first bonding structure in the first dielectric layer, the first sub-conductive structure and the first bonding structure are connected to form the first conductive structure; wherein at least a portion of the first conductive structure in the edge region overlaps with the barrier layer in the height direction.

[0011] In one embodiment of the present application, after the first wafer and the second wafer are bonded, the second surface of the first substrate in the edge area is thinned, and the barrier layer is formed at least in the edge area of ​​the second surface of the first substrate, wherein the second surface of the first substrate serves as the first surface of the wafer stacking structure; and an isolation layer is formed to cover at least part of the barrier layer and the first substrate.

[0012] In one embodiment of the present application, providing a first wafer includes: providing a first substrate; and thinning the edge area of ​​the first surface of the first substrate in the edge area; forming the barrier layer on the first surface of the first substrate so that the barrier layer covers the edge area; forming the first dielectric layer on the first surface of the first substrate, covering the first substrate and the barrier layer, and forming a first sub-conductive structure and the first bonding structure in the first dielectric layer, wherein the first sub-conductive structure and the first bonding structure are connected to form the first conductive structure, the second surface of the first substrate serves as the first surface of the wafer stacking structure, and at least a portion of the first conductive structure overlaps with the barrier layer in the height direction.

[0013] In one embodiment of the present application, providing a second wafer includes: providing a second substrate, wherein the thickness of the second substrate is greater than the thickness of the first substrate in the first wafer; forming a second dielectric layer on the first surface of the second substrate, and forming a second sub-conductive structure and a second bonding structure in the second dielectric layer, wherein the second sub-conductive structure and the second bonding structure are connected to form the second conductive structure.

[0014] In order to solve the above technical problems, another technical solution adopted in the present application is: to provide a semiconductor device, including: a wafer stacking structure, wherein a conductive structure is formed in the wafer stacking structure, and the wafer stacking structure is divided into a central area and an edge area; a barrier layer, arranged on the first surface of the wafer stacking structure, the barrier layer is located in the edge area, and at least a portion of at least one of the conductive structures corresponds to the barrier layer; an isolation layer, covering the barrier layer and the first surface of the wafer stacking structure; a device through hole and an edge through hole, the device through hole is located in the central area, the edge through hole is located in the edge area and formed in the coverage area of ​​the barrier layer, wherein at least one of the conductive structures is exposed through the device through hole, and the first depth of the device through hole is greater than the second depth of the edge through hole.

[0015] In one embodiment of the present application, the wafer stacking structure includes: a first wafer, in which a first conductive structure is formed; a second wafer, in which a second conductive structure is formed; wherein the first wafer and the second wafer are bonded to form the wafer stacking structure, and the first conductive structure and the second conductive structure are connected to form the conductive structure in the wafer stacking structure.

[0016] In one embodiment of the present application, the device through hole penetrates the isolation layer in the central area and extends to the conductive structure of the wafer stacking structure, so that the conductive structure in the central area is exposed; the edge through hole penetrates the isolation layer in the edge area and at least a portion of the barrier layer.

[0017] In one embodiment of the present application, the first wafer includes: a first substrate; a first dielectric layer formed on the first surface of the first substrate, and a first sub-conductive structure and a first bonding structure are formed in the first dielectric layer, wherein the first sub-conductive structure and the first bonding structure are connected to form the first conductive structure; wherein the barrier layer is formed in the edge region of the second surface of the first substrate, and at least a portion of the first conductive structure overlaps with the barrier layer in a height direction.

[0018] In one embodiment of the present application, the first wafer includes: a first substrate; a barrier layer formed in the edge area of ​​the first surface of the first substrate; a first dielectric layer formed on the first surface of the first substrate and covering the barrier layer and the first surface of the first substrate, and a first sub-conductive structure and a first bonding structure are formed in the first dielectric layer, wherein the first sub-conductive structure and the first bonding structure are connected to form the first conductive structure, the second surface of the first substrate serves as the first surface of the wafer stacking structure, and at least a portion of the first conductive structure overlaps with the barrier layer in a height direction.

[0019] In one embodiment of the present application, the second wafer includes: a second substrate, wherein the thickness of the second substrate is greater than the thickness of the first substrate in the first wafer; a second dielectric layer formed on the first surface of the second substrate, and a second sub-conductive structure and a second bonding structure are formed in the second dielectric layer, wherein the second sub-conductive structure and the second bonding structure are connected to form the second conductive structure.

[0020] Different from the prior art, the manufacturing method of the semiconductor device provided in the present application includes: providing a wafer stacking structure, wherein a plurality of conductive structures are formed in the wafer stacking structure, and the wafer stacking structure is divided into a central area and an edge area, a barrier layer and an isolation layer covering the barrier layer are formed in the edge area of ​​the wafer stacking structure, and the barrier layer is located in the edge area, and at least a portion of at least one of the conductive structures corresponds to the barrier layer; forming a device through hole and an edge through hole, wherein the device through hole is located in the central area, and the edge through hole is located in the edge area and formed corresponding to the covering area of ​​the barrier layer, wherein at least one conductive structure is exposed through the device through hole, and the first depth of the device through hole is greater than the second depth of the edge through hole; that is, in the present application, a device through hole and an edge through hole are formed in the central area and the edge area of ​​the wafer stacking structure respectively, and the first depth of the device through hole is greater than the second depth of the edge through hole, and the conductive structure in the central area of ​​the wafer stacking structure is connected to the outside through the device through hole, while the conductive structure in the edge area is not exposed, which can effectively reduce the arc phenomenon of the conductive structure caused by the through silicon via process contacting the conductive structure in the device, thereby improving the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0022] Figure 1 It is a schematic flow chart of an embodiment of a method for manufacturing a semiconductor device in the present application;

[0023] Figure 2 is a structural schematic diagram of a first implementation of a first wafer in this application;

[0024] Figure 3 is a structural schematic diagram of the first embodiment of the wafer stacking structure in the present application;

[0025] Figure 4 is a schematic structural diagram of an embodiment of forming a barrier layer in the present application;

[0026] Figure 5 It is a structural schematic diagram of an embodiment of forming an isolation layer in the present application;

[0027] Figure 6 is a structural schematic diagram of a first embodiment of forming a first part of a device through hole and a first part of an edge through hole in the present application;

[0028] Figure 7 is a structural schematic diagram of a first embodiment of forming a second part of a device through hole and a second part of an edge through hole in the present application;

[0029] Figure 8 is a schematic structural diagram of the second embodiment of the first wafer in the present application;

[0030] Fig. 9 is a schematic diagram of a second embodiment of a wafer stacking structure in the present application;

[0031] Fig.10 is a structural schematic diagram of a second embodiment of forming a first part of a device through hole and a second part of an edge through hole in the present application;

[0032] Fig.11 It is a structural schematic diagram of a second embodiment of forming a second part of a device through hole and a second part of an edge through hole in the present application.

[0033] In the accompanying drawings, there are a wafer stacking structure 100, a first wafer 110, a first substrate 111, a first dielectric layer 112, a first conductive structure 113, a first sub-conductive structure 1131, a first bonding structure 1132, a third dielectric layer 114, a second wafer 120, a second substrate 121, a second dielectric layer 122, a second conductive structure 123, a second sub-conductive structure 1231, a second bonding structure 1232, a fourth dielectric layer 124, a blocking layer 200, an isolation layer 300, a device through hole 401, a first part 4011 of the device through hole, a second part 4012 of the device through hole, an edge through hole 402, a first part 4021 of the edge through hole, a second part 4022 of the edge through hole, a central area A, and an edge area B. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0035] The terms "first", "second", "third" in this application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first", "second", "third" can expressly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the embodiments of this application, all directional indications (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the steps or units listed, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0036] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0037] The present application is described in detail below with reference to the accompanying drawings and embodiments.

[0038] In the manufacturing process of existing semiconductor devices, especially semiconductor devices corresponding to wafer stacking structures, the edge area of ​​the semiconductor device is thinner and the central area is thicker. When performing the through silicon via (TSV) process, the edge area is usually etched and perforated first, while the central area has not been etched through. Therefore, when the central area continues to be etched, the conductive structure corresponding to the edge area will be contacted by the etching liquid, which will cause the conductive structure corresponding to the edge area to form an arc phenomenon. Because the conductive structure in the semiconductor device is connected, the arc phenomenon will cause the conductive structure in the semiconductor device to be damaged, thereby affecting the electrical performance and reliability of the device. The damaged structure may also cause current leakage, increased resistance or signal transmission delay, thereby reducing the overall performance of the semiconductor device.

[0039] Therefore, a method for manufacturing a semiconductor device is provided, which can effectively reduce arcing in the device and thus improve the performance of the semiconductor device.

[0040] See also Figure 1 , Figure 1 It is a flow chart of an embodiment of a method for manufacturing a semiconductor device in the present application.

[0041] like Figure 1 As shown, the semiconductor device manufacturing method of the present application comprises the following steps:

[0042] S100. Provide a wafer stacking structure, wherein a plurality of conductive structures are formed in the wafer stacking structure, and the wafer stacking structure is divided into a central area and an edge area, a barrier layer and an isolation layer covering the barrier layer are formed in the edge area of ​​the wafer stacking structure, the barrier layer is located in the edge area, and at least a portion of at least one conductive structure corresponds to the barrier layer.

[0043] Among them, the wafer stacking structure is a structure in which at least two wafers are stacked together, the conductive structure is any suitable conductive structure known to semiconductor devices, the barrier layer is any suitable barrier layer known to semiconductor devices, and the isolation layer is any suitable isolation layer known to semiconductor devices; the central area refers to the area where a through hole needs to be formed so that the specified target layer is exposed, and the target layer is not exposed in the edge area. The specified target layer here can be a conductive structure, that is, the conductive structure is not exposed in the edge area.

[0044] Specifically, at least two wafers are provided, and the wafers are bonded to obtain a wafer stacking structure, and a conductive structure is preset in the wafer stacking structure to divide the wafer stacking structure into a central area and an edge area; and a barrier layer is formed on the first surface of the wafer stacking structure, and the barrier layer is located in the edge area, and an isolation layer is formed on the barrier layer, so that the isolation layer covers at least part of the barrier layer and the first surface of the wafer stacking structure.

[0045] It can be understood that at least a portion of at least one conductive structure corresponds to the barrier layer. The correspondence here means that in the height direction, the conductive structure located in the edge area of ​​the wafer stacking structure at least partially overlaps with the barrier layer.

[0046] In some embodiments, the central area and the edge area occupy a portion of the first surface of the wafer stacking structure, that is, the first surface of the wafer stacking structure may also be divided into other areas, which may be set according to actual conditions.

[0047] It can be understood that the isolation layer covers the barrier layer and the first surface of the wafer stacking structure; wherein the wafer stacking structure is divided into a first surface and a second surface, and the first surface of the wafer stacking structure corresponds to the second surface of the wafer stacking structure, for example, the first surface of the wafer stacking structure can be an upper surface, and the second surface of the wafer stacking structure can be a lower surface.

[0048] S200, forming a device through hole and an edge through hole, wherein the device through hole is located in the central area, and the edge through hole is located in the edge area and corresponds to the coverage area of ​​the barrier layer, wherein at least one conductive structure is exposed through the device through hole, and a first depth of the device through hole is greater than a second depth of the edge through hole.

[0049] Among them, both the device through-hole and the edge through-hole are formed by the through-silicon via (TSV) process. The device through-hole needs to form a through-hole later to expose the conductive structure, so it is set in the central area. The barrier layer is used to block the continued extension of the edge through-hole, so it is set in the edge area.

[0050] Specifically, after setting a barrier layer and an isolation layer on the first surface of the wafer stacking structure, a device through hole is formed in the central area and an edge through hole is formed in the edge area, respectively. Because a barrier layer is set in the edge area, and there is no barrier layer in the central area where the device through hole is located, the first depth of the device through hole is greater than the second depth of the edge through hole.

[0051] It can be understood that the barrier layer can be a material layer that blocks etching, so that the etching rate corresponding to the edge through hole is smaller than the etching rate corresponding to the device through hole; the edge through hole is formed in the coverage area corresponding to the barrier layer, that is, the edge area of ​​the first surface of the wafer stacking structure covered by the barrier layer is the coverage area of ​​the barrier layer, and the edge through hole is formed in the coverage area of ​​the barrier layer.

[0052] In this embodiment, the wafer stacking structure is divided into a central area and an edge area, and a blocking layer is provided in the edge area to block the formation of silicon through vias in the edge area, so that the first depth of the device through via is greater than the second depth of the edge through via, and the conductive structure corresponding to the device through via in the wafer stacking structure is connected to the outside through the device through via, while the conductive structure corresponding to the edge through via is not exposed, and a portion of the first dielectric layer is present between the bottom of the edge through via and the corresponding conductive structure, so as to avoid the edge through via contacting the conductive structure, and effectively reduce the occurrence of arcing in the conductive structure caused by the edge through via contacting the conductive structure in the device, that is, effectively reduce the occurrence of arcing caused by the exposure of the conductive structure in the edge area, thereby improving the performance of the semiconductor device, and at the same time reducing the trimming process and reducing the cost.

[0053] The following is a description with reference to the accompanying drawings.

[0054] The operation flow of step S10 is as follows:

[0055] A first wafer and a second wafer are provided respectively, wherein a first bonding structure is formed in the first wafer and a second bonding structure is formed in the second wafer, and the first bonding structure and the second bonding structure are bonded to form a wafer stacking structure.

[0056] See also Figure 2 , Figure 2 It is a structural schematic diagram of the first implementation of the first wafer in this application.

[0057] like Figure 2 As shown, in some embodiments, the first wafer 110 may include a first substrate 111, a first dielectric layer 112 is formed on the first surface of the first substrate 111, and a first sub-conductive structure 1131 and a first bonding structure 1132 are formed in the first dielectric layer 112, wherein the first sub-conductive structure 1131 and the first bonding structure 1132 are connected to form a first conductive structure 113.

[0058] In some embodiments, the second wafer 120 may include a second substrate 121, a second dielectric layer 122 is formed on the first surface of the second substrate 121, and a second sub-conductive structure 1231 and a second bonding structure 1232 are formed in the second dielectric layer 122, wherein the second sub-conductive structure 1231 and the second bonding structure 1232 are connected to form a second conductive structure 123; it can be understood that in some embodiments, the structure of the second wafer can be the same as the structure of the first wafer, and the wafer stacking structure of the first wafer and the second wafer bonded can refer to Figure 3 .

[0059] In some embodiments, a third dielectric layer 114 is further formed on the first dielectric layer 112, and a fourth dielectric layer 124 is further formed on the second dielectric layer 122, wherein the third dielectric layer 114 covers the first dielectric layer 112 and exposes the first bonding structure 1132, and the fourth dielectric layer 124 covers the second dielectric layer 122 and exposes the second bonding structure 1232. The material of the third dielectric layer 114 and the fourth dielectric layer 124 can be a material used for isolation, such as an oxidized material. For specific configurations, refer to Figure 3 .

[0060] See also Figure 3 , Figure 3 It is a structural schematic diagram of the first embodiment of the wafer stacking structure in this application.

[0061] The first bonding structure 1132 and the second bonding structure 1232 are then bonded to form the first wafer 110 and the second wafer 120 to form a wafer stacking structure 100. The first sub-conductive structure 1131 is connected to the first bonding structure 1132 to form a first conductive structure 113. The second sub-conductive structure 1231 is connected to the second bonding structure 1232 to form a second conductive structure 123. The first conductive structure 113 is connected to the second conductive structure 123 and serves as a conductive structure in the wafer stacking structure.

[0062] Among them, the first substrate and the second substrate can be any suitable base material known in the art, for example, can be at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI).

[0063] In some embodiments, the wafer stack structure is divided into a central region A and an edge region B to provide etching positions for subsequent through silicon vias. Figure 4 .

[0064] In some embodiments, the area of ​​the first surface of the first wafer 110 is smaller than the area of ​​the first surface of the second wafer 120 .

[0065] Next, a barrier layer 200 is formed on the first surface of the wafer stack structure 100 , and an isolation layer 300 is formed on the barrier layer 200 .

[0066] See also Figure 4 , Figure 4 It is a structural schematic diagram of an embodiment of forming a barrier layer in the present application.

[0067] like Figure 4 As shown, in Figure 2 and Figure 3 On the basis of this, the second surface of the first substrate 111 is set as the first surface of the wafer stacking structure 100, that is, a barrier layer 200 is formed on the second surface of the first substrate 111, wherein the barrier layer 200 is located in the edge area B, and the barrier layer 200 covers at least a portion of at least one conductive structure in the wafer stacking structure, so as to prevent the conductive structure in the edge area from being exposed when the edge through hole is subsequently formed, thereby avoiding the arc generated by the exposed conductive structure of the edge through hole.

[0068] The barrier layer 200 may be made of a material different from that of the first substrate 111 , and the etching selectivity of the barrier layer 200 is greater than that of the first substrate. For example, the barrier layer 200 may be an oxide layer, and the first substrate 111 may be a silicon substrate.

[0069] In some embodiments, before forming the barrier layer 200 , the thickness of the first substrate 111 may be thinned from the second surface of the first substrate 111 , so that the thickness of the first substrate 111 is less than the thickness of the second substrate 121 .

[0070] In some embodiments, the first substrate 111 of the edge region B can be further thinned so that the thickness of the first substrate 111 of the edge region B is less than the thickness of the first substrate 111 of the central region A; wherein, there can be at least two edge regions B, which are respectively arranged on both sides of the central region A. For example, the central region A is arranged at the central position of the wafer stacking structure, and the edge regions B can be arranged at the edge positions on both sides of the wafer stacking structure to form a stepped structure.

[0071] Then, a barrier layer 200 is formed on the second surface of the first substrate 111, and the barrier layer 200 in the central region A is removed, while the barrier layer 200 in the edge region B is retained. In some embodiments, the remaining barrier layer 200 is formed on the stepped structure and is flush with the second surface of the first substrate 111. Furthermore, the sidewalls on both sides of the first wafer 110 may also be covered by the barrier layer 200 to prevent the sidewalls on both sides of the first wafer from being exposed, that is, to prevent the conductive structure in the wafer stacking structure from being exposed from both sides of the first wafer.

[0072] Next, an isolation layer is formed on the barrier layer.

[0073] See also Figure 5 , Figure 5 It is a structural schematic diagram of an embodiment of forming an isolation layer in the present application.

[0074] like Figure 5 As shown, in Figure 4 On the basis of, an isolation layer 300 is formed on the barrier layer 200 , wherein, because the barrier layer 200 is located in the edge region B, the isolation layer 300 covers the barrier layer 200 , and the isolation layer 300 also covers the second surface of the first substrate 111 .

[0075] The isolation layer 300 may be an oxide layer, such as a field oxide layer, and may further be a buried field oxide layer.

[0076] In some embodiments, a photoresist layer may also be covered to cover the isolation layer 300 and the barrier layer 200 on both sides of the first wafer 110 with the photoresist layer; wherein the photoresist layer corresponding to the step structure shrinks so that the thickness of the photoresist layer corresponding to the step structure is smaller than the thickness of the photoresist layer corresponding to other positions, that is, the thickness of the photoresist layer in the edge area B is relatively thin, so that it can be opened in advance during the subsequent through silicon via process.

[0077] Then, step S20 is performed to form a device through hole and an edge through hole. The operation flow of step S20 is as follows:

[0078] Specifically, it can be divided into two stages. The first stage forms the first part of the device through hole and the first part of the edge through hole, and the second stage forms the second part of the device through hole and the second part of the edge through hole, wherein the first part of the device through hole and the second part of the device through hole are connected and constitute the device through hole, and the first part of the edge through hole and the second part of the edge through hole are connected and constitute the edge through hole.

[0079] First, the first stage of etching is performed.

[0080] See also Figure 6 , Figure 6 It is a structural schematic diagram of a first embodiment of forming a first part of a device through hole and a first part of an edge through hole in the present application.

[0081] like Figure 6 As shown, in Figure 5 On the basis of, a first etching method is used to perform a first etching to form a first part 4011 of the device through hole in the central area A, and a first part 4021 of the edge through hole is formed in the edge area B; wherein the first part 4011 of the device through hole extends along the isolation layer 300 to the first dielectric layer 112 in the wafer stacking structure 100, and the first dielectric layer 112 is exposed through the first part 4011 of the device through hole; the first part 4021 of the edge through hole extends along the isolation layer 300 to the barrier layer 200, and the barrier layer 200 is exposed through the first part 4021 of the edge through hole, and the third depth corresponding to the first part 4011 of the device through hole is greater than the fourth depth corresponding to the first part 4021 of the edge through hole.

[0082] The first portion 4011 of the device through hole and the first portion 4021 of the edge through hole are etched synchronously using a first etching method, which may be an etching process or an etching solution.

[0083] Specifically, the first etching method is set to the first etching liquid, and the first etching liquid is used to remove part of the isolation layer 300 in the central area A and part of the first substrate 111 in the wafer stacking structure to form a first part 4011 of the device through hole, and the first dielectric layer 112 in the central area A is exposed through the first part 4011 of the device through hole; at the same time, the first etching liquid is used to remove part of the isolation layer 300 in the edge area B, and the blocking layer 200 is exposed to form the first part 4021 of the edge through hole.

[0084] It can be understood that the first etching rate of the central area A by the first etching method is greater than the second etching rate of the edge area B, that is, the first etching rate of the first etching solution corresponding to the first etching method on the first substrate 111 in the central area A is greater than the second etching rate on the barrier layer 200 in the edge area B, that is, there is a difference in the etching selectivity between the silicon substrate as the first substrate 111 and the silicon oxide as the isolation layer 200, that is, the etching selectivity of the isolation layer 200 is greater than the etching selectivity of the silicon substrate, so that when the first etching is performed, the barrier layer in the edge area B is etched slowly, while the first substrate in the central area A is etched faster.

[0085] Next, the second stage of etching is performed.

[0086] See also Figure 7 , Figure 7 It is a structural schematic diagram of the first embodiment of forming the second part of the device through hole and the second part of the edge through hole in the present application.

[0087] like Figure 7 As shown, in Figure 6 On the basis of the present invention, a second etching method is used to perform a second etching, and a second part 4012 of the device through hole is formed in the first part 4011 of the device through hole in the central area A, thereby forming a device through hole 401, so that the conductive structure of the central area A is exposed through the device through hole 401; and a second part 4022 of the edge through hole is formed in the first part 4021 of the edge through hole in the edge area B, wherein the second part 4021 of the edge through hole extends along the first part 4022 of the edge through hole to at least a part of the barrier layer 200, thereby forming the edge through hole 402.

[0088] Among them, the second part 4012 of the device through hole and the second part 4022 of the edge through hole are etched synchronously using a second etching method. The second etching method can be an etching process or etching liquid, and the second etching liquid corresponding to the second etching method is different from the first etching liquid corresponding to the first etching method.

[0089] Specifically, a second etching liquid is used to remove at least a portion of the first dielectric layer 112 in the wafer stacking structure along the first portion 4011 of the device through hole in the central region A to form a second portion 4012 of the device through hole, and the conductive structure in the central region A is exposed through the second portion 4012 of the device through hole. Simultaneously, a second etching liquid is used to remove at least a portion of the barrier layer 200 along the first portion 4021 of the edge through hole in the edge region B to form a second portion 4022 of the edge through hole.

[0090] It can be understood that the third etching rate of the second etching method for the central area A is greater than the fourth etching rate for the edge area B, that is, the third etching rate of the second etching solution corresponding to the second etching method for the first dielectric layer 112 in the central area A is greater than the fourth etching rate for the barrier layer 200 in the edge area B, that is, as the material of the first dielectric layer 112 and the material of the barrier layer are different, there is a difference in the corresponding etching selectivity, that is, the etching selectivity of the first dielectric layer 112 is greater than the etching selectivity of the barrier layer, so that when the second etching is performed, the first substrate in the edge area B is etched slowly, while the first dielectric layer in the central area A is etched faster.

[0091] In some embodiments, there may also be a difference in etching selectivity between the silicon oxide and the barrier layer of the first dielectric layer 112, so that the area where the second portion 4022 of the edge through hole is located is etched slowly, and when the second portion 4022 of the edge through hole in the edge area is etched to the first substrate, the second portion 4012 of the device through hole is just etched to the conductive structure of the central area A, exposing the conductive structure.

[0092] In some embodiments, the edge through hole 402 extends into the barrier layer 200 and does not penetrate the barrier layer 200; in other embodiments, the edge through hole 402 can penetrate the barrier layer 200 and expose the first substrate 111 of the first wafer in the wafer stacking structure; in other embodiments, the edge through hole 402 can also extend into the first substrate 111; in other embodiments, the edge through hole 402 can also extend into the first dielectric layer 112, but the conductive structure of the edge area B is at a distance from the bottom of the edge through hole 402, so that the conductive structure of the edge area B is not exposed from the edge through hole 402, so as to avoid arcing caused by exposing the conductive structure of the edge through hole.

[0093] In some embodiments, a conductive material may be subsequently filled in the device through hole 401 so that the conductive structure in the central area A of the wafer stacking structure is electrically connected to the outside.

[0094] In this embodiment, when the first part of the through hole is formed, the central area is silicon and the edge area is silicon oxide, and the etching of the edge area is slow. When the second part of the through hole is formed, the central area is silicon oxide and the edge area is silicon, and the etching of the edge area is slow, forming a film inversion between the edge area and the central area, so that the silicon through hole in the edge area cannot contact the conductive structure corresponding to the edge area A in the wafer stacking structure, reducing the occurrence of arc phenomenon and improving the electrical performance of the device; and the barrier layer existing on the side wall can protect the side wall and reduce the formation of a protective dielectric layer (Passive Dielectric, PD).

[0095] In some embodiments, the first wafer may be in another form.

[0096] See also Figure 8 , Figure 8 It is a schematic diagram of the structure of the second embodiment of the first wafer in this application.

[0097] like Figure 8 As shown, a first substrate 111 is provided, and an edge region B of a first surface of the first substrate 111 is thinned, and a barrier layer 200 is formed on the first surface of the first substrate 111 so that the barrier layer 200 covers the edge region; a first dielectric layer 112 is then formed on the first surface of the first substrate 111 so that the first dielectric layer 112 covers the first substrate 111 and the barrier layer 200; and a first sub-conductive structure 1131 and a first bonding structure 1132 are formed in the first dielectric layer 112, and the barrier layer corresponds to at least a portion of the first sub-conductive structure in the edge region B, wherein the first sub-conductive structure 1131 and the first bonding structure 1132 are connected to form a first conductive structure 113.

[0098] The bonding of the first wafer and the second wafer is the same as described above and will not be repeated here.

[0099] See also Fig. 9 , Fig. 9 It is a schematic diagram of the second embodiment of the wafer stacking structure in the present application.

[0100] like Fig. 9 As shown, they are provided Figure 8 The first wafer 110 and the second wafer 120 are shown, wherein a first bonding structure 1132 is formed in the first wafer 110, and a second bonding structure 1232 is formed in the second wafer. The first bonding structure 1132 and the second bonding structure 1232 are bonded to form a wafer stacking structure 100, and an isolation layer 300 is formed on the second surface of the first wafer. The structure of the first wafer 110 can be referred to in Figure 8 The structure of the second wafer can be found in Figure 2 .

[0101] Then, the device via and the edge via are formed, which is also divided into two stages. The first stage forms the first part of the device via and the first part of the edge via, and the second stage forms the second part of the device via and the second part of the edge via.

[0102] First, the first stage of etching is performed.

[0103] See also Fig.10 , Fig.10 It is a structural schematic diagram of a second embodiment of forming a first part of a device through hole and a first part of an edge through hole in the present application.

[0104] like Fig.10 As shown, in Fig. 9 On the basis of, a first etching method is used to perform a first etching to form a first part 4011 of the device through hole in the central area A, and a first part 4021 of the edge through hole is formed in the edge area B; wherein the first part 4011 of the device through hole extends along the isolation layer 300 to the first dielectric layer 112 in the wafer stacking structure 100, and the first dielectric layer 112 is exposed through the first part 4011 of the device through hole; the first part 4021 of the edge through hole extends along the isolation layer 300 to the barrier layer 200, wherein the first substrate 111 of the edge area B is penetrated, and the barrier layer 200 is exposed through the first part 4021 of the edge through hole, and the third depth corresponding to the first part 4011 of the device through hole is greater than the fourth depth corresponding to the first part 4021 of the edge through hole.

[0105] The first portion 4011 of the device through hole and the first portion 4021 of the edge through hole are etched synchronously using a first etching method, which may be an etching process or an etching solution.

[0106] Specifically, the first etching method is set to the first etching liquid, and the first etching liquid is used to remove the portion of the isolation layer 300 in the central area A and the portion of the first substrate 111 in the wafer stacking structure to form the first portion 4011 of the device through hole, that is, to penetrate the isolation layer 300 and the first substrate 111, and to expose the first dielectric layer 112 in the central area A through the first portion 4011 of the device through hole; at the same time, the first etching liquid is used to remove the portion of the isolation layer 300 and the portion of the first substrate 111 in the edge area B, that is, to penetrate the isolation layer 300 and the first substrate 111, and to expose the barrier layer 200 to form the first portion 4021 of the edge through hole. The thickness of the first substrate in the central area A is greater than the thickness of the first substrate in the edge area B.

[0107] It can be understood that the first etching rate of the central area A by the first etching method is greater than the second etching rate of the edge area B, that is, the first etching rate of the first etching solution corresponding to the first etching method on the first substrate 111 in the central area A is greater than the second etching rate on the barrier layer 200 in the edge area B, that is, there is a difference in the etching selectivity between the silicon substrate as the first substrate 111 and the silicon oxide as the isolation layer 200, that is, the etching selectivity of the isolation layer 200 is greater than the etching selectivity of the silicon substrate, so that when the first etching is performed, the barrier layer in the edge area B is etched slowly, while the first substrate in the central area A is etched faster.

[0108] Then the second stage of etching is carried out.

[0109] See also Fig.11 , Fig.11It is a structural schematic diagram of a second embodiment of forming a second part of a device through hole and a second part of an edge through hole in the present application.

[0110] like Fig.11 As shown, in Fig.10 On the basis of the present invention, a second etching method is used to perform a second etching, and a second part 4012 of the device through hole is formed in the first part 4011 of the device through hole in the central area A, thereby forming the device through hole 401, so that the conductive structure of the central area A is exposed through the device through hole 401; and a second part 4022 of the edge through hole is formed in the first part 4021 of the edge through hole in the edge area B, wherein the second part 4022 of the edge through hole extends along the first part 4021 of the edge through hole to at least a part of the barrier layer 200, thereby forming the edge through hole 402.

[0111] Among them, the second part 4012 of the device through hole and the second part 4022 of the edge through hole are etched synchronously using a second etching method. The second etching method can be an etching process or etching liquid, and the second etching liquid corresponding to the second etching method is different from the first etching liquid corresponding to the first etching method.

[0112] Specifically, a second etching liquid is used to remove at least a portion of the first dielectric layer 112 in the wafer stacking structure along the first portion 4011 of the device through hole in the central region A to form a second portion 4012 of the device through hole, i.e., penetrate the first dielectric layer 112, and expose the conductive structure in the central region A through the second portion 4012 of the device through hole; simultaneously, a second etching liquid is used to remove at least a portion of the barrier layer 200 along the first portion 4021 of the edge through hole in the edge region B to penetrate the barrier layer 200, so that the first substrate 111 of the first wafer in the wafer stacking structure is exposed to form a second portion 4022 of the edge through hole.

[0113] It can be understood that the third etching rate of the second etching method for the central area A is greater than the fourth etching rate for the edge area B, that is, the third etching rate of the second etching solution corresponding to the second etching method for the first dielectric layer 112 in the central area A is greater than the fourth etching rate for the barrier layer 200 in the edge area B, that is, the material of the first dielectric layer 112 and the material of the barrier layer 200 are different, and there is a difference in the corresponding etching selectivity, that is, the etching selectivity of the first dielectric layer 112 is greater than the etching selectivity of the barrier layer 200, so that when the second etching is performed, the barrier layer in the edge area B is etched slowly, while the first dielectric layer in the central area A is etched faster.

[0114] In some embodiments, the edge through hole 402 extends into the barrier layer 200 and does not penetrate the barrier layer 200; in other embodiments, the edge through hole 402 can also extend into the first substrate 111; in other embodiments, the edge through hole 402 can also extend into the first dielectric layer 112, but the conductive structure of the edge region B is at a distance from the bottom of the edge through hole 402, so that the conductive structure of the edge region B is not exposed from the edge through hole 402, so as to avoid arcing caused by the conductive structure exposed by the edge through hole.

[0115] In the present embodiment, when the first part of the through hole is formed, the central area is silicon and the edge area is silicon oxide, and the etching of the edge area is slow. When the second part of the through hole is formed, the central area is silicon oxide and the edge area is silicon, and the etching of the edge area is slow, forming a film inversion between the edge area and the central area, so that the silicon through hole in the edge area cannot contact the conductive structure corresponding to the edge area in the wafer stacking structure, that is, avoiding the exposure of the conductive structure in the edge area, which can effectively reduce the occurrence of arc phenomenon caused by the exposure of the conductive structure in the edge area, and improve the electrical performance of the device.

[0116] The present application also provides a semiconductor device, referring to Figure 2-Figure 11 .

[0117] Specifically, the semiconductor device includes: a wafer stacking structure 100, a barrier layer 200, an isolation layer 300, a device through hole 401 and an edge through hole 402. Among them, a plurality of conductive structures are formed in the wafer stacking structure 100, and the wafer stacking structure is divided into a central area A and an edge area B; the barrier layer 200 is arranged on the first surface of the wafer stacking structure 100, and the barrier layer 200 is located in the edge area B, and at least a portion of at least one conductive structure corresponds to the barrier layer 200; the isolation layer 300 covers the barrier layer 200 and the first surface of the wafer stacking structure 100; the device through hole 401 is located in the central area A, the edge through hole 402 is located in the edge area B and is formed in the coverage area of ​​the barrier layer 200, and the device through hole 401 extends along the isolation layer 300 to the wafer stacking structure The conductive structure in the central region A is exposed through the device through hole 401; the edge through hole 402 extends along the isolation layer 300 to at least a portion of the barrier layer 200, and the first depth of the device through hole 401 is greater than the second depth of the edge through hole 402; and the conductive structure corresponding to the edge through hole 402 is not exposed, and a portion of the first dielectric layer is present between the bottom of the edge through hole 402 and the corresponding conductive structure, that is, the edge through hole 402 is prevented from contacting the conductive structure, which can effectively reduce the occurrence of arcing caused by the exposure of the conductive structure in the edge region B, thereby improving the performance of the semiconductor device.

[0118] It can be understood that at least a portion of at least one conductive structure corresponds to the barrier layer. The correspondence here means that in the height direction, the conductive structure located in the edge area of ​​the wafer stacking structure at least partially overlaps with the barrier layer.

[0119] In some embodiments, the wafer stacking structure 100 includes: a first wafer 110, wherein a first conductive structure 113 is formed in the first wafer 110; a second wafer 120, wherein a second conductive structure 123 is formed in the second wafer 120, the second wafer 120 and the first wafer 110 are bonded to form the wafer stacking structure 100, and the first conductive structure 113 and the second conductive structure 123 are connected to form a conductive structure in the wafer stacking structure 100.

[0120] In some embodiments, the device through hole 401 penetrates the isolation layer 300 in the central area A and extends to the conductive structure of the wafer stacking structure 100, exposing the conductive structure in the central area A; the edge through hole 402 penetrates the isolation layer 300 in the edge area B and at least a portion of the barrier layer 200.

[0121] In some embodiments, the first wafer 110 includes: a first substrate 111; a first dielectric layer 112, formed on the first surface of the first substrate 111, and a first sub-conductive structure 1131 and a first bonding structure 1132 are formed in the first dielectric layer 112, wherein the first sub-conductive structure 1131 and the first bonding structure 1132 are connected to form a first conductive structure 113; wherein the barrier layer 200 is formed in an edge region B of the second surface of the first substrate 111, and at least a portion of the first conductive structure 113 overlaps with the barrier layer 200 in the height direction.

[0122] In other embodiments, the first wafer 110 includes: a first substrate 111; a barrier layer 200 formed in an edge region of a first surface of the first substrate 111; a first dielectric layer 112 formed on a first surface of the first substrate 111 and covering the barrier layer 200 and the first surface of the first substrate 111, and a first sub-conductive structure 1131 and a first bonding structure 1132 are formed in the first dielectric layer 112, wherein the first sub-conductive structure 1131 and the first bonding structure 1132 are connected to form a first conductive structure 113, the second surface of the first substrate 111 serves as the first surface of the wafer stacking structure 100, and at least a portion of the first conductive structure 113 overlaps with the barrier layer 200 in a height direction.

[0123] In some embodiments, the edge through hole 402 extends into the barrier layer 200 and does not penetrate the barrier layer 200; in other embodiments, the edge through hole 402 can penetrate the barrier layer 200 and expose the first substrate 111 of the first wafer in the wafer stacking structure; in other embodiments, the edge through hole 402 can also extend into the first substrate 111; in other embodiments, the edge through hole 402 can also extend into the first dielectric layer 112, but the conductive structure of the edge area B is at a distance from the bottom of the edge through hole 402, so that the conductive structure of the edge area B is not exposed from the edge through hole 402, so as to avoid arcing caused by exposing the conductive structure of the edge through hole.

[0124] In some embodiments, the second wafer 120 includes: a second substrate 121, wherein the thickness of the second substrate 121 is greater than the thickness of the first substrate 111 in the first wafer 110; a second dielectric layer 122 is formed on the first surface of the second substrate 121, and a second sub-conductive structure 1231 and a second bonding structure 1232 are formed in the second dielectric layer 122, wherein the second sub-conductive structure 1231 and the second bonding structure 1232 are connected to form a second conductive structure 123, and the second conductive structure 123 and the first conductive structure 113 in the first wafer constitute a conductive structure of a wafer stacking structure.

[0125] In this embodiment, a device through hole is formed in the central area of ​​the wafer stacking structure, and an edge through hole is formed in the edge area, and the first depth of the device through hole is greater than the second depth of the edge through hole, and the conductive structure corresponding to the device through hole in the wafer stacking structure is connected to the outside through the device through hole, while the conductive structure corresponding to the edge through hole is not exposed, and there is a partial first dielectric layer between the bottom of the edge through hole and the corresponding conductive structure, that is, the edge through hole is prevented from contacting the conductive structure; the occurrence of arc phenomenon caused by the exposure of the conductive structure in the edge area can be effectively reduced, thereby improving the electrical performance of the device.

[0126] The above description is only an implementation mode of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: A wafer stacking structure is provided, wherein a plurality of conductive structures are formed in the wafer stacking structure, and the wafer stacking structure is divided into a central area and an edge area, a barrier layer and an isolation layer covering the barrier layer are formed in the edge area of ​​the wafer stacking structure, the barrier layer is located in the edge area, and at least a portion of at least one of the conductive structures corresponds to the barrier layer; A device through hole and an edge through hole are formed, wherein the device through hole is located in the central area, and the edge through hole is located in the edge area and formed corresponding to the covering area of ​​the barrier layer, wherein at least one of the conductive structures is exposed through the device through hole, and a first depth of the device through hole is greater than a second depth of the edge through hole.

2. The method according to claim 1, characterized in that The wafer stacking structure provided comprises: Providing a first wafer, the first wafer comprising: a first substrate, and a first dielectric layer arranged on a first surface of the first substrate, wherein a first conductive structure is formed in the first dielectric layer; Providing a second wafer, the second wafer comprising: a second substrate, and a second dielectric layer arranged on a first surface of the second substrate, wherein a second conductive structure is formed in the second dielectric layer; The first wafer and the second wafer are bonded to form the wafer stacking structure, and the first conductive structure and the second conductive structure are connected to form the conductive structure in the wafer stacking structure.

3. The method according to claim 2, characterized in that The forming of device through holes and edge through holes comprises: Performing a first etching process using a first etching method to form a first portion of the device through hole and a first portion of the edge through hole, wherein the first portion of the device through hole extends along the isolation layer to the first dielectric layer in the wafer stacking structure, and exposes the first dielectric layer; the first portion of the edge through hole extends along the isolation layer to the barrier layer, and exposes the barrier layer, and a third depth of the first portion of the device through hole is greater than a fourth depth of the first portion of the edge through hole; Performing a second etching using a second etching method to form a second portion of the device through hole and a second portion of the edge through hole, wherein the second portion of the device through hole extends along the first portion of the device through hole to the conductive structure and exposes the conductive structure; the second portion of the edge through hole extends along the first portion of the edge through hole to at least a portion of the barrier layer; The first part of the device through hole and the second part of the device through hole constitute the device through hole, and the first part of the edge through hole and the second part of the edge through hole constitute the edge through hole.

4. The method according to claim 3, characterized in that The first etching is performed by using a first etching method to form a first portion of the device through hole and a first portion of the edge through hole, comprising: Using the first etching method, a portion of the isolation layer in the central area and a portion of the first substrate in the wafer stacking structure are removed to form a first portion of the device through hole; and a portion of the isolation layer in the edge area is removed to form a first portion of the edge through hole, and the barrier layer is exposed; The second etching is performed by using a second etching method to form a second portion of the device through hole and a second portion of the edge through hole, comprising: Using the second etching method, at least a portion of the first dielectric layer in the wafer stacking structure is removed along the first portion of the device through hole to form the second portion of the device through hole and to expose the conductive structure; and at least a portion of the barrier layer is removed along the first portion of the edge through hole to form the second portion of the edge through hole.

5. The method according to claim 3 or 4, characterized in that: The first etching rate of the central region by the first etching method is greater than the second etching rate of the edge region; the third etching rate of the central region by the second etching method is greater than the fourth etching rate of the edge region.

6. The method according to claim 2, characterized in that The providing of a first wafer comprises: providing the first substrate; forming the first dielectric layer on the first surface of the first substrate, and forming a first sub-conductive structure and a first bonding structure in the first dielectric layer, wherein the first sub-conductive structure and the first bonding structure are connected to form the first conductive structure; Wherein, at least a portion of the first conductive structure in the edge region overlaps with the barrier layer in a height direction.

7. The method according to claim 6, further comprising: After the first wafer and the second wafer are bonded, the second surface of the first substrate in the edge region is thinned, and the barrier layer is formed at least in the edge region of the second surface of the first substrate, wherein the second surface of the first substrate serves as the first surface of the wafer stacking structure; An isolation layer is formed to cover at least a portion of the barrier layer and the first substrate.

8. The method according to claim 2, characterized in that: The providing of a first wafer comprises: Providing a first substrate; and thinning a first surface of the first substrate in the edge region; forming the barrier layer on the first surface of the first substrate so that the barrier layer covers the edge region; The first dielectric layer is formed on the first surface of the first substrate to cover the first substrate and the barrier layer, and a first sub-conductive structure and a first bonding structure are formed in the first dielectric layer, wherein the first sub-conductive structure and the first bonding structure are connected to form the first conductive structure, the second surface of the first substrate serves as the first surface of the wafer stacking structure, and at least a portion of the first conductive structure overlaps with the barrier layer in a height direction.

9. The method according to claim 2, characterized in that: The providing of the second wafer comprises: Providing the second substrate, wherein the thickness of the second substrate is greater than the thickness of the first substrate in the first wafer; The second dielectric layer is formed on the first surface of the second substrate, and a second sub-conductive structure and a second bonding structure are formed in the second dielectric layer, wherein the second sub-conductive structure and the second bonding structure are connected to form the second conductive structure.

10. A semiconductor device, characterized in that: include: A wafer stacking structure, wherein a plurality of conductive structures are formed in the wafer stacking structure, and the wafer stacking structure is divided into a central area and an edge area; A barrier layer is disposed on the first surface of the wafer stack structure, the barrier layer is located in the edge region, and at least a portion of at least one of the conductive structures corresponds to the barrier layer; an isolation layer, covering the barrier layer and the first surface of the wafer stacking structure; A device through hole and an edge through hole, wherein the device through hole is located in the central area, and the edge through hole is located in the edge area and formed in the covering area of ​​the barrier layer, wherein at least one of the conductive structures is exposed through the device through hole, and the first depth of the device through hole is greater than the second depth of the edge through hole.

11. The semiconductor device according to claim 10, characterized in that The wafer stacking structure comprises: a first wafer, wherein a first conductive structure is formed in the first wafer; a second wafer having a second conductive structure formed therein; The first wafer and the second wafer are bonded to form the wafer stacking structure, and the first conductive structure and the second conductive structure are connected to form the conductive structure in the wafer stacking structure.

12. The semiconductor device according to claim 10 or 11, characterized in that: The device through hole penetrates the isolation layer in the central area and extends to the conductive structure of the wafer stacking structure, so that the conductive structure in the central area is exposed; The edge through hole penetrates the isolation layer in the edge region and at least a portion of the barrier layer.

13. The semiconductor device according to claim 11, characterized in that The first wafer comprises: a first substrate; A first dielectric layer is formed on the first surface of the first substrate, and a first sub-conductive structure and a first bonding structure are formed in the first dielectric layer, wherein the first sub-conductive structure and the first bonding structure are connected to form the first conductive structure; The barrier layer is formed in the edge region of the second surface of the first substrate, and at least a portion of the first conductive structure overlaps with the barrier layer in a height direction.

14. The semiconductor device according to claim 11, characterized in that The first wafer comprises: a first substrate; a barrier layer formed in the edge region of the first surface of the first substrate; A first dielectric layer is formed on the first surface of the first substrate and covers the barrier layer and the first surface of the first substrate, and a first sub-conductive structure and a first bonding structure are formed in the first dielectric layer, wherein the first sub-conductive structure and the first bonding structure are connected to form the first conductive structure, the second surface of the first substrate serves as the first surface of the wafer stacking structure, and at least a portion of the first conductive structure overlaps with the barrier layer in a height direction.

15. The semiconductor device according to claim 11, wherein: The second wafer comprises: a second substrate, wherein the thickness of the second substrate is greater than the thickness of the first substrate in the first wafer; A second dielectric layer is formed on the first surface of the second substrate, and a second sub-conductive structure and a second bonding structure are formed in the second dielectric layer, wherein the second sub-conductive structure and the second bonding structure are connected to form the second conductive structure.

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