Wafer level fabrication of electrostatic discharge devices

Abstract

Embodiments of the invention relate to wafer level fabrication of electrostatic discharge devices. In an example, a package (106A) includes first and second dies (351, 352) that include first and second diodes (313, 315), respectively. The package includes first and second metal contacts (354, 356) coupled to bottom surfaces of the first and second dies, respectively, wherein the first and second metal contacts are exposed to a bottom surface of the package. The package also includes an isolation layer (326) between the first die and the second die and between the first metal contact and the second metal contact, and a metal layer (310) coupled to top surfaces of the first die and the second die. The package also includes a molding compound (320) covering the first and second dies and the metal layer.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductors, and more particularly, to wafer-level fabrication of electrostatic discharge devices. Background Art

[0002] A semiconductor wafer is a circular piece of semiconductor material (e.g., silicon) from which semiconductor chips are made. Typically, many integrated circuits are formed on a single wafer using complex manufacturing processes. Forming such circuits on a wafer is called fabrication. After wafer fabrication, the wafer is cut into multiple pieces, called semiconductor dies, where each die contains one of the circuits. Cutting or sawing the wafer into individual dies is called singulation. Summary of the invention

[0003] In an example, a package includes a first die and a second die, each including a first diode and a second diode. The package includes a first metal contact and a second metal contact coupled to a bottom surface of the first die and the second die, respectively, wherein the first metal contact and the second metal contact are exposed to the bottom surface of the package. The package also includes an isolation layer between the first die and the second die and between the first metal contact and the second metal contact, and a metal layer coupled to a top surface of the first die and the second die. The package also includes a molding compound covering the first die and the second die and the metal layer.

[0004] In an example, a method for manufacturing a package includes forming a metal layer on a first surface of a semiconductor wafer. The wafer includes a first diode and a second diode and a first metal contact and a second metal contact coupled to the first diode and the second diode, the first metal contact and the second metal contact being separated by a first gap. The metal layer is formed on the first metal contact and the second metal contact. The method also includes forming a third metal contact and a fourth metal contact on a second surface of the wafer, the second surface being opposite to the first surface of the wafer, wherein a second gap between the third metal contact and the fourth metal contact is vertically aligned with the first gap. The method includes covering the metal layer and the wafer with a molding compound. The method also includes forming a trench in the wafer passing through the first gap and the second gap, filling the trench with an isolation material, and singulating the wafer to produce a package. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a block diagram of an electronic device including an electrostatic discharge device according to various examples.

[0006] Figure 2 is a flow chart of a method for manufacturing an electrostatic discharge device according to various examples.

[0007] Figures 3A1-3G3 A process flow of a method for manufacturing an electrostatic discharge device according to various embodiments. DETAILED DESCRIPTION

[0008] Various electronic devices (e.g., laptop and desktop computers, consumer electronics such as televisions, appliances, etc.) experience occasional overvoltage conditions that represent a threat to the functional integrity of the device. An overvoltage condition, for example, may be associated with a power surge that may damage the electronic device and render it unusable. For example, a dangerously high voltage may be provided to pins within a Universal Serial Bus (USB) port, potentially damaging the electronic device containing the port and / or any other device that may be coupled to the port.

[0009] Some devices are suitable for mitigating the risks associated with overvoltage conditions. Generally, such devices contain diodes connected to each other using bond wires. As a result, the devices are undesirably large and expensive. Efforts to reduce the size and cost of the devices result in reduced performance.

[0010] The present disclosure describes various examples of electrostatic discharge devices (ESD) that mitigate the challenges described above. Specifically, the ESD is manufactured in a manner that reduces the size and cost typically associated with such devices without reducing performance. In an example, an ESD package includes a first die and a second die, which include a first diode and a second diode, respectively. The package also includes a first metal contact and a second metal contact coupled to the bottom surface of the first die and the second die, respectively, wherein the first metal contact and the second metal contact are exposed to the bottom surface of the package. The package also includes an isolation layer between the first die and the second die and between the first metal contact and the second metal contact, and a metal layer coupled to the top surface of the first die and the second die. The package includes a molding compound covering the first die and the second die and the metal layer.

[0011] Figure 11 is a block diagram of an electronic device 100 including an electrostatic discharge device (ESD) according to various examples. The electronic device 100 may be any suitable type of device, such as a computer (e.g., a laptop, a desktop computer, a notebook computer), a consumer electronic device (e.g., a television, a stereo system), an appliance, a vehicle, an aircraft, a spacecraft, and the like. The electronic device 100 includes an interface connector 102, such as a universal serial bus (USB) port, a high-definition multimedia interface (HDMI) port, and the like. Other types of ports and connectors are contemplated and are included within the scope of the present disclosure. An integrated circuit (IC) 104 is coupled to the connector 102. For example, the IC 104 may include circuitry configured to perform one or more functions to enable or facilitate operation of the electronic device 100. The connector 102 may be coupled to another device external to the electronic device 100, which is implemented with a cable (e.g., a USB or HDMI cable) that facilitates communication between the external device and the IC 104 and with other circuitry and / or devices that may be coupled to the connector 102.

[0012] The electronic device 100 may include an ESD 106 coupled to a connector 102 and an IC 104. In some examples, the connector 102, the IC 104, and the ESD 106 may be coupled to a common printed circuit board (PCB). In other examples, one or more of the connector 102, the IC 104, and the ESD 106 may be coupled to different PCBs. The IC 104 may be coupled to specific pins of the connector 102, and the ESD 106 may be coupled to at least those pins coupled to the IC 104. The ESD 106 is configured to protect the IC 104 from the consequences of an overvoltage condition. Specifically, when an overvoltage condition occurs, the voltage provided from the connector 102 to the IC 104 on a node 108 may exceed a voltage threshold that the IC 104 can safely tolerate. The ESD 106 is configured to close the circuit to ground 110 when the voltage on the node 108 begins to approach this dangerous voltage threshold, but before actually reaching the voltage threshold. In this way, the voltage on node 108 is pulled to or close to ground, thereby reducing risk to IC 104 .

[0013] As described above, the ESD is manufactured using a process that requires multiple diodes to be wire bonded together. Also as described above, the resulting ESD consumes an unacceptable amount of space and has a high manufacturing cost. Techniques used to reduce the size and cost of the ESD result in reduced performance. Figure 2 and 3A1 - The ESD 106 manufacturing process described in 3G3 is cheaper than a manufacturing process using wire bonding for electrical connections and produces less ESD without degrading performance. Figures 3A1-3G3 Structural details of ESD 106 are also depicted.

[0014] Figure 2 is a flow chart of a method 200 for manufacturing an ESD (eg, ESD 106 ) according to various examples. Figures 3A1-3G3 is a process flow of a method for manufacturing an ESD (e.g., ESD 106) according to various embodiments. Figure 2 and 3A1 -3G3.

[0015] Method 200 begins by forming a metal layer on a first surface of a semiconductor wafer (202). The wafer includes a first diode and a second diode and a first metal contact and a second metal contact coupled to the first diode and the second diode (202). The first metal contact and the second metal contact are separated by a first gap (202). The metal layer is formed on the first metal contact and the second metal contact (202). Figure 3A1 A cross-sectional view of wafer 300 is depicted. Diodes 313, 315, 317, and 319 are formed within wafer 300 and are coupled to metal contacts 302, 304, 306, and 308, respectively (e.g., plated or deposited by metal evaporation deposition). The diodes are represented by a diode symbol to better illustrate the anode terminal orientation and cathode terminal orientation. The scope of the present disclosure is not limited to any particular type of diode. Gap 305 separates metal contacts 302 and 304. Gap 309 separates metal contacts 306 and 308. Gap 311 separates metal contacts 304 and 306. In an example, the threshold voltage of each of diodes 313, 315, 317, and 319 (i.e., the voltage at which the diode closes the circuit and allows current to pass) is a fraction of the total threshold voltage of ESD 106. For example, Figure 3A1315 is later singulated vertically (e.g., sawed) at gap 311 to form two separate ESDs 106, as described below. Thus, diodes 313 and 315 will be part of one ESD 106, and diodes 317 and 319 will be part of different ESDs 106. The threshold voltages of diodes 313 and 315 should be combined to equal the desired threshold voltage of the ESD 106 in which the diodes are included. Similarly, the threshold voltages of diodes 317 and 319 should be combined to equal the desired threshold voltage of the ESD 106 in which the diodes are included. For example, for a total combined threshold voltage of 3.2V for the respective ESDs 106, diodes 313 and 315 may each have a threshold voltage of 1.6V. Diode 313 must be oriented (i.e., formed in wafer 300) such that the cathode of diode 313 is closer to metal contact 302 and the anode of diode 313 is farther from metal contact 302. Diode 315 must be oriented such that the anode of diode 315 is closer to metal contact 304 and the cathode of diode 315 is farther from metal contact 304. Diode 317 must be oriented (i.e., formed in wafer 300) such that the cathode of diode 317 is closer to metal contact 306 and the anode of diode 317 is farther from metal contact 306. Diode 319 must be oriented such that the anode of diode 319 is closer to metal contact 308 and the cathode of diode 319 is farther from metal contact 308. Figure 3A2 Based on some examples Figure 3A1 A top view of the structure of Figure 3A2 Wafer saw streets 350 are depicted. Figure 3A3 Based on some examples Figure 3A1 perspective view of the structure.

[0016] The method 200 includes forming a third metal contact and a fourth metal contact on a second surface of the wafer (opposite to the first surface of the wafer) (204). A second gap (204) is present between the third metal contact and the fourth metal contact and is vertically aligned with the first gap. Figure 3B1A cross-sectional view of a metal layer 310 coupled to metal contacts 302 and 304, and a metal layer 312 coupled to metal contacts 306 and 308 is shown. The metal layers 310 and 312 may be deposited by plating or by metal evaporation deposition, as appropriate. Each of the metal layers 310, 312 has a rectangular prism shape. Each of the metal layers 310, 312 has a flat top surface, bottom surface, and lateral surface. Each of the metal layers 310 and 312 has a thickness in the range from 1 micron to 100 microns, below which thickness is disadvantageous because it introduces high resistance and low current carrying capacity, and above which thickness is disadvantageous due to manufacturing challenges and cost inefficiency. The metal layer 310 provides an electrical path between the metal contacts 302 and 304, and the metal layer 312 provides an electrical path between the metal contacts 306 and 308. A gap 321 separates the metal layers 310 and 312. Figure 3B2 Based on various examples Figure 3B1 Top view of the structure. Figure 3B3 Based on various examples Figure 3B1 perspective view of the structure.

[0017] The method 200 includes performing selective wafer backside metallization ( 205 ). Fig.3C1 3 is a cross-sectional view showing a metal layer 314 on the back side of wafer 300. Metal layer 314 is segmented by gap 316, which is vertically aligned with gap 305, and by gap 318, which is vertically aligned with gap 309. Selective wafer backside metallization to apply metal layer 314 to the back side of wafer 300 may be performed using any suitable technique, such as chemical vapor deposition (CVD) using an appropriately patterned mask to form gaps 316 and 318. Key properties of metal layer 314 and gaps 316, 318 are described below. Figure 3C2 Based on various examples Fig.3C1 Bottom view of the structure. Figure 3C3 Based on various examples Fig.3C1 perspective view of the structure.

[0018] The method 200 includes covering the metal layer and the wafer with a molding compound ( 206 ). Figure 3D1 3 is a cross-sectional view depicting the application of a molding compound layer 320 to a wafer 300 and metal layers 310, 312 as shown. Any suitable application technique, such as wafer compression molding, may be suitable for applying the molding compound layer 320. The thickness of the molding compound layer 320 from the top of the molding compound layer 320 to the top surface of the metal layers 310, 312 ranges from 50 microns to 800 microns, with thicknesses below this range being disadvantageous due to an unacceptably increased risk of exposing the die surface, and thicknesses above this range being disadvantageous because they exceed the package thickness specification. Figure 3D2 Based on various examples Figure 3D1 Top view of the structure. Figure 3D3 Based on various examples Figure 3D1 perspective view of the structure.

[0019] The method 200 includes forming a trench in the wafer through the first gap and the second gap (208). Fig.3E1 305, and further depicts a cross-sectional view of a trench 322 formed in wafer 300 through gaps 316 and 305, and further depicts a trench 324 formed in wafer 300 through gaps 318 and 309. Any suitable technique, such as plasma etching, may be applied to form trenches 322, 324. Trench 322 extends from metal layer 310 through gap 305, through wafer 300, and through gap 316. Trench 324 extends from metal layer 312, through gap 309, through wafer 300, and through gap 318. The width of each of trenches 322, 324 is similar to the width of the corresponding gap 316, 318. Figure 3E2 Based on various examples Fig.3E1 Bottom view of the structure. Figure 3E3 Based on various examples Fig.3E1 perspective view of the structure.

[0020] The method 200 includes filling the trenches with an isolation material (210). Any suitable isolation material, such as parylene or resin, may be suitable for use as the isolation material, and any suitable application technique, such as CVD or printing techniques, may be suitable for filling the trenches with the isolation material. Figure 3F1 3 is a cross-sectional view depicting trench 322 being filled with isolation material 326, and trench 324 being filled with isolation material 328. Isolation material 326 contacts metal layer 310, metal contacts 302, 304, wafer 300, and metal layer 314. Isolation material 328 contacts metal layer 312, metal contacts 306, 308, wafer 300, and metal layer 314. Figure 3F2 Based on various examples Figure 3F1 Bottom view of the structure. Figure 3F3 Based on various examples Figure 3F1 perspective view of the structure.

[0021] The method 200 includes singulating the wafer to produce packages ( 212 ). Figure 3G1 It is a depiction Figure 3F1 3. A cross-sectional view of a structure of FIG. 106 is singulated between metal layers 310 and 312. Any suitable singulation technique may be applicable, including mechanical sawing and laser sawing. The singulation creates a gap 330, thereby creating two separate ESDs (eg, packages) 106A, 106B. Figure 3G2 Based on various examples Figure 3G1 Bottom view of the structure. Figure 3G3 Based on various examples Figure 3G1 A perspective view of the structure. Figure 3G1-3G3 , isolation material 326 includes a surface that is exposed to the exterior of package 106A (this is also the case with isolation material 328 and package 106B). Isolation material 326 contacts the side surfaces of dies 351, 352 and the side surfaces of metal contacts 354, 356, and a portion of metal layer 310. Similarly, isolation material 328 contacts the side surfaces of dies 358, 360 and the side surfaces of metal contacts 362, 364, and a portion of metal layer 312.

[0022] The ESD 106A includes semiconductor dies 351, 352. The ESD 106A also includes metal contacts 354, 356 coupled to the dies 351, 352, respectively. Figure 1 and 3G1 , metal contact 354 may be coupled to node 108, and metal contact 356 may be coupled to ground 110. When node 108 is approaching an overvoltage condition, the voltage on node 108 will be high enough to turn on both diodes 313, 315, thereby establishing an electrical path between contacts 354, 356, and thus establishing an electrical path between node 108 and ground 110. Thus, node 108 is pulled down to approximately 0V (e.g., ground), and IC 104 (and possibly other devices) are protected from the consequences of the overvoltage condition. In some examples, metal contacts 354, 356 are rectangular prisms and have flat top, bottom, and lateral surfaces.

[0023] Similarly, ESD 106B includes semiconductor dies 358, 360 and includes metal contacts 362, 364 coupled to dies 358, 360, respectively. Figure 1 and 3G1 , metal contact 362 may be coupled to node 108, and metal contact 364 may be coupled to ground 110. When node 108 is approaching an overvoltage condition, the voltage on node 108 will be high enough to turn on both diodes 317, 319, thereby establishing an electrical path between contacts 362, 364, and thus establishing an electrical path between node 108 and ground 110. Thus, node 108 is pulled down to approximately 0V (e.g., ground), and IC 104 (and possibly other devices) are protected from the consequences of the overvoltage condition. In some examples, metal contacts 362, 364 are rectangular prisms and have flat top, bottom, and lateral surfaces.

[0024] The metal contacts 354, 356, 362, and 364 have specific physical properties that are key to reducing parasitic capacitance in the respective ESDs 106A, 106B. Electrical simulation data indicates that the following capacitances (in femtofarads (fF)) can be achieved at the metal contacts 354, 356 (and similarly, between the metal contacts 362, 364), depending on the thickness of the metal contacts and the spacing between the metal contacts:

[0025]

[0026] Some ESDs as described above will have a contact-to-contact reference capacitance of approximately 40.3 fF. In contrast, as indicated by the simulation data in the table above, the thickness of the metal contacts 354, 356 (and similarly, the metal contacts 362, 364) can be reduced, and the spacing between the metal contacts 354, 356 (and between the metal contacts 362, 364) can be increased to reduce the capacitance between the contacts. The lower capacitance between the metal contacts 354, 356 (and between the metal contacts 362, 364) is advantageous because the ESD 106 is attached to the high-speed signal lines used in the interface connector 102 (e.g., HDMI and USB3.0 / USB-C). The lower the parasitic capacitance of the ESD 106, the less noise is added to the data line, which helps the system keep the signal clear between the ports when transmitting data at high speeds. Higher and higher signal transmission speeds require lower and lower parasitic capacitance to keep the signal clear and readable by the chip (e.g., IC 104) that reads the data being transmitted. For a capacitance of 11.9 fF, the balance of the thickness of the metal contacts 354, 356 (and contacts 362, 364) and the spacing between the metal contacts 354, 356 (and between contacts 362, 364) is optimized at 10 microns and 30 microns, respectively, which achieves a significant reduction in capacitance by maintaining the inter-contact spacing below a spacing of 50 microns while achieving a significant reduction in the size of the ESD. More specifically, relative to some techniques used to reduce the space occupied by the ESD 106A (and ESD 106B), due to the manufacturing method 200, the spacing between the metal contacts 354, 356 (and similarly, between the metal contacts 362, 364) can be significantly reduced. In contrast, some techniques use a lead frame with a minimum spacing of 50 microns, while in some instances, the spacing between the metal contacts 354, 356 (and between the metal contacts 362, 364) ranges from 5 microns to 10 microns. This reduced pitch is possible due to the manufacturing method 200, for example, by forming trenches and using plating and / or metal evaporation deposition techniques, without which such small pitches may not be possible to achieve in manufacturing some ESDs.

[0027] In this description, the term "coupled" may encompass connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C without the intermediate component C changing the functional relationship between device A and device B, so that device B is controlled by device A via the control signal generated by device A.

[0028] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0029] The use of the phrase "ground" in the foregoing description includes chassis ground, ground wire ground, floating ground, virtual ground, digital ground, universal ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification. In this specification, unless otherwise specified, "about", "approximately" or "substantially" before a parameter means within + / -10% of the parameter. Modifications may be made in the described examples, and other examples may be made within the scope of the claims.

Claims

1. A package comprising: a first die and a second die comprising a first diode and a second diode, respectively; a first metal contact and a second metal contact coupled to bottom surfaces of the first die and the second die, respectively, the first metal contact and the second metal contact being exposed to a bottom surface of the package; An isolation layer is disposed between the first die and the second die and between the first metal contact and the between the second metal contacts; a metal layer coupled to top surfaces of the first die and the second die; and A molding compound covers the first die, the second die and the metal layer. 2 . The package of claim 1 , further comprising third and fourth metal contacts exposed to the top surfaces of the first and second dies, wherein the third and fourth metal contacts are positioned below the metal layer. The package of claim 1 , wherein the isolation layer comprises parylene or resin. 4 . The package of claim 1 , wherein a distance between the first metal contact and the second metal contact is in a range between 5 microns and 10 microns.

5. The package of claim 1, wherein: The isolation layer includes a surface exposed from the package; and The isolation layer contacts side surfaces of the first and second dies and side surfaces of the first and second metal contacts, and a portion of the metal layer. The package of claim 1 , wherein the metal layer is a rectangular prism.

7. The package of claim 1, wherein the first metal contact and the second metal contact are rectangular prisms.

8. A package comprising: a first die and a second die comprising a first diode and a second diode, respectively; a first metal contact and a second metal contact coupled to bottom surfaces of the first die and the second die, respectively, the first metal contact and the second metal contact being exposed to a bottom surface of the package; a third metal contact and a fourth metal contact exposed to top surfaces of the first die and the second die, respectively; an isolation material between the first die and the second die, between the first metal contact and the second metal contact, and between the third metal contact and the fourth metal contact; a planar metal layer coupled to top surfaces of the first die and the second die; and a molding compound covering the first die and the second die and the planar metal layer, The first metal contact is spaced 5 microns to 10 microns apart from the second metal contact.

9. The package of claim 8, wherein the first metal contact and the second metal contact are rectangular prisms.

10. The package of claim 8, wherein the planar metal layer is a rectangular prism.

11. The package of claim 8, wherein the planar metal layer has a thickness in a range from 1 micron to 100 microns.

12. The package of claim 8, wherein the isolation material comprises parylene or resin.

13. A method for manufacturing a package, comprising: forming a metal layer on a first surface of a semiconductor wafer, the wafer comprising a first diode and a second diode and a first metal contact and a second metal contact coupled to the first diode and the second diode, the first metal contact and the second metal contact being separated by a first gap, the metal layer being formed on the first metal contact and the second metal contact; forming a third metal contact and a fourth metal contact on a second surface of the wafer, the second surface being opposite to the first surface of the wafer, a second gap between the third metal contact and the fourth metal contact being vertically aligned with the first gap; Covering the metal layer and the wafer with a molding compound; forming a groove in the wafer passing through the first gap and the second gap; filling the trench with an isolation material; and The wafer is singulated to produce packages. The method of claim 13 , wherein forming the metal layer comprises one of a metal evaporation deposition process or a metal plating process.

15. The method of claim 13, wherein covering the metal layer and the wafer with a molding compound comprises using a wafer compression molding process.

16. The method of claim 13, wherein the isolation material is parylene or resin.

17. The method of claim 13, wherein forming the trench comprises plasma etching the wafer.

18. The method of claim 13, wherein filling the trench comprises using a chemical vapor deposition process or a printing process.

19. The method of claim 13, wherein the metal layer has a thickness in a range from 1 micron to 100 microns.

20. The method of claim 13, wherein the metal layer and the third and fourth metal contacts are rectangular prisms.

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