Semiconductor package and manufacturing method thereof

Abstract

The invention relates to a semiconductor package. An example semiconductor package includes a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first bond pad disposed on a first surface of the first semiconductor chip facing the second semiconductor chip, and a second bond pad disposed on a second surface of the second semiconductor chip facing the first surface. The second bonding pad is in contact with the first bonding pad and includes a third surface in contact with the first bonding pad and a fourth surface opposite the third surface. The second semiconductor chip includes a first wiring pad in contact with the fourth surface and a second wiring pad spaced apart from the first wiring pad and the second bonding pad. A thickness of the second wiring pad is less than a thickness of the first wiring pad.

Description

Technical Field

[0001] The present disclosure relates to semiconductor packages and semiconductor package manufacturing methods, including semiconductor packages with improved product reliability. Background Art

[0002] As the electronics industry develops, demands for higher functions, higher speeds, and smaller sizes of electronic components continue to increase. In response to this trend, a method for stacking and mounting multiple semiconductor chips on a single package wiring structure or stacking packages on each other may be used.

[0003] In recent years, the interconnect length between stacked chips has been reduced by vertically stacking multiple dies using direct bonding. Summary of the invention

[0004] In general, according to some aspects, a semiconductor package includes: a first semiconductor chip; a second semiconductor chip on the first semiconductor chip; a first bonding pad, arranged on a first surface of the first semiconductor chip facing the second semiconductor chip; and a second bonding pad, arranged on a second surface of the second semiconductor chip facing the first surface and in contact with the first bonding pad, wherein the second bonding pad includes a third surface in contact with the first bonding pad and a fourth surface opposite to the third surface, wherein the second semiconductor chip includes a first wiring pad in contact with the fourth surface of the second bonding pad and a second wiring pad spaced apart from the first wiring pad and not in contact with the second bonding pad, wherein a thickness of the second wiring pad is less than a thickness of the first wiring pad.

[0005] In general, according to some aspects, a semiconductor package includes: a first semiconductor chip; a second semiconductor chip on the first semiconductor chip; a first bonding pad, arranged on a first surface of the first semiconductor chip facing the second semiconductor chip; and a second bonding pad, arranged on a second surface of the second semiconductor chip facing the first surface and in contact with the first bonding pad, wherein the second semiconductor chip includes a first wiring pad in contact with the second bonding pad and a second wiring pad spaced apart from the first wiring pad and not in contact with the second bonding pad, wherein the first wiring pad includes a third surface in contact with the second bonding pad and a fourth surface opposite to the third surface, wherein the second wiring pad includes a fifth surface facing the first semiconductor chip and a sixth surface opposite to the fifth surface, the fourth surface and the sixth surface are arranged on the same plane, and based on the first surface of the first semiconductor chip, the third surface is located below the fifth surface.

[0006] In general, according to some aspects, a semiconductor package includes: a packaging substrate; a first semiconductor chip on the packaging substrate; a second semiconductor chip on the first semiconductor chip; a first bonding pad, arranged on a first surface of the first semiconductor chip facing the second semiconductor chip; a second bonding pad, arranged on a second surface of the second semiconductor chip facing the first surface and in contact with the first bonding pad; and a molding film, arranged on the packaging substrate and covering the first semiconductor chip and the second semiconductor chip, wherein the second bonding pad includes a third surface in contact with the first bonding pad and a fourth surface opposite to the third surface, the first semiconductor chip includes a first through-electrode in contact with the first bonding pad and a first wiring structure connected to the first through-electrode, wherein the second semiconductor chip includes a first wiring pad in contact with the fourth surface of the second bonding pad, a second wiring structure including a second wiring pad spaced apart from the first wiring pad and not in contact with the second bonding pad, and a second through-electrode connected to the second wiring structure, wherein the first bonding pad and the second bonding pad include copper, the first wiring pad and the second wiring pad include aluminum, and the thickness of the second wiring pad is 50% or less of the thickness of the first wiring pad.

[0007] In general, according to some aspects, a method for manufacturing a semiconductor package includes: forming a first bonding pad on a first surface of a first semiconductor chip; forming a first wiring pad having a first thickness and a second wiring pad having a second thickness smaller than the first thickness on a second surface of a second semiconductor chip; forming an insulating film on the second surface of the second semiconductor chip, the insulating film surrounding the side surface of the first wiring pad and covering the second wiring pad; forming a second bonding pad on the first wiring pad; and bonding the first bonding pad to the second bonding pad.

[0008] However, the aspects of the present disclosure are not limited to the contents set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the detailed explanation of the present disclosure given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects and features of the present disclosure will become more apparent by describing in detail illustrative embodiments of the present disclosure with reference to the attached drawings.

[0010] Figure 1 is a diagram showing an example of a semiconductor package.

[0011] Figure 2 yes Figure 1 An example enlarged view of portion "P" of FIG.

[0012] Figures 3 to 7 is a diagram showing another example of a semiconductor package.

[0013] Figure 8 is a diagram showing another example of a semiconductor package.

[0014] Fig. 9 It is shown Figure 8 Example enlarged view of portion "Q".

[0015] Fig.10 is a diagram showing another example of a semiconductor package.

[0016] Fig.11 is a diagram showing another example of a semiconductor package.

[0017] Fig.12 It is shown Fig.11 An example enlarged view of the portion "R" of FIG.

[0018] Fig.13 is a diagram showing another example of a semiconductor package.

[0019] Figures 14 to 27 are diagrams illustrating intermediate steps of an example of a method of manufacturing a semiconductor package.

[0020] Figures 28 to 33 is a diagram showing an intermediate step of another example of a method for manufacturing a semiconductor package. DETAILED DESCRIPTION

[0021] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0022] Figure 1 is a diagram showing an example of a semiconductor package. Figure 2 yes Figure 1 An example enlarged view of portion "P" of FIG.

[0023] refer to Figure 1 and Figure 2 The semiconductor package includes first to fourth semiconductor chips 100 to 400, a package substrate 500, rear bonding pads 150, 250, 350 and 450, front bonding pads 160, 260 and 360, bonding insulation films 610, 620 and 630, connecting wiring pads 142, 242, 342 and 442, peripheral wiring pads 144, 244, 344 and 444, and a molding film 700.

[0024] The description of the rear bonding pads 150, 250, 350, and 450 may be substantially the same as the description of the first and second rear bonding pads 150 and 250. Therefore, the following description will focus on the first and second rear bonding pads 150 and 250.

[0025] The description of the front bonding pads 160, 260, and 360 and the package bonding pad 560 may be substantially the same as the description of the first front bonding pad 160. Therefore, the first front bonding pad 160 will be mainly described below.

[0026] The description of the connection wiring pads 142, 242, 342, and 442 may be substantially the same as the description of the first connection wiring pad 142 and the second connection wiring pad 242. Therefore, the following description will focus on the first connection wiring pad 142 and the second connection wiring pad 242.

[0027] The description of the peripheral wiring pads 144, 244, 344, and 444 may be substantially the same as the description of the first and second peripheral wiring pads 144 and 244. Therefore, the following explanation will focus on the first and second peripheral wiring pads 144 and 244.

[0028] The first to fourth semiconductor chips 100 to 400 may be logic chips or memory chips. The first to fourth semiconductor chips 100 to 400 may all be memory chips of the same type. For example, the first to fourth semiconductor chips 100 to 400 may be volatile memory chips, such as DRAM (dynamic random access memory) or SRAM (static random access memory). As another example, the first to fourth semiconductor chips 100 to 400 may be non-volatile memory chips, such as PRAM (phase change RAM), MRAM (magnetoresistive RAM), FeRAM (ferroelectric RAM) or RRAM (resistance RAM). As another example, the first to fourth semiconductor chips 100 to 400 may be HBM (high bandwidth memory).

[0029] In addition, some of the first to fourth semiconductor chips 100 to 400 may be memory chips, and others may be logic chips. For example, some of the first to fourth semiconductor chips 100 to 400 may be microprocessors, analog elements, digital signal processors, or application processors.

[0030] The first to fourth semiconductor chips 100 to 400 may be stacked in a vertical direction on a package substrate 500. The first to fourth semiconductor chips 100 to 400 may be electrically connected to each other through rear bonding pads 150, 250, 350 and 450 and front bonding pads 160, 260 and 360, or may be electrically connected to the package substrate 500.

[0031] Widths of the first to fourth semiconductor chips 100 to 400 may be equal to one another. Side surfaces of the first to fourth semiconductor chips 100 to 400 may be disposed on the same plane.

[0032] The first semiconductor chip 100 may include a first semiconductor substrate 110 , a first semiconductor element layer 120 , a first through electrode 130 , a first wiring structure 140 , a first connection wiring pad 142 , a first peripheral wiring pad 144 , a first rear bonding pad 150 , and a first front bonding pad 160 .

[0033] The first semiconductor substrate 110 may be, for example, bulk silicon or silicon-on-insulator (SOI). As another example, the first semiconductor substrate 110 may be a silicon substrate. As yet another example, the first semiconductor substrate 110 may include, but is not limited to, silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0034] The first semiconductor substrate 110 may include a conductive region, for example, a doped well or a doped structure. The first semiconductor substrate 110 may have various element isolation structures, for example, a shallow trench isolation (STI) structure.

[0035] The first semiconductor element layer 120 may be disposed on the lower surface of the first semiconductor substrate 110. The first semiconductor element layer 120 may include a plurality of individual devices of various types and an interlayer insulating film. The individual devices may include various microelectronic devices, for example, MOSFETs (metal oxide semiconductor field effect transistors) such as CMOS transistors (complementary metal insulator semiconductor transistors), system LSIs (large scale integration), flash memories, DRAMs, SRAMs, EEPROMs, PRAMs, MRAMs, RRAMs, image sensors such as CISs (CMOS image sensors), MEMSs (micro-electromechanical systems), active devices, passive devices, and the like.

[0036] The individual devices of the first semiconductor element layer 120 may be electrically connected to the conductive region formed inside the first semiconductor substrate 110. The individual devices of the first semiconductor element layer 120 may be electrically separated from other adjacent individual devices by an insulating film. The first semiconductor element layer 120 may include a first wiring structure 140, which electrically connects at least two of the plurality of individual devices or the plurality of individual devices to the conductive region of the first semiconductor substrate 110.

[0037] The first semiconductor element layer 120 may include a first connection wiring pad 142 and a first peripheral wiring pad 144. The first connection wiring pad 142 and the first peripheral wiring pad 144 may be provided inside the first semiconductor element layer 120.

[0038] The first connection wiring pad 142 and the first peripheral wiring pad 144 may be spaced apart from each other. For example, the first connection wiring pad 142 and the first peripheral wiring pad 144 may be spaced apart horizontally at the same height. For example, the first connection wiring pad 142 and the first peripheral wiring pad 144 may be spaced apart from each other in the first direction X.

[0039] The first connection wiring pad 142 may be connected to the first wiring structure 140 and the first rear bonding pad 150. The first connection wiring pad 142 may be in contact with the first wiring structure 140 and the first rear bonding pad 150. A lower surface of the first connection wiring pad 142 may be in contact with an upper surface of the first rear bonding pad 150. The first connection wiring pad 142 may electrically connect the first wiring structure 140 to the first rear bonding pad 150.

[0040] The first peripheral wiring pad 144 may be connected to the first wiring structure 140. The first peripheral wiring pad 144 may be in contact with the first wiring structure 140. The first peripheral wiring pad 144 may not be connected to the first rear bonding pad 150. The first peripheral wiring pad 144 may not be in contact with the first rear bonding pad 150. The lower surface of the first peripheral wiring pad 144 may be spaced apart from the upper surface of the first rear bonding pad 150. The lower surface of the first peripheral wiring pad 144 may be covered by an insulating film inside the first semiconductor element layer 120. The lower surface of the first peripheral wiring pad 144 may be surrounded by an insulating film inside the first semiconductor element layer 120.

[0041] The first connection wiring pad 142 and the first peripheral wiring pad 144 may include at least one of aluminum (Al) and copper (Cu). For example, the first connection wiring pad 142 and the first peripheral wiring pad 144 may each include aluminum (Al).

[0042] Although the width of the first peripheral wiring pad 144 is shown to be smaller than the width of the first connection wiring pad 142 in the first direction X, embodiments are not limited thereto. For example, the width of the first peripheral wiring pad 144 may be greater than the width of the first connection wiring pad 142 .

[0043] A first passivation layer 121 for protecting the structures inside the first semiconductor element layer 120 different from the first wiring structure 140, the first connection wiring pad 142, and the first peripheral wiring pad 144 from external impact and moisture may be formed on the first semiconductor element layer 120. The first passivation layer 121 may expose a portion of the lower surface of the first connection wiring pad 142.

[0044] The first through electrode 130 may penetrate the first semiconductor substrate 110. The first through electrode 130 may extend from an upper surface to a lower surface of the first semiconductor substrate 110. The first through electrode 130 may be connected to a first wiring structure 140 provided in the first semiconductor element layer 120.

[0045] The first through electrode 130 may include a barrier film formed on the columnar surface and a buried conductive layer for filling the inside of the barrier film. The barrier film may include but is not limited to at least one of Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni and NiB. The buried conductive layer may include but is not limited to at least one of Cu alloys (e.g., Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe and CuW), W, W alloy, Ni, Ru and Co.

[0046] In some embodiments, an insulating film may be interposed between the first semiconductor substrate 110 and the first through electrode 130. The insulating film may include, but is not limited to, an oxide film, a nitride film, a carbide film, a polymer, or a combination thereof.

[0047] The first wiring structure 140 may include a metal wiring layer and a via plug. For example, the first wiring structure 140 may have a multi-layer structure in which two or more metal wiring layers or two or more via plugs are alternately stacked.

[0048] The first wiring structure 140 may be connected to the first connection wiring pad 142 and the first peripheral wiring pad 144. The first wiring structure 140 may be in contact with the first connection wiring pad 142 and the first peripheral wiring pad 144.

[0049] The first rear bonding pad 150 may be disposed on the first semiconductor element layer 120. The first rear bonding pad 150 may be electrically connected to the first wiring structure 140 inside the first semiconductor element layer 120. The first rear bonding pad 150 may be electrically connected to the first through electrode 130 through the first wiring structure 140.

[0050] The first rear bonding pad 150 may be disposed on the first connection wiring pad 142. The first rear bonding pad 150 may be connected to the first connection wiring pad 142. The first rear bonding pad 150 may be in contact with the first connection wiring pad 142. For example, an upper surface of the first rear bonding pad 150 may be in contact with a lower surface of the first connection wiring pad 142.

[0051] The first rear bonding pad 150 may not be connected to the first peripheral wiring pad 144. The first rear bonding pad 150 may not be in contact with the first peripheral wiring pad 144. The first rear bonding pad 150 may be spaced apart from the first peripheral wiring pad 144. The upper surface of the first rear bonding pad 150 may be spaced apart from the lower surface of the first peripheral wiring pad 144.

[0052] The first rear bonding pad 150 may be electrically connected to the package bonding pad 560. The first rear bonding pad 150 may contact the package bonding pad 560. The first rear bonding pad 150 may be bonded to the package bonding pad 560. The first rear bonding pad 150 and the package bonding pad 560 may be directly bonded. The first rear bonding pad 150 and the package bonding pad 560 may be coupled by a high temperature annealing process.

[0053] The first semiconductor chip 100 may be electrically connected to the package substrate 500 by bonding the first rear bonding pad 150 and the package bonding pad 560. For example, by coupling the first rear bonding pad 150 and the package bonding pad 560, the first connection wiring pad 142 connected to the first rear bonding pad 150 and the first wiring structure 140 may be electrically connected to the package bonding pad 560 of the package substrate 500.

[0054] The first rear bonding pads 150 may be provided from the outside with at least one of a control signal, a power signal, or a ground signal for operating the first to fourth semiconductor chips 100 to 400. The first rear bonding pads 150 may be provided from the outside with a data signal to be stored in the first to fourth semiconductor chips 100 to 400. The first rear bonding pads 150 may provide data stored in the first to fourth semiconductor chips 100 to 400 to the outside.

[0055] The first rear bonding pad 150 may include at least one selected from aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au). In some embodiments, the first rear bonding pad 150 may include copper (Cu).

[0056] The first front bonding pad 160 electrically connected to the first through electrode 130 may be formed on the upper surface of the first semiconductor substrate 110. The first front bonding pad 160 may be electrically connected to the first wiring structure 140 through the first through electrode 130. The first front bonding pad 160 may be made of the same material as the first rear bonding pad 150. Although not shown, an upper passivation layer may be formed on the upper surface of the first semiconductor substrate 110 to surround a portion of the side surface of the first through electrode 130.

[0057] The first front bonding pad 160 may be connected to the second rear bonding pad 250. The first front bonding pad 160 may be in contact with the second rear bonding pad 250. For example, the second surface 160S2 of the first front bonding pad may be in contact with the first surface 250S1 of the second rear bonding pad.

[0058] The first front bonding pad 160 may be bonded to the second rear bonding pad 250. The first front bonding pad 160 may be directly bonded to the second rear bonding pad 250. The first front bonding pad 160 and the second rear bonding pad 250 may be coupled through a high temperature annealing process.

[0059] The first front bonding pad 160 may be disposed on the second surface 100S2 of the first semiconductor chip. The second surface 100S2 of the first semiconductor chip may be opposite to the second semiconductor chip 200. For example, the second surface 100S2 of the first semiconductor chip may face the first surface 200S1 of the second semiconductor chip. The first front bonding pad 160 may be disposed inside the first bonding insulating film 610.

[0060] The second semiconductor chip 200 may be electrically connected to the first semiconductor chip 100 by bonding the first front bonding pads 160 and the second rear bonding pads 250. For example, the first through-electrodes 130 of the first semiconductor chip 100 and the second wiring structures 240 of the second semiconductor chip 200 may be electrically connected through the bonded first front bonding pads 160 and the second rear bonding pads 250.

[0061] The first front bonding pad 160 and the second rear bonding pad 250 may be surrounded by the first bonding insulation film 610 . Side surfaces of the first front bonding pad 160 and the second rear bonding pad 250 may be covered by the first bonding insulation film 610 .

[0062] The first front bonding pad 160 and the second rear bonding pad 250 may be bonded with a bonding thickness THB. The bonding thickness THB may refer to a thickness between a first surface 160S1 of the first front bonding pad and a second surface 250S2 of the second rear bonding pad. The first surface 160S1 of the first front bonding pad may be a surface on which the first front bonding pad 160 contacts the second surface 100S2 of the first semiconductor chip. The second surface 250S2 of the second rear bonding pad may be a surface on which the second rear bonding pad 250 contacts the first surface 200S1 of the second semiconductor chip.

[0063] The bonding thickness THB may be smaller than the thickness TH242 of the second connection wiring pad. However, the embodiment is not limited thereto. For example, the bonding thickness THB may be greater than the thickness TH242 of the second connection wiring pad.

[0064] The width of the first front bonding pad 160 may be the same as the width of the second rear bonding pad 250. For example, the side surface of the first front bonding pad 160 and the side surface of the second rear bonding pad 250 may be disposed on the same plane. The width of the first front bonding pad 160 may be greater than the width of the first through electrode 130.

[0065] The thickness of the first front bonding pad 160 may be the same as that of the second rear bonding pad 250. The thickness between the first surface 160S1 and the second surface 160S2 of the first front bonding pad may be the same as the thickness between the first surface 250S1 and the second surface 250S2 of the second rear bonding pad.

[0066] The second semiconductor chip 200 may be disposed on the first semiconductor chip 100 . The second semiconductor chip 200 may be electrically connected to the first semiconductor chip 100 through the first front bonding pads 160 and the second rear bonding pads 250 disposed between the first and second semiconductor chips 100 and 200 .

[0067] The second semiconductor chip 200 may include a second semiconductor substrate 210 , a second semiconductor element layer 220 , a second through electrode 230 , a second wiring structure 240 , a second connection wiring pad 242 , a second peripheral wiring pad 244 , a second rear bonding pad 250 , and a second front bonding pad 260 .

[0068] The second semiconductor element layer 220 may include a second connection wiring pad 242 and a second peripheral wiring pad 244. The second connection wiring pad 242 and the second peripheral wiring pad 244 may be provided inside the second semiconductor element layer 220.

[0069] The second connection wiring pad 242 and the second peripheral wiring pad 244 may be spaced apart from each other. For example, the second connection wiring pad 242 and the second peripheral wiring pad 244 may be spaced apart from each other in the horizontal direction at the same height. For example, the second connection wiring pad 242 and the second peripheral wiring pad 244 may be spaced apart from each other in the first direction X.

[0070] The second connection wiring pad 242 and the second peripheral wiring pad 244 may have different thicknesses from each other. The thickness TH242 of the second connection wiring pad may be greater than the thickness TH244 of the second peripheral wiring pad. The thickness TH242 of the second connection wiring pad may refer to the thickness between the first surface 242S1 and the second surface 242S2 of the second connection wiring pad. The thickness TH244 of the second peripheral wiring pad may refer to the thickness between the first surface 244S1 and the second surface 244S2 of the second peripheral wiring pad.

[0071] The thickness TH244 of the second peripheral wiring pad may be, for example, 50% or less of the thickness TH242 of the second connection wiring pad. The thickness TH242 of the second connection wiring pad may be greater than a bonding thickness THB at which the second rear bonding pad 250 and the first front bonding pad 160 are bonded.

[0072] The second surface 242S2 of the second connection wiring pad and the second surface 244S2 of the second peripheral wiring pad may be disposed on the same plane.

[0073] The second surface 242S2 of the second connection wiring pad may be a surface opposite to the first surface 242S1 of the second connection wiring pad. The first surface 242S1 of the second connection wiring pad may be a surface in contact with the second rear bonding pad 250. The first surface 242S1 of the second connection wiring pad may face the first semiconductor chip 100. The second wiring structure 240 may be in contact with the second surface 242S2 of the second connection wiring pad. The second wiring structure 240 may be connected to the second surface 242S2 of the second connection wiring pad.

[0074] The second surface 244S2 of the second peripheral wiring pad may be a surface opposite to the first surface 244S1 of the second peripheral wiring pad. The first surface 244S1 of the second peripheral wiring pad may face the first semiconductor chip 100. The first surface 244S1 of the second peripheral wiring pad may be covered by the second insulating film 225 inside the second semiconductor element layer 220. The second wiring structure 240 may contact the second surface 244S2 of the second peripheral wiring pad. The second wiring structure 240 may be connected to the second surface 244S2 of the second peripheral wiring pad.

[0075] The first surface 242S1 of the second connection wiring pad and the first surface 244S1 of the second peripheral wiring pad may not be arranged on the same plane. For example, based on the second surface 100S2 of the first semiconductor chip, the first surface 242S1 of the second connection wiring pad may be arranged below the first surface 244S1 of the second peripheral wiring pad. The first surface 242S1 of the second connection wiring pad and the first surface 244S1 of the second peripheral wiring pad may have a height difference.

[0076] The first surface 242S1 of the second connection wiring pad may not be covered by the second insulating film 225 inside the second semiconductor element layer 220. The first surface 242S1 of the second connection wiring pad may not overlap with the second insulating film 225 inside the second semiconductor element layer 220. For example, the second insulating film 225 may not be provided between the second connection wiring pad 242 and the second rear bonding pad 250. The first surface 242S1 of the second connection wiring pad and the second surface 250S2 of the second rear bonding pad may be in direct contact with each other. Only the side surface of the second connection wiring pad 242 may be surrounded by the second insulating film 225 inside the second semiconductor element layer 220.

[0077] The first surface 244S1 of the second peripheral wiring pad may be covered by the second insulating film 225 inside the second semiconductor element layer 220. The first surface 244S1 of the second peripheral wiring pad may overlap with the second insulating film 225 inside the second semiconductor element layer 220. The second insulating film 225 may be provided between the second peripheral wiring pad 244 and the first bonding insulating film 610. The second peripheral wiring pad 244 may be surrounded by the second insulating film 225 inside the second semiconductor element layer 220 not only on the side surface but also on the first surface 244S1.

[0078] The second rear bonding pad 250 may be disposed on the second semiconductor element layer 220. The second rear bonding pad 250 may be electrically connected to the second wiring structure 240 inside the second semiconductor element layer 220. The second rear bonding pad 250 may be electrically connected to the second through electrode 230 through the second wiring structure 240.

[0079] The second rear bonding pad 250 may be disposed on the first surface 200S1 of the second semiconductor chip. For example, the first surface 200S1 of the second semiconductor chip may face the second surface 100S2 of the first semiconductor chip. The second rear bonding pad 250 may be disposed inside the first bonding insulation film 610.

[0080] The second rear bonding pad 250 may be disposed on the second connection wiring pad 242. The second rear bonding pad 250 may be connected to the second connection wiring pad 242. The second rear bonding pad 250 may be in contact with the second connection wiring pad 242. For example, a second surface 250S2 of the second rear bonding pad may be in contact with a first surface 242S1 of the second connection wiring pad.

[0081] The second rear bonding pad 250 may not be connected to the second peripheral wiring pad 244. The second rear bonding pad 250 may not be in contact with the second peripheral wiring pad 244. The second rear bonding pad 250 may be spaced apart from the second peripheral wiring pad 244. The second surface 250S2 of the second rear bonding pad may be spaced apart from the first surface 244S1 of the second peripheral wiring pad.

[0082] The second rear bonding pad 250 may be electrically connected to the first front bonding pad 160. The second rear bonding pad 250 may be in contact with the first front bonding pad 160. The second rear bonding pad 250 may be bonded to the first front bonding pad 160. The second rear bonding pad 250 and the first front bonding pad 160 may be directly bonded. The second rear bonding pad 250 and the first front bonding pad 160 may be coupled by a high temperature annealing process.

[0083] The second rear bonding pads 250 and the first front bonding pads 160 may be bonded to electrically connect the second semiconductor chip 200 to the first semiconductor chip 100. For example, since the second rear bonding pads 250 and the first front bonding pads 160 contact each other, the second connection wiring pads 242 and the second wiring structure 240 connected to the second rear bonding pads 250 may be electrically connected to the first through electrodes 130 of the first semiconductor chip 100.

[0084] The third semiconductor chip 300 may be disposed on the second semiconductor chip 200. The third semiconductor chip 300 may include a third semiconductor substrate 310, a third semiconductor element layer 320, a third through electrode 330, a third wiring structure 340, a third connection wiring pad 342, a third peripheral wiring pad 344, a third rear bonding pad 350, and a third front bonding pad 360.

[0085] The fourth semiconductor chip 400 may be disposed on the third semiconductor chip 300. The fourth semiconductor chip 400 may include a fourth semiconductor substrate 410, a fourth semiconductor element layer 420, a fourth wiring structure 440, a fourth connection wiring pad 442, a fourth peripheral wiring pad 444, and a fourth rear bonding pad 450. Unlike the first to third semiconductor chips 100 to 300, the fourth semiconductor chip 400 may not include a through electrode and a front bonding pad.

[0086] The second to fourth semiconductor chips 200 to 400 may be substantially the same as or similar to the first semiconductor chip 100. Therefore, a detailed explanation of the second to fourth semiconductor chips 200 to 400 will not be provided.

[0087] The package substrate 500 may be, for example, a printed circuit board (PCB), a ceramic substrate, or an interposer. Alternatively, the package substrate 500 may be a semiconductor chip including a semiconductor element. The package substrate 500 may be used as a supporting substrate for a semiconductor package. For example, the first to fourth semiconductor chips 100 to 400 described above may be stacked on the package substrate 500.

[0088] The package substrate 500 may include a substrate body 510, a lower pad 520, and a package bonding pad 560. The lower pad 520 may be disposed on the lower surface of the substrate body 510. The package bonding pad 560 may be disposed on the upper surface of the substrate body 510. The package bonding pad 560 may be disposed inside the upper passivation layer 511. The upper passivation layer 511 may be disposed on the upper surface of the substrate body 510.

[0089] The external connection terminal 540 may be disposed under the package substrate 500. The external connection terminal 540 may be disposed on the lower pad 520. For example, the external connection terminal 540 may be a solder ball or a bump.

[0090] The bonding insulating films 610, 620 and 630 may be disposed between the first to fourth semiconductor chips 100 to 400. The bonding insulating films 610, 620 and 630 may include, for example, silicon oxide. The side surfaces of the bonding insulating films 610, 620 and 630 may be disposed on the same plane as the side surfaces of the first to fourth semiconductor chips 100 to 400. That is, in the first direction X, the width of the bonding insulating films 610, 620 and 630 may be equal to the width of the first to fourth semiconductor chips 100 to 400.

[0091] The first bonding insulating film 610 may fill a space between the first semiconductor chip 100 and the second semiconductor chip 200. The first bonding insulating film 610 may surround the first front bonding pad 160 and the second rear bonding pad 250 disposed between the first semiconductor chip 100 and the second semiconductor chip 200.

[0092] The second bonding insulating film 620 may fill a space between the second semiconductor chip 200 and the third semiconductor chip 300. The second bonding insulating film 620 may surround the second front bonding pad 260 and the third rear bonding pad 350 disposed between the second semiconductor chip 200 and the third semiconductor chip 300.

[0093] The third bonding insulating film 630 may fill a space between the third semiconductor chip 300 and the fourth semiconductor chip 400. The third bonding insulating film 630 may surround the third front bonding pad 360 and the fourth rear bonding pad 450 disposed between the third semiconductor chip 300 and the fourth semiconductor chip 400.

[0094] The mold film 700 may be formed on the package substrate 500. The mold film 700 may cover the first to fourth semiconductor chips 100 to 400. For example, the mold film 700 may include a polymer such as a resin. For example, the mold film 700 may include, but is not limited to, EMC (Epoxy Molding Compound).

[0095] Figures 3 to 7 is a diagram showing another example of a semiconductor package. For ease of explanation, the description will focus on the reference Figure 1 and Figure 2 The following are different points of explanation.

[0096] refer to Figure 3 , the bonding thickness THB and the thickness TH242 of the second connection wiring pad may be the same. The thickness between the first surface 160S1 of the first front bonding pad and the second surface 250S2 of the second rear bonding pad may be the same as the thickness TH242 of the second connection wiring pad.

[0097] refer to Figure 4 , the width of the first front bonding pad 160 may not be constant. For example, the first front bonding pad 160 may have an inverted trapezoidal cross section. The width of the first surface 160S1 of the first front bonding pad may be less than the width of the second surface 160S2 of the first front bonding pad. That is, the width of the first front bonding pad 160 may increase from the first semiconductor chip 100 toward the second semiconductor chip 200.

[0098] The width of the second rear bonding pad 250 may not be constant. For example, the second rear bonding pad 250 may have a trapezoidal cross section. The width of the first surface 250S1 of the second rear bonding pad may be greater than the width of the second surface 250S2 of the second rear bonding pad. That is, the width of the second rear bonding pad 250 may decrease from the first semiconductor chip 100 toward the second semiconductor chip 200.

[0099] The second surface 160S2 of the first front bonding pad and the first surface 250S1 of the second rear bonding pad may have the same width. The first surface 160S1 of the first front bonding pad and the second surface 250S2 of the second rear bonding pad may have the same width.

[0100] refer to Figure 5 , the second surface 160S2 of the first front bonding pad and the first surface 250S1 of the second rear bonding pad may not have the same width. For example, the width of the second surface 160S2 of the first front bonding pad may be greater than the width of the first surface 250S1 of the second rear bonding pad.

[0101] The first surface 160S1 of the first front bonding pad and the second surface 250S2 of the second rear bonding pad may not have the same width. For example, the width of the first surface 160S1 of the first front bonding pad may be greater than the width of the second surface 250S2 of the second rear bonding pad.

[0102] refer to Figure 6 , the first front bonding pads 160 and the second rear bonding pads 250 may be arranged alternately. For example, the centers of the first front bonding pads 160 and the second rear bonding pads 250 may not coincide with each other, but may be offset from each other.

[0103] refer to Figure 7 , the thickness of the first front bonding pad 160 may not be equal to the thickness of the second rear bonding pad 250. The thickness of the first front bonding pad 160 may be less than the thickness of the second rear bonding pad 250. Figure 7 It is only shown that the thickness of the first front bonding pad 160 is less than the thickness of the second rear bonding pad 250 , but the embodiment is not limited thereto. For example, the thickness of the first front bonding pad 160 may be greater than the thickness of the second rear bonding pad 250 .

[0104] Figure 8 is a diagram showing another example of a semiconductor package. Fig. 9 It is shown Figure 8 For ease of explanation, the description will focus on the reference Figure 1 and Figure 2 The following are different points of explanation.

[0105] refer to Figure 8 and Fig. 9 , the semiconductor package includes a first semiconductor chip 100 , a second semiconductor chip 200 , and a mold film 700 .

[0106] The second semiconductor chip 200 may be disposed on the first semiconductor chip 100. The width of the second semiconductor chip 200 may be smaller than the width of the first semiconductor chip 100. The side surface of the second semiconductor chip 200 may not be disposed on the same plane as the side surface of the first semiconductor chip 100. The mold film 700 may cover the second semiconductor chip 200. The mold film 700 may cover the side surface of the second semiconductor chip 200.

[0107] The first semiconductor element layer 120 may be provided on the upper surface of the first semiconductor substrate 110. The first semiconductor element layer 120 may include a fifth connection wiring pad 182. The fifth connection wiring pad 182 may be provided inside the first semiconductor element layer 120.

[0108] The first front bonding pad 160 may be disposed on the first semiconductor element layer 120. The first front bonding pad 160 may be electrically connected to the first wiring structure 140.

[0109] The first front bonding pad 160 may be disposed on the fifth connection wiring pad 182. The first front bonding pad 160 may be in contact with the fifth connection wiring pad 182.

[0110] The fifth connection wiring pad 182 may be connected to the first wiring structure 140 and the first front bonding pad 160. The fifth connection wiring pad 182 may be in contact with the first wiring structure 140 and the first front bonding pad 160. A first surface 182S1 of the fifth connection wiring pad may be in contact with the first wiring structure 140. The fifth connection wiring pad 182 may electrically connect the first wiring structure 140 to the first front bonding pad 160. A second surface 182S2 of the fifth connection wiring pad may be in contact with the first surface 160S1 of the first front bonding pad.

[0111] The fifth connection wiring pad 182 may be surrounded by the first insulating film 125 inside the first semiconductor element layer 120. The side surface of the fifth connection wiring pad 182 may be surrounded by the first insulating film 125 inside the first semiconductor element layer 120. The first surface 182S1 and the second surface 182S2 of the fifth connection wiring pad 182 may not be covered by the first insulating film 125. The first surface 182S1 and the second surface 182S2 of the fifth connection wiring pad 182 may not overlap with the first insulating film 125. The fifth connection wiring pad 182 may include aluminum.

[0112] The first front bonding pad 160 may be disposed between the fifth connection wiring pad 182 and the second rear bonding pad 250. The second rear bonding pad 250 may be disposed between the first front bonding pad 160 and the second connection wiring pad 242.

[0113] Fig.10 FIG. 1 is a diagram showing another example of a semiconductor package. Figure 8 and Fig. 9 The descriptions are different.

[0114] refer to Fig.10 , the first semiconductor chip 100 may include a fifth peripheral wiring pad 184. The fifth peripheral wiring pad 184 may be spaced apart from the fifth connection wiring pad 182. For example, the fifth peripheral wiring pad 184 may be spaced apart from the fifth connection wiring pad 182 in the first direction X.

[0115] The fifth peripheral wiring pad 184 may not contact the first front bonding pad 160. The fifth peripheral wiring pad 184 may be spaced apart from the first front bonding pad 160. The first front bonding pad 160 may not be disposed on the fifth peripheral wiring pad 184.

[0116] The fifth connection wiring pad 182 and the fifth peripheral wiring pad 184 may have different thicknesses from each other. The thickness TH182 of the fifth connection wiring pad may be greater than the thickness TH184 of the fifth peripheral wiring pad. The thickness TH184 of the fifth peripheral wiring pad may be, for example, 50% or less of the thickness TH182 of the fifth connection wiring pad.

[0117] The first surface 182S1 of the fifth connection wiring pad and the first surface 184S1 of the fifth peripheral wiring pad may be disposed on the same plane.

[0118] The first surface 182S1 of the fifth connection wiring pad may be a face on which the first wiring structure 140 contacts the fifth connection wiring pad 182. The first surface 184S1 of the fifth peripheral wiring pad may be a face on which the first wiring structure 140 contacts the fifth peripheral wiring pad 184.

[0119] The second surface 182S2 of the fifth connection wiring pad and the second surface 184S2 of the fifth peripheral wiring pad may not be arranged on the same plane. For example, based on the second surface 100S2 of the first semiconductor chip, the second surface 182S2 of the fifth connection wiring pad may be arranged above the second surface 184S2 of the fifth peripheral wiring pad. The second surface 182S2 of the fifth connection wiring pad and the second surface 184S2 of the fifth peripheral wiring pad may have a height difference.

[0120] The second surface 182S2 of the fifth connection wiring pad may be a face opposite to the first surface 182S1 of the fifth connection wiring pad. The second surface 182S2 of the fifth connection wiring pad may be a face in contact with the first front bonding pad 160. The second surface 182S2 of the fifth connection wiring pad may face the second semiconductor chip 200.

[0121] The second surface 184S2 of the fifth peripheral wiring pad may be opposite to the first surface 184S1 of the fifth peripheral wiring pad. The second surface 184S2 of the fifth peripheral wiring pad may face the second semiconductor chip 200. The second surface 184S2 of the fifth peripheral wiring pad may be covered by the first insulating film 125 inside the first semiconductor element layer 120.

[0122] exist Fig.10In the embodiment, although the thickness TH182 of the fifth connection wiring pad is shown to be equal to the thickness TH242 of the second connection wiring pad, the embodiment is not limited thereto. For example, the thickness TH182 of the fifth connection wiring pad may be less than the thickness TH242 of the second connection wiring pad. Fig.10 , although the thickness TH184 of the fifth peripheral wiring pad is shown to be equal to the thickness TH244 of the second peripheral wiring pad, the embodiment is not limited thereto. For example, the thickness TH184 of the fifth peripheral wiring pad may be less than the thickness TH244 of the second peripheral wiring pad.

[0123] Fig.11 is a diagram showing another example of a semiconductor package. Fig.12 It is shown Fig.11 For ease of explanation, the description will focus on the reference Figure 1 and Figure 2 The following are different points of explanation.

[0124] refer to Fig.11 and Fig.12 , the semiconductor package includes a package substrate 500 , a first semiconductor chip 100 , a second semiconductor chip 200 , and an interposer 800 .

[0125] The package substrate 500 may be mounted on a motherboard of an electronic device, etc. For example, the package substrate 500 may be mounted on a motherboard of an electronic device, etc. through external connection terminals 540. The package substrate 500 may be, but is not limited to, a ball grid array (BGA) substrate.

[0126] The external connection terminals 540 may be, for example, but not limited to, solder bumps. The external connection terminals 540 may have various shapes, such as connection pads, balls, pins, and columns. Of course, the number, spacing, placement, etc. of the external connection terminals 540 are not limited to those shown in the accompanying drawings and may vary according to design.

[0127] The interposer 800 may be disposed on the upper surface of the package substrate 500. The interposer 800 may be, but is not limited to, a silicon interposer or an organic interposer. The interposer 800 may include a lower surface and an upper surface opposite to each other. The lower surface of the interposer 800 may face the upper surface of the package substrate 500. The interposer 800 may be used to facilitate the connection between the package substrate 500, the first semiconductor chip 100, and the second semiconductor chip 200, and to reduce the warpage of the semiconductor package.

[0128] The interposer 800 may include an interposer substrate 810, an interposer rear bonding pad 850, and an interposer front bonding pad 860. Both the interposer rear bonding pad 850 and the interposer front bonding pad 860 may be used to electrically connect the interposer 800 to other components. For example, the interposer rear bonding pad 850 may be exposed from the lower surface of the interposer substrate 810. The interposer front bonding pad 860 may be exposed from the upper surface of the interposer substrate 810. The interposer rear bonding pad 850 and the interposer front bonding pad 860 may include, but are not limited to, metal materials such as copper (Cu) or aluminum (Al).

[0129] The interposer back bonding pad 850 may contact the package bonding pad 560. The interposer back bonding pad 850 may be directly bonded to the package bonding pad 560. The interposer back bonding pad 850 may be electrically connected to the package bonding pad 560. The interposer back bonding pad 850 and the package bonding pad 560 may be bonded to electrically connect the interposer 800 and the package substrate 500.

[0130] The interposer front bonding pad 860 may contact the first rear bonding pad 150 and the second rear bonding pad 250. The interposer front bonding pad 860 may be directly bonded to the first rear bonding pad 150 and the second rear bonding pad 250. The interposer front bonding pad 860 may be electrically connected to the first rear bonding pad 150 and the second rear bonding pad 250. By bonding the interposer front bonding pad 860 and the first rear bonding pad 150, the first semiconductor chip 100 and the interposer 800 may be electrically connected. By bonding the interposer front bonding pad 860 and the second rear bonding pad 250, the second semiconductor chip 200 and the interposer 800 may be electrically connected.

[0131] The first semiconductor chip 100 and the second semiconductor chip 200 may be mounted on an upper surface of the interposer 800. The first semiconductor chip 100 and the second semiconductor chip 200 may be spaced apart from each other and disposed on an upper surface of the interposer 800. The first semiconductor chip 100 and the second semiconductor chip 200 may each be an integrated circuit (IC) in which hundreds to millions or more semiconductor elements are integrated in a single chip.

[0132] In some embodiments, the first semiconductor chip 100 may be a logic semiconductor chip. For example, the first semiconductor chip 100 may be, but is not limited to, an application processor (AP), such as a CPU (central processing unit), a GPU (graphics processing unit), an FPGA (field programmable gate array), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, and an ASIC (application specific IC).

[0133] In some embodiments, the second semiconductor chip 200 may be a storage semiconductor chip. For example, the second semiconductor chip 200 may be a volatile memory such as DRAM (dynamic random access memory) or SRAM (static random access memory), or a non-volatile memory such as flash memory, PRAM (phase change random access memory), MRAM (magnetoresistive random access memory), FeRAM (ferroelectric random access memory), or RRAM (resistance random access memory).

[0134] As an example, the first semiconductor chip 100 may be an ASIC such as a GPU, and the second semiconductor chip 200 may be a stacked memory such as a high bandwidth memory (HBM). Such a stacked memory may have a form in which a plurality of integrated circuits are stacked. The stacked integrated circuits may be electrically connected to each other through TSV (Through Silicon Via) or the like.

[0135] In some embodiments, the second semiconductor chips 200 may be disposed in greater number than the first semiconductor chip 100. For example, a plurality of second semiconductor chips 200 may be disposed around the first semiconductor chip 100. For example, two second semiconductor chips 200 may be disposed on each side of the first semiconductor chip 100.

[0136] The first semiconductor chip 100 may include a first rear bonding pad 150. The first rear bonding pad 150 may be used to electrically connect the first semiconductor chip 100 to other constituent elements. For example, the first rear bonding pad 150 may be exposed from a lower surface of the first semiconductor chip 100.

[0137] The first rear bonding pad 150 may contact the interposer front bonding pad 860. The first rear bonding pad 150 may be disposed on the interposer front bonding pad 860. The first rear bonding pad 150 may be bonded to the interposer front bonding pad 860. Thus, the first semiconductor chip 100 may be electrically connected to the interposer 800.

[0138] The second semiconductor chip 200 may include second rear bonding pads 250. The second rear bonding pads 250 may be used to electrically connect the second semiconductor chip 200 to other constituent elements. For example, the second rear bonding pads 250 may be exposed from the lower surface of the second semiconductor chip 200.

[0139] The second rear bonding pad 250 may contact the interposer front bonding pad 860. The second rear bonding pad 250 may be disposed on the interposer front bonding pad 860. The second rear bonding pad 250 may be bonded to the interposer front bonding pad 860. The second semiconductor chip 200 may be electrically connected to the interposer 800 accordingly.

[0140] The first rear bonding pad 150 and the second rear bonding pad 250 may each include a metal material, such as but not limited to copper (Cu) or aluminum (Al). In some embodiments, the first rear bonding pad 150 and the second rear bonding pad 250 may each include copper (Cu).

[0141] The package substrate 500 may include a sixth connection wiring pad 582 and a sixth peripheral wiring pad 584. The sixth connection wiring pad 582 and the sixth peripheral wiring pad 584 may be connected to the package substrate wiring 530. The sixth connection wiring pad 582 and the sixth peripheral wiring pad 584 may be spaced apart from each other.

[0142] The sixth connection wiring pad 582 may be connected to the package bonding pad 560. The sixth connection wiring pad 582 may be in contact with the package bonding pad 560. The sixth connection wiring pad 582 may be disposed on the package bonding pad 560. An upper surface of the sixth connection wiring pad 582 may be in contact with a lower surface of the package bonding pad 560. The sixth connection wiring pad 582 may electrically connect the package substrate wiring 530 and the package bonding pad 560.

[0143] The sixth peripheral wiring pad 584 may not be connected to the package bonding pad 560. The sixth peripheral wiring pad 584 may not be in contact with the package bonding pad 560. The upper surface of the sixth peripheral wiring pad 584 may not be in contact with the lower surface of the package bonding pad 560. The sixth peripheral wiring pad 584 may be spaced apart from the package bonding pad 560. The upper surface of the sixth peripheral wiring pad 584 may be spaced apart from the lower surface of the package bonding pad 560.

[0144] The thickness of the sixth connection wiring pad 582 may be greater than the thickness of the sixth peripheral wiring pad 584. The lower surface of the sixth connection wiring pad 582 may be disposed on the same plane as the lower surface of the sixth peripheral wiring pad 584. The upper surface of the sixth connection wiring pad 582 may be disposed above the upper surface of the sixth peripheral wiring pad 584 based on the lower surface of the package substrate 500. The upper surface of the sixth connection wiring pad 582 and the upper surface of the sixth peripheral wiring pad 584 may have a step difference.

[0145] Fig.13 is a diagram showing another example of a semiconductor package. For ease of explanation, the description will focus on the reference Figure 1 and Figure 2 The following are different points of explanation.

[0146] refer to Fig.13, the semiconductor package includes a fifth semiconductor chip 20. The fifth semiconductor chip 20 may be spaced apart from the stacked first to fourth semiconductor chips 100 to 400. The fifth semiconductor chip 20 may be disposed on the interposer 800. The fifth semiconductor chip 20 may be spaced apart from the first to fourth semiconductor chips 100 to 400 stacked on the interposer 800. The fifth semiconductor chip 20 may be covered by a mold film 700. A side surface of the fifth semiconductor chip 20 may be covered by the mold film 700.

[0147] The fifth semiconductor chip 20 may include fifth rear bonding pads 25 , seventh connection wiring pads 42 , and seventh peripheral wiring pads 44 .

[0148] The fifth rear bonding pad 25 may be connected to the seventh connection wiring pad 42. The fifth rear bonding pad 25 may be in contact with the seventh connection wiring pad 42. The fifth rear bonding pad 25 may not be connected to the seventh peripheral wiring pad 44. The fifth rear bonding pad 25 may not be in contact with the seventh peripheral wiring pad 44.

[0149] The fifth rear bonding pads 25 may contact the interposer front bonding pads 860. The fifth rear bonding pads 25 may be bonded to the interposer front bonding pads 860. By bonding the fifth rear bonding pads 25 and the interposer front bonding pads 860, the fifth semiconductor chip 50 and the interposer 800 may be electrically connected.

[0150] The interposer front bonding pad 860 may be connected to the interposer wiring 840. The interposer front bonding pad 860 may be connected to the fifth rear bonding pad 25 and the first rear bonding pad 150. The interposer front bonding pad 860 may be in contact with the fifth rear bonding pad 25 and the first rear bonding pad 150.

[0151] The connection bump 870 may be disposed between the interposer rear bonding pad 850 and the package bonding pad 560. However, the embodiment is not limited thereto. For example, the interposer rear bonding pad 850 and the package bonding pad 560 may directly contact each other.

[0152] Figures 14 to 27 are diagrams illustrating intermediate steps of an example of a method of manufacturing a semiconductor package.

[0153] refer to Fig.14 , a first semiconductor element layer 120 can be formed on the first semiconductor substrate 110 .

[0154] The first through electrode 130 may be formed inside the first semiconductor substrate 110 . The first wiring structure 140 connected to the first through electrode 130 may be formed inside the first semiconductor element layer 120 .

[0155] refer to Fig.15 and Fig.16 , a first portion 142P1 of the first connection wiring pad and the first peripheral wiring pad 144 may be formed.

[0156] The first portion 142P1 of the first connection wiring pad and the first peripheral wiring pad 144 may be formed inside the first portion 125a of the first insulating film of the first semiconductor element layer 120. The first portion 125a of the first insulating film may be formed on the first wiring structure 140. The first portion 142P1 of the first connection wiring pad and the first peripheral wiring pad 144 may be connected to the first wiring structure 140.

[0157] The first portion 142P1 of the first connection wiring pad and the first peripheral wiring pad 144 may have the same thickness. The first surface 142PS1 of the first portion of the first connection wiring pad and the first surface 144S1 of the first peripheral wiring pad may be disposed on the same plane.

[0158] refer to Fig.17 , the first connection wiring pad 142 may be formed inside the first insulating film 125 .

[0159] Specifically, refer to Fig.18 , the second portion 125b of the first insulating film may be formed on the first portion 142P1 of the first connection wiring pad and the first peripheral wiring pad 144. A first connection wiring pad groove 142R that penetrates the second portion 125b of the first insulating film and exposes the first portion 142P1 of the first connection wiring pad may be formed. The first surface 142PS1 of the first portion 142P1 of the first connection wiring pad may be exposed through the first connection wiring pad groove 142R. The first surface 144S1 of the first peripheral wiring pad may be covered by the second portion 125b of the first insulating film.

[0160] Next, refer to Fig.19 , can be in the first connection wiring pad groove ( Fig.18 The second portion 142P2 of the first connection wiring pad may fill the first connection wiring pad groove ( Fig.18 142R).

[0161] The second portion 142P2 of the first connection wiring pad may be formed on the first portion 142P1 of the first connection wiring pad. The second portion 142P2 of the first connection wiring pad may cover the first surface ( Fig.18 142PSl).

[0162] Then, refer to Fig. 20 , removing the second portion covering the first insulating film ( Fig.19 The second portion (125b) of the first connection wiring pad on the upper surface Fig.19 142P2) and can form a first connection wiring pad 142 and a first peripheral wiring pad 144.

[0163] The first surface 142S1 of the first connection wiring pad may be exposed from the first insulating film 125. The first surface 144S1 of the first peripheral wiring pad may be covered by the first insulating film 125. The first insulating film 125 may include a first portion ( Fig.19 125a) and Part II ( Fig.19 125b).

[0164] refer to Fig.21 and Fig. 22 , a first rear bonding pad 150 may be formed.

[0165] The first rear bonding pad 150 may be formed on the first connection wiring pad 142. The first rear bonding pad 150 may be in contact with the first connection wiring pad 142.

[0166] The first passivation layer 121 may be formed on the first insulating film 125. The first passivation layer 121 may cover the first insulating film 125. The first rear bonding pad 150 may be formed inside the first passivation layer 121.

[0167] refer to Fig.23 and Fig.24 , the first semiconductor chip 100 can be bonded to the package substrate 500 .

[0168] When the first semiconductor chip 100 is bonded to the package substrate 500, an annealing process may be performed. For example, heat may be applied when the first semiconductor chip 100 is bonded to the package substrate 500. When annealing, the first rear bonding pad 150 may expand. For example, the first surface 150S1 of the first rear bonding pad may protrude beyond the first surface 121S1 of the first passivation layer.

[0169] The first rear bonding pad 150 disposed on the first connection wiring pad 142 thicker than the first peripheral wiring pad 144 may protrude further than the first passivation layer 121. For example, the first connection wiring pad 142 may also expand due to annealing. Therefore, the first rear bonding pad 150 disposed on the first connection wiring pad 142 may expand relatively further than the first passivation layer 121.

[0170] The first passivation layer 121 covering the first peripheral wiring pad 144 thinner than the first connection wiring pad 142 may expand less than the first rear bonding pad 150. For example, the first peripheral wiring pad 144 may also expand due to annealing, but the first passivation layer 121 not in direct contact with the first peripheral wiring pad 144 with a small thickness may expand relatively less than the first rear bonding pad 150. Since the first insulating film 125 is provided on the first peripheral wiring pad 144, the expansion of the first peripheral wiring pad 144 due to annealing may not affect the first passivation layer 121.

[0171] refer to Fig.25 , the first rear bonding pad 150 and the package bonding pad 560 may be bonded.

[0172] Since the first rear bonding pad 150 expands relatively further than the first passivation layer 121 , the first rear bonding pad 150 and the package bonding pad 560 may be stably bonded.

[0173] On the other hand, for example, reference Fig.24 , if the first surface 144S1 of the first peripheral wiring pad is disposed on the same plane as the first surface 142S1 of the first connection wiring pad, the first passivation layer 121 may also expand due to the expansion of the first peripheral wiring pad 144 due to annealing. In this case, since the extent to which the first surface 150S1 of the first rear bonding pad protrudes beyond the first surface 121S1 of the first passivation layer decreases, the first rear bonding pad 150 may not be stably bonded to the package bonding pad 560.

[0174] Since the first surface 144S1 of the first peripheral wiring pad is disposed above the first surface 142S1 of the first connection wiring pad based on the first surface 121S1 of the first passivation layer, even if the first peripheral wiring pad 144 expands due to annealing, the degree of expansion of the first passivation layer 121 due to the expansion of the first peripheral wiring pad 144 can be reduced. Therefore, the first surface 150S1 of the first rear bonding pad protrudes relatively farther than the first surface 121S1 of the first passivation layer, and the first rear bonding pad 150 can be stably bonded to the package bonding pad 560.

[0175] refer to Fig.26 , the second semiconductor chip 200 can be bonded to the first semiconductor chip 100 .

[0176] The first front bonding pad 160 may be formed inside the first portion 610a of the first bonding insulating film disposed on the upper surface of the first semiconductor chip 100. The second rear bonding pad 250 may be formed inside the second portion 610b of the first bonding insulating film disposed on the lower surface of the second semiconductor chip 200.

[0177] The first front bonding pads 160 and the second rear bonding pads 250 may directly contact each other to bond the first semiconductor chip 100 and the second semiconductor chip 200 .

[0178] Similarly, the first semiconductor chip 100 and the second semiconductor chip 200 may be annealed when bonded. Due to the annealing, the second rear bonding pad 250 disposed on the second connection wiring pad 242 thicker than the second peripheral wiring pad 244 may protrude relatively further than the second portion 610b of the first bonding insulation film. Therefore, the second rear bonding pad 250 may be stably bonded to the first front bonding pad 160.

[0179] refer to Fig. 27 , the third semiconductor chip 300 and the fourth semiconductor chip 400 may be bonded to the second semiconductor chip 200 .

[0180] Next, refer to Figure 1 , a mold film 700 covering the first to fourth semiconductor chips 100 to 400 may be formed.

[0181] Figures 28 to 33 is a diagram showing an intermediate step of another example of a method for manufacturing a semiconductor package. For ease of explanation, the description will focus on the reference Figures 14 to 27 The following are different points. For reference, Fig.28 It is shown Fig.14 Diagram of the following steps.

[0182] refer to Fig.14 , Fig.28 and Fig.29 , the first connection wiring pad 142 and the first pre-peripheral wiring pad 144P may be formed.

[0183] The first connection wiring pad 142 and the first pre-peripheral wiring pad 144P may be formed inside the first insulating film 125 of the first semiconductor element layer 120. The first connection wiring pad 142 and the first pre-peripheral wiring pad 144P may be connected to the first wiring structure 140.

[0184] The first connection wiring pad 142 and the first pre-peripheral wiring pad 144P may have the same thickness. The first surface 142S1 of the first connection wiring pad and the first surface 144PS1 of the first pre-peripheral wiring pad may be disposed on the same plane.

[0185] refer to Fig.30 , a first peripheral wiring pad 144 may be formed inside the first insulating film 125 .

[0186] Specifically, refer to Fig.31, a mask layer 129 may be formed on the first insulating film 125. The mask layer 129 may cover the first connection wiring pad 142.

[0187] A first peripheral wiring pad trench 144T penetrating the mask layer 129 and exposing the first pre-peripheral wiring pad 144P may be formed. A first surface 144PS1 of the first pre-peripheral wiring pad may be exposed through the first peripheral wiring pad trench 144T. A first surface 142S1 of the first connection wiring pad may be covered by the mask layer 129.

[0188] Next, refer to Fig.32 , the first pre-peripheral wiring pad ( Fig.31 For example, the first pre-peripheral wiring pad ( 144P) may be etched inside the first peripheral wiring pad trench 144T. Fig.31 144P) on the upper part.

[0189] The first pre-peripheral wiring pad ( Fig.31 The first peripheral wiring pad 144 is formed while the upper portion of the first peripheral wiring pad 144P is formed. Based on the first semiconductor substrate 110, the first surface 144S1 of the first peripheral wiring pad may be located below the first surface 142S1 of the first connection wiring pad.

[0190] Next, refer to Fig.33 , a first insulating film 125 may be formed inside the first peripheral wiring pad trench 144T. The first insulating film 125 may fill the first peripheral wiring pad trench 144T. The first insulating film 125 may cover the first surface 144S1 of the first peripheral wiring pad inside the first peripheral wiring pad trench 144T.

[0191] right Fig.33 The following steps are explained and Figure 21 to Figure 27 The description is the same as that of , so its description will be omitted.

[0192] Although this specification contains many specific implementation details, these details should not be interpreted as limitations on the scope of any invention or the scope that can be claimed, but as descriptions of features of specific embodiments that can be dedicated to specific inventions. In a single embodiment, certain features described in this specification in the context of separate embodiments can also be implemented in combination. Conversely, different features described in the context of a single embodiment can also be implemented in multiple embodiments, respectively, or in appropriate sub-combinations. In addition, although features can be described above as working in certain combinations, one or more features from the combination can be deleted from the combination in some cases, and the combination can be for sub-combinations or variations of sub-combinations.

[0193] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the described embodiments without departing substantially from the principles of the present disclosure. Therefore, the disclosed embodiments are intended to be general and descriptive only and not for purposes of limitation.

Claims

1. A semiconductor package, comprising: a first semiconductor chip; a second semiconductor chip, on the first semiconductor chip; A first bonding pad is disposed on a first surface of the first semiconductor chip, the first surface facing the second semiconductor chip; as well as a second bonding pad disposed on a second surface of the second semiconductor chip, the second surface facing the first surface, and the second bonding pad being in contact with the first bonding pad, Wherein, the second bonding pad comprises: a third surface in contact with the first bonding pad, and a fourth surface opposite to the third surface, Wherein, the second semiconductor chip comprises: a first wiring pad in contact with the fourth surface of the second bonding pad, and a second wiring pad spaced apart from the first wiring pad and the second bonding pad, and Wherein, the thickness of the second wiring pad is smaller than the thickness of the first wiring pad.

2. The semiconductor package according to claim 1, in, The thickness of the second wiring pad is 50% or less of the thickness of the first wiring pad.

3. The semiconductor package according to claim 1, comprising: A bonding insulating film is provided between the first semiconductor chip and the second semiconductor chip, wherein the bonding insulating film surrounds the first bonding pad and the second bonding pad.

4. The semiconductor package according to claim 3, in, A side surface of the bonding insulating film is disposed on the same plane as a side surface of the second semiconductor chip.

5. The semiconductor package according to claim 1, in, The first wiring pad includes: a fifth surface in contact with the fourth surface, and a sixth surface opposite to the fifth surface, Wherein, the second wiring pad comprises: a seventh surface facing the first semiconductor chip, and an eighth surface opposite to the seventh surface, and Wherein, the sixth surface and the eighth surface are arranged on the same plane.

6. The semiconductor package according to claim 5, in, the second semiconductor chip includes an insulating film surrounding the first wiring pad and the second wiring pad, wherein the insulating film covers the side surface of the first wiring pad and does not overlap with the fifth surface and the sixth surface, and The insulating film covers the side surface of the second wiring pad and the seventh surface, and does not overlap with the eighth surface.

7. The semiconductor package according to claim 1, in, The second semiconductor chip comprises: a wiring structure connected to the first wiring pad and the second wiring pad; a semiconductor substrate disposed on the wiring structure; and A through electrode extends through the semiconductor substrate and is connected to the wiring structure.

8. The semiconductor package according to claim 1, in, The first bonding pad and the second bonding pad include copper Cu, and Wherein, the first wiring pad and the second wiring pad include aluminum Al.

9. The semiconductor package according to claim 1, in, The width of the first bonding pad increases in a direction toward the second bonding pad.

10. The semiconductor package according to claim 1, in, A width of the first bonding pad is greater than a width of the second bonding pad.

11. The semiconductor package according to claim 1, comprising: A packaging substrate, disposed below the first semiconductor chip; as well as A mold film is disposed on the package substrate and covers the first semiconductor chip and the second semiconductor chip.

12. A semiconductor package, comprising: a first semiconductor chip; a second semiconductor chip, on the first semiconductor chip; A first bonding pad is disposed on a first surface of the first semiconductor chip, the first surface facing the second semiconductor chip; as well as a second bonding pad disposed on a second surface of the second semiconductor chip, the second surface facing the first surface, and the second bonding pad being in contact with the first bonding pad, Wherein, the second semiconductor chip comprises: a first wiring pad in contact with the second bonding pad, and a second wiring pad spaced apart from the first wiring pad and the second bonding pad, wherein the first wiring pad includes a third surface contacting the second bonding pad and a fourth surface opposite to the third surface, wherein the second wiring pad includes a fifth surface facing the first semiconductor chip and a sixth surface opposite to the fifth surface, wherein the fourth surface and the sixth surface are arranged on the same plane, and The third surface is located below the fifth surface relative to the first surface of the first semiconductor chip.

13. The semiconductor package according to claim 12, in, A first thickness between the fifth surface and the sixth surface is 50% or less of a second thickness between the third surface and the fourth surface.

14. The semiconductor package according to claim 12, in, the second semiconductor chip includes an insulating film surrounding a side surface of the first wiring pad, wherein the insulating film does not overlap with the third surface of the first wiring pad, and wherein the insulating film overlaps with the fifth surface of the second wiring pad.

15. The semiconductor package according to claim 12, in, The first bonding pad and the second bonding pad include copper Cu, and Wherein, the first wiring pad and the second wiring pad include aluminum Al.

16. The semiconductor package according to claim 12, in, The first semiconductor chip includes a through electrode connected to the first bonding pad.

17. The semiconductor package according to claim 16, in, A width of the through electrode is smaller than a width of the first bonding pad.

18. The semiconductor package according to claim 12, in, A width of the first wiring pad is greater than a width of the second bonding pad.

19. The semiconductor package according to claim 12, in, The second semiconductor chip includes an insulating film surrounding a side surface of the first wiring pad and a side surface of the second wiring pad, and Here, the insulating film is not provided between the second bonding pad and the first wiring pad.

20. A semiconductor package, comprising: Package substrate; A first semiconductor chip, on the packaging substrate; a second semiconductor chip, on the first semiconductor chip; A first bonding pad is disposed on a first surface of the first semiconductor chip, the first surface facing the second semiconductor chip; A second bonding pad is disposed on a second surface of the second semiconductor chip, the second surface faces the first surface, and the second bonding pad is in contact with the first bonding pad; as well as a molding film disposed on the packaging substrate, wherein the molding film covers the first semiconductor chip and the second semiconductor chip, The second bonding pad includes a third surface contacting the first bonding pad and a fourth surface opposite to the third surface. wherein the first semiconductor chip includes a first through-electrode in contact with the first bonding pad and a first wiring structure connected to the first through-electrode, Wherein, the second semiconductor chip comprises: a first wiring pad in contact with the fourth surface of the second bonding pad, a second wiring structure including a second wiring pad spaced apart from the first wiring pad and the second bonding pad, and a second through electrode connected to the second wiring structure, Wherein, the first bonding pad and the second bonding pad include copper Cu, wherein the first wiring pad and the second wiring pad include aluminum Al, and Wherein, the thickness of the second wiring pad is 50% or less of the thickness of the first wiring pad.

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