Semiconductor device and method of forming dummy SOP in saw track

Abstract

The invention discloses a semiconductor device and a method for forming a dummy SOP in a saw track. A semiconductor device has a semiconductor wafer or substrate including a plurality of semiconductor dies. A plurality of first bumps are formed over the active surface of the semiconductor wafer. A plurality of second bumps are formed within a saw track of the semiconductor wafer, the saw track separating the plurality of semiconductor dies. A top surface of the first bump is coplanar with a top surface of the second bump. A second bump is formed within a first saw track of the semiconductor wafer and further within a second saw track of the semiconductor wafer different from the first saw track. The first bump is electrically connected to the semiconductor die to provide functionality for the semiconductor die. The second bump is a dummy bump that does not have an electrical function for the semiconductor die. The semiconductor wafer is singulated through the saw channel and the second bump.

Description

Technical Field

[0001] The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices and methods for forming dummy SOPs within saw streets or wires. Background Art

[0002] Semiconductor devices are commonly found in modern electrical products. Semiconductor devices perform a wide range of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electrical devices, optoelectronics, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, power conversion, networking, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.

[0003] Semiconductor devices often include a semiconductor die or substrate with an electrical interconnect structure, such as a redistribution layer (RDL) formed on one or more surfaces of the semiconductor die or substrate to perform necessary electrical functions. A plurality of bumps are formed on the surface of the semiconductor die or substrate for external interconnection.

[0004] It is desirable to provide maximum or at least adequate adhesion between the bump and the surface pad connected to the RDL. To this end, the bump can be further flattened by an embossing process. Embossing is a form of precision stamping in which the bump is subjected to sufficiently high stress under the stamping pressure to induce plastic flow on the surface of the bump to create a flat top surface. Plastic flow also reduces the surface grain size, and processing hardens the material, while the darker material retains the properties of toughness and ductility.

[0005] The imprint process introduces considerable pressure and stress on the bumps and semiconductor wafer. For smaller semiconductor die, such as 4.0 millimeters (mm)×4.0 mm, assuming 19 bumps per die and 1049 dies per wafer, this yields 19,931 bumps to absorb the imprint pressure on the wafer. In some manufacturing processes, the imprint pressure is too large for the 19,931 supporting bumps or becomes non-uniform, resulting in non-similar bumps and lack of control over bump diameter, height, and coplanarity. From a design and manufacturing perspective, it is undesirable to form additional bumps on the active surface of a semiconductor wafer simply to account for the imprint pressure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1a to Figure 1c illustrates a semiconductor wafer having a plurality of semiconductor dies separated by saw streets;

[0007] Figures 2a to 2j A process of forming dummy bumps in saw streets of a semiconductor wafer to distribute imprint pressure is illustrated;

[0008] Figure 3 illustrates a semiconductor die after an imprinting operation and singulation;

[0009] Figures 4a to 4i illustrates a process of forming dummy bumps within saw streets of a substrate including electrical components to distribute imprint pressure;

[0010] Figure 5 illustrates an electrical assembly after an imprinting operation and singulation; and

[0011] Figure 6 A printed circuit board (PCB) is illustrated with different types of packages disposed on a surface of the PCB. DETAILED DESCRIPTION

[0012] The present invention is described in one or more embodiments in the following description with reference to the figures, and similar reference numerals in the figures represent the same or similar elements. Although the present invention is described in terms of the best mode for achieving the purpose of the present invention, it will be appreciated by those skilled in the art that it is intended to cover substitutions, modifications and equivalents that may be included in the spirit and scope of the present invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings. The features shown in the figures are not necessarily drawn to scale. Elements with similar functions in the figures are assigned the same reference numerals. The term "semiconductor die" as used herein refers to both the singular and plural forms of the term, and accordingly may refer to both a single semiconductor device and a plurality of semiconductor devices.

[0013] Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional electrical circuit. Active electrical components, such as transistors and diodes, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, and resistors, create the relationship between voltage and current necessary to perform the electrical circuit function.

[0014] Back-end manufacturing refers to cutting or singulating the completed wafer into individual semiconductor dies and packaging the semiconductor dies for structural support, electrical interconnection, and environmental isolation. In order to singulate the semiconductor dies, the wafer is scribed and broken along the non-functional area of ​​the wafer called saw road or scribe line. The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual semiconductor dies are disposed on a package substrate, which includes pins or contact pads for interconnection with other system components. The contact pads formed on the semiconductor die are then connected to the contact pads in the package. The electrical connection can be made using a conductive layer, a bump, a columnar bump, a conductive paste, or a wiring bond. Encapsulants or other molding materials are deposited on the package to provide physical support and electrical isolation. The completed package is then inserted into the electrical system, and the functionality of the semiconductor device is made available to other system components.

[0015] Figure 1a A semiconductor wafer 100 is shown having a base substrate material 102 such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. A plurality of semiconductor dies or electrical components 104 are formed on the wafer 100, separated by non-active, wafer regions between the dies or saw streets or saw lines 106. The saw streets 106 provide cutting areas to singulate the semiconductor wafer 100 into individual semiconductor dies 104. The saw streets 106a extend in a first direction across the semiconductor wafer 100, and the saw streets 106b are different from the saw streets 106a and extend in a second direction across the semiconductor wafer 100. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 mm.

[0016] Figure 1b A cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each semiconductor die 104 has a back surface or inactive surface 108 and an active surface 110, which contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuits, such as a digital signal processor (DSP), an application specific integrated circuit (ASIC), memory, or other signal processing circuits. The semiconductor die 104 may also include IPDs, such as inductors, capacitors, and resistors, for RF signal processing.

[0017] Conductive layer 112 is formed over active surface 110 using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition processes. Conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. Conductive layer 112 operates as a contact pad electrically connected to the circuit on active surface 110.

[0018] Conductive bump material is deposited on conductive layer 112 using evaporation, electrolytic plating, electroless plating, ball drop or screen printing process. Bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and their combination, and optional flux solution. For example, bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. Bump material is bonded to conductive layer 112 using suitable attachment or bonding process. In one embodiment, the bump material is reflowed to form ball or bump 118 by heating the material above its melting point. In one embodiment, bump 118 is formed on under bump metallization (UBM), and under bump metallization has a wetting layer, a barrier layer and an adhesive layer. Bump 118 can also be compression bonded or thermally compressed bonded to conductive layer 112. In one embodiment, bump 118 is a solder-on-pad (SOP) interconnect structure. Bumps 118 represent one type of interconnect structure that may be formed over conductive layer 112. The interconnect structure may also use bond wires, conductive pastes, stud bumps, micro bumps, or other electrical interconnects.

[0019] It is desirable to provide maximum or at least adequate adhesion between the bump 118 and the conductive layer 112. To this end, the bump 118 can be further planarized by an embossing process. Embossing is a form of precision stamping in which the bump 118 is subjected to sufficiently high stresses under the stamping pressure to induce plastic flow on the surface of the bump to create a flat top surface. Plastic flow also reduces surface grain size, and processing hardens the material, while the darker material retains the properties of toughness and ductility.

[0020] exist Figure 1c In the process, the semiconductor wafer 100 is singulated into individual semiconductor dies 104 through saw streets 106 using a saw blade or laser cutting tool 119. The individual semiconductor dies 104 can be inspected and electrically tested to identify known good dies or known good units (KGD / KGU) after singulation.

[0021] Figure 2a A semiconductor wafer 120 is shown having a base substrate material 122 such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. Figure 1a to Figure 1b, a plurality of semiconductor dies or electrical components 124 are formed on the wafer 120, which are separated by non-active, inter-die wafer regions or saw streets 126. The saw streets 126 provide cutting regions to singulate the semiconductor wafer 120 into individual semiconductor dies 124. The saw streets 126a extend in a first direction across the semiconductor wafer 120, and the saw streets 126b are different from the saw streets 126a and extend in a second direction across the semiconductor wafer 120. In this case, the semiconductor wafer or strip 120 is rectangular in shape, having a width of 240.0 mm and a length of 74.0-95.0 mm.

[0022] Each semiconductor die 124 has a back surface or inactive surface and an active surface 125 that contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuits may include one or more transistors, diodes, and other circuit elements formed within active surface 125 to implement analog or digital circuits, such as DSPs, ASICs, memories, or other signal processing circuits. Semiconductor die 124 may also contain IPDs, such as inductors, capacitors, and resistors, for RF signal processing.

[0023] Conductive layer 127 is formed over active surface 125 using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition process, such as in Figure 2e Conductive layer 127 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Conductive layer 127 operates as a contact pad electrically connected to the circuits on active surface 125 of semiconductor die 124.

[0024] Conductive bump material is deposited on the conductive layer 127 on the active surface 125 of the semiconductor wafer 120 in the active area of ​​the semiconductor die 124 using evaporation, electrolytic plating, electroless plating, ball drop or screen printing. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combinations thereof, as well as optional flux solutions. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is bonded to the conductive layer 127 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 128. In one embodiment, the bump 128 is formed on the UBM, and the UBM has a wetting layer, a barrier layer and an adhesive layer. The bump 128 can also be compression bonded or thermally compressed bonded to the conductive layer 127. Bumps 128 represent one type of interconnect structure that may be formed over conductive layer 127 within active region 125 of semiconductor die 124. The interconnect structure may also use conductive paste, stud bumps, micro bumps, or other electrical interconnects.

[0025] As discussed with respect to bump 118, it is desirable to provide maximum or at least adequate adhesion between bump 128 and conductive layer 127. To this end, bump 128 can be further planarized by an embossing process. Embossing induces plastic flow on the surface of bump 128 to create a flat top surface. Plastic flow also reduces surface grain size, and processing hardens the material, while the deeper material retains the properties of toughness and ductility.

[0026] The imprint process introduces considerable pressure and stress on the bumps 128 of the semiconductor wafer 120. For smaller semiconductor die 124, such as 4.0 mm×4.0 mm, assuming 19 bumps per die and 1049 dies per wafer 120, this produces 19,931 bumps to absorb the imprint pressure on the wafer. In some manufacturing processes, the imprint pressure is too large for the 19,931 supporting bumps or becomes non-uniform, resulting in non-similar bumps and lack of control over bump diameter, height, and coplanarity. The semiconductor wafer 120 may require 23,000 bumps or more to properly handle the imprint pressure. From a design and manufacturing perspective, it is undesirable to form additional bumps on the active surface 125 of the semiconductor die 124 just to address the imprint pressure.

[0027] exist Figure 2bIn the process, a conductive bump material is deposited on a surface 132 of the semiconductor wafer 120 in an area defined by the saw street 126 using evaporation, electrolytic plating, electroless plating, ball drop or screen printing. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combinations thereof, and an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is bonded to the saw street 126 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 130. The bump 130 can also be compression bonded or thermally compression bonded to the saw street 126.

[0028] Bump 130 is a dummy support bump or SOP that does not have an electrical interconnection function. However, the total number of functional bumps 128 and dummy support bumps 130 meets or exceeds the goal of 23,000 bumps per wafer 120. Dummy support bumps or SOP 130 work together with functional bumps 128 to distribute the imprint pressure across semiconductor wafer 120 and maintain control of bump 128 diameter, height and coplanarity. Dummy bumps 130 formed in saw street 126 provide additional support points during the imprint operation without adding bumps to the active surface 125 of semiconductor die 124. Depending on the number of additional support bumps required for the imprint operation, dummy support bumps 130 can be formed completely around each semiconductor die 124 in saw street 126, or partially along certain portions of saw street 126.

[0029] Figure 2c Further details of a portion of semiconductor wafer 120 are illustrated, showing one semiconductor die 124 having bumps 128 and dummy bumps 130 formed around the semiconductor die within saw streets 126 depending on the number of dummy bumps 130 required for the support imprint operation. In one embodiment, dummy support bumps 130 have a pitch P1 of 130.0-200.0 μm within saw streets 126.

[0030] Figure 2d Further details of a portion of semiconductor wafer 120 are illustrated, showing one semiconductor die 124 having bumps 128 and dummy bumps 130 formed along portions of saw streets 126 depending on the number of dummy bumps 130 required for the support imprint operation. In one embodiment, dummy support bumps 130 have a pitch P2 within saw streets 126 that is greater than pitch P1.

[0031] Figure 2e is a first cross-sectional view of semiconductor wafer 120 showing semiconductor die 124 having bumps 128 and dummy bumps 130 formed within saw streets 126 b. Figure 2fis a second cross-sectional view of the semiconductor wafer 120, which is orthogonal to Figure 2e FIG. 1 shows a semiconductor die 124 having bumps 128 and dummy bumps 130 formed within saw streets 126 a. In particular, top surfaces 134 of bumps 128 are coplanar with top surfaces 135 of bumps 130.

[0032] exist Figure 2g to Figure 2h In the embodiment, the semiconductor wafer 120 is subjected to an imprinting operation using a stamping press 136. The stamping press 136 applies pressure to the functional bumps 128 and the dummy bumps 130 under a force F. Figure 2g In FIG. 1 , a stamping press 136 is disposed above the semiconductor wafer 120 , having a pressing surface 137 oriented toward the bumps 128 and 130 . Figure 2h The stamping press 136 is shown contacting the top surface 134 of the functional bump 128 and the top surface 135 of the dummy bump 130 to subject the semiconductor wafer 120 to an imprinting operation. The pressing surface 137 simultaneously contacts the top surface 134 of the coplanar functional bump 128 and the top surface 135 of the dummy bump 130 and distributes the force or pressure of the imprinting operation substantially equally across all bumps 128 and 130. With the dummy bump 130 placed within the saw street 126, the semiconductor wafer 120 has more than 23,000 bumps to distribute the pressure of the imprinting operation across the semiconductor wafer 120 while maintaining control over the bump 128 diameter, height, and coplanarity.

[0033] exist Figure 2i In, from Figure 2e From the perspective of FIG. 1 , a saw blade or laser cutting tool 138 is used to singulate the semiconductor wafer 120 through the saw streets 126 b and the dummy bumps 130 into individual semiconductor dies 124. Figure 2f 's point of view, Figure 2j The semiconductor wafer 120 is shown singulated via the saw streets 126a and the dummy bumps 130. Figure 2g to Figure 2h After the imprint operation in FIG. 1 , singulation destroys or removes the dummy bumps 130 within the saw streets 126 because the dummy bumps have served their purpose and are no longer needed.

[0034] Figure 3The semiconductor die 124 is shown after singulation. The individual semiconductor die 124 can be inspected and electrically tested for identification of known good die or known good units (KGD / KGU). The bumps 128 have a flat top surface 134 from the imprint process. The dummy support bumps or SOPs 130 in the saw streets 126 have worked with the functional bumps 128 to distribute the imprint pressure across the semiconductor wafer 120 and maintain control of the bump 128 diameter, height, and coplanarity. The dummy bumps 130 formed within the saw streets 126 provide additional points of support during the imprint operation without adding bumps to the active surface 125 of the semiconductor die 124.

[0035] In another embodiment, Figure 4a A temporary substrate or carrier 150 is shown, comprising a sacrificial material such as silicon, a polymer, beryllium oxide, glass, or other suitable low-cost, rigid material for structural support. The substrate 150 has a major surface 152 and a major surface 154 opposite the surface 152. In one embodiment, the carrier 150 is a support structure having a temporary bonding layer 156 formed on the carrier. The temporary bonding layer 156 can be a film or foil bonded to the surface 152.

[0036] exist Figure 4b In the embodiment, electrical components 160a-160c are disposed on the surface 152 of the substrate 150. The electrical components 160a-160c can be similar to or made to be similar to the electrical components from Figure 1c The semiconductor die 104 has a back surface 108 oriented toward a surface 152 of the substrate 150. Alternatively, the electrical components 160a-160c may include other semiconductor dies, semiconductor packages, surface mount devices, RF components, discrete electrical devices, or integrated passive devices (IPDs).

[0037] The electrical components 160a-160c are positioned over the substrate 150 using a pick and place operation. The electrical components 160a-160c are brought into contact with the bonding layer 156. Figure 4c The electrical components 160a-160c bonded to the substrate 150 are shown as a reconstituted wafer 164. The electrical components 160a-160c are separated by saw streets or saw lines 168. Figure 4e As in FIG. 1 , the saw streets 168 a extend in a first direction across the substrate 150 , and the saw streets 168 b , unlike the saw streets 168 a , extend in a second direction across the substrate 150 .

[0038] As discussed with respect to bump 128, it is desirable to provide maximum or at least adequate adhesion between bump 118 and conductive layer 112. To this end, bump 118 may be further planarized by an embossing process. Embossing induces plastic flow on the surface of bump 118 to create a flat top surface. Plastic flow also reduces surface grain size, and processing hardens the material, while the deeper material retains the properties of toughness and ductility.

[0039] The imprint process introduces considerable pressure and stress on the bumps 118 on the reconstituted wafer 164. For smaller semiconductor die 104, such as 4.0 mm×4.0 mm, assuming 19 bumps per die and 1049 dies per reconstituted wafer 164, this yields 19,931 bumps to absorb the imprint pressure on the wafer. In some manufacturing processes, the imprint pressure is too great for these 19,931 supporting bumps or becomes non-uniform, resulting in non-similar bumps and a lack of control over bump diameter, height, and coplanarity. The reconstituted wafer 164 should have 23,000 bumps or more to properly handle the imprint pressure. From a design and manufacturing perspective, it is undesirable to form additional bumps on the active surface 110 of the semiconductor die 104 simply to account for the imprint pressure.

[0040] exist Figure 4d In the process, a conductive bump material is deposited on the surface 152 of the substrate 150 in the area defined by the saw street 168 using evaporation, electrolytic plating, electroless plating, ball drop or screen printing. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combinations thereof, and an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is bonded to the saw street 168 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 166. The bump 166 can also be compression bonded or thermally compression bonded to the saw street 168.

[0041] Bumps 166 are dummy support bumps or SOPs that do not have electrical interconnect functionality. However, the total number of functional bumps 118 and dummy support bumps 166 exceeds the goal of 23,000 bumps per reconstructed wafer 164. Dummy support bumps or SOPs 166 work with functional bumps 118 to distribute the imprint pressure across the reconstructed wafer 164 and maintain control of bump 118 diameter, height, and coplanarity. Dummy bumps 166 formed within saw streets 168 provide additional points of support during the imprint operation without adding bumps to the active surfaces of electrical components 160a-160c. Similar to Figure 2c to Figure 2dDepending on the number of additional support bumps required for the imprinting operation, the dummy support bumps 166 may be formed completely around each electrical component 160a-160b within the saw street 168, or partially along certain portions of the saw street 168. In particular, the top surface 170 of the bump 118 is coplanar with the top surface 172 of the bump 166.

[0042] Figure 4e is a top view of electrical components 160 a - 160 c having bumps 118 bonded to reconstituted wafer 164 and dummy bumps 166 formed within saw streets 168 . Figure 4f Further detail of a portion of reconstituted wafer 164 is illustrated, showing one electrical component 160 a having bumps 118 and dummy bumps 166 formed around the electrical component within saw streets 168 .

[0043] exist Figure 4g to Figure 4h In the process, a punch press 180 is used to make Figure 4d-4f The reconstructed wafer 164 undergoes an imprinting operation. The stamping press 180 applies pressure to the functional bumps 118 and the dummy bumps 166 under a force F. Figure 4g In FIG. 1 , a stamping press 180 is disposed above the reconstituted wafer 164 , having a pressing surface 182 oriented toward the bumps 118 and 166 . Figure 4h A stamping press 180 is shown contacting the top surface 170 of the functional bump 118 and the top surface 172 of the dummy bump 166 to subject the reconstructed wafer 164 to an imprinting operation. The pressing surface 182 simultaneously contacts the coplanar functional bumps 118 and the dummy support bumps 166 to distribute the force or pressure of the imprinting operation substantially equally across all bumps 118 and 166. With the dummy bumps 166 placed within the saw streets 168, the reconstructed wafer 164 has over 23,000 bumps to distribute the pressure of the imprinting operation across the substrate while maintaining control over the bump 118 diameter, height, and coplanarity.

[0044] exist Figure 4i In the embodiment, a saw blade or laser cutting tool 180 is used to singulate the reconstructed wafer 164 through the saw streets 168 and the dummy bumps 166 into individual electrical components 160a-160c. Figure 4g to Figure 4h After the imprint operation in FIG. 1 , singulation destroys or removes the dummy bumps 166 within the saw streets 168 because the dummy bumps have served their purpose and are no longer needed.

[0045] Figure 5The electrical component 160a after singulation is shown. The substrate 150 and the bonding layer 156 are removed by chemical etching, chemical mechanical polishing (CMP), mechanical stripping, mechanical grinding, thermal baking, ultraviolet (UV) light or wet stripping. The individual electrical components 160a can be inspected and electrically tested for identification of known good dies or known good units (KGD / KGU). The bumps 118 have a flat top surface 172 from the imprint process. The dummy support bumps or SOPs 166 in the saw streets 168 have worked with the functional bumps 118 to distribute the imprint pressure across the reconstructed wafer 164 and maintain control of the bump 118 diameter, height and coplanarity. The dummy bumps 166 formed in the saw streets 168 provide additional support points during the imprint operation without adding bumps to the active surface 110 of the semiconductor die 104.

[0046] Figure 6 An electrical device 400 is illustrated having a chip carrier substrate or PCB 402 with multiple semiconductor packages, including semiconductor die 124 and electrical components 160a-160c, disposed on a surface of PCB 402. Electrical device 400 may have one type of semiconductor package or multiple types of semiconductor packages depending on the application.

[0047] The electrical device 400 can be an independent system that uses a semiconductor package to perform one or more electrical functions. Alternatively, the electrical device 400 can be a subcomponent of a larger system. For example, the electrical device 400 can be a part of a flat panel, a cellular phone, a digital camera, a communication system, or other electrical equipment. Alternatively, the electrical device 400 can be a graphics card, a network interface card, or other signal processing cards that can be inserted into a computer. The semiconductor package can include a microprocessor, a memory, an ASIC, a logic circuit, an analog circuit, an RF circuit, a discrete device, or other semiconductor die or electrical components. Miniaturization and weight reduction are crucial for the product to be accepted by the market. The distance between semiconductor devices can be reduced to achieve higher density.

[0048] exist Figure 6 In the PCB 402, PCB 402 provides a general base for structural support and electrical interconnection of semiconductor packages deployed on the PCB. Conductive signal traces 404 are formed on the surface or in various layers of PCB 402 using evaporation, electrolytic plating, electroless plating, screen printing or other suitable metal deposition processes. Signal traces 404 provide electrical communication between each of the semiconductor packages, mounted components and other external system components. Traces 404 also provide power and ground connections to each of the semiconductor packages.

[0049] In some embodiments, the semiconductor device has two packaging levels. The first level of packaging is a technology for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second level of packaging involves mechanically and electrically attaching an intermediate substrate to a PCB. In other embodiments, the semiconductor device may have a first level of packaging, in which the die is directly mechanically and electrically deployed on the PCB. For the purpose of illustration, several types of first level packaging are shown on PCB 402, including a bonding wiring package 406 and a flip chip 408. Additionally, several types of second level packaging deployed on PCB 402 are shown, including a ball grid array (BGA) 410, a bump chip carrier (BCC) 412, a land grid array (LGA) 416, a multi-chip module (MCM) or a SIP module 418, a quad flat package (QFN) 420, a quad flat package 422, an embedded wafer-level ball grid array (eWLB) 424, and a wafer-level chip scale package (WLCSP) 426. In one embodiment, eWLB 424 is a fan-out wafer level package (Fo-WLP) and WLCSP 426 is a fan-in wafer level package (Fi-WLP). Depending on the system requirements, any combination of semiconductor packages and other electrical components configured with any combination of first-level packaging styles and second-level packaging styles can be connected to PCB 402. In some embodiments, electrical device 400 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate pre-made components into electrical devices and systems. Because semiconductor packages include complex functionality, electrical devices can be manufactured using less expensive components and assembly line manufacturing processes. The resulting device is less likely to fail and is less expensive to manufacture, resulting in lower costs for consumers.

[0050] While one or more embodiments of the present invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations may be made to those embodiments without departing from the scope of the invention as set forth in the following claims.

Claims

1. A semiconductor device, comprising: a semiconductor wafer or substrate including a plurality of semiconductor dies; a plurality of first bumps formed on an active surface of a semiconductor wafer or substrate; as well as A plurality of second bumps are formed within saw streets of the semiconductor wafer or substrate, the saw streets separating the plurality of semiconductor dies. 2 . The semiconductor device according to claim 1 , wherein a top surface of the first bump is coplanar with a top surface of the second bump. 3 . The semiconductor device according to claim 1 , wherein the plurality of second bumps are formed within a first saw street of a semiconductor wafer or substrate. 4 . The semiconductor device according to claim 3 , wherein the plurality of second bumps are formed in a second saw street of the semiconductor wafer or substrate that is different from the first saw street. 5 . The semiconductor device of claim 1 , wherein the first bump is electrically connected to the semiconductor die to provide a function for the semiconductor die, and the second bump is a dummy bump having no electrical function for the semiconductor die.

6. A semiconductor device comprising: Semiconductor wafers or substrates; a plurality of first bumps formed on an active surface of a semiconductor wafer or substrate; as well as A plurality of second bumps are formed in saw streets of the semiconductor wafer or substrate.

7. The semiconductor device of claim 6, wherein the semiconductor wafer or substrate comprises a plurality of semiconductor dies. 8 . The semiconductor device of claim 7 , wherein the first bump is electrically connected to the semiconductor die to provide a function for the semiconductor die, and the second bump is a dummy bump having no electrical function for the semiconductor die. 9 . The semiconductor device according to claim 6 , wherein the plurality of second bumps are formed within a first saw street of a semiconductor wafer or substrate. 10 . The semiconductor device according to claim 9 , wherein the plurality of second bumps are formed in a second saw street of the semiconductor wafer or substrate that is different from the first saw street.

11. A method for manufacturing a semiconductor device, comprising: Providing a semiconductor wafer or substrate; forming a plurality of first bumps over an active surface of a semiconductor wafer or substrate; as well as A plurality of second bumps are formed in saw streets of the semiconductor wafer or substrate.

12. The method of claim 11, wherein the semiconductor wafer or substrate comprises a plurality of semiconductor dies. 13 . The method of claim 12 , wherein the first bumps are electrically connected to the semiconductor die to provide a function for the semiconductor die, and the second bumps are dummy bumps having no electrical function for the semiconductor die. The method of claim 11 , wherein a top surface of the first bump is coplanar with a top surface of the second bump. 15 . The method of claim 11 , wherein the plurality of second bumps are formed within a first saw street of a semiconductor wafer or substrate and further formed within a second saw street of the semiconductor wafer or substrate that is different from the first saw street.

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