Semiconductor element and manufacturing method thereof

Abstract

The invention discloses a semiconductor element and a manufacturing method thereof. The semiconductor element comprises a semiconductor stack including a first type semiconductor layer and a second type semiconductor layer; the protection layer is located on the semiconductor lamination layer and is provided with n first open holes and m second open holes; the first electrode is positioned on the n first holes, is provided with a first outer surface and is electrically connected with the first type semiconductor layer; the second electrode is positioned on the m second holes, is provided with a second outer surface and is electrically connected with the second type semiconductor layer; the first conductive bump is positioned on the first electrode and is provided with a convex first top part; the second conductive bump is positioned on the second electrode and is provided with a convex second top part; from the sectional view, the contact surface of the first conductive bump and the first electrode has a first horizontal width, the contact surface of the second conductive bump and the second electrode has a second horizontal width, and the ratio of the first horizontal width to the second horizontal width is between 0.8 and 1.2. The first top portion and the second top portion have substantially the same horizontal height.

Description

Technical Field

[0001] The present invention relates to a semiconductor element, and in particular to an electrical connection structure of a semiconductor element and a manufacturing method thereof. Background Art

[0002] In the semiconductor manufacturing process, wire layers at different levels are usually connected by conductive materials filled in holes in the dielectric layer. However, to completely fill the holes of different depths with conductive materials and form a flat surface, it usually takes multiple steps to complete, which is complicated and costly.

[0003] In addition, in the packaging structure of semiconductor chips, conductive bumps are usually used to establish electrical connections with external circuits. However, the existing manufacturing methods of conductive bumps often cannot accurately control the height of the conductive bumps, resulting in the vertices of multiple conductive bumps of the semiconductor chip being unable to be coplanar, thereby affecting the production yield of the semiconductor chip. Summary of the invention

[0004] In view of this, embodiments of the present invention provide a method for precisely controlling the dimensions of an electrical connection structure of a semiconductor device, for example, precisely controlling the height of a conductive bump in a semiconductor device, and provide a semiconductor device manufactured using the manufacturing process.

[0005] According to one embodiment of the present invention, a semiconductor element is provided, comprising a semiconductor stack comprising a first-type semiconductor layer and a second-type semiconductor layer; a protective layer is located on the semiconductor stack and has n first openings and m second openings; a first electrode is located in the n first openings, has a first outer surface and is electrically connected to the first-type semiconductor layer; a second electrode is located in the m second openings, has a second outer surface and is electrically connected to the second-type semiconductor layer; a first conductive bump is located on the first electrode and has a first protruding top; and a second conductive bump is located on the second electrode and has a second protruding top; wherein, from a cross-sectional view, the contact surface between the first conductive bump and the first electrode has a first horizontal width, the contact surface between the second conductive bump and the second electrode has a second horizontal width, and the ratio of the first horizontal width to the second horizontal width is between 0.8 and 1.2; wherein the first top and the second top have substantially the same horizontal height. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order to make the following easier to understand, the drawings and their detailed text descriptions can be referred to when reading the present invention. The specific embodiments of the present invention are explained in detail through the specific embodiments in this article and with reference to the corresponding drawings, and the working principles of the specific embodiments of the present invention are explained. In addition, for the sake of clarity, the features in the drawings may not be drawn according to the actual scale, so the sizes of some features in some drawings may be deliberately enlarged or reduced.

[0007] Figure 1A A three-dimensional diagram of a semiconductor device according to an embodiment of the present invention;

[0008] Figure 1B for Figure 1A A cross-sectional view of the semiconductor element along the line segment A-A';

[0009] Figure 2A A three-dimensional diagram of a semiconductor device according to an embodiment of the present invention;

[0010] Figure 2B Figure 2A A cross-sectional view of the semiconductor element along the line segment BB';

[0011] Figure 3A is a cross-sectional view of a semiconductor device according to another embodiment of the present invention;

[0012] Figure 3B A cross-sectional view of a semiconductor device according to another embodiment of the present invention;

[0013] Figure 4 A cross-sectional view of a semiconductor device according to another embodiment of the present invention;

[0014] Figure 5A to Figure 5D FIG. 4 is a flow chart of manufacturing a semiconductor device according to an embodiment of the present invention.

[0015] Explanation of symbols

[0016] 1, 2, 3, 4…Semiconductor components

[0017] 2a…first conductive bump

[0018] 2b…second conductive bump

[0019] 3a…First electrode

[0020] 3b…Second electrode

[0021] 5a…First opening

[0022] 5a1…first opening

[0023] 5a2…Second first opening

[0024] 5b…Second opening

[0025] 7a…first inner wall

[0026] 7b…Second inner wall

[0027] 10…Substrate

[0028] 10'...Upper surface

[0029] 11…First type semiconductor layer

[0030] 12...Active layer 13...Second type semiconductor layer

[0031] 14…Semiconductor stacking

[0032] 15…Protective layer

[0033] 17…lower surface

[0034] 19…Outermost edge

[0035] 21a…First Top

[0036] 21b…Second top

[0037] 22a, 22b…outermost surface

[0038] 23a…first bonding pad

[0039] 23b…second bonding pad

[0040] 24a, 24b…upper surface

[0041] 30a ... first outer surface

[0042] 30b ... second outer surface

[0043] 83…Rubber

[0044] 100…semiconductor unit 151…outermost upper surface A-A', BB'…line segment D…minimum horizontal distance H…horizontal lines H1, H2…height L…laser energy R1, R2…partial area W1…first (maximum) horizontal width W2…second (maximum) horizontal width θ…inner angle θ1…first angle θ2…second angle DETAILED DESCRIPTION

[0045] The present invention provides several different embodiments that can be used to implement different features of the present invention. For the sake of simplicity of description, the present invention also describes examples of specific components and arrangements. The purpose of providing these embodiments is only to illustrate, not to limit in any way. Various embodiments in the present invention may use repeated reference symbols and / or text notes. The use of these repeated reference symbols and notes is to make the description more concise and clear, rather than to indicate the relevance between different embodiments and / or configurations.

[0046] In addition, for the spatially related descriptive words mentioned in the present invention, such as "under", "low", "down", "above", "on", "top", "bottom" and similar words, for the convenience of description, their usage is to describe the relative relationship between one element or feature and another (or multiple) elements or features in the drawings. In addition to the swing direction shown in the drawings, these spatially related words are also used to describe the orientation of each element during use and operation. As the orientation of each element is different (rotated 90 degrees or other orientations), the related descriptions used to describe its orientation should also be interpreted in a similar manner.

[0047] Although the present invention uses the terms first, second, third, etc. to describe elements, components, regions, layers, and / or blocks (Section), it should be understood that these elements, components, regions, layers, and / or blocks should not be limited by these terms. These terms are only used to distinguish a certain element, component, region, layer, and / or block from another element, component, region, layer, and / or block, and they themselves do not mean or represent any ordinal number of the element, nor do they represent the order of arrangement of a certain element and another element, or the order in the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer, or block discussed below can also be referred to as the second element, component, region, layer, or block.

[0048] The terms "about" or "substantially" mentioned in the present invention generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of a specific description of "about" or "substantially", the meaning of "about" or "substantially" can still be implied.

[0049] The terms "coupling", "coupling", and "electrical connection" mentioned in the present invention include any direct and indirect electrical connection means. For example, if the text describes that a first component is coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

[0050] Figure 1A is a three-dimensional diagram of a semiconductor device 1 according to an embodiment of the present invention. Figure 1B for Figure 1AThe cross-sectional view of the semiconductor element 1 along the line segment A-A' in FIG. The semiconductor element 1 may be a light-emitting diode (LED), a laser diode (LD), or a transistor. The semiconductor element 1 has a first electrode 3a and a second electrode 3b on the side facing away from the substrate 10. A first conductive bump 2a and a second conductive bump 2b are directly disposed on the first electrode 3a and the second electrode 3b, respectively. The upper surfaces of the first conductive bump 2a and the second conductive bump 2b are convex arc-shaped and are not parallel to the upper surfaces of the first electrode 3a and the second electrode 3b.

[0051] The substrate 10 may be a growth substrate for the semiconductor device 1, or a carrier used to replace the growth substrate to support the semiconductor device 1. The material of the substrate 10 includes but is not limited to germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), sapphire (Sapphire), silicon carbide (SiC), silicon (Si), lithium aluminate (LiAlO 2 ), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (AlN), metal, glass, thermal release tape, UV release tape, chemical release tape, heat-resistant tape, blue tape, or tape with a dynamic release layer (DRL).

[0052] The material of the electrode includes a metal, such as gold (Au), silver (Ag), copper (Cu), chromium (Cr), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), or an alloy of the foregoing materials, or a stacked combination of the foregoing materials. The material of the conductive bump may include a metal with a lower melting point or an alloy with a lower liquid melting point (Liquidus Melting Point), for example, the melting point or liquid temperature is lower than 210°C, or for example, the material of the conductive bump includes bismuth (Bi), tin (Sn), indium (In), or an alloy thereof. In one embodiment, the melting point of the metal or the liquid melting point of the alloy is lower than 170°C. The material of the alloy may be a tin-indium alloy or a tin-bismuth alloy.

[0053] The maximum side length of the semiconductor element 1 is not greater than 100 μm, or not greater than 50 μm. For example, the side length of the semiconductor element 1 is about 40 μm and the width is about 20 μm. The first conductive bump 2a and the second conductive bump 2b have opposite polarities (positive and negative), and the minimum horizontal distance D between the two bumps 2a and 2b is less than 40 μm. For example, the maximum side length of the semiconductor element 1 is about 40 μm, and D is about 15 μm. The first conductive bump 2a and the second conductive bump 2b completely cover the electrode (such as Figure 1B The first electrode 3a and the second electrode 3b in the embodiment of the present invention respectively have an outwardly convex arc shape and a first top portion 21a and a second top portion 21b. Figure 1A The first top portion 21a and the second top portion 21b are approximately located at the geometric center of the first conductive bump 2a and the second conductive bump 2b and / or the first electrode 3a and the second electrode 3b.

[0054] In one embodiment, the semiconductor element 1 is a light emitting diode as an example. The semiconductor element 1 (light emitting diode) is placed on a substrate 10 and has a semiconductor stack 14, a protective layer 15, a first electrode 3a, a second electrode 3b, a first conductive bump 2a, a second conductive bump 2b, and a lower surface 17. The outermost edge 19 of the semiconductor stack 14 is an inclined surface, and the inner angle θ between the outermost edge 19 and the horizontal extension line H of the lower surface 17 is greater than 70 degrees but less than 85 degrees. The semiconductor stack 14 includes a first-type semiconductor layer 11, an active layer 12, and a second-type semiconductor layer 13. The first-type semiconductor layer 11 and the second-type semiconductor layer 13 can provide electrons and holes, respectively, so that the electrons and holes are recombined in the active layer 12 to emit light. In another embodiment, the inner angle between the outermost edge 19 of the semiconductor stack 14 and the horizontal extension line H of the lower surface 17 is equal to or close to 90 degrees (not shown). The inner angle can be changed by performing different types of etching processes on the outermost edge 18 of the semiconductor stack 14 or adjusting parameters of the etching process.

[0055] In one embodiment, the semiconductor device 1 is a light emitting diode, and the first type semiconductor layer 11, the active layer 12, and the second type semiconductor layer 13 may include III-V semiconductor materials, such as Al x In y Ga (1-x-y) N or Al x In y Ga (1-x-y)P, where 0≤x, y≤1; (x+y)≤1. Depending on the material of the active layer 12, the semiconductor element 1 (light emitting diode) can emit a red light with a peak value between 610nm and 650nm, a green light with a peak value between 530nm and 570nm, a cyan light with a peak value between 500nm and 485nm, a blue light with a peak value between 450nm and 490nm, a violet light with a peak value between 400nm and 450nm, or an ultraviolet light with a peak value between 280nm and 400nm. The maximum thickness of the semiconductor stack 14 is approximately equal to or less than 10μm. In one embodiment, the lower surface 17 of the first-type semiconductor layer 11 contacts the substrate 10 and is a rough surface with regular or irregular textures, but the portion where the substrate 10 is not in contact with the lower surface 17 is a flat surface. In another embodiment, the lower surface 17 of the first-type semiconductor layer 11 is a substantially flat surface under macroscopic observation (not shown). In another embodiment, the substrate 10 is a growth substrate for epitaxially growing the semiconductor stack 14, and the entire upper surface of the substrate 10 facing the semiconductor stack 14 is a rough surface with regular or irregular texture (not shown), for example, the substrate 10 is a patterned sapphire substrate (Patterned Sapphire Substrate; PSS).

[0056] refer to Figure 1B , the semiconductor element 1 is placed on the substrate 10 and has a semiconductor stack 14, a protective layer 15, a first electrode 3a, a second electrode 3b, a first conductive bump 2a, and a second conductive bump 2b. The semiconductor stack 14 has a first opening 5a for exposing a portion of the first-type semiconductor layer 11 covered by the active layer 12 and the second-type semiconductor layer 13, and the first opening 5a has a first inner sidewall 7a. In addition, the semiconductor stack 14 also has a second opening 5b for exposing a portion of the second-type semiconductor layer 13, and the second opening 5b has a second inner sidewall 7b. The protective layer 15 covers a portion of the upper surface of the second-type semiconductor layer 13, the sidewalls of the first-type semiconductor layer 11, the sidewalls of the active layer 12, and the sidewalls of the second-type semiconductor layer 13, and has an outermost upper surface 151. The lower end of the protective layer 15 can be in direct contact with the substrate 10 (such as Figure 1B The first electrode 3a is partially located in the first opening 5a and electrically connected to the exposed first-type semiconductor layer 11, and another portion is formed on the protective layer 15 and covers the portion of the protective layer 15 around the first opening 5a. The second electrode 3b is partially located in the second opening 5b and electrically connected to the exposed second-type semiconductor layer 13, and another portion is located on the portion of the protective layer 15 around the second opening 5b.

[0057] The protective layer 15 may be a single layer or a multi-layer structure and is electrically insulating. The material of the single layer structure may include oxide, nitride, or polymer. The oxide may include aluminum oxide (Al 2 O 3 ), silicon dioxide (SiO 2 ), titanium dioxide (TiO 2 ), Tantalum Pentoxide 2 O 5 ) or aluminum oxide (AlO x The nitride may include aluminum nitride (AlN), silicon nitride (SiN x The polymer may include polyimide or benzocyclobutane (BCB). The material of the multilayer structure may include aluminum oxide (Al 2 O 3 ), silicon dioxide (SiO 2 ), titanium dioxide (TiO 2 ), niobium pentoxide (Nb 2 O 5 ), Silicon Nitride (SiN x ), or a combination of the above materials. The multilayer structure can also be a Distributed Bragg Reflector (DBR).

[0058] refer to Figure 1B , the first conductive bump 2a is formed on the first electrode 3a and filled in the first opening 5a, and the outermost surface 22a of the first conductive bump 2a is a smooth and convex arc shape in a macroscopic view. The first conductive bump 2a has a first top 21a, which is the area farthest from the first conductive bump 2a to the substrate 10. The second conductive bump 2b is formed on the second electrode 3b and filled in the second opening 5b, and the outermost surface 22b of the second conductive bump 2b is a smooth and convex arc shape in a macroscopic view. The second conductive bump 2b has a second top 21b, which is the area farthest from the second conductive bump 2b to the substrate 10.

[0059] In practice, the bottom surfaces of the first conductive bump 2a and the second conductive bump 2b are usually conformally formed on the first electrode 3a and the second electrode 3b, respectively. If the first conductive bump 2a and the second conductive bump 2b are simultaneously manufactured in the same step, the first electrode 3a and the second electrode 3b are usually at different elevations, resulting in the first top 21a and the second top 21b often not being at the same elevation. In order to solve the above problem, the first conductive bump 2a and the second conductive bump 2b can be formed in different steps with appropriate material amounts and manufacturing process conditions, so that the top 21a of the first conductive bump 2a and the top 21b of the second conductive bump 2b are close to the same elevation, for example, the ratio of the height H1 to the height H2 is between 0.8 and 1.2.

[0060] Figure 2A is a three-dimensional schematic diagram of a semiconductor device 2 according to another embodiment of the present invention. Figure 2B for Figure 2A In order to stably fix the semiconductor element 2 on the conductive circuit of the circuit substrate or the display panel through the conductive bumps, in one embodiment, as shown in FIG. Figure 2B As shown, in the semiconductor element 2, the outermost surface 22a of the first conductive bump 2a is a smooth and convex arc shape in a macroscopic view, the outermost surface 22b of the second conductive bump 2b is a smooth and convex arc shape in a macroscopic view, and the first top 21a and the second top 21b of the second conductive bump 2b are substantially located at the same horizontal height, and the first inner sidewall 7a in the first opening 5a has a first slope, and the second inner sidewall 7b in the second opening 5b has a second slope, and the first slope is different from the second slope. In one embodiment, the first slope is greater than the second slope. In other words, the first inner sidewall 7a of the first opening 5a and the horizontal extension line H of the bottom surface have a first angle θ1, and the second inner sidewall 7b of the second opening 5b and the horizontal extension line H of the bottom surface have a second angle θ2, and θ1 is greater than θ2. The greater the slope of the inner sidewall, the smaller the volume of the opening. Therefore, when the same volume of material is filled to form a conductive bump, the greater the slope of the inner sidewall of the opening, the higher the conductive bump, provided that the material does not collapse. Thus, the height of the conductive bump can be adjusted so that the first top 21a of the first conductive bump 2a and the second top 21b of the second conductive bump 2b are substantially at the same horizontal height, that is, the height H1 is substantially equal to the height H2. The manufacturing process of the conductive bump will be described in the following paragraphs.

[0061] Figure 3A and Figure 3BThey are respectively cross-sectional views of a semiconductor element 3 according to another embodiment of the present invention. In the semiconductor element 3, the outermost surface 22a of the first conductive bump 2a is a smooth and convex arc shape in a macroscopic view, and the outermost surface 22b of the second conductive bump 2b is a smooth and convex arc shape in a macroscopic view. In order to allow the semiconductor element 3 to be stably fixed on the conductive circuit of the circuit substrate or the display panel through the conductive bumps, the first conductive bump 2a and the second conductive bump 2b are at the same horizontal height (the ratio of the height H1 to the height H2 is between 0.9 and 1.1), for example, on the outermost surface 151 of the protective layer 15, and the projection areas are similar in size. Figure 3A In view, the first conductive bump 2a has a first (maximum) horizontal width W1, and the second conductive bump 2b has a second (maximum) horizontal width W2. In one embodiment, the first (maximum) horizontal width W1 is equal to or similar to the second (maximum) horizontal width W2, for example, the ratio of the first (maximum) horizontal width W1 to the second (maximum) horizontal width W2 is between 0.8 and 1.2.

[0062] like Figure 3A As shown, in one embodiment, the structure directly below the first conductive bump 2a, for example, the upper surface of the first electrode 3a (the place in direct contact with the first conductive bump 2a) is a rough surface. In one embodiment, in order to form a rough surface on the upper surface of the first electrode 3a (the place in direct contact with the conductive bump 2a), the upper surface of the first electrode 3a can be roughened by an etching process. In another embodiment, the upper surface of the portion of the first-type semiconductor layer 11 located below the first electrode 3a and in direct contact with it and the outermost upper surface 151 of the protective layer 15 can also be selectively formed into a rough upper surface by an etching process. That is to say, when the surface of the structure directly below (part of the first-type semiconductor layer 11 and the protective layer 15) in contact with the first electrode 3a is a rough surface, when the first electrode 3a is formed, a conformal first electrode 3a is formed along the rough surface of the lower structure, so that the first electrode 3a has a rough upper surface. The detailed structure can be seen from Figure 3A See the enlarged view of the partial area R1 in the middle left half for details.

[0063] In the process of making the conductive bump, the raw material of the conductive bump will first be melted into a liquid state, and the liquid has different surface tensions for contact surfaces of different roughness. Therefore, contact surfaces of different roughness will cause different contact angles between the raw material of the conductive bump and the contact surface, thereby changing the curvature radius and / or height (or horizontal height) of the final formed conductive bump. Generally speaking, the greater the roughness of the contact surface, the greater the cohesion of the raw material of the conductive bump, and the smaller the curvature radius of the conductive bump after forming. Accordingly, by fine-tuning the surface roughness of the structure below the raw material of the first conductive bump 2a and the second conductive bump 2b, the final forming height (or horizontal height) of the first conductive bump 2a and the second conductive bump 2b can be controlled to form a first top 21a and a second top 21b with the same horizontal height.

[0064] exist Figure 3A In the embodiment, the contact surface below the first conductive bump 2a (the first outer surface 30a of the first electrode 3a) has a greater roughness than the contact surface below the second conductive bump 2b (the second outer surface 30b of the second electrode 3b), so the curvature radius of the first conductive bump 2a is smaller than the curvature radius of the second conductive bump 2b. Figure 3B As shown in the enlarged view of the R2 region, the contact surface below the second conductive bump 2b (the second outer surface 30b of the second electrode 3b) is rougher than the contact surface below the first conductive bump 2a (the first outer surface 30a of the first electrode 3a), so the curvature radius of the first conductive bump 2a is greater than the curvature radius of the second conductive bump 2b. As mentioned above, the surface roughening process can be performed by etching the surface of the semiconductor stack, and then further making the protective layer and the electrode stacked thereon conformally have a rough surface, or only etching and roughening the outer surface of the electrode layer therein, and the present invention is not limited thereto.

[0065] exist Figure 3A and Figure 3B As shown in the enlarged view, the outermost surface 151 of the protective layer 15 exposed around the first electrode 3a or the second electrode 3b can also be rough. With this design, even if the raw material of the conductive bump is melted into liquid and then overflows onto the rough outermost surface 151 of the protective layer 15, the surface tension of the contact surface can be changed by the surface roughness of the outermost surface 151 during the manufacturing process, thereby changing the curvature radius of the conductive bump formed subsequently.

[0066] Figure 4FIG. 4 is a cross-sectional view of a semiconductor element 4 according to another embodiment of the present invention. In the semiconductor element 4, the outermost surface 22a of the first conductive bump 2a is a smooth and convex arc shape in a macroscopic view, and the outermost surface 22b of the second conductive bump 2b is a smooth and convex arc shape in a macroscopic view. In order to allow the semiconductor element 4 to be stably fixed on the conductive circuit of the circuit substrate or the display panel through the conductive bumps, the first conductive bump 2a and the second conductive bump 2b have similar projected areas at the same horizontal height (the ratio of the height H1 to the height H2 is between 0.9 and 1.1). Figure 4 As shown, the first conductive bump 2a has a first (maximum) horizontal width W1, and the second conductive bump 2b has a second (maximum) horizontal width W2. In one embodiment, the first (maximum) horizontal width W1 is equal to or similar to the second (maximum) horizontal width W2, for example, the ratio of the first (maximum) horizontal width W1 to the second (maximum) horizontal width W2 is between 0.8 and 1.2.

[0067] like Figure 4 As shown, in one embodiment, the protective layer 15 has n first openings below the first conductive bump 2a, n=2, which are the first first opening 5a1 and the second first opening 5a2, and the first electrode 3a is conformally disposed in the two first openings 5a1 and 5a2 and electrically connected to the first type semiconductor layer 11; the protective layer 15 has m second openings 5b below the second conductive bump 2b, m=1, and the second electrode 3b is conformally disposed in the second opening 5b and electrically connected to the second type semiconductor layer 13. In the above configuration, the numbers n and m are only examples, and the total volume inside the openings can be controlled by appropriately changing the number of openings below the conductive bump. Therefore, when a conductive bump is made of a material with a similar volume, it can be used to adjust the height of the conductive bump so that the conductive bump formed subsequently has a first top 21a and a second top 21b located at the same horizontal height (the ratio of the height H1 to the height H2 is between 0.9 and 1.1). In addition, the ratio of the first opening to the second opening may be different in the cross-sectional view and the top view, depending on the position of the cross-sectional view and the arrangement pattern of the openings. In one embodiment, ignoring the conductive bumps, in the top view of the semiconductor element 4, the number of n first openings and m second openings may be the same or different. If n and / or m is greater than or equal to a specific number, the overall shape presented by the n first openings and / or the m second openings may be an irregular shape or a regular shape, and the regular shape may be, for example, a circle, a rectangle, a triangle, or other polygons. If n and / or m is greater than or equal to 3, the distance between two adjacent openings may be a fixed value or a variable value.

[0068] Figure 5A to Figure 5D Schematic diagram of the steps of manufacturing a semiconductor device 1 according to an embodiment of the present invention. Figure 5AAs shown, a plurality of semiconductor units 100 are disposed on a substrate 10. The semiconductor unit 100 includes a semiconductor stack 14, a protective layer 15, a first electrode 3a, and a second electrode 3b. The semiconductor unit 100 is disposed on the substrate 10 in a manner that the first electrode 3a and the second electrode 3b are away from the substrate 10. In one embodiment, the semiconductor stack 14 is a light emitting diode and includes a first-type semiconductor layer 11, an active layer 12, and a second-type semiconductor layer 13. The first electrode 3a and the second electrode 3b each have a concave portion corresponding to an opening, and the detailed structural description can refer to the above-mentioned relevant paragraphs. First, a first bonding pad 23a and a second bonding pad 23b are formed on the first electrode 3a and the second electrode 3b respectively by electroplating, chemical plating, or evaporation. The upper surface 24a of the first bonding pad 23a and the upper surface 24b of the second bonding pad 23b are roughly conformal to the upper surfaces of the first electrode 3a and the second electrode 3b, that is, the contours of the two are similar, and have concave portions and / or rough textures. A single mass of glue 83 is formed on the semiconductor unit 100, the first bonding pad 23a, and the second bonding pad 23b. In one embodiment, the glue 83 only includes resin. In another embodiment, the glue 83 may include resin and conductive particles (not shown) having the same composition as the bonding pads 23a and / or 23b. In one embodiment, the glue 83 may be formed by printing, coating, spraying, or dispensing. Among them, the printing method may include aerosol jet printing or ink-jet printing. The material of the resin includes thermosetting plastic and solder flux. The thermosetting plastic may be epoxy, silicone, polymethyl methacrylate, and episulfide. When the glue 83 contains conductive particles, the melting point of the conductive particles is lower than the curing temperature of the resin. In one embodiment, the material of the conductive particles may be gold, silver, copper, or tin. In another embodiment, the material of the conductive particles may be a metal with a low melting point or an alloy with a low liquid melting point. In one embodiment, the melting point or liquefaction temperature of the metal with a low melting point or the alloy with a low liquid melting point is lower than 210° C. In another embodiment, the melting point or liquefaction temperature of the metal with a low melting point or the alloy with a low liquid melting point is lower than 170° C. The material of the alloy with a low liquid melting point may be a tin alloy, such as a tin-indium alloy or a tin-bismuth alloy.

[0069] like Figure 5BAs shown, a laser energy L is used to irradiate the positions of the first bonding pad 23a and the second bonding pad 23b to heat the adhesive 83, the first bonding pad 23a and the second bonding pad 23b. The laser energy L may include an ultraviolet (UV) laser beam, a visible light laser beam, or an infrared (IR) laser beam. In one embodiment, the laser energy L is an infrared laser beam having a wavelength in the range of 750 to 2,000 nm. Figure 5C It is shown that during the heating process, the first bonding pad 23a and the second bonding pad 23b are melted in the glue 83 by the heat, and gather on the first electrode 3a and the second electrode 3b (if the resin contains conductive particles, the conductive particles will also partially or completely move toward the first electrode 3a and the second electrode 3b after being heated) or partially overflow to the upper surface of the protective layer around the electrodes (not shown), forming a first conductive bump 2a and a second conductive bump 2b with an outward convex arc shape. The glue 83 moves to the first conductive bump 2a, the second conductive bump 2b, and the area 18 between the first electrode 3a and the second electrode 3b. After the heating is completed, the first conductive bump 2a and the second conductive bump 2b will solidify, and the glue 83 (or resin) covering them will also heat up but has not yet completely solidified, and is in a liquid or semi-liquid state. Then, as Figure 5D It is shown that a cleaning step is performed to remove the uncured glue 83 (or resin) so that the first conductive bump 2a and the second conductive bump 2b are exposed to the external environment. The cleaning step can be performed using a solvent, and the solvent can include N-Methylpyrrolidinone (NMP), Methyl Ethyl Ketone (MEK), Acetone (ACE), or Isopropyl Alcohol (ACE).

[0070] The above-mentioned manufacturing process is only one manufacturing process, and the present invention is not limited thereto. The manufacturing process of heating and reshaping the bonding pad can be applied to form conductive bumps 2a and 2b with a convex shape on the semiconductor elements 2, 3, and 4 in any of the aforementioned embodiments; after adjusting the structure of the semiconductor element through the aforementioned implementation method, the conductive bumps 2a and 2b on the final semiconductor elements 2, 3, and 4 can have a first top 21a and a second top 21b that are substantially located at the same horizontal height. Such a structure can ensure that the semiconductor element can be stably bonded when it is subsequently fixed to the conductive circuit of the circuit substrate / display panel through conductive bump welding, thereby increasing the reliability of the overall structure.

[0071] Although the invention of the present invention is described above by specific embodiments, the inventive principle of the present invention can also be applied to other embodiments. In addition, in order not to obscure the spirit of the present invention, certain details will be omitted, and these omitted details belong to the knowledge scope of ordinary technicians in the relevant technical field.

Claims

1. A semiconductor device comprising: A semiconductor stack, comprising a first semiconductor layer and a second semiconductor layer; The protective layer is located on the semiconductor stack and has n first openings and m second openings; A first electrode, located in the n first openings, has a first outer surface and is electrically connected to the first semiconductor layer; A second electrode, located in the m second openings, having a second outer surface and electrically connected to the second semiconductor layer; A first conductive bump, located on the first electrode, having a first convex top; as well as A second conductive bump, located on the second electrode, having a second convex top; Wherein, in the cross-sectional view, the contact surface between the first conductive bump and the first electrode has a first horizontal width, the contact surface between the second conductive bump and the second electrode has a second horizontal width, and the ratio of the first horizontal width to the second horizontal width is between 0.8 and 1.2; The first top portion and the second top portion have substantially the same horizontal height.

2. The semiconductor device according to claim 1, wherein In the cross-sectional view, the first opening has a first inner side wall, the second opening has a second inner side wall, and the extension direction of the first inner side wall and the extension direction of the second inner side wall respectively have different first angles and second angles with the horizontal line.

3. The semiconductor device according to claim 2, wherein: The first angle is greater than the second angle.

4. The semiconductor device according to claim 1, wherein In the cross-sectional view, the first conductive bump contacts the first outer surface, the second conductive bump contacts the second outer surface, and the first outer surface and the second outer surface have different roughnesses.

5. The semiconductor device according to claim 4, wherein: The roughness of the first outer surface is greater than the roughness of the second outer surface.

6. The semiconductor device according to claim 4, wherein: The protection layer covers the first electrode and the second electrode, and n=m=1.

7. The semiconductor device according to claim 1, wherein: In the cross-sectional view, the first conductive bump contacts a first electrode outer surface of the first electrode, the second conductive bump contacts a second electrode outer surface of the second electrode, and the first electrode outer surface and the second electrode outer surface have different roughnesses.

8. The semiconductor device according to claim 7, wherein: The roughness of the outer surface of the first electrode is greater than the roughness of the outer surface of the second electrode.

9. The semiconductor device according to claim 7, wherein: The first electrode and the second electrode cover the protection layer, and n=m=1.

10. The semiconductor device according to claim 1, wherein In this cross-sectional view, n is not equal to m.

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