Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device and a method for manufacturing a semiconductor device are provided. The semiconductor device includes a substrate; a lower portion of the first conductive pattern disposed over the substrate and extending in a second direction; a stack structure disposed over a lower portion of the first conductive pattern and having a columnar shape, the stack structure including an upper portion of the first conductive pattern, an oxide semiconductor channel, and a second conductive pattern; and a word line extending in a first direction intersecting the second direction and facing at least a portion of a sidewall of the oxide semiconductor channel, the word line and the oxide semiconductor channel having a gate insulating layer therebetween, in which the first conductive pattern includes a first conductive metal oxide, and a lower portion of the first conductive pattern corresponds to the bit line, and an upper portion of the first conductive pattern corresponds to the drain electrode.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2023-0115279, filed on August 31, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to semiconductor technology, and in particular, to a semiconductor device including a transistor and a method for manufacturing the semiconductor device. Background Art

[0004] With the development of the electronics industry, electronic products are becoming smaller, with higher performance and higher integration, and at the same time, the operating speed of electronic products is required to be improved.

[0005] In order to meet these demands, it is necessary to develop a technology capable of maintaining and / or improving the characteristics of unit elements (such as transistors) constituting electronic products while reducing the size thereof. Summary of the invention

[0006] In an embodiment of the present disclosure, a semiconductor device may include: a substrate; a lower portion of a first conductive pattern disposed on the substrate and extending in a second direction; a stacking structure disposed on the lower portion of the first conductive pattern and having a columnar shape, the stacking structure including an upper portion of the first conductive pattern, an oxide semiconductor channel, and a second conductive pattern; and a word line, the word line extending in a first direction intersecting the second direction and facing at least a portion of a side wall of the oxide semiconductor channel, with a gate insulating layer between the word line and the oxide semiconductor channel, wherein the first conductive pattern includes a first conductive metal oxide, and the lower portion of the first conductive pattern corresponds to a bit line, and the upper portion of the first conductive pattern corresponds to a drain electrode.

[0007] In another embodiment of the present disclosure, a semiconductor device may include: a substrate; a bit line disposed on the substrate and extending in a second direction; a stacked structure disposed on the bit line and having a columnar shape, the stacked structure including a drain electrode, an oxide semiconductor channel, and a conductive pattern; and a word line, the word line extending in a first direction intersecting the second direction and facing at least a portion of a side wall of the oxide semiconductor channel, with a gate insulating layer between the word line and the oxide semiconductor channel, wherein the conductive pattern includes a conductive metal oxide, and a lower portion of the conductive pattern corresponds to a source electrode, and an upper portion of the conductive pattern corresponds to a lower electrode of the capacitor.

[0008] In another embodiment of the present disclosure, a method for manufacturing a semiconductor device may include: forming a first conductive layer, an oxide semiconductor layer, and a second conductive layer on a substrate; patterning an upper portion of the first conductive layer, the oxide semiconductor layer, and the second conductive layer to form a stacked structure, the stacked structure including an upper first conductive pattern, an oxide semiconductor channel, and a second conductive pattern, and having a columnar shape; patterning a lower portion of the first conductive layer to form a lower first conductive pattern having a linear shape extending in a second direction; and forming a word line, the word line extending in a first direction intersecting the second direction and facing at least a portion of a side wall of the oxide semiconductor channel, with a gate insulating layer between the word line and the oxide semiconductor channel, wherein the first conductive layer includes a first conductive metal oxide, and the lower first conductive pattern corresponds to a bit line, and the upper first conductive pattern corresponds to a drain electrode.

[0009] In another embodiment, a method for manufacturing a semiconductor device may include: forming a bit line extending in a second direction over a substrate; forming a stacked structure over the bit line, the stacked structure including a drain electrode, an oxide semiconductor channel and a conductive pattern, and having a columnar shape, the conductive pattern including a conductive metal oxide; forming a word line, the word line extending in a first direction intersecting the second direction and facing at least a portion of a side wall of the oxide semiconductor channel, with a gate insulating layer between the word line and the oxide semiconductor channel; forming an insulating pattern, the insulating pattern covering the word line and causing an upper portion of the conductive pattern to protrude; and forming an upper electrode of a capacitor, the upper electrode facing an upper portion of the conductive pattern, with a gate insulating layer or a capacitor insulating layer between the upper electrode and the upper portion of the conductive pattern, wherein the upper portion of the conductive pattern corresponds to a lower electrode of the capacitor, and the lower portion of the conductive pattern except the upper portion of the conductive pattern corresponds to a source electrode.

[0010] In another embodiment of the present disclosure, a semiconductor device may include: a substrate; a first conductive pattern arranged on the substrate and extending in a second direction, the first conductive pattern including a linear-shaped bottom covering the top surface of the substrate and a plurality of spaced-apart columnar-shaped tops rising above the bottom in a vertical direction; a plurality of stacked structures, each stacked structure being arranged on a corresponding columnar-shaped top among the columnar-shaped tops of the first conductive pattern and having a columnar shape, each stacked structure including sequentially stacked oxide semiconductor channels, and a second conductive pattern; and a word line, the word line extending in a first direction intersecting the second direction and facing at least a portion of a side wall of the oxide semiconductor channel, with a gate insulating layer between the word line and the oxide semiconductor channel.

[0011] These and other features and advantages of the present invention will be better understood through the detailed description of specific example embodiments taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figures 1A to 11 is a simplified schematic diagram showing a semiconductor device and a method for manufacturing the semiconductor device according to an embodiment of the present disclosure;

[0013] Fig.12 and Fig.13 is a simplified cross-sectional view schematic diagram illustrating a semiconductor device and a method for manufacturing the semiconductor device according to another embodiment of the present disclosure;

[0014] Fig.14 and Fig.15 is a simplified cross-sectional view schematic diagram illustrating a semiconductor device and a method for manufacturing the semiconductor device according to another embodiment of the present disclosure; and

[0015] Fig.16 is a simplified cross-sectional view schematic diagram illustrating a semiconductor device and a method for manufacturing the semiconductor device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0017] The drawings are not necessarily drawn to scale. In some cases, the proportions of at least some structures in the drawings may have been exaggerated to clearly illustrate certain features of the described embodiments. When presenting a specific example in a drawing or description having two or more layers in a multilayer structure, the relative positioning relationship of such layers as shown or the order of arranging the layers reflects the specific implementation of the described or shown examples, and different relative positioning relationships or orders of arranging the layers are possible. In addition, the described or shown examples of multilayer structures may not reflect all layers present in the specific multilayer structure (for example, one or more additional layers may exist between the two layers shown). As a specific example, when the first layer in the multilayer structure described or shown is referred to as being "on" or "above" the second layer, or being "on" or "above" the substrate, the first layer may be directly formed on the second layer or the substrate, but may also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or the substrate.

[0018] Figures 1A to 11 is a simplified schematic diagram illustrating a semiconductor device and a method for manufacturing the semiconductor device according to an embodiment of the present disclosure. Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5 , Figure 6 , Figure 7 , Fig. 8A , Fig. 9A , Fig.10 and Fig.11is a simplified cross-sectional schematic diagram, and Figure 1B , Figure 2B , Figure 3B , Figure 4B , Figure 8B and Fig. 9B are respectively Figure 1A , Figure 2A , Figure 3A , Figure 4A , Fig. 8A and Fig. 9A The corresponding simplified floor plan diagram. Figure 1B , Figure 2B , Figure 3B , Figure 4B , Figure 8B and Fig. 9B The cross sections of the line A-A' in can correspond to Figure 1A , Figure 2A , Figure 3A , Figure 4A , Fig. 8A and Fig. 9A . Figure 4C It is shown Figure 4A and Figure 4B A simplified perspective diagram of a portion of a .

[0019] First, a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is described.

[0020] refer to Figure 1A and Figure 1B , a first conductive layer 110, an oxide semiconductor layer 120, a second conductive layer 130, a first hard mask layer 140, and a first mask pattern 145 may be formed on the substrate 100. The first conductive layer 110, the oxide semiconductor layer 120, the second conductive layer 130, the first hard mask layer 140, and the first mask pattern 145 may be sequentially formed on the substrate 100 in the above order. The first conductive layer 110, the oxide semiconductor layer 120, the second conductive layer 130, and the first hard mask layer 140 may have a plate shape to cover the substrate 100. In Figure 1B In the plan view of FIG. 1 , only the first mask pattern 145 is shown. Figure 1B In the plan view schematic diagrams and in other simplified plan view schematic diagrams to be described later, unpatterned components may be omitted for ease of description.

[0021] The substrate 100 may include a semiconductor material such as silicon, and may include a required substructure (not shown). As an example, the substrate 100 may include a peripheral circuit, an insulating layer covering the peripheral circuit, and the like.

[0022] The first conductive layer 110 can be used as a bit line and a drain electrode by a patterning process described later, and can include at least one of various conductive materials. In particular, in the present embodiment, the first conductive layer 110 may include a conductive metal oxide such as indium tin oxide (ITO), indium oxide (In2O3), or a metal oxide semiconductor. A metal oxide semiconductor may refer to a material having a higher metal content than a typical oxide semiconductor and a lower resistance than a typical oxide semiconductor and thus having conductivity. For example, a metal oxide semiconductor may include indium-rich indium gallium zinc oxide (IGZO). Indium-rich IGZO may refer to a material having a higher indium content than a gallium content and a higher zinc content, for example, a material having an indium content of 40% or more.

[0023] The oxide semiconductor layer 120 may be a portion used as a channel of a transistor by a patterning process described later. The oxide semiconductor layer 120 may include at least one of various oxide semiconductors such as indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), zinc tin oxide (ZTO), indium gallium oxide (IGO), InO2, etc.

[0024] The second conductive layer 130 can be used as a lower electrode and a source electrode of the capacitor by a patterning process described later, and can include at least one of various conductive materials. In the present embodiment, the second conductive layer 130 can include a conductive metal oxide such as ITO, In2O3 or a metal oxide semiconductor. The second conductive layer 130 can be formed of the same material as the first conductive layer 110 or a different material.

[0025] The first hard mask layer 140 may be a portion used as an etch stopper when etching a portion of the first conductive layer 110 , the oxide semiconductor layer 120 , and the second conductive layer 130 , and may include at least one of various materials such as silicon oxide, silicon nitride, polysilicon, carbon, or a combination thereof.

[0026] Each of the first conductive layer 110 , the oxide semiconductor layer 120 , the second conductive layer 130 , and the first hard mask layer 140 may be formed using at least one of various deposition methods.

[0027] The first mask pattern 145 may include a photoresist and may have an island shape. In the present embodiment, the first mask pattern 145 is shown in a plan view as having a circular shape. However, the present disclosure is not limited thereto, and the first mask pattern 145 may have at least one of various shapes in a plan view, such as an elliptical shape, a rectangular shape, or a square shape. A plurality of first mask patterns 145 may be arranged in a matrix form in a spaced relationship from each other along the first direction and the second direction. For reference, the first direction and the second direction may be substantially parallel to a surface of the substrate 100, such as an upper surface, and may intersect with each other. The first direction and the second direction may be orthogonal to each other.

[0028] refer to Figure 2A and Figure 2B , the first hard mask layer 140, the second conductive layer 130, the oxide semiconductor layer 120, and a portion of the first conductive layer 110 may be etched using the first mask pattern 145 as an etch barrier to form a first hard mask pattern 142, a second conductive pattern 132, an oxide semiconductor pattern 122, and an initial first conductive pattern 112. During this etching process, the first mask pattern 145 may be removed. Alternatively, the first mask pattern 145 may be removed by a separate removal process, such as an oxygen stripping process.

[0029] The initial first conductive pattern 112 may include an etched upper portion 112B and an unetched lower portion 112A. The stacked structure of the upper portion 112B of the initial first conductive pattern 112, the oxide semiconductor pattern 122, the second conductive pattern 132, and the first hard mask pattern 142 may have a columnar shape, and a plurality of stacked structures may be arranged in a matrix along the first direction and the second direction. In the present embodiment, the columnar shape stacked structure is shown as having a circular shape in a plan view. However, the present disclosure is not limited thereto, and the stacked structure may have at least one of various shapes in a plan view, such as an elliptical shape, a rectangular shape, or a square shape. The lower portion 112A of the initial first conductive pattern 112 may maintain a flat plate shape. The upper portion 112B of the initial first conductive pattern 112 may correspond to a drain electrode, the oxide semiconductor pattern 122 may correspond to a channel of a transistor, the lower portion of the second conductive pattern 132 may correspond to a source electrode, and the upper portion of the second conductive pattern 132 may correspond to a lower electrode of a capacitor. Since the lower and upper portions of the second conductive pattern 132 are defined by subsequent processes, they will be described in more detail in corresponding parts.

[0030] refer to Figure 3A and Figure 3B, a first insulating layer 150 may be formed to fill a space between the stacked structure of the upper portion 112B of the preliminary first conductive pattern 112 , the oxide semiconductor pattern 122 , the second conductive pattern 132 , and the first hard mask pattern 142 .

[0031] The first insulating layer 150 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The first insulating layer 150 may be formed by depositing a covering Figure 2A and Figure 2B An insulating material as a result of the process is formed, and a planarization process such as a CMP (chemical mechanical polishing) process is performed, thereby exposing a top surface of the first hard mask pattern 142.

[0032] Subsequently, a second mask pattern 155 may be formed over the first hard mask pattern 142 and the first insulating layer 150. Although not shown, an additional hard mask material may be further formed over the first hard mask pattern 142 and the first insulating layer 150 before the second mask pattern 155 is formed.

[0033] The second mask pattern 155 may include a photoresist and may have a linear shape extending in the second direction so as to cover the stack structure of the upper portion 112B of the initial first conductive pattern 112, the oxide semiconductor pattern 122, the second conductive pattern 132, and the first hard mask pattern 142 arranged in the second direction. In order to sufficiently cover the stack structure in the first direction, the width of the second mask pattern 155 in the first direction may be greater than the width of the stack structure in the first direction.

[0034] refer to FIG. 4A to FIG. 4C , the first insulating layer 150 and the lower portion 112A of the initial first conductive pattern 112 may be etched using the second mask pattern 155 as an etching barrier to form the initial first insulating pattern 152 and the first conductive pattern 114. During this etching process, the second mask pattern 155 may be removed. Alternatively, the second mask pattern 155 may be removed by a separate removal process, such as an oxygen stripping process. During this etching process, a portion of the substrate 100 may be recessed due to over-etching.

[0035] The upper portion 114B of the first conductive pattern 114 may be maintained in the same columnar shape as the upper portion 112B of the initial first conductive pattern 112 described above. On the other hand, since the lower portion 114A of the first conductive pattern 114 is formed using the second mask pattern 155, it may have a linear shape extending in the second direction. The lower portion 114A of the first conductive pattern 114 may correspond to a bit line. The width of the lower portion 114A of the first conductive pattern 114 in the first direction may be greater than the width of the stacked structure of the upper portion 114B of the first conductive pattern 114, the oxide semiconductor pattern 122, the second conductive pattern 132, and the first hard mask pattern 142 in the first direction.

[0036] The initial first insulating pattern 152 can cover the sidewalls of the stacked structure of the upper portion 114B of the first conductive pattern 114 , the oxide semiconductor pattern 122 , the second conductive pattern 132 , and the first hard mask pattern 142 , and can be disposed above the lower portion 114A of the first conductive pattern 114 to expose the sidewalls of the lower portion 114A of the first conductive pattern 114 .

[0037] refer to Figure 5 , the second insulating layer 160 may be formed to fill the spaces between the lower portions 114A of the first conductive patterns 114 and between the preliminary first insulating patterns 152 .

[0038] The second insulating layer 160 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The second insulating layer 160 may be formed by depositing a covering Figure 4A and Figure 4B An insulating material as a result of the process is formed, and a planarization process such as a CMP process is performed, thereby exposing a top surface of the second conductive pattern 132.

[0039] refer to Figure 6 , the preliminary first insulating pattern 152 and the second insulating layer 160 may be recessed to expose the sidewalls of the oxide semiconductor pattern 122 , thereby forming the first insulating pattern 154 and the second insulating pattern 162 .

[0040] The recess process may be performed by a dry or wet etching method using a gas or chemical that can selectively remove only the insulating material. When the initial first insulating pattern 152 and the second insulating layer 160 are formed of the same material, they may be recessed simultaneously using the same etching gas or chemical. The upper surfaces of the first insulating pattern 154 and the second insulating pattern 162 formed by the recess process may be located at substantially the same height from the surface of the substrate 100.

[0041] In the present embodiment, a recess process may be performed to expose the entire sidewall of the oxide semiconductor pattern 122. That is, the top surface of the first insulating pattern 154 and the top surface of the second insulating pattern 162 may be positioned at substantially the same height as the bottom surface of the oxide semiconductor pattern 122. However, the present disclosure is not limited thereto, and a recess process may be performed to expose a portion of the sidewall of the oxide semiconductor pattern 122. In this case, the top surface of the first insulating pattern 154 and the top surface of the second insulating pattern 162 may be located at a height between the bottom surface and the top surface of the oxide semiconductor pattern 122. In the recess process, the second conductive pattern 132 extending above the oxide semiconductor pattern 122 may be exposed.

[0042] refer to Figure 7 , the gate insulating layer 170 may be Figure 6 Thus, the gate insulating layer 170 may be formed to cover the sidewalls and top surfaces of the stacked structure of the oxide semiconductor pattern 122 and the second conductive pattern 132 , and the upper surfaces of the first insulating pattern 154 and the second insulating pattern 162 .

[0043] The gate insulating layer 170 may be formed by at least one of various deposition methods, and may include at least one of various insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant material having a higher dielectric constant than silicon oxide.

[0044] Subsequently, a third conductive layer 180 may be formed over the gate insulating layer 170 to a thickness filling a space between the oxide semiconductor patterns 122 .

[0045] In the present embodiment, the third conductive layer 180 may be formed to a thickness that completely fills the space between the oxide semiconductor patterns 122. That is, the height of the top surface of the third conductive layer 180 may be substantially the same as the height of the top surface of the oxide semiconductor pattern 122. However, the present disclosure is not limited thereto, and the height of the top surface of the third conductive layer 180 may be changed in various ways as long as it is less than or equal to the height of the top surface of the oxide semiconductor pattern 122. For example, the top surface of the third conductive layer 180 may be located at a height between the top surface and the bottom surface of the oxide semiconductor pattern 122, and accordingly, the third conductive layer 180 may partially fill the space between the oxide semiconductor patterns 122.

[0046] The third conductive layer 180 may include at least one of various conductive materials, for example, a metal such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), titanium (Ti), ruthenium (Ru), or molybdenum (Mo); a metal compound such as a metal nitride, for example titanium nitride (TiN); or a metal alloy. The third conductive layer 180 may be formed by depositing a conductive material having a thickness covering a process result in which the gate insulating layer 170 is formed and recessing the conductive material. The recessing process may be performed by a dry or wet etching method using a gas or chemical capable of selectively removing the conductive material.

[0047] refer to Fig. 8A and Figure 8B , can form coverage Figure 7 A third insulating layer 190 is formed as a result of the process, and then a second hard mask layer 200 and a third mask pattern 205 may be sequentially formed on the third insulating layer 190 .

[0048] The third insulating layer 190 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The third insulating layer 190 may be deposited to cover Figure 7 An insulating material of the process result is formed and a planarization process is performed to have a flat upper surface.

[0049] The second hard mask layer 200 may be a portion used as an etch stopper when etching the third insulating layer 190 and the third conductive layer 180 , and may include at least one of various materials such as silicon oxide, silicon nitride, polysilicon, carbon, or a combination thereof.

[0050] The third mask pattern 205 may include a photoresist and may have a linear shape extending in the first direction to cover the stack structure of the upper portion 114B of the first conductive pattern 114, the oxide semiconductor pattern 122, and the second conductive pattern 132 arranged in the first direction. In order to sufficiently cover the stack structure in the second direction, the width of the third mask pattern 205 in the second direction may be greater than the width of the stack structure in the second direction.

[0051] refer to Fig. 9A and Fig. 9B , the second hard mask layer 200, the third insulating layer 190, and the third conductive layer 180 may be etched using the third mask pattern 205 as an etch barrier to form a second hard mask pattern 202, an initial third insulating pattern 192, and a third conductive pattern 182. During this etching process, the third mask pattern 205 may be removed. Alternatively, the third mask pattern 205 may be removed by a separate removal process, such as an oxygen stripping process.

[0052] The third conductive pattern 182 may have a linear shape extending in the first direction. The third conductive pattern 182 may correspond to a gate line and / or a word line. The width of the third conductive pattern 182 in the second direction may be greater than the width of the stacked structure of the upper portion 114B of the first conductive pattern 114, the oxide semiconductor pattern 122, and the second conductive pattern 132 in the second direction.

[0053] The initial third insulating pattern 192 and the second hard mask pattern 202 may cover the gate insulating layer 170 protruding above the third conductive pattern 182, and may have a linear shape extending in the first direction in a plan view. Although not shown, in the second direction, the linear shape space may be located between the initial third insulating pattern 192 and the second hard mask pattern 202. After the etching process, an additional insulating material may be formed to fill the space.

[0054] refer to Fig.10 , the second hard mask pattern 202 may be removed, and then the initial third insulating pattern 192 and the gate insulating layer 170 may be recessed to expose a portion of the top surface and sidewalls of the second conductive pattern 132 , thereby forming a third insulating pattern 194 and a gate insulating pattern 172 .

[0055] The portion of the second conductive pattern 132 protruding above the third insulating pattern 194 and the gate insulating pattern 172 will be referred to as an upper portion UP of the second conductive pattern 132, and the remaining portion of the second conductive pattern 132 will be referred to as a lower portion LP of the second conductive pattern 132. As described above, the lower portion LP of the second conductive pattern 132 may correspond to a source electrode, and the upper portion UP of the second conductive pattern 132 may correspond to a lower electrode of the capacitor. The thickness of the upper portion UP of the second conductive pattern 132 may be greater than the thickness of the lower portion LP of the second conductive pattern 132. This may ensure or improve the capacitance of the capacitor by increasing the thickness of the lower electrode of the capacitor.

[0056] The recess process can be performed using a dry or wet etching method that uses a gas or chemical that can selectively remove only the insulating material. When the initial third insulating pattern 192 and the gate insulating layer 170 are formed of the same material, they can be recessed in a single step (simultaneously) using the same etching gas or chemical. Alternatively, when the initial third insulating pattern 192 and the gate insulating layer 170 are formed of different materials, in particular when they are formed of materials with different etching rates, the initial third insulating pattern 192 can be recessed for the first time, and then the gate insulating layer 170 exposed by the initial recess can be recessed for the second time to form the third insulating pattern 194 and the gate insulating pattern 172. The top surface of the third insulating pattern 194 formed by the recess process and the top surface of the gate insulating pattern 172 can be positioned at substantially the same height.

[0057] refer to Fig.11 , the capacitor insulating layer 210 can be Fig.10 Thus, the capacitor insulating layer 210 may be formed to cover the upper portion UP of the second conductive pattern 132, ie, the sidewall and the top surface of the lower electrode of the capacitor.

[0058] The capacitor insulating layer 210 may be formed using at least one of various deposition methods. The capacitor insulating layer 210 may include a high dielectric constant material having a dielectric constant higher than that of silicon oxide. The high dielectric constant material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5) and strontium titanate (SrTiO3) or a combination thereof. The capacitor insulating layer 210 may include a material different from the gate insulating pattern 172, for example, a material having a dielectric constant higher than that of the gate insulating pattern 172. Alternatively, the capacitor insulating layer 210 may include the same material as the gate insulating pattern 172.

[0059] Subsequently, a fourth conductive layer 220 may be formed over the capacitor insulating layer 210 .

[0060] The fourth conductive layer 220 may be used as an upper electrode of a capacitor. The fourth conductive layer 220 may include at least one of various conductive materials, for example, a metal such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), titanium (Ti), ruthenium (Ru), or molybdenum (Mo); a metal compound such as a metal nitride, for example titanium nitride (TiN); or a metal alloy. The fourth conductive layer 220 may be formed to a sufficient thickness so that it extends above the top surface of the second conductive pattern 132 while completely filling the space between the upper portions UP of the second conductive pattern 132. The fourth conductive layer 220 may be formed by depositing a conductive material and performing a planarization process to have a flat upper surface.

[0061] The above-mentioned manufacturing method can be used to manufacture Fig.11 The semiconductor device shown.

[0062] Reference again Fig.11 and Fig. 9B, the semiconductor device of this embodiment may include: a substrate 100; a lower portion 114A of a first conductive pattern 114 disposed on the substrate 100 and extending in the second direction; and a stacked structure of an upper portion 114B of the first conductive pattern 114 disposed on the lower portion 114A of the first conductive pattern 114 and having a columnar shape, an oxide semiconductor pattern 122, and a second conductive pattern 132; a third conductive pattern 182 extending in the first direction while surrounding the sidewall of the oxide semiconductor pattern 122 and having a gate insulating pattern 172 interposed between the oxide semiconductor pattern 122; a third insulating pattern 194 covering the third conductive pattern 182 and filling a space between lower portions LP of the second conductive pattern 132; a capacitor insulating layer 210 formed along the sidewall and top surface of the upper portion UP of the second conductive pattern 132 and protruding from the third insulating pattern 194; and a fourth conductive layer 220 covering the capacitor insulating layer 210.

[0063] The lower portion 114A of the first conductive pattern 114 may be referred to as a bit line. The upper portion 114B of the first conductive pattern 114 may be referred to as a drain electrode, the oxide semiconductor pattern 122 may be referred to as an oxide semiconductor channel, the lower portion LP of the second conductive pattern 132 may be referred to as a source electrode, and the third conductive pattern 182 may be referred to as a word line. An oxide semiconductor channel 122, a drain electrode 114B and a source electrode LP respectively connected to the bottom and top of the one oxide semiconductor channel 122, and a word line 182 surrounding the one oxide semiconductor channel 122 and having a gate insulating pattern 172 between the one oxide semiconductor channel 122 may form a transistor. In the present embodiment, the word line 182 is shown in a plan view as surrounding the entire sidewall of the oxide semiconductor channel 122, but the present disclosure is not limited thereto. In another embodiment, the word line 182 may face a portion of the sidewall of the oxide semiconductor channel 122 in a plan view, with the gate insulating pattern 172 between the word line 182 and the oxide semiconductor channel 122. Since the bit line 114A and the drain electrode 114B are formed as an integral element (a single piece), they may be formed of the same conductive metal oxide and there may be no interface between them. Here, the same conductive metal oxide may mean that the constituent elements are the same, and the contents of the constituent elements may be different. For example, as described later Fig.14 and Fig.15 In an embodiment, the bit line 114A and the drain electrode 114B may include the same conductive metal oxide, but the metal content and / or the oxygen content may be different from each other.

[0064] The upper portion UP of the second conductive pattern 132 may be referred to as a lower electrode of a capacitor, and the fourth conductive layer 220 may be referred to as an upper electrode of a capacitor. One lower electrode UP and the upper electrode 220 surrounding the sidewall and top surface of the one lower electrode UP may form one capacitor together with the capacitor insulating layer 210 interposed therebetween. Since the source electrode LP and the lower electrode UP are formed as a single piece, they may be formed of the same metal oxide and there may be no interface between them.

[0065] Therefore, a 1T-1C semiconductor device including a transistor having a channel extending in a vertical direction and a capacitor connected to the transistor can be realized.

[0066] A detailed description of the components of the semiconductor device of the present embodiment has been described in the above-mentioned manufacturing method, and thus will be omitted.

[0067] According to the semiconductor device and the method for manufacturing the same of the present embodiment, the following advantages can be obtained.

[0068] First, since the oxide semiconductor channel 122 extends in the vertical direction and the bit line 114A is buried under the oxide semiconductor channel 122 , the area of ​​the semiconductor device can be reduced.

[0069] In addition, since an oxide semiconductor material is used as a channel of a transistor, obtained advantages such as reduction in off-state current can be ensured.

[0070] In addition, process simplification is possible. For example, ion implantation processes for forming wells, channels, source / drain regions, etc. can be omitted, the bit line 114A and the drain electrode 114B can be integrally formed, and the source electrode LP and the lower electrode UP of the capacitor can be integrally formed.

[0071] In addition, by using a conductive metal oxide as the drain electrode 114B and the source electrode LP, the contact resistance can be reduced compared to the comparative example using a metal source electrode or a metal drain electrode. This may be because the formation of an insulating metal oxide at the interface between the metal source electrode and the oxide semiconductor channel or between the metal drain electrode and the oxide semiconductor channel is suppressed. In addition, in the comparative example, the metal source electrode or the metal drain electrode may take away oxygen from the oxide semiconductor channel, resulting in an undesirable increase in oxygen vacancies in the oxide semiconductor channel and causing degradation of the channel characteristics. In this embodiment, this problem can be solved.

[0072] Furthermore, since the bit line 114A uses a conductive metal oxide such as a metal oxide semiconductor instead of a highly doped semiconductor material, sheet resistance can be reduced.

[0073] Therefore, the characteristics of the semiconductor device can be improved, and the area of ​​the semiconductor device can be reduced, and the manufacturing process can be simplified.

[0074] In the present embodiment, the first case in which the bit line 114A and the drain electrode 114B are formed of the same conductive metal oxide, and the second case in which the source electrode LP and the lower electrode UP of the capacitor are formed of the same conductive metal oxide have been described. However, one of the first case and the second case may be possible. As an example, the bit line 114A and the drain electrode 114B may be formed as in the present embodiment, and the source electrode and the lower electrode of the capacitor may be formed separately. As another example, the source electrode LP and the lower electrode UP may be formed as in the present embodiment, and the bit line and the drain electrode may be formed separately.

[0075] Fig.12 and Fig.13 1 is a simplified cross-sectional view schematic diagram showing a semiconductor device and a method for manufacturing the semiconductor device according to another embodiment of the present disclosure. The description will focus on the differences from the above-described embodiment.

[0076] refer to Fig.12 , when executing the above Fig. 9A and Fig. 9B After the process, the second hard mask pattern 202 may be removed, and the initial third insulating pattern 192 may be recessed to form the third insulating pattern 194, and the upper portion UP of the second conductive pattern 132 protrudes above the formed third insulating pattern 194. Fig.10 Unlike the process of FIG. 1 , in this process, the gate insulating layer 170 can be maintained without being recessed.

[0077] An upper portion UP of the second conductive pattern 132 protruding above the third insulating pattern 194 may correspond to a lower electrode of the capacitor, and a lower portion LP of the second conductive pattern 132 may correspond to a source electrode.

[0078] The recess process may be performed using a dry or wet etching method using a gas or chemical that can selectively remove only the initial third insulating pattern 192. To this end, the third insulating pattern 192 and the gate insulating layer 170 may be formed of materials having different etching rates. Fig.13As described, the gate insulating layer 170 may also be used as a capacitor insulating layer, so it may include a high dielectric constant material to ensure sufficient capacitance. As an example, the third insulating pattern 192 may include a silicon-containing insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, and the gate insulating layer 170 may include a high dielectric constant material such as hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), strontium titanate (SrTiO3), or a combination thereof.

[0079] refer to Fig.13 , you can Fig.12 A fourth conductive layer 220' is formed on the result of the process.

[0080] The fourth conductive layer 220' may be used as an upper electrode of a capacitor. The gate insulating layer 170 between the fourth conductive layer 220' and the second conductive pattern 132 may be used as a capacitor insulating layer. On the other hand, the gate insulating layer 170 between the third conductive pattern 182 and the oxide semiconductor pattern 122 may perform its own function, that is, the function of a gate insulator.

[0081] According to the present embodiment, since the gate insulating layer 170 also functions as a capacitor insulating layer, a separate process for forming the capacitor insulating layer may not be required. Therefore, process simplification is possible.

[0082] Fig.14 and Fig.15 1 is a simplified cross-sectional view schematic diagram showing a semiconductor device and a method for manufacturing the semiconductor device according to another embodiment of the present disclosure. The description will focus on the differences from the above-described embodiment.

[0083] refer to Fig.14 , a first conductive layer 310, an oxide semiconductor layer 320, a second conductive layer 330, a first hard mask layer 340, and a first mask pattern 345 may be formed on the substrate 300. In addition to the first conductive layer 310, the substrate 300, the oxide semiconductor layer 320, the second conductive layer 330, the first hard mask layer 340, and the first mask pattern 345 may correspond to Figure 1A and 1B The substrate 100 , the oxide semiconductor layer 120 , the second conductive layer 130 , the first hard mask layer 140 and the first mask pattern 145 are shown.

[0084] The first conductive layer 310 may include a conductive metal oxide such as ITO, In2O3 or a metal oxide semiconductor. In the present embodiment, the first conductive layer 310 may include a stacked structure of a lower first conductive layer 310A and an upper first conductive layer 310B. Through a patterning process described later, the lower first conductive layer 310A and the upper first conductive layer 310B may be used as a bit line and a drain electrode, respectively.

[0085] The lower first conductive layer 310A and the upper first conductive layer 310B may include a conductive metal oxide. The content of a specific metal element in the lower first conductive layer 310A may be greater than the content of a specific metal element in the upper first conductive layer 310B. Here, when the lower first conductive layer 310A and the upper first conductive layer 310B include two or more metal elements, the specific metal element may refer to a metal element having the greatest binding force with oxygen in the two or more metal elements. As an example, when the lower first conductive layer 310A and the upper first conductive layer 310B include ITO, the tin (Sn) content of the lower first conductive layer 310A may be greater than the Sn content of the upper first conductive layer 310B. The etching rate of the conductive metal oxide may decrease as the content of the specific metal element in the conductive metal oxide increases. For example, the etching rate of ITO may decrease as the tin content in ITO increases. Therefore, the etching rate of the lower first conductive layer 310A may be less than the etching rate of the upper first conductive layer 310B. Therefore, when etching the upper first conductive layer 310B (to be described later), the etching can be stopped at the lower first conductive layer 310A more easily.

[0086] Alternatively, the lower first conductive layer 310A and the upper first conductive layer 310B may include a conductive metal oxide, and the oxygen content of the lower first conductive layer 310A may be greater than the oxygen content of the upper first conductive layer 310B. As the oxygen content in the conductive metal oxide increases, the oxygen vacancies of the conductive metal oxide may decrease, and thus the porosity and etching rate of the conductive metal oxide may decrease. Oxygen vacancies may refer to the absence of oxygen atoms in the lattice of the metal oxide material. Therefore, the porosity of the lower first conductive layer 310A may be less than the porosity of the upper first conductive layer 310B, and due to the lower porosity, the etching rate of the lower first conductive layer 310A may be less than the etching rate of the upper first conductive layer 310B. Therefore, when etching the upper first conductive layer 310B (to be described later), it may be easier to stop etching at the lower first conductive layer 310A.

[0087] When each of the lower first conductive layer 310A and the upper first conductive layer 310B includes two or more metal elements, a method of controlling the etching rate by adjusting the content of a specific metal element in the lower first conductive layer 310A and the upper first conductive layer 310B may be applied. When each of the lower first conductive layer 310A and the upper first conductive layer 310B includes one metal element or two or more metal elements, a method of controlling the etching rate by adjusting the oxygen content in the lower first conductive layer 310A and the upper first conductive layer 310B may be applied.

[0088] The lower first conductive layer 310A and the upper first conductive layer 310B may be deposited in situ. The deposition may be performed by increasing the content of a specific metal such as tin when depositing the lower first conductive layer 310A and reducing the content of a specific metal such as tin when depositing the upper first conductive layer 310B. As an example, when the lower first conductive layer 310A and the upper first conductive layer 310B are formed by co-sputtering and depositing an ITO material, the Sn content may be increased during the formation of the lower first conductive layer 310A by increasing the power of the SnO2 target compared to the In2O3 target, and the Sn content may be reduced during the formation of the upper first conductive layer 310B by reducing the power of the SnO2 target compared to the In2O3 target. Alternatively, as another example, when the lower first conductive layer 310A and the upper first conductive layer 310B are formed by depositing an ITO material using an ALD (atomic layer deposition) method, the Sn content can be increased during the formation of the lower first conductive layer 310A by increasing the number of SnO2 sub-cycles compared to the number of In2O3 sub-cycles, and the Sn content can be reduced during the formation of the upper first conductive layer 310B by reducing the number of SnO2 sub-cycles compared to the number of In2O3 sub-cycles.

[0089] Alternatively, deposition may be performed by reducing a flow rate of an oxygen-containing gas such as O 2 gas during deposition of the upper first conductive layer 310B compared to a flow rate of an oxygen-containing gas such as O 2 gas during deposition of the lower first conductive layer 310A.

[0090] refer to Fig.15 , the first hard mask layer 340 , the second conductive layer 330 , the oxide semiconductor layer 320 , and the first conductive layer 310 may be etched using the first mask pattern 345 as an etch barrier to form a first hard mask pattern 342 , a second conductive pattern 332 , an oxide semiconductor pattern 322 , and an initial first conductive pattern 312 .

[0091] Here, the initial first conductive pattern 312 may include an etched upper first conductive pattern 312B and an unetched initial lower first conductive pattern 312A. The stacked structure of the upper first conductive pattern 312B, the oxide semiconductor pattern 322, the second conductive pattern 332, and the first hard mask pattern 342 may have a columnar shape. The initial first lower conductive pattern 312A may maintain a flat plate shape. The upper first conductive pattern 312B may correspond to a drain electrode. The initial lower first conductive pattern 312A may be patterned into a linear shape in a subsequent process and may be used as a bit line.

[0092] According to the present embodiment, since the etching rate of the lower first conductive layer 310A is lower than the etching rate of the upper first conductive layer 310B, the etching can be easily stopped at the lower first conductive layer 310A during the etching process. In this case, since the lower first conductive layer 310A has a substantially uniform thickness, the distribution of the bit line thickness, that is, the distribution of the bit line resistance can be improved.

[0093] Fig.16 1 is a simplified cross-sectional view schematic diagram showing a semiconductor device and a method for manufacturing the semiconductor device according to another embodiment of the present disclosure. The description will focus on the differences from the above-described embodiment.

[0094] refer to Fig.16 , a first conductive layer 410, an oxide semiconductor layer 420, a second conductive layer 430, a first hard mask layer 440, and a first mask pattern 445 may be formed on the substrate 400. The first conductive layer 410, the oxide semiconductor layer 420, the second conductive layer 430, the first hard mask layer 440, and the first mask pattern 445 may be sequentially formed on the substrate 400 according to the above order. Except for the second conductive layer 430, the substrate 400, the first conductive layer 410, the oxide semiconductor layer 420, the first hard mask layer 440, and the first mask pattern 445 may correspond to Figure 1A and Figure 1B The substrate 100 , the first conductive layer 110 , the oxide semiconductor layer 120 , the first hard mask layer 140 and the first mask pattern 145 are shown.

[0095] The second conductive layer 430 may include a conductive metal oxide, such as ITO, In2O3 or a metal oxide semiconductor. In the present embodiment, the second conductive layer 430 may include a conductive metal oxide, wherein the content of a specific metal element and / or the oxygen content increases from the bottom to the top. The content of a specific metal element or oxygen in the second conductive layer 430 may be indicated in the graph on the right side of the second conductive layer 430. As described above, as the content of a specific metal element or the oxygen content in the conductive metal oxide increases, the etching rate of the conductive metal oxide decreases. Therefore, in the process of etching the second conductive layer 430 to form a columnar second conductive pattern (not shown), the phenomenon that the upper portion of the second conductive pattern is lost and has a curved profile can be minimized and / or prevented. The sidewall of the second conductive pattern may have a vertical profile substantially perpendicular to the surface of the substrate 400.

[0096] A method in which the content of a specific metal element is increased from the bottom to the top may be used when depositing the second conductive layer 430. Alternatively, when depositing the second conductive layer 430, the flow rate of the oxygen-containing gas may be increased from the bottom to the top.

[0097] The above embodiments may be applicable to semiconductor devices including NMOS transistors, PMOS transistors or CMOS transistors and methods for manufacturing the same. For example, the above embodiments may be applicable to at least one of various semiconductor devices, for example, non-volatile memory such as flash memory, resistive random access memory (RRAM), phase change random access memory (PRAM), or magnetoresistive random access memory (MRAM); volatile memory such as dynamic random access memory (DRAM) or static random access memory (SRAM); non-memory such as logic circuits or CIS (CMOS image sensor).

[0098] According to the above-described embodiments of the present disclosure, it is possible to provide a semiconductor device which improves its characteristics and reduces its area while simplifying the manufacturing process.

[0099] Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present teachings as defined in the following claims. Furthermore, these embodiments may be combined to form additional embodiments.

Claims

1. A semiconductor device, comprising: substrate; A lower portion of the first conductive pattern is disposed on the substrate and extends in a second direction; a stacked structure disposed on a lower portion of the first conductive pattern and having a columnar shape, the stacked structure including an upper portion of the first conductive pattern, an oxide semiconductor channel, and a second conductive pattern; as well as a word line extending in a first direction and facing at least a portion of a side wall of the oxide semiconductor channel, wherein a gate insulating layer is provided between the word line and the oxide semiconductor channel, wherein the first direction intersects with the second direction, wherein the first conductive pattern comprises a first conductive metal oxide, and A lower portion of the first conductive pattern corresponds to a bit line, and an upper portion of the first conductive pattern corresponds to a drain electrode. 2 . The semiconductor device according to claim 1 , wherein no interface exists between a lower portion of the first conductive pattern and an upper portion of the first conductive pattern. 3 . The semiconductor device according to claim 1 , wherein in the first direction, a width of a lower portion of the first conductive pattern is greater than a width of the stacked structure.

4. The semiconductor device according to claim 1, wherein the first conductive pattern comprises two or more metal elements, The metal element having the greatest binding force with oxygen among the two or more metal elements is called the first metal element, and The content of the first metal element in the lower portion of the first conductive pattern is greater than the content of the first metal element in the upper portion of the first conductive pattern. 5 . The semiconductor device according to claim 1 , wherein an oxygen content of a lower portion of the first conductive pattern is greater than an oxygen content of an upper portion of the first conductive pattern. 6 . The semiconductor device according to claim 1 , wherein the first conductive metal oxide comprises ITO, In 2 O 3 , or a metal oxide semiconductor. 7 . The semiconductor device according to claim 1 , wherein the second conductive pattern includes a lower portion corresponding to a source electrode and an upper portion corresponding to a lower electrode of a capacitor. 8 . The semiconductor device according to claim 7 , wherein no interface exists between a lower portion of the second conductive pattern and an upper portion of the second conductive pattern. 9 . The semiconductor device according to claim 7 , wherein the second conductive pattern comprises a second conductive metal oxide.

10. The semiconductor device according to claim 9, wherein the second conductive pattern comprises two or more metal elements, The metal element having the greatest binding force with oxygen among the two or more metal elements is called the first metal element, and The content of the first metal element in the second conductive pattern increases from the bottom of the second conductive pattern to the top of the second conductive pattern. 11 . The semiconductor device according to claim 9 , wherein the oxygen content of the second conductive pattern increases from the bottom to the top. 12 . The semiconductor device according to claim 9 , wherein the second conductive metal oxide comprises ITO, In 2 O 3 , or a metal oxide semiconductor.

13. The semiconductor device according to claim 7, further comprising: a capacitor insulating layer surrounding a side wall and a top surface of an upper portion of the second conductive pattern; as well as The upper electrode of the capacitor is formed on the capacitor insulating layer. 14 . The semiconductor device according to claim 13 , wherein the gate insulating layer and the capacitor insulating layer include the same material.

15. A semiconductor device comprising: substrate; A bit line is disposed on the substrate and extends in a second direction; a stack structure disposed above the bit line and having a pillar shape, the stack structure including a drain electrode, an oxide semiconductor channel, and a conductive pattern; as well as a word line extending in a first direction and facing at least a portion of a side wall of the oxide semiconductor channel, wherein a gate insulating layer is provided between the word line and the oxide semiconductor channel, wherein the first direction intersects with the second direction, wherein the conductive pattern comprises a conductive metal oxide, and A lower portion of the conductive pattern corresponds to a source electrode, and an upper portion of the conductive pattern corresponds to a lower electrode of the capacitor. 16 . The semiconductor device according to claim 15 , wherein no interface exists between a lower portion of the conductive pattern and an upper portion of the conductive pattern.

17. The semiconductor device according to claim 15, wherein the conductive pattern comprises two or more metal elements, The metal element having the greatest binding force with oxygen among the two or more metal elements is called the first metal element, and The content of the first metal element in the conductive pattern increases from the bottom to the top. 18 . The semiconductor device according to claim 15 , wherein the oxygen content of the conductive pattern increases from the bottom to the top.

19. The semiconductor device according to claim 15, wherein the conductive metal oxide comprises ITO, In2O3 or a metal oxide semiconductor.

20. The semiconductor device according to claim 15, further comprising: a capacitor insulating layer surrounding a side wall and a top surface of an upper portion of the conductive pattern; as well as The upper electrode of the capacitor is formed on the capacitor insulating layer. 21 . The semiconductor device according to claim 20 , wherein the gate insulating layer and the capacitor insulating layer include the same material.

22. A method for manufacturing a semiconductor device, the method comprising: forming a first conductive layer, an oxide semiconductor layer, and a second conductive layer on a substrate; patterning an upper portion of the first conductive layer, the oxide semiconductor layer, and the second conductive layer to form a stacked structure including an upper first conductive pattern, an oxide semiconductor channel, and a second conductive pattern, and having a pillar shape; patterning a lower portion of the first conductive layer to form a lower first conductive pattern having a linear shape extending in a second direction; as well as forming a word line extending in a first direction and facing at least a portion of a side wall of the oxide semiconductor channel, with a gate insulating layer between the word line and the oxide semiconductor channel, the first direction intersecting the second direction, wherein the first conductive layer comprises a first conductive metal oxide, and The lower first conductive pattern corresponds to a bit line, and the upper first conductive pattern corresponds to a drain electrode. 23 . The method according to claim 22 , wherein in the first direction, a width of the lower first conductive pattern is greater than a width of the stacked structure.

24. The method of claim 22, wherein forming the first conductive layer comprises: depositing a lower portion of the first conductive layer; as well as depositing an upper portion of the first conductive layer, wherein the first conductive layer comprises two or more metal elements, The metal element having the greatest binding force with oxygen among the two or more metal elements is called the first metal element, and Wherein the deposition of the lower portion of the first conductive layer is performed by increasing the content of the first metal element compared to the deposition of the upper portion of the first conductive layer.

25. The method of claim 22, wherein forming the first conductive layer comprises: depositing a lower portion of the first conductive layer; as well as depositing an upper portion of the first conductive layer, The flow rate of the oxygen-containing gas used in the deposition of the lower portion of the first conductive layer is greater than the flow rate of the oxygen-containing gas used in the deposition of the upper portion of the first conductive layer.

26. The method of claim 22, further comprising: After forming the word line, forming an insulating pattern, the insulating pattern covering the word line and making an upper portion of the second conductive pattern protrude; as well as forming an upper electrode of a capacitor, the upper electrode facing the upper portion of the second conductive pattern, with a gate insulating layer or a capacitor insulating layer between the upper electrode and the upper portion of the second conductive pattern, wherein an upper portion of the second conductive pattern corresponds to a lower electrode of the capacitor, and A lower portion of the second conductive pattern except an upper portion of the second conductive pattern corresponds to a source electrode.

27. The method of claim 22, wherein the second conductive layer comprises a second conductive metal oxide.

28. The method according to claim 27, wherein the second conductive layer comprises two or more metal elements, The metal element having the greatest binding force with oxygen among the two or more metal elements is called the first metal element, and The forming of the second conductive layer is performed by a deposition method in which the content of the first metal element is increased from the bottom to the top. 29 . The method of claim 27 , wherein forming the second conductive layer is performed by a deposition method in which a flow rate of the oxygen-containing gas is increased from the bottom to the top.

30. A method for manufacturing a semiconductor device, the method comprising: forming a bit line on the substrate, the bit line extending in a second direction; forming a stack structure over the bit line, the stack structure including a drain electrode, an oxide semiconductor channel, and a conductive pattern and having a pillar shape, the conductive pattern including a conductive metal oxide; forming a word line extending in a first direction and facing at least a portion of a sidewall of the oxide semiconductor channel, with a gate insulating layer between the word line and the oxide semiconductor channel, the first direction intersecting the second direction; forming an insulating pattern, the insulating pattern covering the word line and causing an upper portion of the conductive pattern to protrude; as well as forming an upper electrode of a capacitor, the upper electrode facing the upper portion of the conductive pattern, with the gate insulating layer or the capacitor insulating layer between the upper electrode and the upper portion of the conductive pattern, wherein an upper portion of the conductive pattern corresponds to a lower electrode of the capacitor, and A lower portion of the conductive pattern except an upper portion of the conductive pattern corresponds to a source electrode.

31. The method of claim 30, wherein forming the conductive pattern comprises: depositing a conductive layer; as well as patterning the conductive layer into a pillar shape, wherein the conductive layer comprises two or more metal elements, The metal element having the greatest binding force with oxygen among the two or more metal elements is called the first metal element, and During the deposition of the conductive layer, the content of the first metal element increases from the bottom to the top.

32. The method of claim 30, wherein forming the conductive pattern comprises: depositing a conductive layer; as well as patterning the conductive layer into a pillar shape, During the deposition of the conductive layer, the flow rate of the oxygen-containing gas is increased from the bottom to the top.

33. A semiconductor device comprising: substrate; a first conductive pattern disposed on the substrate and extending in a second direction, the first conductive pattern consisting of a linear shape bottom covering a top surface of the substrate and a plurality of spaced-apart columnar shape tops rising above the linear shape bottom in a vertical direction; a plurality of stacked structures, each stacked structure being disposed above a corresponding one of the columnar-shaped tops of the first conductive pattern and having a columnar shape, each stacked structure including an oxide semiconductor channel and a second conductive pattern stacked sequentially; as well as A word line extends in a first direction and faces at least a portion of a side wall of the oxide semiconductor channel, with a gate insulating layer between the word line and the oxide semiconductor channel, and the first direction intersects the second direction. 34 . The semiconductor device according to claim 33 , wherein no interface exists between the linear-shaped bottom of the first conductive pattern and the columnar-shaped top of the first conductive pattern.

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