Semiconductor device and preparation method thereof, and memory system

Abstract

The invention provides a semiconductor device, a preparation method thereof and a memory system, the semiconductor device comprises a first semiconductor structure, and the first semiconductor structure comprises a stacking structure; the marking structure is located in the stacking structure; the mark structure comprises a plurality of first channel structures, a part of the plurality of first channel structures form a first mark pattern, the other part of the plurality of first channel structures form a second mark pattern, and the other part of the plurality of first channel structures form a supporting mark pattern; the supporting mark pattern surrounds the second mark pattern, and the first mark pattern is located on one side of the supporting mark pattern. According to the semiconductor device, the preparation method thereof and the memory system provided by the invention, the mark pattern can be prevented from collapsing.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a semiconductor device and a method for manufacturing the same, as well as a memory system. Background Art

[0002] In the method for preparing a semiconductor structure, a grid line mark (GL mark) located on a cutting path is usually used for alignment, or the mark deviation between the current layer and the previous layer on the cutting line is measured during overlay error measurement to achieve the purpose of measuring the overlay error between the previous and next processes. The method for preparing a semiconductor device also includes a step of removing the silicon nitride layer in the stacked structure, which easily causes the GL mark on the cutting line to collapse. Summary of the invention

[0003] In view of this, the present application provides a semiconductor device and a manufacturing method thereof, as well as a memory system that can solve the above-mentioned technical problems.

[0004] To solve the above problems, the technical solutions provided by this application are as follows:

[0005] The present application provides a semiconductor device, including a first semiconductor structure, which includes: a stacked structure; and a marking structure located in the stacked structure; wherein the marking structure includes a plurality of first channel structures, a portion of the first channel structures in the plurality of the first channel structures constitute a first marking pattern, another portion of the first channel structures in the plurality of the first channel structures constitute a second marking pattern, and another portion of the first channel structures in the plurality of the first channel structures constitute a supporting marking pattern, the supporting marking pattern surrounds the second marking pattern, and the first marking pattern is located on one side of the supporting marking pattern.

[0006] In some embodiments, the first semiconductor structure also includes: a first insulating layer, located on one side of the stacked structure; the first insulating layer covers the supporting mark pattern and the second mark pattern, and the orthographic projection of the first insulating layer on the stacked structure falls on the periphery of the first mark pattern; and a second insulating layer; a portion of the second insulating layer is located on a side of the first insulating layer away from the stacked structure, and another portion of the second insulating layer covers the first channel structure in the first mark pattern close to one end of the first insulating layer.

[0007] In some embodiments, there is a gap between two adjacent first channel structures; the second insulating layer includes a third marking pattern, and the third marking pattern includes a convex portion and a concave portion adjacent to the convex portion; wherein the orthographic projection of the convex portion on the stacked structure at least partially overlaps with the multiple first channel structures of the first marking pattern, and the orthographic projection of the concave portion on the stacked structure at least partially overlaps with the gap of the first marking pattern.

[0008] In some embodiments, the stacked structure, the first insulating layer and the second insulating layer are stacked in a first direction; a second direction and a third direction perpendicular to the first direction are used as the X-axis and Y-axis of the two-dimensional coordinate system, respectively, and the marking structure is divided into four quadrants; in one of the quadrants, a first marking graphic and a second marking graphic are adjacently arranged along the first direction or the second direction, and in the arrangement direction of the first marking graphic and the second marking graphic, the first marking graphic is closer to the X-axis or the Y-axis than the second marking graphic.

[0009] In some embodiments, the first mark pattern includes a first mark group; each of the first mark groups includes a plurality of first sub-mark groups, and each of the first sub-mark groups includes a plurality of first channel structures arranged in an array.

[0010] In some embodiments, two adjacent first marking groups are L-shaped, the first sub-marking groups in one of the two adjacent first marking groups are arranged along the X-axis, and the first sub-marking groups in the other first marking group are arranged along the Y-axis.

[0011] In some embodiments, each of the second mark graphics includes multiple second mark groups, each of the second mark groups includes multiple second sub-mark groups arranged along the first direction or the second direction, and each of the second sub-mark groups includes multiple first channel structures arranged in an array; wherein, in one of the quadrants, the arrangement direction of the second sub-mark groups in the second mark group is the same as the arrangement direction of the first sub-mark groups in the first mark group.

[0012] In some embodiments, in one of the quadrants and in the arrangement direction of the first mark group and the second mark group, one of the second sub-mark groups is opposite to the gap position between two adjacent first sub-mark groups; in the arrangement direction of the first sub-mark groups, the outermost first sub-mark group is opposite to the gap position between the supporting mark pattern and a second sub-mark group adjacent to the supporting mark pattern.

[0013] In some embodiments, the first insulating layer includes a first insulating portion and a second insulating portion, the first insulating portion covers the second marking pattern and the supporting marking pattern, the second insulating portion extends from the first insulating portion, and the orthographic projection of the second insulating portion on the stacking structure is located between the first marking pattern and the supporting marking pattern.

[0014] In some embodiments, in one of the quadrants, a plurality of the second insulating portions are arranged at intervals, and an orthographic projection of the second insulating portion on the stacked structure is arranged opposite to the first sub-mark group.

[0015] In some embodiments, the first semiconductor structure also includes: a first gate line structure, located in the stacked structure and passing through the second insulating layer, the first insulating layer and the stacked structure; wherein a plurality of the first gate line structures constitute a plurality of first gate line structure groups, and the orthographic projection of each of the first gate line structure groups on the stacked structure is located between two adjacent second sub-marking groups or between the second sub-marking group and the supporting mark pattern.

[0016] In some embodiments, a plurality of the first gate line structures in one first gate line structure group are arranged along the first direction or the second direction.

[0017] In some embodiments, the stacked structure includes a core area, a connection area and a cutting road area; the connection area is located on one side of the core area, the cutting road area is located on a side of the connection area away from the core area, and the marking structure is located in the cutting road area; wherein, the first semiconductor structure also includes a second gate line structure and a third gate line structure, the second gate line structure and the third gate line structure are located in the stacked structure and pass through the second insulating layer, the first insulating layer and the stacked structure, the second gate line structure is located in the core area, and the third gate line structure is located in the connection area.

[0018] In some embodiments, the first insulating layer also covers the core region and the connection region.

[0019] In some embodiments, the stacked structure includes a gate electrode layer and a dielectric layer, and the gate electrode layer and the dielectric layer are alternately arranged in the stacking direction of the stacked structure and the first insulating layer; wherein the first insulating layer is located on a side of one of the dielectric layers away from the gate electrode layer; the marking structure is located in the stacked structure and penetrates the gate electrode layer and the dielectric layer along the stacking direction; the second insulating layer is also connected to a portion of the dielectric layer connected to the first insulating layer and a portion of the gate electrode layer closest to the first insulating layer in the stacking direction.

[0020] In some embodiments, the first semiconductor structure further includes: a top selection gate located in the first insulating layer and spaced apart from the gate electrode layer by the dielectric layer.

[0021] In some embodiments, the stacked structure, the first insulating layer and the second insulating layer are stacked in a first direction; the semiconductor device also includes a second semiconductor structure, which has circuit elements that control the first semiconductor structure and is located on one side of the first semiconductor structure; wherein the second semiconductor structure is bonded to the first semiconductor structure in the first direction.

[0022] The present application also provides a method for manufacturing a semiconductor device, including: forming a first stacking structure; and forming a plurality of first channel structures in the first stacking structure, and arranging a portion of the first channel structures in the plurality of the first channel structures into a first marking pattern, and another portion of the first channel structures in the plurality of the first channel structures into a second marking pattern, and another portion of the first channel structures in the plurality of the first channel structures constituting a supporting marking pattern, wherein the supporting marking pattern surrounds the second marking pattern, the first marking pattern is located on one side of the supporting marking pattern, and the first marking pattern, the second marking pattern and the supporting marking pattern constitute a marking structure.

[0023] In some embodiments, the first channel structure extends along a first direction; each of the second mark patterns includes a plurality of second mark groups, each of the second mark groups includes a plurality of second sub-mark groups arranged along a second direction or a third direction perpendicular to the first direction, and each of the second sub-mark groups includes a plurality of the first channel structures arranged in an array; after the step of forming a plurality of first channel structures in the first stacked structure, the step further includes: forming a first gate line structure, and making the first gate line structure located in the first stacked structure, and the orthographic projection of the first gate line structure on the first stacked structure is located between two adjacent second sub-mark groups or between the second sub-mark group and the supporting mark pattern.

[0024] In some embodiments, after the step of forming multiple first channel structures in the first stacking structure and before forming the first gate line structure, it also includes: forming a first initial insulating layer on one side of the first stacking structure, and making the first initial insulating layer cover the marking structure; wherein the first initial insulating layer and the first stacking structure are stacked in the first direction; patterning the first initial insulating layer to obtain a first insulating layer, and making one end of each first channel structure corresponding to the first marking pattern exposed from the first insulating layer; and forming a second insulating layer on a side of the first insulating layer away from the stacking structure, and making the second insulating layer cover one end of the first channel structure in the first marking pattern close to the first insulating layer.

[0025] In some embodiments, a third marking pattern is formed at a position of the second insulating layer corresponding to the first marking pattern; the step of forming a first gate line structure includes: forming a hard mask layer on the second insulating layer, and a fourth marking pattern is formed at a position of the hard mask layer corresponding to the third marking pattern; forming a photoresist layer on the hard mask layer; patterning the photoresist layer with the fourth marking pattern as a mark to form a first gate line structure pattern at a position of the photoresist layer corresponding to the second marking pattern and the supporting marking pattern; transferring the first gate line structure pattern to the hard mask layer to obtain a second gate line structure pattern; transferring the second gate line structure pattern to the second insulating layer, the first insulating layer and the first stacked structure in sequence; forming the first gate line structure on the first stacked structure; and removing the photoresist layer and the hard mask layer.

[0026] In some embodiments, in the step of patterning the first initial insulating layer, the first insulating layer includes a first insulating portion and a second insulating portion, the first insulating portion covers the second marking pattern and the supporting marking pattern, the second insulating portion extends from the first insulating portion, and the orthographic projection of the second insulating portion on the stacking structure is located between the first marking pattern and the supporting marking pattern.

[0027] In some embodiments, the stacking structure includes a core area, a connection area and a cutting road area; the connection area is located on one side of the core area, and the cutting road area is located on a side of the connection area away from the core area; in the step of forming a plurality of first channel structures in the first stacking structure, the marking structure is located in the cutting road area; while forming a plurality of first channel structures in the first stacking structure, it also includes: forming a second gate line structure in the core area that passes through the second insulating layer, the first insulating layer and the stacking structure; and forming a third gate line structure in the connection area that passes through the second insulating layer, the first insulating layer and the stacking structure.

[0028] The present application also provides a memory system, comprising: at least one semiconductor device as described above; and a controller configured to control the semiconductor device.

[0029] The semiconductor device and its manufacturing method and memory system provided by the present application form a first mark pattern, a second mark pattern and a support mark pattern by using a plurality of first channel structures located in a stacked structure, and the support mark pattern surrounds the second mark pattern, and the first mark pattern is located on one side of the support mark pattern. The first channel structure can support the stacked structure in the step of removing the silicon nitride film layer so that it does not collapse. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in some embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 A cross-sectional view of a semiconductor device (first semiconductor structure) provided in the present application.

[0032] Figure 2 for Figure 1 A top view of a first channel structure in a semiconductor device is shown.

[0033] Figure 3 A top view of a marking structure provided for some embodiments of the present application.

[0034] Figure 4 For along Figure 3 A cross-sectional view taken along line IV-IV is shown.

[0035] Figure 5 A schematic diagram of a module of a semiconductor device including a second semiconductor structure provided for some other embodiments of the present application.

[0036] Figure 6 A top view of a marking structure provided for some other embodiments of the present application.

[0037] Figure 7 A top view of a marking structure provided in some further embodiments of the present application.

[0038] Figure 8 A flow chart of a method for preparing a semiconductor device provided in the present application.

[0039] Fig. 9 A partial cross-sectional view of a first stacking structure provided in some embodiments of the present application.

[0040] Fig.10 For Fig. 9 A cross-sectional view of one side of the first stacked structure after a first initial insulating layer is formed is shown.

[0041] Fig.11 for Fig.10 A top view of the first initial insulating layer is shown.

[0042] Fig.12 For patterning Fig.10 The first initial insulating layer shown is a cross-sectional view after obtaining the first insulating layer.

[0043] Fig.13 for Fig.12 A cross-sectional view of a first stacked structure with a first insulating layer is shown.

[0044] Fig.14 For Fig.12 A cross-sectional view is shown after a second insulating layer, a hard mask layer and a photoresist layer are formed on the first insulating layer.

[0045] Fig.15 for Fig.14 A top view of a first stacked structure with a first insulating layer, a second insulating layer, a hard mask layer and a photoresist layer is shown.

[0046] Fig.16 Cross-sectional views of other positions of the first stacking structure provided for some embodiments of the present application.

[0047] Fig.17 To remove Fig.16 A cross-sectional view of a portion of the initial insulating layer of the first stacked structure after forming a first cavity is shown.

[0048] Fig.18 For Fig.17 The cross-sectional view is shown after the first cavity is filled with semiconductor material to form an initial semiconductor layer.

[0049] Fig.19 To remove Fig.18 A cross-sectional view of the initial semiconductor layer and the initial insulating layer located in the core area is shown.

[0050] Fig. 20 A module diagram of a memory system provided for some embodiments of the present application. DETAILED DESCRIPTION

[0051] The following will be combined with the drawings in some embodiments of the present application to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application.

[0052] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0053] In the description of the present application, it is to be understood that the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range that is less than the range of a lower or upper structure. In addition, a layer may be a region of a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of a continuous structure. A layer may extend horizontally, vertically and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (where interconnects and / or via contacts are formed), and one or more dielectric sublayers.

[0054] The present application may repeat reference numerals and / or reference letters in different implementations. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various implementations and / or settings discussed.

[0055] The present application aims at the technical problem that the GL mark on the semiconductor cutting road is easy to collapse. By using a plurality of first channel structures located in a stacked structure to form a first mark pattern, a second mark pattern and a supporting mark pattern, the supporting mark pattern surrounds the second mark pattern, and the first mark pattern is located on one side of the supporting mark pattern. The first channel structure can support the stacked structure in the step of removing the silicon nitride film layer so that it does not collapse.

[0056] The following will be combined Figures 1 to 6 , specifically describe the specific structure of the semiconductor structure.

[0057] See also Figures 1 to 4Some embodiments of the present application provide a semiconductor device 100, the semiconductor device 100 includes a first semiconductor structure 1001, the first semiconductor structure 1001 includes a stacked structure 110 and a marking structure 120, and the marking structure 120 is located in the stacked structure 110. The marking structure 120 includes a plurality of first channel structures 10, a portion of the first channel structures 10 in the plurality of the first channel structures 10 constitutes a first marking pattern 20, another portion of the first channel structures 10 in the plurality of the first channel structures 10 constitutes a second marking pattern 30, and another portion of the first channel structures 10 in the plurality of the first channel structures 10 constitutes a supporting marking pattern 40, the supporting marking pattern 40 surrounds the second marking pattern 30, and the first marking pattern 20 is located on one side of the supporting marking pattern 40.

[0058] The semiconductor device 100 provided in the present application forms a first marking pattern 20, a second marking pattern 30 and a supporting marking pattern 40 by using a first channel structure 10 located in a stacked structure 110, and the supporting marking pattern 40 surrounds the second marking pattern 30, and the first marking pattern 20 is located on one side of the supporting marking pattern 40. The first channel structure 10 can support the stacked structure 110 in the step of removing the initial oxide layer 13 (silicon nitride film layer) so that it does not collapse. In addition, since the marking structure of the semiconductor device 100 provided in the application is formed by arranging the channel structure 10 located in the stacked structure, the marking structure 120 can be completely retained in the process of removing the initial oxide layer 13 (silicon nitride film layer), and the process is simple and the cost is low.

[0059] The stacking structure 110 includes a core area 101 , a connection area 102 and a cutting area 103 . The connection area 102 is located at one side of the core area 101 . The cutting area 103 is located at a side of the connection area 102 away from the core area 101 . The marking structure 120 is located in the cutting area 103 .

[0060] The stacked structure 110 includes a gate electrode layer 12, a dielectric layer 11 and an initial insulating layer 13. The gate electrode layer 12 and the dielectric layer 11 are alternately stacked in the stacked structure 110 along a first direction Z. The gate electrode layer 12 is located in the core region 101, the connection region 102 and the cutting street region 103. The initial insulating layer 13 is located in the connection region 102 and the cutting street region 103. The gate electrode layer 12 and the initial insulating layer 13 are arranged in the same layer. At least part of the first channel structure 10 penetrates the gate electrode layer 12 and the dielectric layer 11, and at least part of the first channel structure 10 penetrates the initial insulating layer 13 and the dielectric layer 11.

[0061] The dielectric layer 11 and the initial insulating layer 13 are made of insulating materials such as silicon oxide, silicon nitride or silicon oxynitride. The dielectric layer 11 and the initial insulating layer 13 are made of different materials. In this embodiment, the dielectric layer 11 is made of silicon oxide, and the initial insulating layer 13 is made of silicon nitride.

[0062] The constituent material of the gate electrode layer 12 includes a conductive material, such as single crystal silicon, polycrystalline silicon, doped single crystal silicon, doped polycrystalline silicon, tungsten, copper, aluminum, platinum, titanium or ruthenium, etc. In this embodiment, the constituent material of the gate electrode layer 12 is polycrystalline silicon.

[0063] The first channel structure 10 includes a channel layer (not shown), a functional layer (not shown) and a filling layer (not shown), the functional layer includes a charge capture layer, a tunnel layer and a blocking layer, the channel layer is arranged around the filling layer, the tunnel layer is arranged around the channel layer, the charge capture layer is arranged around the tunnel layer, the blocking layer is arranged around the charge capture layer and faces the stacked structure 110. That is, the channel layer is located between the filling layer and the tunnel layer, and the charge capture layer is located between the blocking layer and the tunnel layer.

[0064] Please refer again Figure 1 The first semiconductor structure 1001 further includes a second channel structure 310 and a third channel structure 320. The structures of the second channel structure 310 and the third channel structure 320 are the same as those of the first channel structure 10 and are respectively located in the stacked structure 110. The second channel structure 310 is located in the core region 101, and the third channel structure 320 is located in the connection region 102. Both the second channel structure 310 and the third channel structure 320 penetrate the gate electrode layer 12 and the dielectric layer 11.

[0065] Please refer again Figures 2 to 4 In some embodiments, the first semiconductor structure 1001 further includes a first insulating layer 50 and a second insulating layer 60, wherein the first insulating layer 50 is located on one side of the stacked structure 110, and the second insulating layer 60 is located on a side of the first insulating layer 50 away from the stacked structure 110. The first insulating layer 50 covers the support mark pattern 40 and the second mark pattern 30, and the orthographic projection of the first insulating layer 50 on the stacked structure 110 falls on the periphery of the first mark pattern 20. A portion of the second insulating layer 60 is located on a side of the first insulating layer 50 away from the stacked structure 110, and another portion of the second insulating layer 60 covers an end of the first channel structure 10 in the first mark pattern 20 close to the first insulating layer 50.

[0066] One end of the first channel structure 10 close to the first insulating layer 50 is the first end 1011, and the other part of the second insulating layer 60 covers the first end 1011 of the first channel structure 10. That is, the first insulating layer 50 includes a first opening 52, and the outermost dielectric layer 11 of the stacked structure 110 includes a second opening 111, the second opening 111 is connected to the first opening 52 and is located opposite to the first opening 52, the first end 1011 of the first channel structure 10 is exposed from the second opening 111, and the second insulating layer 60 is filled in the second opening 111 and the first opening 52.

[0067] Please refer again Figure 4 In some embodiments, there is a gap 1012 between two adjacent first channel structures 10, and part of the second insulating layer 60 is filled in the gap 1012. The second insulating layer 60 includes a third marking pattern 61, and the third marking pattern 61 includes a convex portion 611 and a concave portion 612 adjacent to the convex portion 611. The orthographic projection of one convex portion 611 on the stacked structure 110 at least partially overlaps with one of the first channel structures 10 of the first marking pattern 20, and the orthographic projection of the concave portion 612 on the stacked structure 110 at least partially overlaps with the gap 1012 of the first channel structure 10 of the first marking pattern 20. The third marking pattern 61 serves as a mark for the subsequent formation of a gate line structure, etc. Since there is a gap 1012 between two adjacent first channel structures 10 and the first end 1011 of the first channel structure 10 is exposed from the second opening 111, when the second insulating layer 60 is formed, the portion of the second insulating layer 60 corresponding to the first end 1011 forms the convex portion 611, and the position of the second insulating layer 60 corresponding to the gap 1012 forms the concave portion 612, and the convex portion 611 and the concave portion 612 constitute the third marking pattern 61.

[0068] Please refer again Figure 2 In some embodiments, the stacked structure 110, the first insulating layer 50 and the second insulating layer 60 are stacked in a first direction Z, and a second direction X and a third direction Y perpendicular to the first direction Z are used as the X-axis and Y-axis of the two-dimensional coordinate system, respectively, and the marking structure 120 is divided into four quadrants. In one of the quadrants, a first marking graphic 20 and a second marking graphic 30 are adjacently arranged along the first direction Z or the second direction X. In the arrangement direction of the first marking graphic 20 and the second marking graphic 30, the first marking graphic 20 is closer to the X-axis or the Y-axis than the second marking graphic 30.

[0069] In some embodiments, the first mark pattern 20 includes a first mark group 21 , each of the first mark groups 21 includes a plurality of first sub-mark groups 211 , and each of the first sub-mark groups 211 includes a plurality of first channel structures 10 arranged in an array.

[0070] In some embodiments, two adjacent first marking groups 21 are L-shaped, and the first sub-marking groups 211 in one of the two adjacent first marking groups 21 are arranged along the X-axis, and the first sub-marking groups 211 in the other first marking group 21 are arranged along the Y-axis.

[0071] In some embodiments, each of the second marking patterns 30 includes a plurality of second marking groups 31, each of the second marking groups 31 includes a plurality of second sub-marking groups 311 arranged along the first direction Z or the second direction X, and each of the second sub-marking groups 311 includes a plurality of first channel structures 10 arranged in an array. In one of the quadrants, the arrangement direction of the second sub-marking groups 311 in the second marking group 31 is the same as the arrangement direction of the first sub-marking groups 211 in the first marking group 21.

[0072] In some embodiments, in one of the quadrants, and in the arrangement direction of the first mark groups 21 and the second mark groups 31, one of the second sub-mark groups 311 is opposite to the gap between two adjacent first sub-mark groups 211. In the arrangement direction of the first sub-mark groups 211, the outermost first sub-mark group 211 is opposite to the gap between the support mark pattern 40 and a second sub-mark group 311 adjacent to the support mark pattern 40.

[0073] Please refer again Figure 2 In some embodiments, the width of the gap between two adjacent first sub-marking groups 211 in the arrangement direction of the first sub-marking groups 211 is less than or equal to the width of one second sub-marking group 311 in the arrangement direction of the first sub-marking groups 211.

[0074] Please refer again Figure 3 In some embodiments, the first insulating layer 50 includes a first insulating portion 501, which covers the second marking pattern 30 and the supporting marking pattern 40 but does not cover the first marking pattern 20, so as to expose the first marking pattern 20, which is conducive to forming the third marking pattern 61 as a mark for the subsequent formation of a gate line structure, etc.

[0075] Please refer again Figure 1In some embodiments, the first semiconductor structure 1001 further includes a first gate line structure 104, which is located in the stacked structure 110 and penetrates the second insulating layer 60, the first insulating layer 50 and the stacked structure 110. A plurality of the first gate line structures 104 constitute a plurality of first gate line structure groups 1041, and the orthographic projection of each of the first gate line structure groups 1041 on the stacked structure 110 is located between two adjacent second sub-marking groups 311 or between the second sub-marking group 311 and the supporting mark pattern 40.

[0076] In some embodiments, a plurality of the first gate line structures 104 in one first gate line structure group 1041 are arranged along the first direction Z or the second direction X.

[0077] Please refer again Figure 1 In some embodiments, the first semiconductor structure 1001 also includes a second gate line structure 105 and a third gate line structure 106, the second gate line structure 105 and the third gate line structure 106 are located in the stacked structure 110 and penetrate the second insulating layer 60, the first insulating layer 50 and the stacked structure 110, the second gate line structure 105 is located in the core area 101, and the third gate line structure 106 is located in the connection area 102.

[0078] In some embodiments, the first insulating layer 50 also covers the core region 101 and the connection region 102 .

[0079] Please refer again Figure 1 In some embodiments, the first semiconductor structure 1001 further includes a top selection gate 53 , which is located in the first insulating layer 50 and is separated from the gate electrode layer 12 by the dielectric layer 11 . The top selection gate 53 is connected to the second channel structure 310 .

[0080] See also Figure 5 In some embodiments, the semiconductor device 100 further includes a second semiconductor structure 1002 having a circuit element (not shown) for controlling the first semiconductor structure 1001 and located on one side of the first semiconductor structure 1001, and the second semiconductor structure 1002 is bonded to the first semiconductor structure 1001 in the first direction Z.

[0081] In some embodiments, the second semiconductor structure 1002 is a peripheral circuit.

[0082] See also Figure 2 and Figure 6The present application also provides a semiconductor device 200, the structure of the semiconductor device 200 is similar to that of the semiconductor device 100, except that: the marking structure of the semiconductor device 200 is not completely the same as that of the semiconductor device 100, the first insulating layer 50 of the marking structure of the semiconductor device 200 further includes a second insulating portion 502, the second insulating portion 502 extends from the first insulating portion 501, the orthographic projection of the second insulating portion 502 on the stacked structure 110 is located between the first marking pattern 20 and the supporting marking pattern 40, in one quadrant, a plurality of the second insulating portions 502 are arranged at intervals, and the orthographic projection of the second insulating portion 502 on the stacked structure 110 is arranged opposite to the first sub-marking group 211. In some embodiments, the second insulating portion 502 extends along the second direction X and / or the third direction Y. In the same quadrant, the extension direction of the second insulating portion 502 is perpendicular to the arrangement direction of the plurality of the first sub-marking groups 211.

[0083] The second insulating portion 502 can further increase the recognizability of the marking structure of the semiconductor device 200 .

[0084] See also Figure 2 , Figure 3 and Figure 7 The present application also provides a semiconductor device 300, the structure of which is similar to that of the semiconductor device 100, except that: the first gate line structure 104 of the semiconductor device 100 is arranged in a column or a row, and the first gate line structure 107 of the semiconductor device 300 is arranged in an array.

[0085] See also Figures 8 to 19 The present application also provides a method for manufacturing a semiconductor device, comprising:

[0086] Step S1, see Figure 8 and Fig. 9 , forming a first stacking structure 130 .

[0087] The first stacking structure 130 includes a dielectric layer 11 and an initial insulating layer 13 . The initial insulating layer 13 and the dielectric layer 11 are alternately stacked along a first direction Z in the stacking structure 110 .

[0088] The dielectric layer 11 and the initial insulating layer 13 are made of insulating materials such as silicon oxide, silicon nitride or silicon oxynitride. The dielectric layer 11 and the initial insulating layer 13 are made of different materials. In this embodiment, the dielectric layer 11 is made of silicon oxide, and the initial insulating layer 13 is made of silicon nitride.

[0089] Step S2, see Figure 2 , Figure 8 and Fig. 9 , a plurality of first channel structures 10 are formed in the first stacking structure 130, and a portion of the first channel structures 10 in the plurality of the first channel structures 10 are arranged into a first marking pattern 20, another portion of the first channel structures 10 in the plurality of the first channel structures 10 are arranged into a second marking pattern 30, and another portion of the first channel structures 10 in the plurality of the first channel structures 10 constitute a supporting marking pattern 40, the supporting marking pattern 40 surrounds the second marking pattern 30, the first marking pattern 20 is located on one side of the supporting marking pattern 40, and the first marking pattern 20, the second marking pattern 30 and the supporting marking pattern 40 constitute a marking structure 120.

[0090] The first stacking structure 130 includes a core area 101 , a connection area 102 and a cutting area 103 . The connection area 102 is located at one side of the core area 101 . The cutting area 103 is located at a side of the connection area 102 away from the core area 101 . The marking structure 120 is located in the cutting area 103 .

[0091] Please refer again Figure 1 The first semiconductor structure 1001 further includes a second channel structure 310 and a third channel structure 320. The structures of the second channel structure 310 and the third channel structure 320 are the same as those of the first channel structure 10 and are respectively located in the first stacked structure 130. The second channel structure 310 is located in the core area 101, and the third channel structure 320 is located in the connection area 102. The second channel structure 310 and the third channel structure 320 both penetrate the initial insulating layer 13 and the dielectric layer 11.

[0092] In some embodiments, the first mark pattern 20 includes a first mark group 21 , each of the first mark groups 21 includes a plurality of first sub-mark groups 211 , and each of the first sub-mark groups 211 includes a plurality of first channel structures 10 arranged in an array.

[0093] In some embodiments, two adjacent first marking groups 21 are L-shaped, and the first sub-marking groups 211 in one of the two adjacent first marking groups 21 are arranged along the X-axis, and the first sub-marking groups 211 in the other first marking group 21 are arranged along the Y-axis.

[0094] In some embodiments, the first channel structure 10 extends along a first direction Z; each of the second mark patterns 30 includes a plurality of second mark groups 31, each of the second mark groups 31 includes a plurality of second sub-mark groups 311 arranged along a second direction X or a third direction Y perpendicular to the first direction Z, and each of the second sub-mark groups 311 includes a plurality of the first channel structures 10 arranged in an array. In one of the quadrants, the arrangement direction of the second sub-mark groups 311 in the second mark group 31 is the same as the arrangement direction of the first sub-mark groups 211 in the first mark group 21.

[0095] In some embodiments, in one of the quadrants, and in the arrangement direction of the first mark groups 21 and the second mark groups 31, one of the second sub-mark groups 311 is opposite to the gap between two adjacent first sub-mark groups 211. In the arrangement direction of the first sub-mark groups 211, the outermost first sub-mark group 211 is opposite to the gap between the support mark pattern 40 and a second sub-mark group 311 adjacent to the support mark pattern 40.

[0096] Step S3, see Figure 2 , Figure 8 and Figure 10 to Figure 11 , a first initial insulating layer 51 is formed on one side of the first stacking structure 130 , and the first initial insulating layer 51 covers the marking structure 120 ; the first initial insulating layer 51 and the first stacking structure 130 are stacked in the first direction Z.

[0097] In some embodiments, the first initial insulating layer 51 is located in the core region 101 , the connection region 102 , and the scribe line region 103 .

[0098] Step S4, see Figure 2 , Figure 3 , Figure 6 , Figure 8 and Figure 12 to Figure 13 , patterning the first initial insulating layer 51 to obtain a first insulating layer 50 , and making one end of each of the first channel structures 10 corresponding to the first marking pattern 20 exposed from the first insulating layer 50 .

[0099] In some embodiments, see Figure 3 The first insulating layer 50 includes a first insulating portion 501, which covers the second marking pattern 30 and the supporting marking pattern 40 but does not cover the first marking pattern 20, so as to expose the first marking pattern 20, which is conducive to forming the third marking pattern 61 as a mark for the subsequent formation of a gate line structure, etc.

[0100] In some embodiments, see Figure 6 , the first insulating layer 50 includes a first insulating portion 501 and a second insulating portion 502, the first insulating portion 501 covers the second mark pattern 30 and the supporting mark pattern 40 and does not cover the first mark pattern 20 to expose the first mark pattern 20, the second insulating portion 502 extends from the first insulating portion 501, and the orthographic projection of the second insulating portion 502 on the stacked structure 110 is located between the first mark pattern 20 and the supporting mark pattern 40. In one quadrant, a plurality of the second insulating portions 502 are arranged at intervals, and the orthographic projection of the second insulating portion 502 on the stacked structure 110 is arranged opposite to the first sub-mark group 211. In some embodiments, the second insulating portion 502 extends along the second direction X and / or the third direction Y. In the same quadrant, the extension direction of the second insulating portion 502 is perpendicular to the arrangement direction of the plurality of the first sub-mark groups 211.

[0101] In some embodiments, a gap 1012 is provided between two adjacent first channel structures 10 .

[0102] In step S4, the dielectric layer 11 in contact with the first insulating layer 50 is also patterned, the dielectric layer 11 includes a second opening 111, the first insulating layer 50 includes a first opening 52, the second opening 111 is connected to the first opening 52 and is positioned opposite to the first opening 52, the first end 1011 of the first channel structure 10 is exposed from the second opening 111, and the second insulating layer 60 is filled in the second opening 111 and the first opening 52.

[0103] Step S5, see Figure 2 , Figure 8 and Figure 14 to Figure 15 A second insulating layer 60 is formed on a side of the first insulating layer 50 away from the first stacked structure 130 , and the second insulating layer 60 covers an end of the first channel structure 10 in the first marking pattern 20 close to the first insulating layer 50 .

[0104] A third marking pattern 61 is formed at a position of the second insulating layer 60 corresponding to the first marking pattern 20. The third marking pattern 61 includes a convex portion 611 and a concave portion 612 adjacent to the convex portion 611; wherein the orthographic projection of one of the convex portions 611 on the stacked structure 110 at least partially overlaps with one of the first channel structures 10 of the first marking pattern 20, and the orthographic projection of the concave portion 612 on the stacked structure 110 at least partially overlaps with the gap 1012 of the first channel structure 10 of the first marking pattern 20. The third marking pattern 61 serves as a mark for the subsequent formation of a gate line structure, etc.

[0105] A patterned first insulating layer 50 is first formed on a first stacked structure 130 having a first channel structure 10 (for forming a marking structure 120) to expose the first marking pattern 20, and a second insulating layer 60 is formed on the first insulating layer 50, and part of the second insulating layer 60 is filled in the gap 1012 between two adjacent first channel structures 10 of the first marking pattern 20, thereby forming a third marking pattern 61 on the second insulating layer 60. The third marking pattern 61 can be used as a mark for the subsequent formation of a gate line structure. In this way, after development inspection (ADI) and after etching inspection (AEI, also called overlay measurement) can be achieved.

[0106] Step S6, see Figure 2 , Figure 3 , Figure 8 and Figures 14 to 16 , a first gate line structure 104 is formed with the marking structure 120 as a mark, and the first gate line structure 104 is located in the first stacked structure 130, and the positive projection of the first gate line structure 104 on the first stacked structure 130 is located between two adjacent second sub-marking groups 311 or between the second sub-marking group 311 and the supporting mark pattern 40.

[0107] In some embodiments, see Figure 3 , Figures 14 to 16 Step S6 includes: first, forming a hard mask layer 70 on the second insulating layer 60, wherein a fourth mark pattern 71 corresponding to the third mark pattern 61 is formed on the hard mask layer 70 at a position corresponding to the third mark pattern 61. Secondly, forming a photoresist layer 80 on the hard mask layer 70, wherein a fifth mark pattern 81 corresponding to the fourth mark pattern 71 is formed on the photoresist layer 80 at a position corresponding to the fourth mark pattern 71. Thirdly, patterning the photoresist layer 80 with the fifth mark pattern 81 as a mark to form a first gate line structure pattern at a position of the photoresist layer 80 corresponding to the second mark pattern 30 and the support mark pattern 40. Afterwards, transferring the first gate line structure pattern to the hard mask layer 70 to obtain a second gate line structure pattern, and transferring the second gate line structure pattern to the second insulating layer 60, the first insulating layer 50 and the first stacked structure 130 in sequence; finally, forming the first gate line structure 104 on the first stacked structure 130 and removing the photoresist layer and the hard mask layer.

[0108] In some embodiments, the fourth marking pattern 71 includes a first convex portion 711 and a first concave portion 712, wherein the first convex portion 711 is opposite to the convex portion 611, and the first concave portion 712 is opposite to the concave portion 612. The fifth marking pattern 81 includes a second convex portion 811 and a second concave portion 812, wherein the second convex portion 811 is opposite to the first convex portion 711, and the second concave portion 812 is opposite to the first concave portion 712.

[0109] In some embodiments, while forming multiple first channel structures 10 in the first stacked structure 130, it also includes: forming a second gate line structure 105 in the core area 101 that penetrates the second insulating layer 60, the first insulating layer 50 and the first stacked structure 130; and forming a third gate line structure 106 in the connection area 102 that penetrates the second insulating layer 60, the first insulating layer 50 and the first stacked structure 130.

[0110] Step S7, see Figure 1 , Figure 8 and Figures 16 to 19 , at least a portion of the initial insulating layer 13 is replaced with the gate electrode layer 12 to obtain a first stacked structure 110 and a semiconductor device 100 (a first semiconductor structure 1001 ).

[0111] In some embodiments, step S7 includes: first, refer to Fig.16 and Fig.17 , remove part of the initial insulating layer 13 in the connection area 102 and the cutting road area 103 to obtain a first cavity 131; secondly, refer to Fig.18 , filling the first cavity 131 with semiconductor material to form an initial semiconductor layer 14; again, refer to Fig.19 , remove the initial semiconductor layer 14 and the initial insulating layer 13 located in the core area 101 to obtain a second cavity 133; then, refer to Figure 1 , a gate electrode material is filled in the second cavity 133 to form a gate electrode layer 12 .

[0112] See also Fig. 20 The present application also provides a memory system 1000, which includes one or more semiconductor devices 100 / 200 / 300 and a controller 400 as described above. The controller 400 is connected to the semiconductor device 100 / 200 / 300, and the controller 400 is configured to control the semiconductor device 100 / 200 / 300.

[0113] The memory system 1000 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. The controller may be configured to control operations of the semiconductor device, such as read, erase, and program operations.

[0114] In some embodiments, the controller is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0115] In some embodiments, the controller is designed to operate in a high duty cycle environment Solid State Disk (SSD) or Embedded Multi Media Card (eMMC), which is used as data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.

[0116] The semiconductor device and its manufacturing method and memory system provided by the present application form a first mark pattern, a second mark pattern and a support mark pattern by using a plurality of first channel structures located in a stacked structure, and the support mark pattern surrounds the second mark pattern, and the first mark pattern is located on one side of the support mark pattern. The first channel structure can support the stacked structure in the step of removing the initial oxide layer (silicon nitride film layer) so that it does not collapse.

[0117] In addition, since the marking structure of the semiconductor device provided in the application is formed by arranging the channel structure in the stacked structure, the marking structure can be completely retained during the removal of the initial oxide layer (silicon nitride film layer), and the process is simple and the cost is low.

[0118] In addition, a first insulating layer is first formed on a first stacked structure having a first channel structure (for forming a marking structure), a first marking pattern is exposed by patterning the first insulating layer, and a second insulating layer is formed on the first insulating layer, and part of the second insulating layer is filled in a gap between two adjacent first channel structures of the first marking pattern, thereby forming a third marking pattern on the second insulating layer. The third marking pattern can be used as a mark for subsequently forming a gate line structure, so that after development inspection (ADI) and after etching inspection (AEI, also called overlay measurement) can be achieved.

[0119] In summary, although the present application has been disclosed as above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Ordinary technicians in this field can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined in the claims.

Claims

1. A semiconductor device comprising a first semiconductor structure, characterized in that: The first semiconductor structure comprises: stacked structure; and A marking structure, located in the stacking structure; Wherein, the marking structure includes a plurality of first channel structures, a portion of the first channel structures among the plurality of the first channel structures constitute a first marking pattern, another portion of the first channel structures among the plurality of the first channel structures constitute a second marking pattern, and another portion of the first channel structures among the plurality of the first channel structures constitute a supporting marking pattern, the supporting marking pattern surrounds the second marking pattern, and the first marking pattern is located on one side of the supporting marking pattern.

2. The semiconductor device according to claim 1, wherein The first semiconductor structure further comprises: A first insulating layer is located on one side of the stacked structure; the first insulating layer covers the support mark pattern and the second mark pattern, and the orthographic projection of the first insulating layer on the stacked structure falls on the periphery of the first mark pattern; and a second insulating layer; a portion of the second insulating layer is located on a side of the first insulating layer away from the stacking structure, and another portion of the second insulating layer covers an end of the first channel structure in the first marking pattern close to the first insulating layer.

3. The semiconductor device according to claim 2, wherein: There is a gap between two adjacent first channel structures; The second insulating layer includes a third marking pattern, and the third marking pattern includes a convex portion and a concave portion adjacent to the convex portion; The orthographic projection of one of the protrusions on the stacked structure at least partially overlaps with one of the first channel structures of the first marking pattern, and the orthographic projection of the concave portion on the stacked structure at least partially overlaps with the gap of the first marking pattern.

4. The semiconductor device according to claim 2, wherein: The stacked structure, the first insulating layer and the second insulating layer are stacked in a first direction; A second direction and a third direction perpendicular to the first direction are used as the X-axis and Y-axis of the two-dimensional coordinate system respectively, and the marking structure is divided into four quadrants; in one of the quadrants, a first marking pattern and a second marking pattern are adjacently arranged along the first direction or the second direction, and in the arrangement direction of the first marking pattern and the second marking pattern, the first marking pattern is closer to the X-axis or the Y-axis than the second marking pattern.

5. The semiconductor device according to claim 4, wherein: The first mark pattern includes a first mark group; each of the first mark groups includes a plurality of first sub-mark groups, and each of the first sub-mark groups includes a plurality of first channel structures arranged in an array.

6. The semiconductor device according to claim 5, characterized in that Two adjacent first marking groups are L-shaped, the first sub-marking groups in one of the two adjacent first marking groups are arranged along the X-axis, and the first sub-marking groups in the other of the two adjacent first marking groups are arranged along the Y-axis.

7. The semiconductor device according to claim 5, characterized in that Each of the second mark patterns includes a plurality of second mark groups, each of the second mark groups includes a plurality of second sub-mark groups arranged along the first direction or the second direction, and each of the second sub-mark groups includes a plurality of the first channel structures arranged in an array; Wherein, in one of the quadrants, an arrangement direction of the second sub-marking group in the second marking group is the same as an arrangement direction of the first sub-marking group in the first marking group.

8. The semiconductor device according to claim 7, wherein: In one of the quadrants, and in the arrangement direction of the first mark group and the second mark group, one of the second sub-mark groups is opposite to the gap between two adjacent first sub-mark groups; In the arrangement direction of the first sub-mark groups, the outermost first sub-mark group is opposite to the gap between the support mark pattern and a second sub-mark group adjacent to the support mark pattern.

9. The semiconductor device according to claim 5, characterized in that The first insulating layer includes a first insulating portion and a second insulating portion, the first insulating portion covers the second marking pattern and the supporting marking pattern, the second insulating portion extends from the first insulating portion, and the orthographic projection of the second insulating portion on the stacking structure is located between the first marking pattern and the supporting marking pattern.

10. The semiconductor device according to claim 9, wherein: In one of the quadrants, a plurality of the second insulating portions are arranged at intervals, and an orthographic projection of the second insulating portion on the stacked structure is arranged opposite to the first sub-mark group.

11. The semiconductor device according to claim 7 or 8, characterized in that The first semiconductor structure further comprises: A first gate line structure, located in the stacked structure and passing through the second insulating layer, the first insulating layer and the stacked structure; The plurality of first gate line structures constitute a plurality of first gate line structure groups, and the orthographic projection of each of the first gate line structure groups on the stacked structure is located between two adjacent second sub-marking groups or between the second sub-marking group and the supporting mark pattern.

12. The semiconductor device according to claim 11, wherein A plurality of the first gate line structures in one first gate line structure group are arranged along the first direction or the second direction.

13. The semiconductor device according to claim 11, wherein The stacking structure comprises a core area, a connection area and a cutting road area; the connection area is located at one side of the core area, the cutting road area is located at a side of the connection area away from the core area, and the marking structure is located at the cutting road area; Among them, the first semiconductor structure also includes a second gate line structure and a third gate line structure, the second gate line structure and the third gate line structure are located in the stacked structure and penetrate the second insulating layer, the first insulating layer and the stacked structure, the second gate line structure is located in the core area, and the third gate line structure is located in the connection area.

14. The semiconductor device according to claim 13, wherein: The first insulating layer also covers the core area and the connection area.

15. The semiconductor device according to claim 2, wherein: The stacked structure comprises a gate electrode layer and a dielectric layer, and the gate electrode layer and the dielectric layer are alternately arranged in a stacking direction of the stacked structure and the first insulating layer; Wherein, the first insulating layer is located on a side of one of the dielectric layers away from the gate electrode layer; the marking structure is located in the stacked structure and penetrates the gate electrode layer and the dielectric layer along the stacking direction; The second insulating layer is also connected to a portion of the dielectric layer connected to the first insulating layer and a portion of the gate electrode layer closest to the first insulating layer in the stacking direction.

16. The semiconductor device according to claim 15, wherein: The first semiconductor structure further comprises: The top selection gate is located in the first insulating layer and is spaced apart from the gate electrode layer by the dielectric layer.

17. The semiconductor device according to claim 1, wherein The stacked structure, the first insulating layer and the second insulating layer are stacked in a first direction; The semiconductor device further includes a second semiconductor structure having a circuit element for controlling the first semiconductor structure and located on one side of the first semiconductor structure; The second semiconductor structure is bonded to the first semiconductor structure in the first direction.

18. A method for preparing a semiconductor device, characterized in that: include: forming a first stacking structure; and A plurality of first channel structures are formed in the first stacking structure, and a portion of the first channel structures are arranged into a first marking pattern, another portion of the first channel structures are arranged into a second marking pattern, and another portion of the first channel structures constitute a supporting marking pattern, the supporting marking pattern surrounds the second marking pattern, the first marking pattern is located on one side of the supporting marking pattern, and the first marking pattern, the second marking pattern and the supporting marking pattern constitute a marking structure.

19. The method for preparing a semiconductor device according to claim 18, wherein: The first channel structure extends along a first direction; Each of the second mark patterns includes a plurality of second mark groups, each of the second mark groups includes a plurality of second sub-mark groups arranged along a second direction or a third direction perpendicular to the first direction, and each of the second sub-mark groups includes a plurality of the first channel structures arranged in an array; After the step of forming a plurality of first channel structures in the first stacked structure, the method further includes the steps of: A first gate line structure is formed using the mark structure as a mark, and the first gate line structure is located in the first stacked structure, and the orthographic projection of the first gate line structure on the first stacked structure is located between two adjacent second sub-mark groups or between the second sub-mark group and the supporting mark pattern.

20. The method for preparing a semiconductor device according to claim 19, wherein: After the step of forming a plurality of first channel structures in the first stacked structure and before forming the first gate line structure, the method further includes: forming a first initial insulating layer on one side of the first stacking structure, and making the first initial insulating layer cover the marking structure; wherein the first initial insulating layer and the first stacking structure are stacked in the first direction; Patterning the first initial insulating layer to obtain a first insulating layer, and making one end of each of the first channel structures corresponding to the first marking pattern exposed from the first insulating layer; and A second insulating layer is formed on a side of the first insulating layer away from the first stacking structure, and the second insulating layer covers an end of the first channel structure in the first marking pattern close to the first insulating layer.

21. The method for preparing a semiconductor device according to claim 20, wherein: A third marking pattern is formed on the second insulating layer at a position corresponding to the first marking pattern; The step of forming the first gate line structure includes: forming a hard mask layer on the second insulating layer, wherein a fourth mark pattern is formed on the hard mask layer at a position corresponding to the third mark pattern; forming a photoresist layer on the hard mask layer; forming a fifth mark pattern corresponding to the fourth mark pattern at a position of the photoresist layer corresponding to the fourth mark pattern; The photoresist layer is patterned with the fifth mark pattern as a mark, so as to form a first gate line structure pattern at a position of the photoresist layer corresponding to the second mark pattern and the support mark pattern; Transferring the first gate line structure pattern onto the hard mask layer to obtain a second gate line structure pattern, and sequentially transferring the second gate line structure pattern onto the second insulating layer, the first insulating layer and the first stacked structure; and The first gate line structure is formed on the first stacked structure, and the photoresist layer and the hard mask layer are removed.

22. The method for preparing a semiconductor device according to claim 20, wherein: In the step of patterning the first initial insulating layer, the first insulating layer includes a first insulating portion and a second insulating portion, the first insulating portion covers the second marking pattern and the supporting marking pattern, the second insulating portion extends from the first insulating portion, and the orthographic projection of the second insulating portion on the stacking structure is located between the first marking pattern and the supporting marking pattern.

23. The method for preparing a semiconductor device according to claim 20, characterized in that: The first stacking structure includes a core area, a connection area and a cutting road area; the connection area is located at one side of the core area, and the cutting road area is located at a side of the connection area away from the core area; In the step of forming a plurality of first channel structures in the first stacked structure, the marking structure is located in the scribe line region; While forming a plurality of first channel structures in the first stacked structure, the method further includes: forming a second gate line structure in the core area that penetrates the second insulating layer, the first insulating layer and the first stacked structure; A third gate line structure is formed in the connection region and penetrates the second insulating layer, the first insulating layer and the first stacked structure.

24. A memory system, characterized in that: include: At least one semiconductor device according to any one of claims 1 to 19; and A controller is configured to control the semiconductor device.

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