Chip packaging structure and manufacturing method thereof

Abstract

The invention discloses a chip packaging structure and a manufacturing method thereof. The chip packaging structure comprises a substrate, a first chip, an insulating layer and a plurality of wiring layers. The substrate has a first metal pad and a second metal pad. The first chip is disposed on the first metal pad. The insulating layer is disposed on the substrate and partially covers the first metal pad, the second metal pad and the first chip. The plurality of wiring layers are arranged on the substrate and electrically connected with the first metal pad, the second metal pad and the first chip. The problem that the ceramic substrate is warped and deformed through a high-temperature process is solved by using an insulating material as a buffer structure of ceramic packaging, stress generated by existing routing is eliminated by using a graphic design that a conductive circuit is formed by electro-coppering, the elasticity of circuit design is increased, and the packaging structure achieves better reliability.

Description

Technical Field

[0001] The present application relates to a packaging structure and a manufacturing method thereof, and in particular to a chip packaging structure and a manufacturing method thereof. Background Art

[0002] At present, the packaging structure of power components generally uses aluminum as the pad for welding with metal wires during the wire bonding process. However, as the power and reliability requirements of power components become higher and higher, the use of traditional aluminum pads and metal wires for welding is prone to excessive stress. In addition, high-power components are prone to warping of ceramic substrates in high-temperature environments, resulting in poor contact between the chip and the ceramic substrate, which in turn affects the reliability and life of the packaging structure.

[0003] Therefore, how to overcome the above-mentioned defects through improvement of structural design has become one of the important issues to be solved in this field. Summary of the invention

[0004] The present application provides a chip packaging structure and a manufacturing method thereof, so as to solve the problems in the prior art that the ceramic substrate of the packaging structure of the power component is prone to warping and the conductive circuit is subjected to excessive stress during wiring.

[0005] In order to solve the above technical problems, one of the technical solutions adopted in the present application is to provide a chip packaging structure, which includes a substrate, a first chip, an insulating layer and a plurality of wiring layers. The substrate has a first metal pad and a second metal pad. The first chip is arranged on the first metal pad. The insulating layer is arranged on the substrate and partially covers the first metal pad, the second metal pad and the first chip. The plurality of wiring layers are arranged on the substrate and electrically connect the first metal pad, the second metal pad and the first chip.

[0006] In order to solve the above-mentioned technical problems, another technical solution adopted in the present application is to provide a method for manufacturing a chip packaging structure, which includes: providing a substrate, the substrate having a first metal pad and a second metal pad; arranging a chip on the first metal pad; forming an insulating layer on the substrate, the insulating layer covering the first metal pad, the second metal pad and the chip; forming a plurality of openings in the insulating layer through an etching process to expose the first metal pad, the second metal pad and a portion of the chip; forming a photoresist layer through a lithography process to cover a portion of the insulating layer, the first metal pad, the second metal pad and the substrate; forming a plurality of wiring layers through an electroplating process to cover the portions of the insulating layer, the first metal pad, the second metal pad and the substrate that are not covered by the photoresist layer, and filling the plurality of openings.

[0007] One of the beneficial effects of the present application is that the chip packaging structure and the manufacturing method thereof provided by the present application can solve the problem of warping and deformation of the ceramic substrate caused by high-temperature process by using insulating materials as a buffer structure of the ceramic package through the technical solutions of "an insulating layer is arranged on the substrate and partially covers the first metal pad, the second metal pad and the first chip" and "multiple wiring layers are arranged on the substrate and electrically connect the first metal pad, the second metal pad and the first chip", and use the graphic design of the conductive circuit formed by electroplating copper to eliminate the stress generated by the existing wiring, increase the flexibility of the circuit design, and make the packaging structure achieve better reliability.

[0008] To further understand the features and technical contents of the present application, please refer to the following detailed description and drawings of the present application. However, the drawings provided are only for reference and illustration and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a schematic cross-sectional view of the chip packaging structure of the first embodiment of the present application.

[0010] Figure 2 It is a cross-sectional schematic diagram of another implementation aspect of the chip packaging structure of the first embodiment of the application.

[0011] Figure 3 It is a schematic cross-sectional view of a chip packaging structure according to a second embodiment of the present application.

[0012] Figure 4 It is a cross-sectional schematic diagram of another implementation aspect of the chip packaging structure of the second embodiment of the present application.

[0013] Figures 5 to 10 It is a schematic diagram of the steps of the method for manufacturing the chip packaging structure of the present application.

[0014] Fig.11 This is a flow chart of a method for manufacturing a chip packaging structure of the present application.

[0015] Fig.12 It is a schematic cross-sectional view of a chip packaging structure according to the third embodiment of the present application.

[0016] Fig.13 It is an equivalent circuit diagram of the chip packaging structure of the third embodiment of the present application.

[0017] Fig.14 It is a front view schematic diagram of a chip packaging structure according to a fourth embodiment of the present application.

[0018] Fig.15 It is an equivalent circuit diagram of the chip packaging structure of the fourth embodiment of the present application. DETAILED DESCRIPTION

[0019] The following is an explanation of the implementation methods of the "chip packaging structure and its manufacturing method" disclosed in this application through specific embodiments. Those skilled in the art can understand the advantages and effects of this application from the contents disclosed in this specification. This application can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed based on different viewpoints and applications without deviating from the concept of this application. In addition, the drawings of this application are only simple schematic illustrations and are not depicted according to actual sizes. It is stated in advance. The following implementation methods will further explain the relevant technical contents of this application in detail, but the disclosed contents are not intended to limit the scope of protection of this application.

[0020] It should be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are mainly used to distinguish one element from another element. In addition, the term "or" used herein may include any one or more combinations of the associated listed items depending on the actual situation.

[0021] First embodiment

[0022] See also Figure 1 As shown, Figure 1 Schematic cross-sectional view of the chip packaging structure of the first embodiment of the present application. The first embodiment of the present application provides a chip packaging structure M, which includes a substrate 1, a first chip 21, an insulating layer 3 and a plurality of wiring layers 4. The substrate 1 has a first metal pad 11 and a second metal pad 12. The first chip 21 is disposed on the first metal pad 11. The insulating layer 3 is disposed on the substrate 1 and partially covers the first metal pad 11, the second metal pad 12 and the first chip 21. The plurality of wiring layers 4 are disposed on the substrate 1 and electrically connect the first metal pad 11, the second metal pad 12 and the first chip 21.

[0023] For example, the substrate 1 may be a ceramic substrate. The first chip 21 may be a power semiconductor chip, such as a metal oxide semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT). The material of the insulating layer 3 may be a photosensitive and thermosetting insulating material. The material of the wiring layer 4 may be a metal material, such as copper.

[0024] Specifically, the first chip 21 is arranged on the first metal pad 11 in a chip first / die face up manner. The insulating layer 3 is coated on the upper surface area of ​​the substrate 1 through an exposure lithography process, and is exposed through an etching or cutting process to expose a portion of the first chip 21, the first metal pad 11 and the second metal pad 12, that is, to open up the bonding area between the first chip 21 and the substrate 1. The thickness of the insulating layer 3 can be selected according to the required dielectric strength. Optionally, in the present application, the dielectric strength of the insulating layer 3 is greater than 100V / m, so the thickness of the insulating layer 3 is between 0.5μm and 200μm.

[0025] In addition, the wiring layer 4 is formed on the insulating layer 3 by copper electroplating, and is electrically connected to the exposed first chip 21, the first metal pad 11 and the second metal pad 12. It should be noted that before forming the wiring layer 4, a photoresist layer is first formed on the surface of the insulating layer 3 area that does not require electroplating to prevent the electroplating solution from electroplating in unnecessary areas. The thickness of the electroplated layer, that is, the thickness of the wiring layer 4, can be calculated by calculating the fusing current. The fusing current refers to the maximum current that can pass through the wire when it is fused. Optionally, the thickness of the wiring layer 4 is between 30μm and 300μm.

[0026] In advanced packaging processes, many different types of components usually need to be sealed on the same substrate, so the substrate is prone to warping and deformation due to the high temperature of reflow soldering. The present application forms a photosensitive and thermosetting insulating layer 3 as a buffer structure of the substrate 1 in a pre-molding manner, which can reduce the probability of the substrate 1 being warped and deformed due to the high temperature of the process. In addition, the present application forms a conductive circuit pattern by electroplating copper, replacing the prior art of welding with aluminum pads and metal wires, thereby eliminating the stress generated by traditional wire bonding on the chip surface. By electroplating conductive circuit patterns, the flexibility of circuit design can be increased and the reliability of the packaging structure can be improved.

[0027] See also Figure 2 As shown, Figure 2 FIG. 2 is a cross-sectional schematic diagram of another embodiment of the chip packaging structure of the first embodiment of the present application. The chip packaging structure M further includes a packaging body 5, which at least partially covers the substrate 1, the first chip 21, the insulating layer 3 and the plurality of wiring layers 4. The packaging body 5 may be, for example, a liquid compound or a molding compound, which is not limited in the present application.

[0028] Second embodiment

[0029] See also Figure 3 and Figure 4As shown, Figure 3 is a schematic cross-sectional view of a chip packaging structure according to a second embodiment of the present application, Figure 4 This is a cross-sectional schematic diagram of another implementation of the chip packaging structure of the second embodiment of the present application. The second embodiment of the present application provides a chip packaging structure M, which includes a substrate 1, a first chip 21, an insulating layer 3 and a plurality of wiring layers 4. The chip packaging structure M of the second embodiment of the present application is similar to the structure of the first embodiment, and the similarities are not repeated here. Specifically, the difference between the second embodiment and the first embodiment is that the chip packaging structure M of the second embodiment has at least one opening 30 in the insulating layer 3, so that the first chip 21 and the second metal pad 12 are exposed. The present application is not limited to the number of openings 30. As Figure 4 As shown, the chip package structure M can be welded to the package support LF through at least one opening 30, so that the components (such as the first chip 21 and the second metal pad 12) in the chip package structure M are electrically connected to other external components. Therefore, the chip package structure M provides more design flexibility for the needs of subsequent processes by forming at least one opening 30 in the insulating layer 3 as a reserved welding area.

[0030] See also Figures 5 to 10 ,as well as Fig.11 As shown, Figures 5 to 10 Schematic diagram of the steps of the method for manufacturing the chip packaging structure of the present application. Fig.11 Flow chart of the manufacturing method of the chip packaging structure of the present application. The present application provides a manufacturing method of a chip packaging structure, which can be used to manufacture the chip packaging structure M described in the first and second embodiments. The manufacturing method comprises at least the following steps:

[0031] Step S11: providing a substrate 1, wherein the substrate 1 has a first metal pad 11 and a second metal pad 12;

[0032] Step S12: placing a chip 21 on the first metal pad 11;

[0033] Step S13: forming an insulating layer 3 on the substrate 1, the insulating layer 3 covers the first metal pad 11, the second metal pad 12 and the chip 21;

[0034] Step S14: forming a plurality of openings 30 in the insulating layer 3 through an etching process, so that the first metal pad 11, the second metal pad 12 and a portion of the chip 21 are exposed;

[0035] Step S15: forming a photoresist layer PR covering a portion of the insulating layer 3, the first metal pad 11, the second metal pad 12 and the substrate 1 through a lithography process; and

[0036] Step S16 : forming a plurality of wiring layers 4 by an electroplating process to cover the portion of the insulating layer 3 not covered by the photoresist layer PR and fill the plurality of openings 30 .

[0037] The substrate 1 may be a ceramic substrate, and the first chip 21 may be a power semiconductor chip, such as a metal oxide semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT). The material of the insulating layer 3 may be a photosensitive and thermosetting insulating material. The material of the wiring layer 4 may be a metal material, such as copper.

[0038] Specifically, the first chip 21 is arranged on the first metal pad 11 in a chip first / die face up manner. The insulating layer 3 is coated on the upper surface area of ​​the substrate 1 by an exposure lithography process, and a plurality of openings 30 are formed by an etching process to expose a portion of the first chip 21, the first metal pad 11 and the second metal pad 12. The function of the plurality of openings 30 is to open up the bonding area between the first chip 21 and the substrate 1, so that the external pin bracket can be electrically connected to the first chip 21, the first metal pad 11 and the second metal pad 12 through the plurality of openings 30. The thickness of the insulating layer 3 can be selected according to the required dielectric strength. Optionally, the dielectric strength of the insulating layer 3 is greater than 100V / m, so the thickness of the insulating layer 3 is between 0.5μm and 200μm.

[0039] The wiring layer 4 is formed on the insulating layer 3 by copper electroplating, and is electrically connected to the exposed first chip 21, the first metal pad 11 and the second metal pad 12. It should be noted that before forming the wiring layer 4, a photoresist layer is first coated on the surface of the insulating layer 3 area that does not require electroplating to prevent the plating solution from electroplating in unnecessary areas. The thickness of the electroplated layer, that is, the thickness of the wiring layer 4 can be calculated by calculating the fuse current, and the thickness of the wiring layer 4 can be adjusted according to the thickness of the photoresist layer PR. Optionally, the thickness of the wiring layer 4 is between 30μm and 300μm. After forming the wiring layer 4, the photoresist layer PR can be removed to obtain Figure 1 The chip packaging structure M is shown.

[0040] Step S17 : forming a package body 5 to at least partially cover the substrate 1 , the chip 21 , the insulating layer 3 and the plurality of wiring layers 4 .

[0041] After forming the substrate 1, the first chip 21, the insulating layer 3 and the plurality of wiring layers 4, the chip package structure M can further form a package body 5 to at least partially cover the substrate 1, the chip 21, the insulating layer 3 and the plurality of wiring layers 4 to enhance the overall structural strength.

[0042] Third embodiment

[0043] See also Fig.12 and Fig.13 As shown, Fig.12 This is a cross-sectional schematic diagram of a chip packaging structure according to a third embodiment of the present application. Fig.13 : is an equivalent circuit diagram of the chip packaging structure of the third embodiment of the present application. The third embodiment of the present application provides a chip packaging structure M, which can be manufactured by the above-mentioned manufacturing method. The chip packaging structure M provided by the third embodiment includes a substrate 1, a first chip 21, an insulating layer 3 and a plurality of wiring layers 4. The chip packaging structure M of the third embodiment of the present application is similar to the structure of the first embodiment, and the similarities are not repeated here.

[0044] Specifically, the chip package structure M of the third embodiment further includes a second chip 22, the second chip 22 is disposed on the second metal pad 12, and the plurality of wiring layers 4 are further electrically connected to the second chip 22. In other words, the present application is not limited by the number of chips. The second chip 22 and the first chip 21 are power semiconductor chips of the same type, such as metal oxide semiconductor field effect transistors (MOSFETs) or insulated gate bipolar transistors (IGBTs).

[0045] For example, the chip package structure M of the third embodiment can be further formed into a half-bridge structure and applied to the architecture of a power inverter. Fig.12 and Fig.13 As shown, the plurality of wiring layers 4 include a first conductive circuit 41, a second conductive circuit 42, a third conductive circuit 43, a fourth conductive circuit 44 and a fifth conductive circuit 45. The first conductive circuit 41 is electrically connected to the first metal pad 11, the second conductive circuit 42 is electrically connected to the first chip 21, the third conductive circuit 43 is electrically connected to the first chip 21 and the second metal pad 12, and the fourth conductive circuit 44 and the fifth conductive circuit 45 are electrically connected to the second chip 22.

[0046] The first chip 21 and the second chip 22 are P-channel metal oxide semiconductor field effect transistors. Fig.12 and Fig.13 As shown, one end of the first conductive line 41 can be electrically connected to the drain 211 of the first chip 21 through the first metal pad 11, and the other end of the first conductive line 41 can be electrically connected to the positive electrode of the external power supply unit (Power supply unit, PSU) (see Fig.13The second conductive line 42 is electrically connected to the gate 212 of the first chip 21. One end of the third conductive line 43 is electrically connected to the source 213 of the first chip 21, and the other end can be electrically connected to the drain 221 of the second chip 22 through the second metal pad 12. The fourth conductive line 44 is electrically connected to the gate 222 of the second chip 22. One end of the fifth conductive line 45 is electrically connected to the source 223 of the second chip 22, and the other end is electrically connected to the negative electrode of the voltage supply unit (see Fig.13 Vdc) in the electrical connection.

[0047] When the first chip 21 is turned on by applying an appropriate voltage, and the second chip 22 is turned off, the current flows as follows: Fig.13 When the first chip 21 is not turned on and the second chip 22 is turned on by applying an appropriate voltage, the current direction is as shown in FIG. Fig.13 The current direction is shown by D2.

[0048] It should be noted that the first chip 21 and the second chip 22 of the present application are illustrated by metal oxide semiconductor field effect transistors. When the first chip 21 and the second chip 22 are illustrated by insulated gate bipolar transistors (IGBTs), the drain of the chip is the collector, and the source of the chip is the emitter.

[0049] Fourth embodiment

[0050] See also Fig.14 and Fig.15 As shown, Fig.14 This is a top view of a chip packaging structure according to a fourth embodiment of the present application. Fig.15 : is an equivalent circuit diagram of the chip packaging structure of the fourth embodiment of the present application. The fourth embodiment of the present application provides a chip packaging structure M, which can be manufactured by the above-mentioned manufacturing method. The chip packaging structure M provided by the fourth embodiment includes a substrate 1, a first chip 21 and a plurality of wiring layers 4. The chip packaging structure M of the fourth embodiment of the present application is similar to the structure of the third embodiment, and the similarities are not repeated here.

[0051] Specifically, the chip package structure M of the fourth embodiment further includes a second chip 22, a third chip 23 and a fourth chip 24, and the substrate 1 further includes a third metal pad 13, a fourth metal pad 14 and a fifth metal pad 15. The second chip 22 and the fourth chip 24 are disposed on the second metal pad 12, and the third chip 23 is disposed on the first metal pad 11. The third metal pad 13, the fourth metal pad 14 and the fifth metal pad 15 surround the first metal pad 11 and the second metal pad 12, and the plurality of wiring layers 4 are further electrically connected to the second chip 22, the third chip 23, the fourth chip 24, the third metal pad 13, the fourth metal pad 14 and the fifth metal pad 15.

[0052] For example, the chip package structure M of the fourth embodiment can be further formed into a full-bridge structure and applied to the architecture of a power inverter. Fig.14 and Fig.15 As shown, the plurality of wiring layers 4 include a first conductive line 41, a second conductive line 42, a third conductive line 43, a fourth conductive line 44, a fifth conductive line 45 and a sixth conductive line 46. The first conductive line 41 is electrically connected to the first metal pad 11. The second conductive line 42 is electrically connected to the first chip 21 and the fifth metal pad 15. The third conductive line 43 is electrically connected to the first chip 21 and the second metal pad 12. The fourth conductive line 44 is electrically connected to the second chip 22, the fourth chip 24 and the third metal pad 13. The fifth conductive line 45 is electrically connected to the third chip 23 and the second metal pad 12. The sixth conductive line 46 is electrically connected to the third chip 23, the fourth chip 24 and the fourth metal pad 14.

[0053] The first chip 21, the second chip 22, the third chip 23 and the fourth chip 24 are exemplified as P-channel metal oxide semi-conductor field effect transistors. Fig.14 and Fig.15 As shown, the first conductive circuit 41 is electrically connected to the drain 211 of the first chip 21 and the drain 231 of the third chip 23, and is electrically connected to the positive electrode of the external voltage supply unit (see Fig.15 The second conductive line 42 is electrically connected to the gate 212 of the first chip 21 and the gate 222 of the second chip 22. One end of the third conductive line 43 is electrically connected to the source 213 of the first chip 21, and the other end is electrically connected to the drain 221 of the second chip 22 (through the second metal pad 12). The fourth conductive line 44 is electrically connected to the source 223 of the second chip 22 and the source 243 of the fourth chip 24. One end of the fifth conductive line 45 is electrically connected to the source 233 of the third chip 23, and the other end is electrically connected to the drain 241 of the fourth chip 24 (through the second metal pad 12). The sixth conductive line 46 is electrically connected to the gate 232 of the third chip 23 and the gate 242 of the fourth chip 24.

[0054] When the first chip 21 and the second chip 22 are turned on by applying appropriate voltage, and the third chip 23 and the fourth chip 24 are turned off, the current flow is as follows: Fig.15 When the first chip 21 and the second chip 22 are not turned on, and the third chip 23 and the fourth chip 24 are turned on by applying appropriate voltage, the current direction is as shown in FIG. Fig.15 The current direction is shown by D4.

[0055] Advantageous Effects of Embodiments

[0056] In advanced packaging processes, it is usually necessary to seal many different types of components on the same substrate, so the substrate is prone to warping and deformation due to the high temperature of reflow soldering. The present application forms a photosensitive and thermosetting insulating layer 3 as a buffer structure of the substrate 1 in a pre-molding manner, which can reduce the probability of the substrate 1 being warped and deformed due to the high temperature of the process. In addition, the present application replaces the welding of aluminum pads and metal wires in the prior art by electroplating copper to form a conductive circuit pattern, thereby eliminating the stress generated by traditional wire bonding on the chip surface, and further improving the packaging density and heat dissipation performance of the packaging structure. By electroplating the conductive circuit pattern, the flexibility of the circuit design can be increased and the reliability of the packaging structure can be improved. In addition, the chip packaging structure M provides more design flexibility for the needs of subsequent processes by forming at least one opening 30 in the insulating layer 3 as a reserved welding area.

[0057] The contents disclosed above are only optional feasible embodiments of the present application, and are not intended to limit the protection scope of the claims of the present application. Therefore, all equivalent technical changes made using the contents of the present application specification and drawings are included in the protection scope of the claims of the present application.

Claims

1. A chip packaging structure, characterized in that: The chip packaging structure comprises: A substrate having a first metal pad and a second metal pad; a first chip, disposed on the first metal pad; an insulating layer, disposed on the substrate and partially covering the first metal pad, the second metal pad and the first chip; and A plurality of wiring layers are disposed on the substrate and electrically connect the first metal pad, the second metal pad and the first chip.

2. The chip packaging structure according to claim 1, characterized in that: The material of the plurality of wiring layers is a metal material.

3. The chip packaging structure according to claim 2, characterized in that: The thickness of the wiring layers is between 30 μm and 300 μm.

4. The chip packaging structure according to claim 1, characterized in that: The material of the insulating layer is photosensitive and thermosetting insulating material.

5. The chip packaging structure according to claim 4, characterized in that: The thickness of the insulating layer is between 0.5 μm and 200 μm.

6. The chip packaging structure according to claim 4, characterized in that: The dielectric strength of the insulating layer is greater than 100 V / m.

7. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure further includes a packaging body, which at least partially covers the substrate, the first chip, the insulating layer and the plurality of wiring layers.

8. The chip packaging structure according to claim 1, characterized in that: The insulating layer has at least one opening to expose the first chip and the second metal pad.

9. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure also includes a second chip disposed on the second metal pad, and the plurality of wiring layers are further electrically connected to the second chip.

10. The chip packaging structure according to claim 9, characterized in that: The multiple wiring layers include a first conductive circuit, a second conductive circuit, a third conductive circuit, a fourth conductive circuit and a fifth conductive circuit, the first conductive circuit is electrically connected to the first metal pad, the second conductive circuit is electrically connected to the first chip, the third conductive circuit is electrically connected to the first chip and the second metal pad, and the fourth conductive circuit and the fifth conductive circuit are electrically connected to the second chip.

11. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure also includes a second chip, a third chip and a fourth chip, and the substrate also includes a third metal pad, a fourth metal pad and a fifth metal pad. The second chip and the fourth chip are arranged on the second metal pad, and the third chip is arranged on the first metal pad. The third metal pad, the fourth metal pad and the fifth metal pad surround the first metal pad and the second metal pad, and the multiple wiring layers are further electrically connected to the second chip, the third chip, the fourth chip, the third metal pad, the fourth metal pad and the fifth metal pad.

12. The chip packaging structure according to claim 11, characterized in that: The multiple wiring layers include a first conductive circuit, a second conductive circuit, a third conductive circuit, a fourth conductive circuit, a fifth conductive circuit and a sixth conductive circuit, the first conductive circuit is electrically connected to the first metal pad, the second conductive circuit is electrically connected to the first chip and the fifth metal pad, the third conductive circuit is electrically connected to the first chip and the second metal pad, the fourth conductive circuit is electrically connected to the second chip, the fourth chip and the third metal pad, the fifth conductive circuit is electrically connected to the third chip and the second metal pad, and the sixth conductive circuit is electrically connected to the third chip, the fourth chip and the fourth metal pad.

13. A method for manufacturing a chip packaging structure, characterized in that: The manufacturing method of the chip packaging structure comprises: Providing a substrate, the substrate having a first metal pad and a second metal pad; Disposing a first chip on the first metal pad; forming an insulating layer on the substrate, wherein the insulating layer covers the first metal pad, the second metal pad and the first chip; Forming a plurality of openings in the insulating layer through an etching process to expose the first metal pad, the second metal pad and a portion of the first chip; forming a photoresist layer covering a portion of the insulating layer, the first metal pad, the second metal pad and the substrate through a lithography process; and A plurality of wiring layers are formed by an electroplating process to cover the portion of the insulating layer not covered by the photoresist layer and fill the plurality of openings.

14. The method for manufacturing a chip packaging structure according to claim 13, characterized in that: The material of the plurality of wiring layers is copper.

15. The method for manufacturing a chip packaging structure according to claim 14, characterized in that: The thickness of the wiring layers ranges from 30 μm to 300 μm.

16. The method for manufacturing a chip packaging structure according to claim 13, characterized in that: The material of the insulating layer is photosensitive and thermosetting insulating material.

17. The method for manufacturing a chip packaging structure according to claim 16, characterized in that: The thickness of the insulating layer is between 0.5 μm and 200 μm.

18. The method for manufacturing a chip packaging structure according to claim 16, characterized in that: The dielectric strength of the insulating layer is greater than 100 V / m.

19. The method for manufacturing a chip packaging structure according to claim 13, characterized in that: The manufacturing method of the chip packaging structure further includes: forming a packaging body to at least partially cover the substrate, the first chip, the insulating layer and the plurality of wiring layers.

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