Carrier synchronization method and system based on PWM period adjustment

Abstract

The invention discloses a carrier synchronization method and system based on PWM period adjustment, and relates to the technical field of photovoltaic and energy storage, and the method comprises the steps: adjusting DSP interrupt logic, and adjusting a carrier counting limit value in real time; determining an annular band width according to the carrier counting limit value; and the DSP signal after the PWM period is adjusted is used as a trigger pulse of a driving circuit to be given to an inverter, so that a parallel operation synchronization function is realized. According to the carrier synchronization method based on PWM period adjustment, the carrier counting value and the carrier counting direction are read in real time through a program, and the carrier counting peak value is dynamically adjusted. According to the method, the problem that the output voltage and current waveforms of the inverter are abnormal due to carrier distortion can be well solved.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic and energy storage technology, and in particular to a carrier synchronization method and system based on PWM cycle adjustment. Background Art

[0002] With the rapid growth of the photovoltaic and energy storage industries, multiple inverters are running in parallel in more and more scenarios. However, if the carrier signals of the inverter controllers are not synchronized, the system may generate large high-frequency circulating currents, thus affecting the stability of the system.

[0003] The existing carrier synchronization method will load the PWM comparison threshold after the program is executed in each interrupt cycle, forcing the PWM cycle to the count peak, resulting in carrier distortion. In addition, it will cause abnormally wide pulses, which will eventually make the voltage and current waveforms of the inverter output abnormal. Therefore, a new carrier synchronization method is urgently needed to solve the current problem. Summary of the invention

[0004] In view of the above-mentioned problems, the present invention is proposed.

[0005] Therefore, the technical problem solved by the present invention is: the existing carrier synchronization method is to forcibly modify the count value of the PWM control unit of the DSP according to the synchronization signal and synchronize it to the initial value of the phase register. When the initial value is forcibly modified, the waveform at that moment will be distorted. In the present invention, synchronization is achieved by adjusting the value of the period register. There is no operation of forcibly modifying the calculated value of the control unit, which can effectively improve the problem of abnormal output voltage and current waveform of the inverter caused by carrier distortion.

[0006] In order to solve the above technical problems, the present invention provides the following technical solutions: a carrier synchronization method based on PWM cycle adjustment, comprising:

[0007] Adjust DSP interrupt logic and adjust carrier count limit in real time;

[0008] Determine the ring width according to the carrier count limit;

[0009] The DSP signal after adjusting the PWM cycle is transmitted to the drive circuit to realize the parallel synchronization function.

[0010] As a preferred solution of the carrier synchronization method based on PWM cycle adjustment described in the present invention, wherein: the adjustment of DSP interrupt logic includes reading the current carrier count value CTR and carrier count direction DIR when the DSP program enters an interrupt cycle.

[0011] As a preferred scheme of the carrier synchronization method based on PWM cycle adjustment described in the present invention, wherein: the real-time adjustment of the carrier count limit includes reading the current carrier count value CTR and the carrier count direction DIR. When DIR=0, if CTR is greater than the bandwidth T0, the carrier count peak is reduced according to the first adjustment strategy.

[0012] As a preferred scheme of the carrier synchronization method based on PWM cycle adjustment described in the present invention, wherein: the real-time adjustment of the carrier count limit also includes reading the current carrier count value CTR and the carrier count direction DIR. When DIR=1, if it is found that CTR is greater than T0, the carrier count peak is increased according to the second adjustment strategy.

[0013] As a preferred solution of the carrier synchronization method based on PWM cycle adjustment described in the present invention, wherein: the determination of the loop width includes making the carrier count value CTR in each interrupt cycle within a preset loop width according to the carrier cycle after adjusting the carrier count limit.

[0014] As a preferred solution of the carrier synchronization method based on PWM cycle adjustment described in the present invention, wherein: the preset loop width is expressed as,

[0015] CTR∈(0,T 0 ).

[0016] As a preferred solution of the carrier synchronization method based on PWM cycle adjustment described in the present invention, wherein: the realization of the parallel synchronization function includes giving the DSP signal after adjusting the PWM cycle as a trigger pulse of the drive circuit to the inverter.

[0017] Another object of the present invention is to provide a carrier synchronization system based on PWM cycle adjustment, which can solve the problems of carrier asynchrony and high-frequency circulating current in the existing inverter parallel operation by constructing a carrier synchronization system based on PWM cycle adjustment, improve system stability and optimize the output voltage and current waveform problems.

[0018] To solve the above technical problems, the present invention provides the following technical solutions: a carrier synchronization system based on PWM cycle adjustment, comprising: a carrier count limit adjustment module, a loop width adjustment module and a carrier synchronization module; the carrier count limit adjustment module is used to adjust the DSP interrupt logic and adjust the carrier count limit in real time; the loop width adjustment module is used to determine the loop width according to the carrier count limit; the carrier synchronization module is used to transmit the DSP signal after the PWM cycle is adjusted to the drive circuit to realize the parallel synchronization function.

[0019] A computer device comprises a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of the carrier synchronization method based on PWM cycle adjustment as described above are implemented.

[0020] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the carrier synchronization method based on PWM cycle adjustment as described above.

[0021] Beneficial effects of the present invention: The carrier synchronization method based on PWM cycle adjustment provided by the present invention dynamically adjusts the carrier count peak value through the carrier count value and carrier count direction read in real time by the program. The method can well solve the problem of abnormal output voltage and current waveform of the inverter caused by carrier distortion. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0023] Figure 1 An overall flow chart of a carrier synchronization method based on PWM cycle adjustment provided by an embodiment of the present invention.

[0024] Figure 2 A flow chart of adjusting a carrier count limit value of a carrier synchronization method based on PWM cycle adjustment is provided in accordance with an embodiment of the present invention.

[0025] Figure 3 A carrier synchronization principle diagram of a carrier synchronization method based on PWM cycle adjustment provided by an embodiment of the present invention.

[0026] Figure 4 Another carrier synchronization principle diagram of a carrier synchronization method based on PWM cycle adjustment provided by an embodiment of the present invention.

[0027] Figure 5 A comparison diagram of carrier values ​​of a carrier synchronization method based on PWM cycle adjustment provided by an embodiment of the present invention.

[0028] Figure 6 A diagram showing the synchronization of trigger pulses between inverters in a carrier synchronization method based on PWM cycle adjustment provided by an embodiment of the present invention.

[0029] Figure 7A comparison diagram of experimental results of a carrier synchronization method based on PWM cycle adjustment provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0030] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the drawings of the specification. Obviously, the described embodiments are part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary persons in the art without creative work should fall within the scope of protection of the present invention.

[0031] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0032] Example 1, reference Figure 1-Figure 2 , as an embodiment of the present invention, provides a carrier synchronization method based on PWM cycle adjustment, comprising:

[0033] Step 1: Adjust the DSP interrupt logic and adjust the carrier count limit in real time, such as Figure 2 As shown;

[0034] When the DSP program enters an interrupt cycle, it reads the current carrier count value CTR and carrier count direction DIR, and adjusts the carrier count peak value in real time, such as Figure 1 As shown:

[0035]

[0036] As shown in formula (1), the program reads the current carrier count value CTR and the carrier count direction DIR. When DIR=0 (count decreases), if it is found that CTR is greater than the bandwidth T0, the carrier count peak value needs to be reduced; when DIR=1 (count increases), if it is found that CTR is less than the bandwidth T0, the carrier count peak value also needs to be reduced;

[0037]

[0038] As shown in formula (2), the program reads the current carrier count value CTR and the carrier count direction DIR. When DIR=0 (count decreases), if it is found that CTR is less than the bandwidth T0, the carrier count peak value needs to be increased; when DIR=1 (count increases), if it is found that CTR is greater than T0, the carrier count peak value also needs to be increased.

[0039] It should be noted that T0 represents the count value at the start time that can ensure system synchronization, which is a data range with an upper data limit and a lower data limit. The range adjusted in adjusting the carrier count limit is |CTR-T0|;

[0040] When the carrier count value CTR is within the range of T0, it means that the synchronization signal cycle is completely consistent with the interrupt cycle;

[0041] When the carrier count value CTR is greater than the upper limit of T0, it means that the interrupt cycle value is less than the synchronization signal cycle, and the CNT count limit needs to be increased according to the difference between CNT-T0;

[0042] When the carrier count value CTR is less than the lower limit of T0, it means that the interruption period value is greater than the synchronization signal period. It is necessary to reduce the CNT count limit value according to the difference between CNT-T0.

[0043] Step 2: According to the carrier count limit in the previous step, determine the appropriate ring width to ensure that the carrier count value of each interruption cycle falls within the ring width.

[0044] According to the carrier cycle adjusted in step 1, the carrier count value CTR in each interrupt cycle is within the loop width of 0-T0. Among them, the T0 loop width limit needs to be strictly tested. If it is set too small, synchronization will not be possible, and if it is too large, the synchronization effect will be poor:

[0045] CTR∈(0,T 0 )(3)

[0046] The ring width can be obtained through testing. By giving different values ​​and observing the consistency of the synchronization signal, a suitable value is selected, which is the same T0.

[0047] It should be noted that T0 is obtained through testing, and different T0 values ​​are set to observe the synchronization effect of the output signal to obtain the optimal value.

[0048] Step 3: The DSP signal after adjusting the PWM cycle is given to the inverter as the trigger pulse of the drive circuit to realize the parallel synchronization function.

[0049] By using the improved DSP program to judge the signal sent by the central government to adjust its own carrier cycle in time, the DSP signal after adjusting the PWM cycle is given to the inverter as the trigger pulse of the drive circuit, and the parallel synchronization function can be realized.

[0050] The value of the comparison counter is obtained through the calculation module and compared with the CTR count value. When the values ​​are equal, the output signal is level-inverted to generate a PWM signal, which is output as a drive signal.

[0051] Embodiment 2 is an embodiment of the present invention, which provides a carrier synchronization system based on PWM cycle adjustment, including:

[0052] Carrier count limit adjustment module, loop width adjustment module and carrier synchronization module;

[0053] The carrier count limit adjustment module is used to adjust the DSP interrupt logic and adjust the carrier count limit in real time;

[0054] The loop width adjustment module is used to adjust the loop width according to the carrier count limit;

[0055] The carrier synchronization module is used to transmit the DSP signal after adjusting the PWM period to the drive circuit to realize the parallel synchronization function.

[0056] Embodiment 3, an embodiment of the present invention, is different from the first two embodiments in that:

[0057] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc., which can store program codes.

[0058] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in conjunction with such instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in conjunction with such instruction execution systems, devices or apparatuses.

[0059] More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk case (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be a paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, deciphering or, if necessary, processing in another suitable manner, and then stored in a computer memory.

[0060] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0061] Example 4, reference Figure 3-Figure 7 , which is an embodiment of the present invention, provides a carrier synchronization method based on PWM cycle adjustment. In order to verify the beneficial effects of the present invention, scientific demonstration is carried out through simulation experiments.

[0062] Figure 3 and Figure 4 In the program, a DSP synchronization pulse is input to trigger an external interrupt. Each time an interrupt is triggered, the program reads the current carrier count value CTR and the carrier count direction DIR. When DIR=0 (count decreases), if CTR is found to be greater than the loop width T0, it means that the maximum loop width Tmax increases and the carrier count peak value needs to be reduced; when DIR=1 (count increases), if CTR is found to be greater than T0, it means that Tmax decreases and the carrier count peak value needs to be increased.

[0063] Figure 5 In the figure, CH1 is the carrier count value, and CH2 is the carrier cycle number. It can be seen that the carrier count value is stable within the loop width, and the carrier cycle is also stable, and there is no problem of carrier distortion.

[0064] Figure 6The trigger pulse synchronization between the two inverters under the carrier synchronization method with PWM cycle adjustment is shown in the figure. CH1 is the pulse trigger waveform of the first inverter, and CH3 is the pulse trigger waveform of the second inverter. When the DSP input signal is a 16kHz square wave signal, the pulse trigger time between the two inverters differs by only 170ns, accounting for 0.272% of the entire carrier cycle, achieving parallel carrier synchronization.

[0065] Attached Figure 7 The actual operation of two inverters in parallel under the carrier synchronization method with PWM cycle adjustment. CH1 is the output AC current of the first inverter, CH2 is the output AC current of the second inverter, CH3 is the AC voltage output by the inverter, and CH4 is the zero-sequence current waveform. From the voltage and current waveforms output by the two inverters, it can be seen that this improved carrier synchronization method is effective and the zero-sequence circulating current is very small.

[0066] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A carrier synchronization method based on PWM cycle adjustment, characterized in that: include: Adjust DSP interrupt logic and adjust carrier count limit in real time; Determine the ring width according to the carrier count limit; The DSP signal after adjusting the PWM period is transmitted to the drive circuit to realize the parallel synchronization function.

2. The carrier synchronization method based on PWM cycle adjustment as claimed in claim 1, characterized in that: The adjusting of the DSP interrupt logic includes reading the current carrier count value CTR and the carrier count direction DIR when the DSP program enters an interrupt cycle.

3. The carrier synchronization method based on PWM cycle adjustment as claimed in claim 2, characterized in that: The real-time adjustment of the carrier count limit includes reading the current carrier count value CTR and the carrier count direction DIR. When DIR=0, if CTR is greater than the bandwidth T0, the carrier count peak value is reduced according to the first adjustment strategy.

4. The carrier synchronization method based on PWM cycle adjustment as claimed in claim 3, characterized in that: The real-time adjustment of the carrier count limit value also includes reading the current carrier count value CTR and the carrier count direction DIR. When DIR=1, if it is found that CTR is greater than T0, the carrier count peak value is increased according to the second adjustment strategy.

5. The carrier synchronization method based on PWM cycle adjustment as claimed in claim 4, characterized in that: The determining of the loop width includes making the carrier count value CTR in each interruption cycle within a preset loop width according to the carrier cycle after adjusting the carrier count limit.

6. The carrier synchronization method based on PWM cycle adjustment as claimed in claim 5, characterized in that: The preset ring width is expressed as, CTR∈(0,T0).

7. The carrier synchronization method based on PWM cycle adjustment as claimed in claim 6, characterized in that: The implementation of the parallel synchronization function includes providing the DSP signal after adjusting the PWM period as a trigger pulse of the drive circuit to the inverter.

8. A system using the carrier synchronization method based on PWM cycle adjustment as claimed in any one of claims 1 to 7, characterized in that: include: Carrier count limit adjustment module, loop width adjustment module and carrier synchronization module; The carrier count limit adjustment module is used to adjust the DSP interrupt logic and adjust the carrier count limit in real time; The loop width adjustment module is used to adjust the loop width according to the carrier count limit; The carrier synchronization module is used to transmit the DSP signal after adjusting the PWM period to the drive circuit to realize the parallel synchronization function.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the carrier synchronization method based on PWM cycle adjustment according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the carrier synchronization method based on PWM cycle adjustment according to any one of claims 1 to 7 are implemented.

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