Oscillation circuit of MEMS resonator

Abstract

The invention provides an oscillating circuit of an MEMS resonator. A bias circuit provides direct current bias voltage and tail current source bias voltage of PMOS cross coupling pair transistors for a main oscillator core circuit; therefore, each branch in the main oscillator core circuit can be connected in series with only three transistors, and the three transistors can realize the function of generating oscillation sine wave signals by the main oscillator core circuit without stacking more transistors; the number of series transistors is small, the working voltage of the main oscillator core circuit is correspondingly reduced, the main oscillator core circuit can work in a low power supply voltage environment, the power consumption of the main oscillator core circuit is reduced, and in other words, the oscillation circuit of the MEMS resonator provided by the invention can improve the reliability of the MEMS resonator on the premise of ensuring low phase noise and providing the same negative resistance. Therefore, the power consumption of the oscillator is reduced, and the quality factor of the oscillator is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronics, and more specifically, particularly relates to an oscillation circuit of a MEMS resonator. Background Art

[0002] With the booming development of portable devices, the Internet of Things, and wearable technology, battery life and energy efficiency have become key indicators for measuring the performance of electronic devices. In these devices, oscillators are important components of integrated circuits, and their performance directly affects the stability and energy efficiency of the entire system. Therefore, how to reduce the power consumption of oscillators while maintaining low phase noise and stable frequency has become a hot topic in current research.

[0003] Traditionally, LC oscillators are widely used in various electronic devices. However, with the advancement of technology and changes in application requirements, MEMS oscillators are gradually emerging. MEMS oscillators use micromechanical resonators as frequency-determining elements, and compared with LC oscillators, they have significant advantages in providing lower phase noise and more stable frequency at the same power consumption. These characteristics make MEMS oscillators have broad application prospects in fields such as wireless communications, sensor networks, and consumer electronics.

[0004] In order to reduce power consumption, MEMS resonator-based oscillators usually adopt a complementary cross-coupling structure. This structure introduces positive feedback through cross-coupling, thereby increasing the overall small signal gain without increasing the current and reducing the start-up power consumption. However, this structure is limited by the transistor stacking effect, resulting in a reduced output swing, and the operating voltage is usually above 1V, which limits the application of the oscillator in a low power supply voltage environment and further reduction of power consumption. Summary of the invention

[0005] In view of this, an object of the present invention is to provide an oscillation circuit of a MEMS resonator, which is used to reduce transistor stacking and lower power supply voltage while ensuring low phase noise and providing the same negative resistance, thereby reducing the power consumption of the oscillator and improving the quality factor of the oscillator.

[0006] The present application discloses an oscillation circuit of a MEMS resonator, comprising: a main oscillator core circuit and a bias circuit;

[0007] The first output terminal of the bias circuit is connected to the first input terminal of the master oscillator core circuit;

[0008] The second output terminal of the bias circuit is connected to the second input terminal of the master oscillator core circuit;

[0009] The bias circuit is used to provide a tail current source bias voltage for the master oscillator core circuit through its second output terminal, and to provide a direct current bias voltage of a PMOS cross-coupled pair of transistors for the master oscillator core circuit through its first output terminal;

[0010] The master oscillator core circuit is used to generate an oscillating sine wave signal; the master oscillator core circuit includes two branches both arranged between the power supply and the ground; three transistors are connected in series in the branches.

[0011] Optionally, the switches on the two branches in the master oscillator core circuit form three switch groups;

[0012] The two switch groups are connected by a cross-coupling structure; wherein the first switch group forms a cross-coupling structure only under AC conditions;

[0013] The source of each transistor in the first switch group is directly connected to the power supply.

[0014] Optionally, the first switch group includes: a first PMOS transistor and a second PMOS transistor;

[0015] A source of the first PMOS transistor and a source of the second PMOS transistor are both connected to a power supply;

[0016] A first resistor and a second resistor connected in series are provided between the gate of the first PMOS transistor and the gate of the second PMOS transistor;

[0017] The connection point between the first resistor and the second resistor serves as a first input terminal of the master oscillator core circuit;

[0018] The drain of the first PMOS transistor is connected to the gate of the second PMOS transistor via a second capacitor;

[0019] The drain of the second PMOS transistor is connected to the gate of the first PMOS transistor through a first capacitor;

[0020] The drain of the first PMOS transistor is also connected to the first output terminal of the main oscillator core circuit;

[0021] The drain of the second PMOS transistor is also connected to the second output terminal of the main oscillator core circuit.

[0022] Optionally, the second switch group includes: a first NMOS transistor and a second NMOS transistor;

[0023] The drain of the first NMOS transistor is connected to the gate of the second NMOS transistor, and the connection point is connected to the first output terminal of the main oscillator core circuit;

[0024] The drain of the second NMOS transistor is connected to the gate of the first NMOS transistor, and the connection point is connected to the second output terminal of the main oscillator core circuit.

[0025] Optionally, the third switch group includes: a third NMOS transistor and a fourth NMOS transistor;

[0026] The drain of the third NMOS transistor is connected to one end of the fourth capacitor and the source of the first NMOS transistor respectively;

[0027] The drain of the fourth NMOS transistor is connected to the other end of the fourth capacitor and the source of the second NMOS transistor respectively;

[0028] The gate of the third NMOS transistor is connected to the gate of the fourth NMOS transistor, and the connection point serves as the second input terminal of the main oscillator core circuit;

[0029] A source of the third NMOS transistor and a source of the fourth NMOS transistor are both grounded.

[0030] Optionally, the master oscillator core circuit further includes: a MEMS resonator and a third capacitor;

[0031] The MEMS resonator and the third capacitor are connected in parallel and are arranged between the first output terminal and the second output terminal of the main oscillator core circuit.

[0032] Optionally, the bias circuit includes: a current branch and a voltage branch;

[0033] The current branch and the voltage branch are both arranged between the power supply and the ground;

[0034] The output end of the current branch is connected to the control end of the voltage branch, and the connection point serves as the second output end of the bias circuit;

[0035] The output end of the voltage branch serves as the first output end of the bias circuit.

[0036] Optionally, the current branch includes: a fifth NMOS transistor and a current source;

[0037] The input end of the current source is connected to a power supply;

[0038] The output end of the current source is connected to the gate and drain of the fifth NMOS transistor respectively, and the connection point serves as the output end of the current branch;

[0039] A source of the fifth NMOS transistor is grounded.

[0040] Optionally, the voltage branch includes: a sixth NMOS transistor and a third PMOS transistor;

[0041] The source of the third PMOS transistor is connected to a power supply;

[0042] The drain of the third PMOS transistor is connected to the gate of the third PMOS transistor and the drain of the sixth NMOS transistor respectively, and the connection point serves as the output end of the voltage branch;

[0043] The gate of the sixth NMOS transistor serves as a control terminal of the voltage branch;

[0044] A source of the sixth NMOS transistor is grounded.

[0045] Optionally, two transistors in the same switch group have the same size.

[0046] It can be seen from the above technical scheme that the present invention provides an oscillation circuit of a MEMS resonator, wherein: a bias circuit is used to provide a DC bias voltage and a tail current source bias voltage of a PMOS cross-coupled pair of tubes for a main oscillator core circuit; therefore, each branch in the main oscillator core circuit can have only three transistors in series, and the three transistors can realize the function of the main oscillator core circuit generating an oscillating sinusoidal wave signal without stacking more transistors; the number of transistors in series is small, and the operating voltage of the main oscillator core circuit is correspondingly reduced, and the main oscillator core circuit can operate in a low power supply voltage environment, thereby reducing the power consumption of the main oscillator core circuit, that is, the oscillation circuit of the MEMS resonator provided in the present application can reduce transistor stacking and reduce the power supply voltage while ensuring low phase noise and providing the same negative resistance, thereby reducing the power consumption of the oscillator and improving the quality factor of the oscillator. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0048] Figure 1 is a schematic diagram of an oscillation circuit of a MEMS resonator provided by an embodiment of the present invention;

[0049] Figure 2 is a schematic diagram of an oscillation circuit of another MEMS resonator provided by an embodiment of the present invention;

[0050] Figure 3It is a schematic diagram of an oscillation circuit of another MEMS resonator provided in an embodiment of the present invention.

[0051] Reference numerals:

[0052] 101-main oscillator core circuit; 102-bias circuit; 103-current branch; 104-voltage branch; I1-current source; MP1-first PMOS transistor; MP2-second PMOS transistor; MP3-third PMOS transistor; MN1-first NMOS transistor; MN2-second NMOS transistor; MN3-third NMOS transistor; MN4-fourth NMOS transistor; MN5-fifth NMOS transistor; MN6-sixth NMOS transistor; C1-first capacitor; C2-second capacitor; C3-third capacitor; C4-fourth capacitor; R1-first resistor; R2-second resistor; M1-MEMS resonator; N1-first input terminal of the main oscillator core circuit 101; N2-second input terminal of the main oscillator core circuit 101; VDD-power supply; GND-ground; Vout1-first output terminal of the main oscillator core circuit 101; Vout2-second output terminal of the main oscillator core circuit 101. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0054] In the present application, the term "comprise", "include" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the sentence "comprise one ..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements. In addition, the terms "first", "second", "third", "fourth", etc. (if present) in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable in appropriate circumstances, so that the embodiments of the present application described here can be implemented in an order other than those illustrated or described here, for example.

[0055] An embodiment of the present application provides an oscillation circuit of a MEMS resonator, which is used to solve the problem that the existing structure is limited by the transistor stacking effect, resulting in a reduced output swing and an operating voltage generally above 1V, which limits the application of the oscillator in a low power supply voltage environment and further reduction of power consumption.

[0056] See also Figure 1 , including: a main oscillator core circuit 101 and a bias circuit 102.

[0057] A first output terminal of the bias circuit 102 is connected to a first input terminal of the master oscillator core circuit 101 .

[0058] A second output terminal of the bias circuit 102 is connected to a second input terminal of the master oscillator core circuit 101 .

[0059] The bias circuit 102 is used to provide a tail current source bias voltage to the main oscillator core circuit 101 through its second output terminal, and to provide a DC bias voltage of a PMOS cross-coupled pair of transistors to the main oscillator core circuit 101 through its first output terminal.

[0060] That is to say, the design of the bias circuit 102 realizes the connection and functional coordination with the main oscillator core circuit 101. Specifically, the first output terminal of the bias circuit 102 is connected to the first input terminal of the main oscillator core circuit 101, and this connection is used to provide the necessary DC bias voltage for the PMOS cross-coupled transistor in the main oscillator core circuit 101, ensuring that the circuit can work stably and efficiently.

[0061] At the same time, the second output terminal of the bias circuit 102 is connected to the second input terminal of the main oscillator core circuit 101. This connection is particularly critical because it is responsible for providing a tail current source bias voltage to the main oscillator core circuit 101. The tail current source bias voltage plays a vital role in adjusting the oscillation frequency, stability and overall performance of the circuit.

[0062] In summary, the bias circuit 102 not only provides the necessary DC bias voltage for the main oscillator core circuit 101 through its two carefully designed output terminals, but also ensures the accurate supply of the tail current source bias voltage, thereby jointly ensuring that the main oscillator core circuit 101 can perform its oscillation function normally and efficiently.

[0063] The main oscillator core circuit 101 is used to generate an oscillating sine wave signal; the main oscillator core circuit 101 includes two branches both arranged between the power supply and the ground; three transistors are connected in series in the branch.

[0064] The main oscillator core circuit 101 is the core component of the oscillation system, and its main function is to generate a stable oscillating sine wave signal. To achieve this goal, the circuit is cleverly designed to include two parallel branches, both of which span between the power supply and the ground.

[0065] In each branch, three transistors are connected in series. The arrangement and connection of these transistors in the circuit are crucial. They work together to achieve precise control of the circuit current by periodically turning on and off. This control mechanism is the key to generating a stable sine wave signal.

[0066] Specifically, when the transistors in a branch perform switching operations according to a specific timing, it guides the current to flow between and and forms voltage fluctuations at both ends of the branch. Under the joint action of multiple branches, this voltage fluctuation is finally superimposed and converted into a stable sine wave signal.

[0067] Therefore, the master oscillator core circuit 101 successfully achieves stable generation of an oscillating sine wave signal through its dual-branch design and precise control of transistors.

[0068] In this embodiment, the bias circuit 102 provides the main oscillator core circuit 101 with a DC bias voltage and a tail current source bias voltage of the PMOS cross-coupled pair of tubes; therefore, each branch in the main oscillator core circuit 101 can have only three transistors in series, and the three transistors can realize the function of the main oscillator core circuit 101 to generate an oscillating sinusoidal wave signal, without the need to stack more transistors; the number of transistors connected in series is small, and the operating voltage of the main oscillator core circuit 101 is correspondingly reduced, and the main oscillator core circuit 101 can operate in a low power supply voltage environment, thereby reducing the power consumption of the main oscillator core circuit 101, that is, the oscillation circuit of the MEMS resonator provided in the present application can reduce transistor stacking and reduce the power supply voltage while ensuring low phase noise and providing the same negative resistance, thereby reducing the power consumption of the oscillator and improving the quality factor of the oscillator.

[0069] Optionally, the switches on the two branches in the main oscillator core circuit 101 form three switch groups.

[0070] The two switch groups are connected using a cross-coupling structure; wherein the first switch group forms a cross-coupling structure only under AC conditions.

[0071] The source of each transistor in the first switch group is directly connected to the power source VDD.

[0072] Among the three switch groups, two groups are specially connected by cross-coupling. The cross-coupling structure is an effective circuit design method. It can enhance the small signal gain of the circuit through current reuse without adding additional current, thereby reducing the start-up power consumption. The application of this structure in the main oscillator core circuit 101 undoubtedly provides strong support for the optimization of its performance.

[0073] In summary, the master oscillator core circuit 101 achieves efficient, stable and precise oscillation of the circuit through its unique three-switch group design, the cross-coupling connection mode of two of the switch groups, and the direct connection between the transistors in the first switch group and the power supply VDD.

[0074] Optional, such as Figure 2 As shown, the first switch group includes: a first PMOS transistor MP1 and a second PMOS transistor MP2.

[0075] The source of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2 are both connected to the power supply VDD; that is, the source of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2 are commonly connected to the power supply VDD, ensuring that both share the same power supply VDD.

[0076] A first resistor R1 and a second resistor R2 connected in series are disposed between the gate of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2 ; a connection point between the first resistor R1 and the second resistor R2 serves as a first input terminal N1 of the master oscillator core circuit 101 .

[0077] A first resistor R1 and a second resistor R2 are cleverly connected in series between the gate of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2 to form a voltage divider circuit. The connection point between the two resistors is designed as the first input terminal N1 of the main oscillator core circuit 101 for receiving a DC bias voltage.

[0078] The drain of the first PMOS transistor MP1 is connected to the gate of the second PMOS transistor MP2 through the second capacitor C2; the drain of the second PMOS transistor MP2 is connected to the gate of the first PMOS transistor MP1 through the first capacitor C1.

[0079] In order to increase the complexity and stability of the circuit, the drain of the first PMOS transistor MP1 is connected to the gate of the second PMOS transistor MP2 through a second capacitor C2, forming a feedback path. At the same time, the drain of the second PMOS transistor MP2 is also connected to the gate of the first PMOS transistor MP1 through a first capacitor C1, forming another feedback path. The introduction of these two capacitors helps to adjust the oscillation frequency and stability of the circuit.

[0080] The drain of the first PMOS transistor MP1 is also connected to the first output terminal Vout1 of the master oscillator core circuit 101 ; the drain of the second PMOS transistor MP2 is also connected to the second output terminal Vout2 of the master oscillator core circuit 101 .

[0081] In addition, the drain of the first PMOS transistor MP1 is directly connected to the first output terminal Vout1 of the master oscillator core circuit 101, and the drain of the second PMOS transistor MP2 is connected to the second output terminal Vout2 of the master oscillator core circuit 101, providing two independent output signals for the circuit. It should be noted that the two output signals can output sinusoidal wave signals separately or together constitute a sinusoidal wave signal, but differential output is generally used when used, that is, the two output terminals together constitute a sinusoidal signal.

[0082] Optionally, the second switch group includes: a first NMOS transistor MN1 and a second NMOS transistor MN2.

[0083] The drain of the first NMOS transistor MN1 is connected to the gate of the second NMOS transistor MN2 , and the connection point is connected to the first output terminal Vout1 of the master oscillator core circuit 101 .

[0084] The drain of the second NMOS transistor MN2 is connected to the gate of the first NMOS transistor MN1 , and the connection point is connected to the second output terminal Vout2 of the master oscillator core circuit 101 .

[0085] That is, the first NMOS transistor MN1 and the second NMOS transistor MN2 are connected to the output terminal of the main oscillator core circuit 101 in a cross-connection manner.

[0086] That is, the first NMOS transistor MN1 and the second NMOS transistor MN2 in the second switch group are connected to the output terminal of the main oscillator core circuit 101 in a cross-connection manner.

[0087] Optionally, the third switch group includes: a third NMOS transistor MN3 and a fourth NMOS transistor MN4.

[0088] The drain of the third NMOS transistor MN3 is respectively connected to one end of the fourth capacitor C4 and the source of the first NMOS transistor MN1; the drain of the fourth NMOS transistor MN4 is respectively connected to the other end of the fourth capacitor C4 and the source of the second NMOS transistor MN2; the gate of the third NMOS transistor MN3 is connected to the gate of the fourth NMOS transistor MN4, and the connection point serves as the second input terminal N2 of the main oscillator core circuit 101; the source of the third NMOS transistor MN3 and the source of the fourth NMOS transistor MN4 are both grounded GND.

[0089] That is, the drain of the third NMOS transistor MN3 is not only connected to one end of the fourth capacitor C4, but also connected to the source of the first NMOS transistor MN1, forming a current path.

[0090] The drain of the fourth NMOS transistor MN4 is connected to the other end of the fourth capacitor C4 and the source of the second NMOS transistor MN2 to form another current path.

[0091] It is worth noting that the gate of the third NMOS transistor MN3 is connected to the gate of the fourth NMOS transistor MN4, and this connection point is designed as the second input terminal N2 of the main oscillator core circuit 101 for receiving the tail current bias voltage.

[0092] The sources of the two NMOS transistors are both grounded to GND, ensuring stable operation of the circuit.

[0093] Optionally, two transistors in the same switch group have the same size.

[0094] In order to ensure the consistency and stability of the circuit, the sizes of the two transistors in the same switch group are designed to be the same. That is, the sizes of the first PMOS transistor MP1 and the second PMOS transistor MP2 in the first switch group are exactly the same, the sizes of the first NMOS transistor MN1 and the second NMOS transistor MN2 in the second switch group are also exactly the same, and the sizes of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 in the third switch group are also the same. This design helps to reduce mismatches and errors in the circuit and improve the performance and stability of the entire circuit.

[0095] At the same time, the capacitance values ​​of the first capacitor C1 and the second capacitor C2 may be configured to be equal; and the resistance values ​​of the first resistor R1 and the second resistor R2 may be configured to be equal.

[0096] Optionally, the master oscillator core circuit 101 further includes: a MEMS resonator M1 and a third capacitor C3.

[0097] The MEMS resonator M1 and the third capacitor C3 are arranged in parallel between the first output terminal Vout1 and the second output terminal Vout2 of the master oscillator core circuit 101 .

[0098] The MEMS resonator M1 and the third capacitor C3 form a resonant cavity of the master oscillator core circuit 101 .

[0099] That is to say, the first output terminal Vout1 and the second output terminal Vout2 of the master oscillator core circuit 101 are respectively disposed at two ends of the resonant cavity.

[0100] The specific structure of the main oscillator core circuit 101 is described below by way of example:

[0101] The master oscillator core circuit 101 includes: a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a MEMS resonator M1, a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4.

[0102] The first PMOS transistor MP1, the first NMOS transistor MN1 and the third NMOS transistor MN3 are connected in series in sequence to form a first branch. The source of the first PMOS transistor MP1 is connected to the power supply VDD. The drain of the third NMOS transistor MN3 is connected to the ground GND.

[0103] The second PMOS transistor MP2, the second NMOS transistor MN2 and the fourth NMOS transistor MN4 are connected in series in sequence to form a second branch. The source of the second PMOS transistor MP2 is connected to the power supply VDD. The drain of the fourth NMOS transistor MN4 is connected to the ground GND.

[0104] One end of the first capacitor C1 is connected to one end of the first resistor R1 and the gate of the first PMOS transistor MP1 respectively.

[0105] The other end of the first capacitor C1 is respectively connected to the drain of the second PMOS transistor MP2, one end of the MEMS resonator M1, one end of the third capacitor C3, the gate of the first NMOS transistor MN1 and the drain of the second NMOS transistor MN2, and the connection point serves as the second output terminal Vout2 of the main oscillator core circuit 101.

[0106] One end of the second capacitor C2 is connected to one end of the second resistor R12 and the gate of the second PMOS transistor MP2 respectively.

[0107] The other end of the second capacitor C2 is respectively connected to the drain of the first PMOS transistor MP1, the other end of the MEMS resonator M1, the other end of the third capacitor C3, the gate of the second NMOS transistor MN2 and the drain of the first NMOS transistor MN1, and the connection point serves as the first output terminal Vout1 of the main oscillator core circuit 101.

[0108] The other end of the first resistor R1 is connected to the other end of the second resistor R12 , and the connection point serves as a first input terminal N1 of the master oscillator core circuit 101 to receive the DC bias voltage output by the bias circuit 102 .

[0109] The source of the first NMOS transistor MN1 is connected to the drain of the third NMOS transistor MN3 and one end of the fourth capacitor C4 respectively.

[0110] The source of the second NMOS transistor MN2 is connected to the drain of the fourth NMOS transistor MN4 and the other end of the fourth capacitor C4 respectively.

[0111] The gate of the third NMOS transistor MN3 is connected to the gate of the fourth NMOS transistor MN4 , and the connection point serves as the second input terminal N2 of the main oscillator core circuit 101 , receiving the micro-current bias voltage output by the bias circuit 102 .

[0112] That is to say, the MEMS resonator M1 and the capacitor C3 form a resonant cavity circuit, and the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, the fourth NMOS transistor MN4, the first PMOS transistor MP1, the second PMOS transistor MP2, the first capacitor C1, the second capacitor C2, the fourth capacitor C4, the first resistor R1, and the second resistor R2 form an active network, providing a negative resistance to compensate for the loss of the resonant cavity. The first NMOS transistor MN1 and the second NMOS transistor MN2 introduce positive feedback by cross-coupling, and the first PMOS transistor MP1 and the second PMOS transistor MP2 also introduce positive feedback by cross-coupling, which increases the overall small signal gain, thereby increasing the negative conductance of the circuit and reducing power consumption.

[0113] It should be noted that, since a capacitor and a resistor are provided between the gates of the first PMOS transistor PM1 and the second PMOS transistor PM2 in the master oscillator core circuit 101, under DC working conditions, the first capacitor C1 and the second capacitor C2 are equivalent to an open circuit, the gates of the first PMOS transistor MP1 and the second PMOS transistor MP2 are connected, and their drains are not connected, and no cross coupling is formed. The DC bias voltage is provided by the bias circuit 102, which prevents DC locking. Therefore, the source of the first PMOS transistor PM1 and the source of the second PMOS transistor PM2 can be connected to the power supply VDD, which saves a layer of transistors, reduces the required power supply voltage, and increases the voltage margin. Under AC working conditions, the first capacitor C1 and the second capacitor C2 are equivalent to a short circuit, and the first PMOS transistor PM1 and the second PMOS transistor PM2 introduce positive feedback by cross coupling, which increases the overall small signal gain, thereby increasing the negative conductance of the circuit, generating negative resistance, and making it easier for the oscillator to start.

[0114] The reason why some structures require four or more layers of transistors (such as Figure 3 As shown in the figure), the MEMS resonator M1 and the third capacitor C2 constitute a resonant cavity circuit, and the active transistors MN1, MN2, MN3, MN4, MP1, MP2, MP3, and MP4 provide negative resistance to offset the loss of the resonant circuit. Among them, the PMOS transistors MP3 and MP4 introduce positive feedback by cross-coupling, and the NMOS transistors MN1 and MN2 introduce positive feedback by cross-coupling, which increases the overall small signal gain without increasing the current, thereby increasing the negative conductance of the circuit and reducing power consumption. However, this circuit structure involves the stacking of four layers of transistors, and the operating voltage is usually above 1V, so it is difficult to meet the working requirements of low power supply voltage. That is, Figure 3 There are no capacitors and resistors in the cross-coupling, so both DC and AC conditions are cross-coupled structures. If the source of the MEMS cross-coupled oscillator is directly connected to GND or VDD, it will cause DC lock. Therefore, the cross-coupled tube cannot be directly connected to GND or VDD, and an extra layer of transistors is required.

[0115] The source-drain voltage VDS of each layer of transistors is greater than 0, so reducing one layer of transistors reduces the voltage consumption of one layer, which will reduce the required power supply voltage. In addition, since the first PMOS transistor PM1 and the second PMOS transistor PM2 do not form cross coupling under DC, the DC bias voltage is provided by the bias voltage 102, so the voltage of the first input terminal N1 of the main oscillator core circuit 101 can be set lower than the gate voltage of MN1 and MN2 (i.e., the VOUT point voltage), which also reduces the required power supply voltage.

[0116] That is, a complementary cross-coupled oscillator circuit is used as a core circuit, a first capacitor C1 is introduced between the gate of the first PMOS transistor MP1 and the drain of the second PMOS transistor MP2, a second capacitor C2 is introduced between the gate of the second PMOS transistor MP2 and the drain of the first PMOS transistor MP1, the gate of the first PMOS transistor MP1, the first resistor R1, the second resistor R2, and the gate of the second PMOS transistor MP2 are connected in series in sequence, a first node N1 is provided at the connection between the first resistor R1 and the second resistor R2, a gate of the sixth NMOS transistor MN6 of the voltage branch 104 is connected to the first node N1, and a DC bias voltage is provided, so that the source of the first PMOS transistor MP1 and the second PMOS transistor MP2 can be directly connected to the power supply VDD, thereby meeting the low power supply voltage requirement.

[0117] It should also be noted that Cadence simulation shows that when using a MEMS resonator, the phase noise can reach -137.34dBc / Hz@1MHz when the output frequency is 2.45GHz, the power supply voltage is 0.5V, the power consumption is 0.05mW, and the quality factor is -218dB. It can be seen that the disclosed example can reduce the power supply voltage while ensuring low phase noise, thereby reducing the power consumption of the oscillator and improving the quality factor of the oscillator, which is suitable for low power supply voltage and high performance application background.

[0118] In this embodiment, the stacking of transistors is reduced, and the power supply voltage is lowered while ensuring low phase noise and providing the same negative resistance, thereby reducing the power consumption of the oscillator and improving the quality factor of the oscillator; the stacking of transistors is reduced, thereby increasing the output swing of the oscillator.

[0119] Optional, such as Figure 2 As shown, the bias circuit 102 includes a current branch 103 and a voltage branch 104 .

[0120] The current branch 103 and the voltage branch 104 are both arranged between the power source VDD and the ground GND.

[0121] Specifically, the power supply end of the current branch 103 is connected to the power supply VDD, and the ground end of the current branch 103 is connected to the ground GND.

[0122] A power supply end of the voltage branch 104 is connected to a power supply VDD, and a ground end of the voltage branch 104 is connected to a ground GND.

[0123] The output end of the current branch 103 is connected to the control end of the voltage branch 104, and the connection point serves as the second output end of the bias circuit 102, outputting the tail current bias voltage.

[0124] The output end of the voltage branch 104 serves as the first output end of the bias circuit 102 and outputs a DC bias voltage.

[0125] Optionally, the current branch 103 includes: a fifth NMOS transistor MN5 and a current source I1.

[0126] An input terminal of the current source I1 is connected to a power source VDD, and the power source VDD supplies power to the current source I1.

[0127] The output end of the current source I1 is connected to the gate and the drain of the fifth NMOS transistor MN5 respectively, and the connection point serves as the output end of the current branch 103 .

[0128] That is, the output end of the current source I1 , the gate of the fifth NMOS transistor MN5 , and the drain of the fifth NMOS transistor MN5 are connected, and the connection point together constitutes the output end of the current branch 103 .

[0129] The source of the fifth NMOS transistor MN5 is connected to the ground GND, which ensures the correct operation of the circuit.

[0130] Optionally, the voltage branch 104 includes: a sixth NMOS transistor MN6 and a third PMOS transistor MP3.

[0131] A source of the third PMOS transistor MP3 is connected to the power source VDD.

[0132] The drain of the third PMOS transistor MP3 is connected to the gate of the third PMOS transistor MP3 and the drain of the sixth NMOS transistor MN6 respectively, and the connection point serves as the output end of the voltage branch 104 .

[0133] The gate of the sixth NMOS transistor MN6 serves as a control terminal of the voltage branch 104 .

[0134] A source of the sixth NMOS transistor MN6 is connected to the ground GND.

[0135] In this embodiment, the DC bias voltage of the PMOS transistor is generated by the voltage branch 104, thereby reducing external signal input.

[0136] The sixth NMOS transistor MN6 in the voltage branch 104 has the same size as the fifth NMOS transistor MN5 in the current branch 103 .

[0137] The sizes of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 of the master oscillator core circuit 101 are both larger than the fifth NMOS transistor MN5 of the current branch 103 and are integer multiples of the fifth NMOS transistor MN5 .

[0138] The features recorded in the various embodiments in this specification can be replaced or combined with each other, and the same and similar parts between the various embodiments can refer to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system or system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can refer to the partial description of the method embodiment. The system and system embodiments described above are only schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative work.

[0139] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0140] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An oscillation circuit of a MEMS resonator, characterized in that: include: A master oscillator core circuit (101) and a bias circuit (102); The first output terminal of the bias circuit (102) is connected to the first input terminal of the master oscillator core circuit (101); The second output terminal of the bias circuit (102) is connected to the second input terminal of the master oscillator core circuit (101); The bias circuit (102) is used to provide a tail current source bias voltage for the master oscillator core circuit (101) through its second output terminal, and to provide a direct current bias voltage of a PMOS cross-coupled pair of transistors for the master oscillator core circuit (101) through its first output terminal; The master oscillator core circuit (101) is used to generate an oscillating sine wave signal; the master oscillator core circuit (101) comprises two branches both arranged between a power supply (VDD) and a ground (GND); three transistors are connected in series in the branches.

2. The oscillation circuit of the MEMS resonator according to claim 1, characterized in that: The switches on the two branches in the master oscillator core circuit (101) form three switch groups; The two switch groups are connected by a cross-coupling structure; wherein the first switch group forms a cross-coupling structure only under AC conditions; The source of each transistor in the first switch group is directly connected to the power supply (VDD).

3. The oscillation circuit of the MEMS resonator according to claim 2, characterized in that: The first switch group includes: a first PMOS transistor (MP1) and a second PMOS transistor (MP2); A source of the first PMOS transistor (MP1) and a source of the second PMOS transistor (MP2) are both connected to a power supply (VDD); A first resistor (R1) and a second resistor (R2) connected in series are provided between the gate of the first PMOS transistor (MP1) and the gate of the second PMOS transistor (MP2); The connection point between the first resistor (R1) and the second resistor (R2) serves as a first input terminal of the master oscillator core circuit (101); The drain of the first PMOS transistor (MP1) is connected to the gate of the second PMOS transistor (MP2) via a second capacitor (C2); The drain of the second PMOS transistor (MP2) is connected to the gate of the first PMOS transistor (MP1) via a first capacitor (C1); The drain of the first PMOS transistor (MP1) is also connected to the first output terminal of the master oscillator core circuit (101); The drain of the second PMOS transistor (MP2) is also connected to the second output terminal of the master oscillator core circuit (101).

4. The oscillation circuit of the MEMS resonator according to claim 2, characterized in that: The second switch group includes: a first NMOS transistor (MN1) and a second NMOS transistor (MN2); The drain of the first NMOS transistor (MN1) is connected to the gate of the second NMOS transistor (MN2), and the connection point is connected to the first output terminal of the main oscillator core circuit (101); The drain of the second NMOS transistor (MN2) is connected to the gate of the first NMOS transistor (MN1), and the connection point is connected to the second output terminal of the main oscillator core circuit (101).

5. The oscillation circuit of the MEMS resonator according to claim 2, characterized in that: The third switch group includes: a third NMOS transistor (MN3) and a fourth NMOS transistor (MN4); The drain of the third NMOS transistor (MN3) is respectively connected to one end of the fourth capacitor (C4) and the source of the first NMOS transistor (MN1); The drain of the fourth NMOS transistor (MN4) is respectively connected to the other end of the fourth capacitor (C4) and the source of the second NMOS transistor (MN2); The gate of the third NMOS transistor (MN3) is connected to the gate of the fourth NMOS transistor (MN4), and the connection point serves as the second input terminal of the master oscillator core circuit (101); A source of the third NMOS transistor (MN3) and a source of the fourth NMOS transistor (MN4) are both grounded (GND).

6. The oscillation circuit of the MEMS resonator according to claim 1, characterized in that: The master oscillator core circuit (101) further includes: a MEMS resonator (M1) and a third capacitor (C3); The MEMS resonator (M1) and the third capacitor (C3) are connected in parallel and are arranged between the first output end and the second output end of the master oscillator core circuit (101).

7. The oscillation circuit of the MEMS resonator according to claim 1, characterized in that: The bias circuit (102) comprises: a current branch (103) and a voltage branch (104); The current branch (103) and the voltage branch (104) are both arranged between a power supply (VDD) and a ground (GND); The output end of the current branch (103) is connected to the control end of the voltage branch (104), and the connection point serves as the second output end of the bias circuit (102); The output end of the voltage branch (104) serves as the first output end of the bias circuit (102).

8. The oscillation circuit of the MEMS resonator according to claim 7, characterized in that: The current branch (103) comprises: a fifth NMOS transistor (MN5) and a current source (I1); The input end of the current source (I1) is connected to a power supply (VDD); The output end of the current source (I1) is respectively connected to the gate and the drain of the fifth NMOS transistor (MN5), and the connection point serves as the output end of the current branch (103); A source of the fifth NMOS transistor (MN5) is connected to the ground (GND).

9. The oscillation circuit of the MEMS resonator according to claim 7, characterized in that: The voltage branch (104) includes: a sixth NMOS transistor (MN6) and a third PMOS transistor (MP3); The source of the third PMOS transistor (MP3) is connected to a power supply (VDD); The drain of the third PMOS transistor (MP3) is respectively connected to the gate of the third PMOS transistor (MP3) and the drain of the sixth NMOS transistor (MN6), and the connection point serves as the output end of the voltage branch (104); The gate of the sixth NMOS transistor (MN6) serves as a control terminal of the voltage branch (104); A source of the sixth NMOS transistor (MN6) is connected to the ground (GND).

10. The oscillation circuit of the MEMS resonator according to claim 2, characterized in that: The two transistors of the same switch group have the same size.

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