High-frequency driving amplifying circuit

Abstract

The invention discloses a high-frequency driving amplifying circuit which comprises a driving chip and a load circuit. The load circuit comprises a first inductor and a load resistor, the first inductor is connected between a first pin and a second pin of the driving chip, a first end of the load resistor is directly or indirectly connected with the second pin of the driving chip, and a second end of the load resistor is connected with a reference potential; the driving chip comprises an LDO circuit and a driving circuit, the LDO circuit is connected between the power supply voltage of the driving chip and the first pin and used for generating an output voltage based on the power supply voltage, the output voltage is smaller than the power supply voltage, and the driving circuit is connected between the second pin and the reference potential and used for generating an output signal at the second pin. High-frequency driving is achieved with low power consumption and high linearity, stray capacitance is reduced by adopting the low-voltage MOS tube, alternating current is prevented from being shunted, power loss of the high-frequency driving amplification circuit is reduced, the first inductor with a large inductance value can be selected under the same resonant frequency, and the chip design difficulty is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a high-frequency driving amplifier circuit. Background Art

[0002] The output stage driver amplifier is mainly used to drive the low impedance load outside the chip (usually a 50 ohm resistor). At high frequencies, due to the low resistance, a large amount of current is usually consumed to achieve a certain output power or voltage swing, thereby increasing the system power consumption.

[0003] The output driver amplifier needs to support an operating frequency range of 53.125MHz to 6.8GHz. Because it needs to support output frequencies of tens of MHz and several GHz at the same time, it is difficult to meet the inductor and capacitor load matching requirements at the same time.

[0004] For some application scenarios, the output stage driver amplifier needs to operate at an output frequency of 20 GHz while providing an output power greater than 0 dBm. When the output frequency continues to increase, such as reaching 30 to 40 GHz, the parasitic capacitance of the output stage driver amplifier will cause a large amount of high-frequency current to be lost, thereby causing power loss.

[0005] In addition, as the output frequency continues to increase, the influence of parasitic capacitance increases, which leads to a smaller selection range of RF inductors and a greater influence of wire bonding inductance, increasing the difficulty of design.

[0006] In addition to considering output power and current consumption, linearity is also an important indicator. The precise model of power amplifier linearity is relatively complex. It can be assumed that only the fundamental harmonic (main signal) is amplified, and other sub-harmonics and higher harmonics are attenuated. Parasitic capacitance has different frequency responses to different sub-harmonics and higher harmonics, so it will also affect the linearity of the output driver amplifier.

[0007] Therefore, in view of the above technical problems, it is necessary to provide a high-frequency driving amplifier circuit. Summary of the invention

[0008] An object of the present invention is to provide a high-frequency driving amplifier circuit which can realize high-frequency driving with low power consumption and high linearity.

[0009] In order to achieve the above object, a technical solution provided by a specific embodiment of the present invention is as follows:

[0010] A high-frequency drive amplifier circuit, the high-frequency drive amplifier circuit comprising a drive chip and a load circuit;

[0011] The load circuit includes a first inductor and a load resistor, wherein a first end of the first inductor is connected to a first pin of the driver chip, and a second end of the first inductor is connected to a second pin of the driver chip, a first end of the load resistor is directly or indirectly connected to the second pin of the driver chip, and a second end of the load resistor is connected to a reference potential;

[0012] The driver chip includes an LDO circuit and a driver circuit. The LDO circuit is connected between the driver chip power supply voltage and a first pin, and is used to generate an output voltage based on the power supply voltage. The output voltage is less than the power supply voltage. The driver circuit is connected between the second pin and a reference potential, and is used to generate an output signal at the second pin.

[0013] In one or more embodiments of the present invention, the driving circuit includes an amplifying unit and a biasing unit, wherein;

[0014] The bias unit is connected between the power supply voltage and the reference potential, and is used to output a bias voltage at the first output node;

[0015] The amplifying unit is connected to the first output node and is used to generate an output signal based on an input signal and a bias voltage.

[0016] In one or more embodiments of the present invention, the amplifying unit includes a first MOS tube and a second MOS tube; wherein,

[0017] The first end of the first MOS tube is connected to the reference potential, the second end is connected to the first end of the second MOS tube, and the control end receives an input signal;

[0018] The second end of the second MOS tube is connected to the second pin, and the control end is connected to the bias unit to receive the bias voltage.

[0019] In one or more embodiments of the present invention, the first MOS transistor and the second MOS transistor are low-voltage MOS transistors.

[0020] In one or more embodiments of the present invention, the gate length of the second MOS transistor is greater than the gate length of the first MOS transistor.

[0021] In one or more embodiments of the present invention, the bias unit includes a first resistor, a second resistor, a third resistor and a control tube; wherein,

[0022] A first end of the first resistor is connected to a power supply voltage, and a second end is connected to a first output node;

[0023] A first end of the second resistor is connected to the first output node, and a second end is connected to the reference potential;

[0024] The control end of the control tube receives an enable signal, the first end is connected to the reference potential, the second end is connected to the second end of the third resistor, and the first end of the third resistor is connected to the first output node.

[0025] In one or more embodiments of the present invention, when the enable signal is at a first level, the bias voltage is a first voltage, and when the enable signal is at a second level, the bias voltage is a second voltage, and the first voltage is greater than the second voltage.

[0026] In one or more embodiments of the present invention, the bias unit further includes a first filter capacitor, a first end of the first filter capacitor is connected to the first output node, and a second end of the first filter capacitor is connected to a reference potential.

[0027] In one or more embodiments of the present invention, the load circuit further includes a second capacitor and a third capacitor; wherein,

[0028] A first end of the second capacitor is connected to the first pin, and a second end is connected to a reference potential;

[0029] The first end of the third capacitor is connected to the second pin, and the second end is connected to the first end of the load resistor.

[0030] In one or more embodiments of the present invention, the driving circuit includes a third MOS tube, a first end of the third MOS tube is connected to the reference potential, a control end receives an input signal, and a second end is connected to the second pin; the third MOS tube is a low-voltage MOS tube.

[0031] Compared with the prior art, the high-frequency driving amplifier circuit of the present invention generates an output voltage lower than the power supply voltage through the LDO circuit, and the driving unit generates an output signal based on the output voltage to drive the load circuit, thereby realizing high-frequency driving with low power consumption and high linearity;

[0032] By using low-voltage MOS tubes to significantly reduce parasitic capacitance, AC current is prevented from being shunted, and the power loss of the high-frequency drive amplifier circuit is reduced. At the same resonant frequency, a first inductor with a larger inductance value can be selected to reduce the difficulty of chip design.

[0033] For the same output power, the first MOS tube can be of smaller size, which reduces the load of the front-stage clock buffer of the high-frequency driving amplifier circuit and further reduces the power consumption of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0035] Figure 1 is a schematic diagram of a high frequency driving amplifier circuit in Embodiment 1 of the present invention;

[0036] Figure 2 Schematic diagram of a high frequency driving amplifier circuit in Embodiment 2 of the present invention. DETAILED DESCRIPTION

[0037] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0038] The term "coupled" or "connected" or "connected" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include connection through other active or passive devices on the basis of achieving the same or similar functional purpose, such as connection through circuits or components such as switches and follower circuits. In addition, in the present invention, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity or order between these technical features.

[0039] Embodiment 1:

[0040] like Figure 1 As shown, the high-frequency driving amplifier circuit in this embodiment includes a driving chip 10 and a load circuit 20 .

[0041] Specifically, the load circuit 20 includes a first inductor Lx and a load resistor R L The first end of the first inductor Lx is connected to the first pin P1 of the driver chip 10, and the second end is connected to the second pin P2 of the driver chip 10. The load resistor R L The first end of the load resistor R is directly or indirectly connected to the second pin P2 of the driver chip 10, and the second end is connected to the reference potential Vss. Lis 50Ω.

[0042] The driver chip 10 includes an LDO circuit and a driver circuit. The LDO circuit is connected to a power supply voltage V RF Between the first pin P1, for the power supply voltage V RF Generates output voltage V PA The driving circuit is connected between the second pin P2 and the reference potential Vss, and is used to generate an output signal Vx at the second pin P2.

[0043] In this embodiment, the power supply voltage V RF is the external 3.3V power supply voltage of the driver chip 10, the power supply voltage V RF Used to power the LDO (low dropout linear regulator) circuit. The output voltage V generated at the output end of the LDO circuit is PA It is about 2.5 V. It can be understood that the output end of the LDO is connected to the first pin P1 located outside the chip through a binding wire.

[0044] The first inductor Lx in this embodiment is a radio frequency inductor or a choke inductor, which plays the role of passing direct current and blocking alternating current. It can be understood that the first inductor Lx is connected between the first pin P1 and the second pin P2 of the driver chip 10, wherein the output voltage V PA is a DC voltage, therefore, the voltage on the second pin P2 is a DC voltage of about 2.5V.

[0045] like Figure 1 As shown, in this embodiment, the load circuit also includes a second capacitor C byp and the third capacitor C AC ; Wherein, the second capacitor C byp The first end of the second capacitor C is connected to the first pin P1, the second end is connected to the reference potential Vss, and the byp is the filter capacitor. The third capacitor C AC The first end is connected to the second pin P2, and the second end is connected to the load resistor R L The first end of the third capacitor C AC is the AC coupling capacitor.

[0046] like Figure 1 As shown, the driving circuit includes an amplifying unit 12 and a biasing unit 11 .

[0047] The bias unit 11 is connected to the power supply voltage V RF and the reference potential Vss, for outputting a bias voltage V at the first output node P0 B .

[0048] The amplifying unit 12 is connected to the first output node P0 and is used to generate an output signal based on the input signal Vin and the bias voltage V B An output signal Vx is generated at the second pin P2.

[0049] like Figure 1 As shown, the amplifying unit 12 includes a first MOS transistor M1 and a second MOS transistor M2; wherein,

[0050] The first end of the first MOS tube is connected to the reference potential Vss, the second end is connected to the first end of the second MOS tube, and the control end receives the input signal Vin;

[0051] The second end of the second MOS tube is connected to the second pin P2, and the control end is connected to the bias unit 11 to receive the bias voltage V B Furthermore, in this embodiment, the second end of the second MOS transistor M2 is connected to the second pin P2 outside the driving chip through a binding wire.

[0052] like Figure 1 As shown, the first MOS transistor M1 and the second MOS transistor M2 are low-voltage MOS transistors. In the 40nm CMOS process, the gate lengths of the first MOS transistor M1 and the second MOS transistor M2 can both be 40nm. In this embodiment, the first MOS transistor M1 and the second MOS transistor M2 are both NMOS transistors, and the first end is the source, the second end is the drain, and the control end is the gate.

[0053] Furthermore, when the output signal Vx generated by the second pin P2 is relatively high, the gate length of the second MOS transistor can be set to be greater than the gate length of the first MOS transistor to improve the reliability of the amplifying unit 12 .

[0054] like Figure 1 As shown, the bias unit 11 is used to provide a bias voltage V for the control terminal of the second MOS tube. B , including a first resistor R1, a second resistor R2, a third resistor R3 and a control tube M N .

[0055] A first terminal of the first resistor R1 is connected to a power supply voltage V RF The second end is connected to the first output node P0;

[0056] A first end of the second resistor R2 is connected to the first output node P0, and a second end is connected to the reference potential Vss;

[0057] Control tube M N The control end receives the enable signal ENb, the first end is connected to the reference potential Vss, the second end is connected to the second end of the third resistor R3, and the first end of the third resistor R3 is connected to the first output node P0.

[0058] When the enable signal ENb is at the first level, the bias voltage V B is the first voltage V B_on , when the enable signal ENb is at the second level, the bias voltage V B is the second voltage V B_off , where the first voltage V B_on Greater than the second voltage V B_off .

[0059] When the chip is working, the enable signal Enb is 0 (first level), and the control tube M N Shutdown, the bias voltage V B is the first voltage V B_on , V B_on =R2 / (R2+R1)*V RF When the chip is turned off, the enable signal Enb is 1 (second level), and the control tube M N Turn on, bias voltage V B The second voltage V B_off , V B_off ={(R2 / / R3) / (R2 / / R3+R1)}*V RF .

[0060] In this embodiment, by reasonably selecting the values ​​of the first resistor R1, the second resistor R2 and the third resistor R3, the first voltage V B_on is about 1.8V, and the second voltage V B_off When the chip is working, the voltage at point Y (the voltage at the second end of the first MOS tube M1) is about 1.2V, and the DC voltage at point X (the voltage at the second end of the second MOS tube M2) is about 2.5V, and neither the first MOS tube M1 nor the second MOS tube M2 will have overvoltage operation. When the chip is turned off, the voltage at point Y is still about 1.2V, the DC voltage at point X is about 2.5V, and no current flows through the first MOS tube M1 and the second MOS tube M2, thereby ensuring the reliability of the amplification unit 12.

[0061] It is understandable that when the frequency of the output signal Vx on the second pin P2 is high, the influence of the parasitic capacitance at point X increases, which will cause the selection range of the RF inductor Lx to become smaller and the influence of the wire bonding inductance to increase, thereby increasing the design difficulty.

[0062] like Figure 1 As shown, in this embodiment, the second MOS tube M2 adopts a low-voltage tube, and the parasitic capacitances at points X and Y are greatly reduced. Therefore, the AC current can flow to the load resistor R with the maximum amplitude. L, avoiding the AC current of the second MOS tube M2 from being shunted, greatly reducing the power loss of the high-frequency amplification drive circuit. For the same output power, the first MOS tube M1 can adopt a smaller size, thereby reducing the load of the front-stage clock buffer of the high-frequency amplification drive circuit, further reducing the system power consumption.

[0063] Furthermore, since the parasitic capacitance at point X is greatly reduced, the value of the first inductor Lx can be increased at the same resonant frequency. For example, in this embodiment, when a 40 GHz output signal Vx needs to be supported, the first inductor Lx can be about 0.2 nH. If the parasitic capacitance at point X is too large, when supporting a 40 GHz output signal Vx, the first inductor Lx can only be about 0.1 nH, resulting in the system being unable to drive the load resistor R L .

[0064] Based on the circuit design and optimization of this embodiment, the high-frequency driving amplifier circuit can achieve an output power of 5-10 dBm under high frequency conditions.

[0065] like Figure 1 As shown, the bias unit 11 of this embodiment further includes a first filter capacitor C1, a first end of which is connected to the first output node P0, and a second end of which is connected to the reference potential Vss. The first filter capacitor C1 provides an AC ground potential for the gate of the second MOS transistor M2.

[0066] Embodiment 2:

[0067] like Figure 2 As shown, the high-frequency driving amplifier circuit in this embodiment includes a driving chip 10 and a load circuit 20 .

[0068] Specifically, the load circuit includes a first inductor Lx and a load resistor R L The first end of the first inductor Lx is connected to the first pin P1 of the driver chip 10, and the second end is connected to the second pin P2 of the driver chip 10. The load resistor R L The first end is directly or indirectly connected to the second pin P2 of the driving chip 10, and the second end is connected to the reference potential Vss.

[0069] The driver chip 10 includes an LDO circuit and a driver circuit. The LDO circuit is connected to a power supply voltage V RF Between the first pin P1, for the power supply voltage V RF Generates output voltage V PA The driving circuit is connected between the second pin P2 and the reference potential Vss, and is used to generate an output signal Vx at the second pin P2.

[0070] In this embodiment, the power supply voltage V RFis the external 3.3V power supply voltage of the driver chip 10, the power supply voltage V RF Used to power the LDO (low dropout linear regulator) circuit. The output voltage V generated at the output end of the LDO circuit is PA It is about 1.2 V. It can be understood that the output end of the LDO is connected to the first pin P1 located outside the chip through a binding wire.

[0071] The first inductor Lx in this embodiment is a radio frequency inductor or a choke inductor, which plays the role of passing direct current and blocking alternating current. It can be understood that the first inductor Lx is connected between the first pin P1 and the second pin P2 of the driver chip 10, wherein the output voltage V PA It is a DC voltage of about 1.2V, so the voltage on the second pin P2 is a DC voltage of about 1.2V.

[0072] like Figure 2 As shown, in this embodiment, the load circuit also includes a second capacitor C byp and the third capacitor C AC Among them, the second capacitor C byp The first end of the second capacitor C is connected to the first pin P1, the second end is connected to the reference potential Vss, and the byp is the filter capacitor. The third capacitor C AC The first end is connected to the second pin P2, and the second end is connected to the load resistor R L The first end of the third capacitor C AC is the AC coupling capacitor.

[0073] like Figure 2 As shown, the driving circuit includes a third MOS transistor M3, a first end of the third MOS transistor M3 is connected to a reference potential Vss, a control end receives an input signal Vin, and a second end is connected to a second pin P2;

[0074] The third MOS tube M3 is a low-voltage NMOS tube. Since the DC voltage at point X is 1.2V and the output power is not high, the third MOS tube M3 will not be over-voltage. This embodiment is suitable for situations where the output frequency requirement is particularly high (for example, greater than 40GHz) and the output power target is around 0dBm.

[0075] It can be seen from the above technical solutions that the present invention has the following beneficial effects:

[0076] An output voltage lower than the power supply voltage is generated by an LDO circuit, and a driving unit generates an output signal based on the output voltage to drive a load circuit, thereby realizing high-frequency driving with low power consumption and high linearity;

[0077] By using low-voltage MOS tubes to significantly reduce parasitic capacitance, AC current is prevented from being shunted, and the power loss of the high-frequency drive amplifier circuit is reduced. At the same resonant frequency, a first inductor with a larger inductance value can be selected to reduce the difficulty of chip design.

[0078] For the same output power, the first MOS tube can be of smaller size, which reduces the load of the front-stage clock buffer of the high-frequency driving amplifier circuit and further reduces the power consumption of the system.

[0079] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0080] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A high frequency drive amplifier circuit, characterized in that: The high-frequency driving amplifier circuit includes a driving chip and a load circuit; The load circuit includes a first inductor and a load resistor, wherein a first end of the first inductor is connected to a first pin of the driver chip, and a second end of the first inductor is connected to a second pin of the driver chip, a first end of the load resistor is directly or indirectly connected to the second pin of the driver chip, and a second end of the load resistor is connected to a reference potential; The driver chip includes an LDO circuit and a driver circuit. The LDO circuit is connected between the driver chip power supply voltage and a first pin, and is used to generate an output voltage based on the power supply voltage. The output voltage is less than the power supply voltage. The driver circuit is connected between the second pin and a reference potential, and is used to generate an output signal at the second pin.

2. The high-frequency driving amplifier circuit according to claim 1, characterized in that: The driving circuit comprises an amplifying unit and a biasing unit, wherein; The bias unit is connected between the power supply voltage and the reference potential, and is used to output a bias voltage at the first output node; The amplifying unit is connected to the first output node and is used to generate an output signal based on an input signal and a bias voltage.

3. The high-frequency driving amplifier circuit according to claim 2, characterized in that: The amplification unit includes a first MOS tube and a second MOS tube; wherein, The first end of the first MOS tube is connected to the reference potential, the second end is connected to the first end of the second MOS tube, and the control end receives an input signal; The second end of the second MOS tube is connected to the second pin, and the control end is connected to the bias unit to receive the bias voltage.

4. The high-frequency driving amplifier circuit according to claim 3, characterized in that: The first MOS transistor and the second MOS transistor are low-voltage MOS transistors.

5. The high-frequency driving amplifier circuit according to claim 3, characterized in that: The gate length of the second MOS tube is greater than the gate length of the first MOS tube.

6. The high-frequency driving amplifier circuit according to claim 2, characterized in that: The bias unit includes a first resistor, a second resistor, a third resistor and a control tube; wherein, A first end of the first resistor is connected to a power supply voltage, and a second end is connected to a first output node; A first end of the second resistor is connected to the first output node, and a second end is connected to the reference potential; The control end of the control tube receives an enable signal, the first end is connected to the reference potential, the second end is connected to the second end of the third resistor, and the first end of the third resistor is connected to the first output node.

7. The high-frequency driving amplifier circuit according to claim 6, characterized in that: When the enable signal is at a first level, the bias voltage is a first voltage, and when the enable signal is at a second level, the bias voltage is a second voltage, and the first voltage is greater than the second voltage.

8. The high-frequency driving amplifier circuit according to claim 6, characterized in that: The bias unit further includes a first filter capacitor, a first end of the first filter capacitor is connected to the first output node, and a second end of the first filter capacitor is connected to a reference potential.

9. The high-frequency driving amplifier circuit according to claim 1, characterized in that: The load circuit also includes a second capacitor and a third capacitor; wherein, A first end of the second capacitor is connected to the first pin, and a second end is connected to a reference potential; The first end of the third capacitor is connected to the second pin, and the second end is connected to the first end of the load resistor.

10. The high-frequency driving amplifier circuit according to claim 1, characterized in that: The driving circuit comprises a third MOS tube, a first end of the third MOS tube is connected to the reference potential, a control end receives an input signal, and a second end is connected to the second pin; The third MOS tube is a low-voltage MOS tube.

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