Three-stage series IO voltage-withstanding driving circuit, electronic device and equipment

Abstract

The invention relates to the technical field of integrated circuits, in particular to a three-stage series IO voltage-withstanding driving circuit, an electronic device and equipment, and the circuit comprises a three-stage series module which is used for receiving a driving signal, a protection signal and a switching signal; the on-off condition is adjusted according to the logic level of the driving signal; under the condition that the on-off condition is on, limiting the working voltage according to the protection signal; adjusting an output signal output to the driven end according to the switching signal; and the switching signal generation module is used for receiving the protection signal, the driven end feedback signal and the three-stage series feedback signal, and adjusting and generating a switching signal according to the protection signal, the driven end feedback signal and the three-stage series feedback signal, so that the stability of the series technology is improved, and the overvoltage working scene of the driving circuit is enabled to operate stably.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a three-stage series IO withstand voltage driving circuit, electronic device and equipment. Background Art

[0002] With the advancement of technology, the thickness of the oxide layer of the gate of the metal oxide semiconductor field effect transistor is getting thinner and thinner, and its voltage resistance is getting weaker and weaker. For example, the voltage resistance of thick oxide devices is 3.3V under the 0.18um process, and when the process develops to the 28nm process and below, the voltage resistance of thick oxide devices is reduced to 1.8V. Considering the level compatibility with other chips of the previous generation, the output drive circuit designed under the advanced process still needs to use a 3.3V power supply voltage. Therefore, thick oxide devices under advanced processes need to use series connection technology for voltage protection to meet the needs of overvoltage working scenarios of the drive circuit.

[0003] The current voltage withstand protection technology is usually two-stage series connection, which is not comprehensive enough for device protection and lacks stability. As a result, the device is damaged due to the HCI effect during overvoltage operation, resulting in degradation of the drive circuit performance. The above problems need to be solved. Summary of the invention

[0004] In order to improve the stability of the series connection technology and make the overvoltage working scenario of the driving circuit run stably, the present application provides a three-stage series connection IO withstand voltage driving circuit, electronic device and equipment, which adopts the following technical solutions:

[0005] In a first aspect, the present application provides a three-stage series IO withstand voltage driving circuit, comprising:

[0006] The three-stage series module is used to receive the driving signal, the protection signal and the switching signal; adjust the on-off state according to the logic high and low of the driving signal; when the on-off state is conductive, limit the working voltage according to the protection signal; and adjust the output signal output to the driven end according to the switching signal;

[0007] The switching signal generating module is used to receive the protection signal, the driven end feedback signal and the three-stage series feedback signal, and to adjust and generate the switching signal according to the protection signal, the driven end feedback signal and the three-stage series feedback signal.

[0008] Preferably, the three-stage series module includes a first driver submodule and a second driver submodule;

[0009] Wherein, the first driver submodule is used to be turned on when the P drive signal is logic low, and drive the IO output high;

[0010] The second driving submodule is used to be turned on when the N driving signal is logic high, and to drive the IO output low.

[0011] Preferably, it also includes:

[0012] A parasitic capacitance module, used for adjusting the switching signal according to the driving signal, and providing undershoot and overshoot to the switching signal respectively;

[0013] The parasitic capacitance module includes a parasitic capacitance Cp and a parasitic capacitance Cn;

[0014] Wherein, the parasitic capacitor Cp is used to adjust the P switching signal according to the P driving signal and provide an undershoot for the P switching signal;

[0015] The parasitic capacitor Cn is used to adjust the N switching signal according to the N driving signal and provide an overshoot for the N switching signal.

[0016] Preferably, the switching signal generating module comprises a first switching signal submodule and a second switching signal submodule;

[0017] The first switching signal submodule is used to adjust and generate a P switching signal according to the P protection signal of the first driving submodule, the driven end feedback signal and the three-stage series feedback signal;

[0018] The second switching signal submodule is used to adjust and generate an N switching signal according to the N protection signal of the second driving submodule, the driven end feedback signal and the three-stage series feedback signal.

[0019] Preferably, the first driving submodule includes a first PMOS tube, a second PMOS tube and a third PMOS tube, the gate of the first PMOS tube is connected to a P driving signal, the source of the first PMOS tube is connected to an operating voltage, the drain of the first PMOS tube is connected to a source of the second PMOS tube, the gate of the second PMOS tube is connected to a P protection signal, the drain of the second PMOS tube is connected to a source of a third PMOS tube, the gate of the third PMOS tube is connected to a P switching signal, and the drain of the third PMOS tube is connected to a driven end.

[0020] Preferably, the second driving submodule includes a first NMOS tube, a second NMOS tube and a third NMOS tube, the gate of the first NMOS tube is connected to an N driving signal, the source of the first NMOS tube is grounded, the drain of the first NMOS tube is connected to the source of the second NMOS tube, the gate of the second NMOS tube is connected to an N protection signal, the drain of the second NMOS tube is connected to the source of the third NMOS tube, the gate of the third NMOS tube is connected to an N switching signal, and the drain of the third NMOS tube is connected to a driven end.

[0021] Preferably, the first switching signal submodule includes a tube MN1, a tube MN2 and a tube MN3, wherein the tube MN1, the tube MN2 and the tube MN3 are all NMOS tubes, the gate of the tube MN1 is connected to the drain of the second PMOS tube, the drain of the tube MN1 is connected to the P protection signal, the source of the tube MN1 is connected to the P switching signal, the gate of the tube MN2 is connected to the P protection signal, the drain of the tube MN2 is connected to the source of the tube MN1, the source of the tube MN2 is connected to the P switching signal, the gate of the tube MN3 is connected to the driven end, the drain of the tube MN3 is connected to the P protection signal, and the source of the tube MN3 is connected to the P switching signal.

[0022] Preferably, the second switching signal submodule includes a tube MP1, a tube MP2 and a tube MP3, wherein the tube MP1, the tube MP2 and the tube MP3 are all PMOS tubes, the gate of the tube MP1 is connected to the drain of the second NMOS tube, the source of the tube MP1 is connected to the N protection signal, the drain of the tube MP1 is connected to the N switching signal, the gate of the tube MP2 is connected to the N protection signal, the source of the tube MP2 is connected to the drain of the tube MP1, the drain of the tube MP2 is connected to the N switching signal, the gate of the tube MP3 is connected to the driven end, the source of the tube MP3 is connected to the N protection signal, and the drain of the tube MP3 is connected to the N switching signal.

[0023] In a second aspect, the present application provides an electronic device, comprising the three-stage series IO withstand voltage driving circuit as described above.

[0024] In a third aspect, the present application provides a device comprising the three-stage series IO withstand voltage driving circuit as described above.

[0025] In summary, compared with the prior art, the technical solution provided by this application has at least the following beneficial effects:

[0026] The present application receives a driving signal through a three-stage series module, determines the logical high and low of the driving signal, and realizes the on and off of the three-stage series module according to the judgment result. When the three-stage series module is currently turned on, the working voltage of the three-stage series module is limited according to the protection signal, so that the three-stage series module will not be over-voltage. The switching signal generation module generates a switching signal acting on the three-stage series module according to the protection signal, the driven end feedback signal and the three-stage series feedback signal. When the driven end starts to rise from low or starts to decrease from high, the protection signal is always equal to the lowest value between the switching signal and the driven end, and effectively when the driven end rises from low voltage or drops from high voltage to exceed the protection signal, the switching signal is correctly switched from the driven end to a lower protection signal, thereby improving the stability of the series technology and making the overvoltage working scenario of the driving circuit run stably. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a structural schematic diagram of a three-stage series IO withstand voltage driving circuit described in an embodiment of the present application.

[0028] Figure 2 It is a schematic diagram of the equivalent model structure of the drive circuit sending the signal described in the embodiment of the present application.

[0029] Figure 3 It is a schematic diagram of a signal sent by the driving circuit described in an embodiment of the present application being reflected.

[0030] Figure 4 It is a schematic diagram of high and low node voltages output by the driving circuit described in an embodiment of the present application.

[0031] Figure 5 It is a schematic diagram of the overshoot change of the P switching signal described in the embodiment of the present application.

[0032] Figure 6 Schematic diagram of the overshoot change of the N switching signal described in the embodiment of the present application.

[0033] Figure 7 It is a schematic diagram of the influence of P switching circuits with different structures on Rn and VB described in the embodiments of the present application. DETAILED DESCRIPTION

[0034] The following combination Figure 1-Figure 7 The present application is described in further detail. The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to be limiting.

[0035] The current two-stage series connection method is not comprehensive enough for device protection and lacks stability, which causes damage to the device due to the HCI effect during overvoltage operation, resulting in degradation of the drive circuit performance. Although the three-stage series structure can well meet the needs of withstand voltage protection, the output equivalent internal resistance of the drive circuit is much larger than the two-stage series structure. If the periodic signal output by the drive circuit encounters reflection, especially when the relationship between the period Tclk of the periodic signal and the delay Td of the signal routing is Tclk=4*Td, the amplitude of the high-speed signal output by the drive circuit will not be full of the swing. For details, refer to Figure 2, the figure is an equivalent model of the signal sent by the driving circuit. Point A is the equivalent ideal voltage source inside the three-stage cascade driving circuit, Rn is the equivalent internal resistance inside the three-stage cascade driving circuit, point B is the actual output point of the driving circuit, and point D is the remote receiving end. There is a transmission line between B and D that is either long or short, and the equivalent impedance of the transmission line is Zo, and it has a fast or slow transmission line delay Td. The D end will be subject to total reflection due to the equivalent infinite impedance. The ideal voltage value VA sent by the ideal voltage source point A, after voltage division, the voltage VB at the B end is VA*Zo / (Rn+Zo), so we can get a formula for Rn that changes with VB: Rn=(VA-VB)*Zo / VB, and VB is VD=2*VB after the delay of the transmission line and total reflection, so the amplitude of the voltage VD at the remote receiving end is actually closely related to VB. The larger the VB amplitude, the larger the VD amplitude, and vice versa. When the transmission signal period Tclk of the ideal voltage source A is 4 times the transmission line delay Td (Tclk = 4*Td), the reflection situation is as follows: Figure 3, the ideal voltage source VA@1 of the driving circuit sends a signal with an amplitude of VCCIO. After Tclk / 2, VA@2 sends a signal with an amplitude of -VCCIO. After Tclk / 2, VA@3 sends a signal with an amplitude of VCCIO. Through such repeated transmission, the driving circuit realizes the function of sending a periodic signal with an amplitude varying between 0 and VCCIO and a period of Tclk. Since Tclk=4*Td, VB@3 at point B is exactly the superposition of the voltage-divided signal of VA@3 and the reflected signal of VD@2, and is affected by both. The internal resistance Rn of the driving circuit can also be obtained by measuring or simulating the output current of the driving circuit, that is, Rn=(VA-VB) / Iout, where Iout is the output current of the driving circuit when VB changes. Therefore, when Tclk=4*Td, at VB@3, we found two formulas for Rn to change with VA@3 and VB@3. To be more precise, since the ideal voltage source VA is generally fixed, we have obtained two formulas for Rn to change with VB. The intersection of these two formulas is the final value of VB@3. Taking the output logic high of the driving circuit as an example, in the ordinary three-stage cascade driving circuit architecture, since the output impedance Rn of the driving circuit is relatively large as a whole, as the VB voltage gradually increases, the output impedance Rn of the driving circuit gradually decreases, but the two Rn formula curves will eventually intersect at the larger Rn, or at the smaller VB, which will also reduce the voltage amplitude of VD at the far-end receiving end. To change this situation, it is necessary to make Rn decrease more as VB increases. The common way is to reduce the equivalent output impedance Rn of the three-stage cascade driving circuit as a whole by increasing the width-to-length ratio of each tube in the three-stage cascade structure, that is, Width / Length. However, the disadvantages are also obvious. The area of ​​the driving circuit will be relatively large, and the equivalent load will also increase, which will affect both the maximum output speed of the driving circuit and the overvoltage protection function of the driving circuit. This problem needs to be solved.

[0036] Reference Figure 1 The present application relates to a three-stage series IO withstand voltage driving circuit, which specifically includes:

[0037] The three-stage series module is used to receive the driving signal, the protection signal and the switching signal; adjust the on-off state according to the logic high and low of the driving signal; when the on-off state is conductive, limit the working voltage according to the protection signal; and adjust the output signal output to the driven end according to the switching signal;

[0038] The switching signal generating module is used to receive the protection signal, the driven end feedback signal and the three-stage series feedback signal, and to adjust and generate the switching signal according to the protection signal, the driven end feedback signal and the three-stage series feedback signal.

[0039] Specifically, one end of the three-stage series module of the present application is connected to VCCIO, that is, the working voltage of the thick oxygen transistor, or grounded, and the other end is the output end, connected to the driven end, that is, connected to VPAD. The present application receives the driving signal through the three-stage series module, judges the logical high and low of the driving signal, and realizes the on and off of the three-stage series module according to the judgment result. When the three-stage series module is currently turned on, the working voltage of the three-stage series module is limited according to the protection signal, so that the three-stage series module will not be over-voltage. The switching signal generation module generates a switching signal acting on the three-stage series module according to the protection signal, the driven end feedback signal and the three-stage series feedback signal. When the driven end starts to rise from low or starts to decrease from high, the protection signal is always equal to the lowest value between the switching signal and the driven end, and effectively makes it possible to correctly switch the switching signal from the driven end to a lower protection signal when the driven end rises from low voltage or drops from high voltage to exceed the protection signal. The P switching signal and N switching signal generation circuit proposed in the present application reduce the occurrence of reflection phenomenon in the prior art, improve the stability of the series technology, and make the overvoltage working scene of the driving circuit run stably.

[0040] As one implementation mode, the three-stage series module includes a first driver submodule and a second driver submodule;

[0041] Wherein, the first driver submodule is used to be turned on when the P drive signal is logic low, and drive the IO output high;

[0042] The second driving submodule is used to be turned on when the N driving signal is logic high, and to drive the IO output low.

[0043] Specifically, the three-stage series module of the embodiment of the present application is divided into a first driver submodule and a second driver submodule. One end of the input of the first driver submodule is connected to VIICO, that is, the power supply voltage of the IO driver circuit, and the other end is connected to VPAD. The first driver submodule is turned on when the P drive signal is logically low, and drives the IO output high, and is disconnected when the P drive signal is logically high. One end of the second driver submodule is grounded, and the other end is connected to VPAD. The second driver submodule is turned on when the N drive signal is logically high, and drives the IO output low, and is disconnected when the N drive signal is logically low. Voltage resistance protection is achieved by the first driver submodule and the second driver submodule.

[0044] As one implementation mode, the first driving submodule includes a first PMOS tube, a second PMOS tube and a third PMOS tube, the gate of the first PMOS tube is connected to a P driving signal, the source of the first PMOS tube is connected to an operating voltage, the drain of the first PMOS tube is connected to a source of the second PMOS tube, the gate of the second PMOS tube is connected to a P protection signal, the drain of the second PMOS tube is connected to a source of the third PMOS tube, the gate of the third PMOS tube is connected to a P switching signal, and the drain of the third PMOS tube is connected to a driven end.

[0045] Specifically, in the embodiment of the present application, the first PMOS tube needs to be connected to the P drive signal because it is directly connected to the power supply. The P drive signal is a control signal that controls the output of the entire three-stage cascade PMOS to be high. When the P drive signal is logic high, the three-stage cascade PMOS output is turned off, and the state of IO is determined by the three-stage cascade NMOS. When the P drive signal is logic low, the three-stage cascade PMOS output is turned on, driving the IO output high.

[0046] The P protection signal is to protect the three-stage cascade PMOS from overvoltage when working at high voltage, that is, Vds overvoltage, to prevent the occurrence of hot carrier HCI phenomenon. If the protection circuit composed of the P protection signal and the second PMOS, as well as the P switching signal and the third PMOS tube is missing, when the IO output state is low, the Vds of the first PMOS tube will be equal to VCCIO, which exceeds the working voltage range of the first PMOS tube.

[0047] Only having a P protection signal and a second PMOS tube, but lacking a P switching signal and a third PMOS tube as a protection circuit, will cause the second PMOS tube to have a Vds overvoltage during the switching process of IO from low output to high. Figure 4 As shown in (a), the voltage difference between the pmid1 point and the pmid0 point of the second PMOS tube will exceed the voltage resistance range of the second PMOS tube during the rising process of IO from low to high, wherein pmid1 is the node between the first PMOS tube and the second PMOS tube, and pmid0 is the node between the second PMOS tube and the third PMOS tube, so the third-level PMOS tube needs to be connected to the P switching signal.

[0048] Reference Figure 4 (a) is a voltage diagram of pmid0 / pmid1 / VPAD when the drive circuit outputs a high signal. If there is no voltage divider protection of the third PMOS tube, when the P drive signal switches from logic high to logic low, pmid1 will be quickly pulled up, causing the source-drain voltage difference of the second PMOS to exceed the withstand voltage range, and then be affected by the HCI effect, which will damage the reliability of the drive circuit.

[0049] As one of the implementation modes, the second driving submodule includes a first NMOS tube, a second NMOS tube and a third NMOS tube, the gate of the first NMOS tube is connected to an N driving signal, the source of the first NMOS tube is grounded, the drain of the first NMOS tube is connected to the source of the second NMOS tube, the gate of the second NMOS tube is connected to an N protection signal, the drain of the second NMOS tube is connected to the source of the third NMOS tube, the gate of the third NMOS tube is connected to an N switching signal, and the drain of the third NMOS tube is connected to a driven end.

[0050] Specifically, in the embodiment of the present application, the N drive signal is a control signal that controls the entire three-stage cascade NMOS output to be low. When the N drive signal is logic low, the three-stage cascade NMOS output is turned off, and the state of the IO is determined by the three-stage cascade PMOS. When the N drive signal is logic high, the three-stage cascade NMOS output is turned on, driving the IO output to be low.

[0051] The N protection signal is to protect the three-stage cascade NMOS from overvoltage when working at high voltage, that is, Vds overvoltage, to prevent the occurrence of hot carrier HCI phenomenon. If the protection circuit composed of the N protection signal and the second NMOS, as well as the N switching signal and the third NMOS tube is missing, when the IO output state is low, it exceeds the working voltage range of the first PMOS tube.

[0052] Among them, nmid1 is a node between the first NMOS tube and the second NMOS tube, and nmid0 is a node between the second NMOS tube and the third NMOS tube.

[0053] Reference Figure 4 (b) is a voltage diagram of nmid0 / nmid1 / VPAD when the drive circuit outputs a low signal. If there is no voltage divider protection of the third NMOS tube, when the N drive signal switches from logic low to logic high, nmid1 will be quickly pulled down, causing the source-drain voltage Vds difference of the second NMOS to exceed the withstand voltage range, and then be affected by the HCI effect, which will damage the reliability of the drive circuit.

[0054] As one implementation mode, the protection signal of the embodiment of the present application is 1.8V.

[0055] Specifically, in the embodiment of the present application, VCCIO, i.e., the power supply voltage of the IO driving circuit, is 3.3 V, and VPAD, i.e., the voltage signal of the IO PAD, varies from 0 to 3.3 V. When working at high voltage, VCCIO=3.3 V. In order to prevent the first driving submodule or the second driving submodule from overvoltage, the P protection signal, i.e., the protection signal of the second PMOS tube, is 1.8 V, and the N protection signal, i.e., the protection signal of the second NMOS tube, is 1.8 V.

[0056] As another implementation, when VCCIO, i.e., the IO driving circuit power supply voltage, is 3.3V, the P protection signal, i.e., the protection signal of the second PMOS tube, is 1.65V, and the N protection signal, i.e., the protection signal of the second NMOS tube, is 1.65V.

[0057] As another implementation, when VCCIO, ie, the IO driving circuit power supply voltage, is 2.5V, the P protection signal, ie, the protection signal of the second PMOS tube, is 0.9V, and the N protection signal, ie, the protection signal of the second NMOS tube, is 0.9V.

[0058] As one implementation manner, the switching signal generating module includes a first switching signal submodule and a second switching signal submodule;

[0059] The first switching signal submodule is used to adjust and generate a P switching signal according to the P protection signal of the first driving submodule, the driven end feedback signal and the three-stage series feedback signal;

[0060] The second switching signal submodule is used to adjust and generate an N switching signal according to the N protection signal of the second driving submodule, the driven end feedback signal and the three-stage series feedback signal.

[0061] Specifically, the switching signal generating module of the embodiment of the present application is divided into a first switching signal submodule and a second switching signal submodule, wherein the output end of the first switching signal submodule is correspondingly connected to the third PMOS tube of the first driving submodule, and the output end of the second switching signal submodule is correspondingly connected to the third NMOS tube of the second driving submodule. The first switching signal submodule generates a P switching signal according to the P protection signal of the first driving submodule, the driven end feedback signal and the three-stage series feedback signal. The second switching signal submodule generates an N switching signal according to the N protection signal of the second driving submodule, the driven end feedback signal and the three-stage series feedback signal.

[0062] As one implementation manner, the first switching signal submodule includes a tube MN1, a tube MN2 and a tube MN3, the gate of the tube MN1 is connected to the drain of the second PMOS tube, the drain of the tube MN1 is connected to the P protection signal, the source of the tube MN1 is connected to the P switching signal, the gate of the tube MN2 is connected to the P protection signal, the drain of the tube MN2 is connected to the source of the tube MN1, the source of the tube MN2 is connected to the P switching signal, the gate of the tube MN3 is connected to the driven end, the drain of the tube MN3 is connected to the P protection signal, and the source of the tube MN3 is connected to the P switching signal.

[0063] Specifically, when the gate of MN3 is connected to VPAD, that is, VB, the source is connected to the P switching signal, the drain is connected to the P protection signal, and the gate of MN2 is connected to the P protection signal, the source is connected to the P switching signal, and the drain is connected to VPAD, MN2 and MN3 together form a low-voltage gating circuit. The main function is that when the IO output is high, when VPAD starts to rise from low, the low-voltage gating circuit ensures that the P protection signal will always be equal to the lowest value between the P switching signal and VPAD. However, there is a problem with such a low-voltage gating circuit, that is, when VPAD rises from a low voltage to a moment T0 equal to or slightly exceeding the P protection signal, the P switching signal cannot correctly select the signal with the lowest voltage between the two. Even if VPAD slightly exceeds the P protection signal, the P switching signal is still equal to VPAD, forming an overshoot. Only when VPAD exceeds a threshold voltage of the P protection signal, the low-voltage gating circuit will switch the P switching signal from VPAD to a lower P protection signal at T1. This threshold voltage is related to the process and is roughly between 0.4V and 0.7V. Figure 5 As shown in (a), the overshoot between T0 and T1 will seriously deteriorate the output impedance of the third PMOS in the three-stage cascade IO, and the overall internal resistance Rn of the IO driving circuit will increase instead of decrease as VPAD, that is, as VB increases.

[0064] The transistor MN1, the transistor MN2 and the transistor MN3 of the present application are all NMOS transistors.

[0065] The embodiment of the present application adds an MN1 on the basis of the low voltage gating circuit constructed by MN2 and MN3. The gate of MN1 is connected to pmid0, the source is connected to the P switching signal, and the drain is connected to the P protection signal. MN1 can effectively help the low voltage gating circuit to correctly switch the P switching signal from VPAD to a lower P protection signal when VPAD rises from a low voltage to exceed the P protection signal. Its working principle is that when VPAD rises from a low voltage to equal to or slightly exceeds the P protection signal, pmid0 has already risen to VCCIO relative to VPAD, so MN1 is in a fully on state, thereby smoothly switching the P protection signal to the P switching signal. Figure 5 (b) shows, thus removing Figure 5 (a) The overshoot of the P switching signal is reduced, thereby improving the stability of the series technology and making the overvoltage working scenario of the drive circuit stable.

[0066] As one implementation manner, the second switching signal submodule includes a tube MP1, a tube MP2 and a tube MP3, the gate of the tube MP1 is connected to the drain of the second NMOS tube, the source of the tube MP1 is connected to the N protection signal, the drain of the tube MP1 is connected to the N switching signal, the gate of the tube MP2 is connected to the N protection signal, the source of the tube MP2 is connected to the drain of the tube MP1, the drain of the tube MP2 is connected to the N switching signal, the gate of the tube MP3 is connected to the driven end, the source of the tube MP3 is connected to the N protection signal, and the drain of the tube MP3 is connected to the N switching signal.

[0067] Specifically, refer to Figure 6 (a), when the gate of MP3 is connected to VPAD, the source is connected to the N switching signal, and the drain is connected to the N protection signal, and the gate of MP2 is connected to the N protection signal, the source is connected to the N switching signal, and the drain is connected to VPAD, MP2 and MP3 together form a common high voltage gating circuit. The main function is that when the IO output is low, when VPAD starts to decrease from high, the high voltage gating circuit ensures that the N protection signal is always equal to the highest value between the N switching signal and VPAD. Such a high voltage gating circuit has a significant disadvantage. When VPAD is reduced from high voltage to equal to or slightly lower than the N protection signal at T0, the N switching signal cannot correctly select the signal with the highest voltage between the two. Even if VPAD is slightly lower than the N protection signal, the N switching signal is still equal to VPAD. Only when VPAD is lower than the N protection signal by a threshold voltage, the high voltage gating circuit will switch the N switching signal from VPAD to the higher N protection signal at T1. This threshold voltage is related to the process and is roughly between 0.4V and 0.7V.

[0068] The tube MP1, the tube MP2 and the tube MP3 of the present application are all PMOS tubes.

[0069] In the embodiment of the present application, an additional MP1 is designed on the low voltage gating circuit. The gate of MP1 is connected to nmid0, the source is connected to the N switching signal, and the drain is connected to the N protection signal. MP1 can help the high voltage gating circuit to correctly switch the N switching signal from VPAD to a higher N protection signal when VPAD drops from high voltage to below the N protection signal. Its working principle is that when VPAD drops from high voltage to equal to or slightly lower than the N protection signal, nmid0 has already reached 0 relative to VPAD, so MP1 is in a fully on state, thereby smoothly switching the N protection signal to the N switching signal. Figure 6 (b) is shown. Figure 6 (a), thereby improving the stability of the series technology and making the overvoltage working scenario of the drive circuit stable.

[0070] As one implementation mode, a parasitic capacitance module is further included, which is used to adjust the switching signal according to the driving signal and provide undershoot and overshoot for the switching signal respectively.

[0071] The parasitic capacitor module includes a parasitic capacitor Cp and a parasitic capacitor Cn; wherein the parasitic capacitor Cp is used to adjust the P switching signal according to the P driving signal and provide an undershoot for the P switching signal; the parasitic capacitor Cn is used to adjust the N switching signal according to the N driving signal and provide an overshoot for the N switching signal.

[0072] Specifically, the embodiment of the present application not only provides a low voltage gating circuit for the tube MN1, but also adds a parasitic capacitor Cp, which is connected between the P switching signal and the P driving signal. Its function is to allow the P driving signal to pass through the coupling effect of Cp, so that there is not only no overshoot on the P switching signal, but also an additional undershoot is generated, such as Figure 5 As shown in (c). Since the P switching signal is the gate control voltage of the third PMOS tube, this undershoot can make the on-resistance of the third PMOS tube lower, as shown in Figure 7 As shown, the overall internal resistance Rn of the IO driving circuit is effectively reduced, and the output amplitude of VPAD is increased, thereby avoiding the influence of reflection on the IO driving circuit, improving the stability of the series connection technology, and making the overvoltage working scenario of the driving circuit run stably.

[0073] The generation method of the P switching signal includes only MN2 and MN3 in the prior art, such as Figure 5 (a), only MN1, MN2 and MN3, such as Figure 5 (b), and the waveforms of the P switching signals generated by the three circuits MN1, MN2, MN3 and Cp, as shown in Figure 5 (c). Of these only Figure 5 (c) The third-stage PMOS tube controlled by the P switching signal generated can completely ensure that IO will not be affected by reflection.

[0074] The embodiment of the present application also provides a low voltage gating circuit for the tube MP1 and further adds a parasitic capacitor Cn, which is connected between the N switching signal and the N driving signal. Its function is to allow the N driving signal to generate an additional overshoot on the N switching signal through the coupling effect of Cn, such as Figure 6 As shown in (c), since the N switching signal is the gate control voltage of the third NMOS tube, this overshoot can reduce the on-resistance of the third NMOS tube, avoid the influence of IO on reflection, and make the overvoltage working scenario of the driving circuit run stably.

[0075] As one implementation manner, the capacitance of the parasitic capacitor Cp and the parasitic capacitor Cn are both 40fF to 100fF.

[0076] Specifically, the function of the parasitic capacitor Cp in the embodiment of the present application is to introduce an undershoot on the P switching signal through a signal that can generate a falling edge through coupling of Cp, thereby reducing the on-resistance of the third PMOS tube. Therefore, one end of Cp needs to be connected to the P switching signal, and the other end can be connected to the P drive signal or the N drive signal. It needs to be connected to a signal that can generate a falling edge when the IO output is high. The P switching signal is a signal that can generate a falling edge, and the falling edge is coupled to the P switching signal through the Cp capacitor, so that the P switching signal simultaneously generates an undershoot, thereby reducing the on-resistance of the third PMOS tube. The same applies to the parasitic capacitor Cn.

[0077] The lower limit of the capacitance value of Cp in the embodiment of the present application needs to be determined according to the internal resistance when the IO is designed. If the overall internal resistance of the IO is relatively large, Cp needs a larger capacitance value to generate a sufficiently large undershoot to lower the on-resistance of the third PMOS tube, ensuring that the overall output internal resistance Rn of the three-stage cascaded IO can stably intersect at a lower resistance value, thereby outputting a higher VPAD voltage, that is, VB voltage. The same is true for Cn.

[0078] The upper limit of Cp capacitance needs to be determined according to the maximum output frequency when IO is designed. No matter one end of Cp is connected to P drive signal or N drive signal, it will become an additional load of P drive signal or N drive signal. When Cp is too large, IO will not reach the designed maximum output frequency due to excessive load of drive signal. The maximum output frequency of general IO will not exceed 200MHz, so the upper limit of Cp capacitance should not exceed 5pF.

[0079] That is, the lowest capacitance value of the capacitor must be able to ensure that the P switching signal can generate an undershoot or the N switching signal can generate an overshoot waveform. The highest capacitance value must be able to ensure that the driving speed of the P drive or N drive signal is not affected. The capacitor Cp or Cn can be regarded as an additional load for the P drive or N drive signal at this time. Too high a capacitance value will reduce the driving speed of the P drive or N drive signal. Therefore, the upper limit of the capacitance value is determined according to the design indicators of the actual circuit, such as the maximum output frequency and the acceptable degree of reflection. The capacitance of the embodiment of the present application is between 40fF and 100fF.

[0080] In the embodiment of the present application, Figure 5 Schematic diagram of the waveform of the P switching signal generated by the P switching signal generating circuits with different structures when the driving circuit outputs a high signal. From left to right, Figure 5 (a) is a schematic diagram of the P switching signal waveform generated when there is only MN2 / MN3. Figure 5 (b) is a schematic diagram of the P switching signal waveform generated when only MN1 / MN2 / MN3 is present. Figure 5(c) is a schematic diagram of the P switching signal waveform generated by MN1 / MN2 / MN3 / Cp. When there is only MN2 / MN3, the P switching signal increases with the increase of VPAD. At T0, the P switching signal and VPAD both rise to the same amplitude as the P protection signal, but the P switching signal will continue to rise with VPAD, forming an overshoot waveform. It is not until T1 that the P switching signal switches to the P protection signal and remains consistent. At this time, the high signal output by the driving circuit will have an insufficient swing in the case of reflection.

[0081] When there are only MN1 / MN2 / MN3, the P switching signal increases with the increase of VPAD. At T0, the P switching signal and VPAD both rise to the same amplitude as the P protection signal. After that, the P switching signal will switch to the P protection signal and remain consistent with it. At this time, the high signal output by the driving circuit may still have a full swing phenomenon under reflection. When MN1 / MN2 / MN3 / Cp are composed together, the P switching signal increases with the increase of VPAD. Before T0, the P switching signal will form an undershoot waveform due to Cp. At T0, the P switching signal and VPAD both rise to the same amplitude as the P protection signal. After that, the P switching signal will switch to the P protection signal and remain consistent. At this time, the high signal output by the driving circuit will not have a full swing phenomenon under reflection, but will output a normal full swing signal. Improve the stability of the series technology and make the overvoltage working scenario of the driving circuit run stably.

[0082] Figure 6 Schematic diagram of the waveform of the N switching signal generated by the N switching signal generating circuits with different structures when the driving circuit outputs a low signal. From left to right, Figure 6 (a) is a schematic diagram of the N switching signal waveform generated when there is only MP2 / MP3. Figure 6 (b) is a schematic diagram of the N switching signal waveform generated when there are only MP1 / MP2 / MP3. Figure 6 (c) is a schematic diagram of the N-switching signal waveform generated by MP1 / MP2 / MP3 / Cn. The N-switching signal not only protects the third NMOS tube, but also ensures that the drive circuit outputs a low signal with a full swing. This improves the stability of the series connection technology and enables the drive circuit to operate stably in overvoltage working scenarios.

[0083] An embodiment of the present application provides an electronic device, including the three-stage series-connected IO withstand voltage driving circuit as described above.

[0084] An embodiment of the present application provides a device, including the three-stage series-connected IO withstand voltage driving circuit as described above.

[0085] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-described device and product can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0086] In several embodiments provided in this application, it should be understood that the disclosed methods, systems, devices and program products may be implemented in other ways.

[0087] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0088] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A three-stage series IO withstand voltage driving circuit, characterized in that: include: The three-stage series module is used to receive the drive signal, protection signal and switching signal; it adjusts the on-off status according to the logic level of the drive signal; When the on-off condition is on, the operating voltage is limited according to the protection signal; the output signal output to the driven end is adjusted according to the switching signal; The switching signal generating module is used to receive the protection signal, the driven end feedback signal and the three-stage series feedback signal, and to adjust and generate the switching signal according to the protection signal, the driven end feedback signal and the three-stage series feedback signal.

2. The three-stage series IO withstand voltage driving circuit according to claim 1, characterized in that: The three-stage series module includes a first driver submodule and a second driver submodule; Wherein, the first driver submodule is used to be turned on when the P drive signal is logic low, and drive the IO output high; The second driving submodule is used to be turned on when the N driving signal is logic high, and to drive the IO output low.

3. The three-stage series IO withstand voltage driving circuit according to claim 1, characterized in that: Also includes: A parasitic capacitance module, used for adjusting the switching signal according to the driving signal, and providing undershoot and overshoot to the switching signal respectively; The parasitic capacitance module includes a parasitic capacitance Cp and a parasitic capacitance Cn; Wherein, the parasitic capacitor Cp is used to adjust the P switching signal according to the P driving signal and provide an undershoot for the P switching signal; The parasitic capacitor Cn is used to adjust the N switching signal according to the N driving signal and provide an overshoot for the N switching signal.

4. The three-stage series IO withstand voltage driving circuit according to claim 2, characterized in that: The switching signal generating module comprises a first switching signal submodule and a second switching signal submodule; The first switching signal submodule is used to adjust and generate a P switching signal according to the P protection signal of the first driving submodule, the driven end feedback signal and the three-stage series feedback signal; The second switching signal submodule is used to adjust and generate an N switching signal according to the N protection signal of the second driving submodule, the driven end feedback signal and the three-stage series feedback signal.

5. The three-stage series IO withstand voltage driving circuit according to claim 4, characterized in that: The first driving submodule includes a first PMOS tube, a second PMOS tube and a third PMOS tube, the gate of the first PMOS tube is connected to a P driving signal, the source of the first PMOS tube is connected to an operating voltage, the drain of the first PMOS tube is connected to a source of the second PMOS tube, the gate of the second PMOS tube is connected to a P protection signal, the drain of the second PMOS tube is connected to a source of a third PMOS tube, the gate of the third PMOS tube is connected to a P switching signal, and the drain of the third PMOS tube is connected to a driven end.

6. The three-stage series IO withstand voltage driving circuit according to claim 4, characterized in that: The second driving submodule includes a first NMOS tube, a second NMOS tube and a third NMOS tube, the gate of the first NMOS tube is connected to an N driving signal, the source of the first NMOS tube is grounded, the drain of the first NMOS tube is connected to the source of the second NMOS tube, the gate of the second NMOS tube is connected to an N protection signal, the drain of the second NMOS tube is connected to the source of the third NMOS tube, the gate of the third NMOS tube is connected to an N switching signal, and the drain of the third NMOS tube is connected to a driven end.

7. The three-stage series IO withstand voltage driving circuit according to claim 5, characterized in that: The first switching signal submodule includes a tube MN1, a tube MN2 and a tube MN3, wherein the tube MN1, the tube MN2 and the tube MN3 are all NMOS tubes, the gate of the tube MN1 is connected to the drain of the second PMOS tube, the drain of the tube MN1 is connected to the P protection signal, the source of the tube MN1 is connected to the P switching signal, the gate of the tube MN2 is connected to the P protection signal, the drain of the tube MN2 is connected to the source of the tube MN1, the source of the tube MN2 is connected to the P switching signal, the gate of the tube MN3 is connected to the driven end, the drain of the tube MN3 is connected to the P protection signal, and the source of the tube MN3 is connected to the P switching signal.

8. The three-stage series IO withstand voltage driving circuit according to claim 6, characterized in that: The second switching signal submodule includes a tube MP1, a tube MP2 and a tube MP3, wherein the tube MP1, the tube MP2 and the tube MP3 are all PMOS tubes, the gate of the tube MP1 is connected to the drain of the second NMOS tube, the source of the tube MP1 is connected to the N protection signal, the drain of the tube MP1 is connected to the N switching signal, the gate of the tube MP2 is connected to the N protection signal, the source of the tube MP2 is connected to the drain of the tube MP1, the drain of the tube MP2 is connected to the N switching signal, the gate of the tube MP3 is connected to the driven end, the source of the tube MP3 is connected to the N protection signal, and the drain of the tube MP3 is connected to the N switching signal.

9. An electronic device, characterized in that: A three-stage series IO withstand voltage driving circuit comprising any one of claims 1-8.

10. A device, characterized in that: A three-stage series IO withstand voltage driving circuit comprising any one of claims 1-8.

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