An implementation device of SOT-based digital and gate and or gate

Abstract

The application discloses an implementation device of a digital and gate and or gate based on SOT, comprising two magnetic tunnel junctions, an SOT coupling layer, four MOS tubes and a reading control circuit; one end of the SOT coupling layer is connected with the source of a first MOS tube and the source of a second MOS tube, and the other end is grounded; two magnetic tunnel junctions MTJ1 and MTJ2 with different sizes are fixed on the surface of the SOT coupling layer, the magnetic tunnel junctions are sequentially composed of a free layer, an oxide isolation layer and a fixed layer from bottom to top, and the fixed layer of the magnetic tunnel junctions is connected with the source of a third MOS tube and the source of a fourth MOS tube respectively; the drain and the gate of the third MOS tube and the fourth MOS tube are connected with the reading control circuit. The current data measured by the application will not be lost due to power failure, and the application has a storage function and a small structure size area, and is suitable for a high-density memory-computing integrated structure.

Description

Technical Field

[0001] The invention belongs to the technical field of circuit design and relates to a device for realizing a digital AND gate and an OR gate based on a SOT. Background Art

[0002] A magnetic tunnel junction (MTJ) is a device affected by the spin-orbit torque (SOT) effect, with high and low resistance states. Its resistance state is determined by the polarization directions of the reference and free layers. The SOT coupling layer utilizes strong spin-orbit interaction, converting charge flow into spin current through the spin Hall effect or Rashba effect, which is injected into the free layer. This exerts a spin-orbit torque, driving magnetic moment reversal or magnetic domain wall movement, and changing the polarization direction. When the polarization directions are parallel, the probability of electron tunneling is high and the resistance is low; when they are antiparallel, the probability of tunneling is low and the resistance is high. Under the action of an applied current, the MTJ can switch between these two resistance states. As a new storage technology, more and more semiconductor manufacturers are increasing their research and development and investment in MRAM technology to seek more cost-effective, faster, and more efficient storage solutions.

[0003] Today, digital and analog integrated circuits based on the von Neumann architecture have rapidly developed, becoming a key force driving the internet and an indispensable cornerstone of information processing in modern society. However, as technology advances and the demand for information processing and storage for complex tasks continues to increase, the traditional von Neumann architecture has become a limiting factor, forcing people to explore new architectures.

[0004] To overcome the von Neumann bottleneck, researchers have proposed a memory-based, in-memory computing architecture. This new computer architecture performs logical operations directly in memory, eliminating the need to move data between memory and the processor. This significantly improves data processing efficiency and reduces device power consumption.

[0005] To develop in-memory computing, a device with both storage and computing capabilities is needed. A magnetic tunnel junction (MTJ) can represent a logical state through its resistance state. MTJs with different threshold currents will partially flip while others will not under the same constant current. This property can be used to construct a variety of logic circuits. Furthermore, MTJs maintain their state after power failure, offering advantages such as non-volatility, radiation resistance, erasure resistance, and high speed. These advantages make them suitable for harsh environments, extend their lifespan, and improve efficiency. Their small size also facilitates chip integration.

[0006] Compared with the already proposed STT-MTJ as the core device of the storage and computing integrated circuit, SOT-MTJ has lower write latency, reduces data transmission delay, and is more suitable for high-performance computing needs; and the read and write circuits are separated, reducing read and write interference and improving parallel processing capabilities. Summary of the Invention

[0007] In response to the shortcomings of existing research, the present invention proposes an implementation device of digital AND gates and OR gates based on SOT to reliably and stably implement "AND" and "OR" operations, which can be widely used in in-memory operations.

[0008] A device for realizing a digital AND gate and an OR gate based on SOT comprises two magnetic tunnel junctions, an SOT coupling layer, four MOS tubes and a read control circuit.

[0009] The SOT-based digital AND gate and OR gate implementation device specifically includes: one end of a SOT coupling layer is connected to the source of a first MOS transistor and the source of a second MOS transistor, and the other end is grounded; two magnetic tunnel junctions of different sizes are fixed on the surface of the SOT coupling layer, the two magnetic tunnel junctions are MTJ1 and MTJ2, the magnetic tunnel junctions are composed of a free layer, an oxide isolation layer and a fixed layer from bottom to top, and the two magnetic tunnel junctions require different switching threshold currents, the fixed layers of the magnetic tunnel junctions are respectively connected to a third MOS transistor and a fourth MOS transistor, wherein the source of the third MOS transistor is connected to the fixed layer of MTJ1, and the source of the fourth MOS transistor is connected to the fixed layer of MTJ2; the drains and gates of the third and fourth MOS transistors are both connected to a read control circuit.

[0010] The read control circuit is used to select whether to perform an AND operation or an OR operation. If the AND operation is performed, the third MOS transistor is turned on, the remaining MOS transistors are turned off, and the AND operation result is output through the sense amplifier. If the OR operation is performed, the fourth MOS transistor is turned on, the remaining MOS transistors are turned off, and the OR operation result is output through the sense amplifier. The gate of the first MOS transistor is connected to a first input voltage, and the gate of the second MOS transistor is connected to a second input voltage. The drain of the first MOS transistor is connected to a fixed voltage VIN1, and the drain of the second MOS transistor is connected to a fixed voltage VIN2. The resistance of the magnetic tunnel junction is adjusted according to the input voltage.

[0011] Preferably, the SOT coupling layer conductor may be made of platinum, tantalum, tungsten, or a combination thereof.

[0012] Preferably, the two magnetic tunnel junctions are made of the same material and diameter but have different heights.

[0013] Preferably, the two magnetic tunnel junctions are made of the same material and height but have different diameters.

[0014] As an example, the read control circuit is specifically as follows: one end of the sense amplifier SA1 is connected to the drain of the third MOS tube, and the other end is connected to the reference resistor R ref1 Ground; one end of the sensitive amplifier SA2 is connected to the drain of the fourth MOS tube, and the other end is connected to the reference resistor R ref2 The third MOS transistor gate and the fourth MOS transistor gate are connected to fixed voltages C and D respectively.

[0015] The magnetic tunnel junction consists of a free layer, an oxide isolation layer, and a pinned layer, from bottom to top. Both the pinned and free layers are ferromagnetic materials, and the magnetization direction of the pinned layer remains fixed. The magnetization direction of the free layer is affected by the SOT effect. When the magnetization directions of the two layers are aligned, the magnetic tunnel junction exhibits a low-resistance state; when the magnetization directions are opposite, it exhibits a high-resistance state. The oxide isolation layer is a non-magnetic insulating material.

[0016] Assume that the equivalent resistance value of the magnetic tunnel junction MTJ1 when it is low resistance is R1, the equivalent resistance value of MTJ2 when it is low resistance is R2, the equivalent resistance value of MTJ1 when it is high resistance is R3, and the equivalent resistance value of MTJ2 when it is high resistance is R4; wherein the equivalent resistance values ​​R1<R2<R3<R4.

[0017] The implementation principle of the digital AND gate and OR gate implementation device based on SOT of the present invention is as follows:

[0018] Initialize the two magnetic tunnel junctions, pass a flip current into the SOT coupling layer, flip the magnetic tunnel junctions on the surface to a low-resistance state, and then remove the flip current.

[0019] The gate voltages of the first MOS transistor and the second MOS transistor are controlled, and currents of different magnitudes are applied to the current input end of the SOT coupling layer to change the state of the magnetic tunnel junction.

[0020] Remove the input current, disconnect the coupling layer between the MOS tube and the SOT, and read the resistance of the magnetic tunnel junction collected by the control circuit.

[0021] Define different Rs as different logic outputs, establish a logical relationship table between input voltage and output voltage, and construct "AND" logic and "OR" logic according to the input and output control of different MOS tubes.

[0022] The present invention has the following beneficial effects:

[0023] 1. Two magnetic tunnel junctions of different sizes are used to form a logic gate circuit.

[0024] 2. Due to the non-volatile characteristics of the magnetic tunnel junction, the measured current data will not be lost due to power failure and has storage function.

[0025] 3. The structural size and area of ​​this device are relatively small, making it suitable for high-density storage and computing integrated structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Schematic diagram of a device for implementing a digital AND gate and an OR gate based on SOT in an embodiment;

[0027] Figure 2A flow chart of an implementation device of a digital AND gate and OR gate based on SOT;

[0028] Figure 3 A schematic diagram of a circuit for measuring the resistance state of an MTJ in an embodiment;

[0029] Figure 4 A structural diagram of a single MTJ and a schematic diagram of the magnetic moment direction of the MTJ;

[0030] In the figure: 01-SOT coupling layer, 02-MTJ1, 03-MTJ2, 04-third MOS tube, 05-fourth MOS tube, 06-first MOS tube, 07-second MOS tube. DETAILED DESCRIPTION

[0031] In general, in order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Of course, the described embodiments are a part of the embodiments of the present application, not all the embodiments. The components of the embodiments of the present application described and shown in the drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the present application.

[0032] The embodiments of the present application will be described in detail below, and examples of the embodiments are shown in the drawings, wherein the same or similar reference signs represent the same or similar elements or elements with the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and are intended to explain the present application, and cannot be understood as a limitation of the present application.

[0033] In the following, the embodiments of the present application will be described in detail with reference to the drawings.

[0034] An implementation device of a digital AND gate and OR gate based on SOT, as shown in Figure 1As shown in Fig. 1, it is a structure block diagram of the implementation device of the digital AND gate and OR gate based on SOT, which is connected by the SOT coupling layer 01 and two MTJs with different sizes through two necessary input signals. The whole logic unit can be equivalent to a 2T2M (two MTJs and two MOS tubes) structure, in which the MTJ is used for storing the non-volatile resistance value, and the read control circuit is used for reading the state of the MTJ; two MOS tubes are connected between the read control circuit and the MTJ, and each MOS tube represents different logic operation. The third MOS tube 04 is turned on, representing the result of the "AND" operation, and the fourth MOS tube 05 is turned on, representing the result of the "OR" operation. The two MOS tubes connected with the SOT coupling layer 01 are responsible for the resistance state inversion control of the MTJ.

[0035] When the first MOS tube 06 or the second MOS tube 07 is turned on, the input current makes the MTJ1 02 flip, and the MTJ2 03 does not flip; when the first MOS tube 06 and the second MOS tube 07 are both turned on, the input current makes the MTJ1 02 and the MTJ2 03 both flip.

[0036] As shown in Fig. 2, it is a flow chart of the implementation device of the digital AND gate and OR gate based on SOT, and the implementation principle is as follows: Figure 2

[0037] The above logic device is constructed, in which the size of the MTJ1 02 is smaller, the flip threshold current is small, the size of the MTJ2 03 is larger, the flip threshold current is large, and either the first input voltage or the second input voltage can make the MTJ1 02 reach its flip threshold current, the MTJ2 03 does not reach its flip threshold current, and the resistance value of the MTJ1 02 flips, and the resistance value of the MTJ2 03 does not change; the first input voltage and the second input voltage are simultaneously turned on, which can make the MTJ1 02 and the MTJ2 03 both reach their flip threshold currents, and the resistance values of the MTJ1 02 and the MTJ2 03 both flip.

[0038] Initialization, a large enough initialization current is input to the SOT layer, so that the MTJ1 02 and the MTJ2 03 are both in the low resistance state.

[0039] The opening and closing of the gate of the first MOS tube 06 is controlled by the fixed voltage first input voltage (A), the opening and closing of the gate of the second MOS tube 07 is controlled by the fixed voltage second input voltage (B), and different sizes of current are applied to the current input end on the SOT coupling layer 01, so that the state of the magnetic tunnel junction changes.

[0040] According to Figure 3 ​As shown, the input current is removed, and the gate voltage (A) of the first MOS transistor 06 and the gate voltage (B) of the second MOS transistor 07 are disconnected; when the "AND" operation is performed, the gate of the third MOS transistor 04 is controlled by the fixed voltage (C), and the third MOS transistor 04 and the sensitive amplifier SA1 are turned on. One end of SA1 is connected to the third MOS transistor 04, and the other end is connected to the reference resistor R ref1 , its resistance is (R1+R3) / 2, when the resistance of MTJ1 02 is low resistance R1, the output OUT1 = 0; when the resistance of MTJ1 02 is high resistance R3, the output OUT1 = 1; when the "OR" operation is performed, the gate of the fourth MOS tube 05 is controlled by a fixed voltage (D), the fourth MOS tube 05 and the sensitive amplifier SA2 are turned on, one end of SA2 is connected to the fourth MOS tube 05, and the other end is connected to the reference resistor R ref2 , its resistance is (R2+R4) / 2. When the resistance of MTJ203 is low resistance R2, the output OUT2=0; when the resistance of MTJ203 is high resistance R4, the output OUT2=1.

[0041] like Figure 4 As shown, the magnetic tunnel junction (MTJ) has a multi-layer film structure, including a free layer and a fixed layer composed of magnetic materials, and an oxide isolation layer between the two. When the current flowing from the fixed layer to the free layer exceeds a certain critical value for a certain period of time, the direction of the magnetic moment of the free layer is parallel to the direction of the magnetic moment of the fixed layer, and the MTJ presents a low resistance "0" state; conversely, when the current flowing from the free layer to the fixed layer exceeds a certain critical value for a certain period of time, the direction of the magnetic moment of the free layer is antiparallel to the direction of the magnetic moment of the fixed layer, and the MTJ presents a high resistance "1" state. The corresponding truth tables are shown in Tables 1 and 2 below:

[0042] Table 1: Truth table of logical "AND" operation

[0043]

[0044] Table 2: Logical OR operation truth table

[0045]

[0046] The above description is merely a partial embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. An implementation apparatus of SOT-based digital AND gate and OR gate, characterized in that, The application relates to a magnetic tunnel junction (MTJ) memory cell, which comprises two magnetic tunnel junctions, an SOT coupling layer, four MOS transistors and a read control circuit. One end of the SOT coupling layer is connected with the source of the first MOS transistor and the source of the second MOS transistor, and the other end is grounded; two magnetic tunnel junctions MTJ1 and MTJ2 with different sizes are fixed on the surface of the SOT coupling layer, the magnetic tunnel junctions MTJ1 and MTJ2 are sequentially provided with a free layer, an oxide isolation layer and a fixed layer from bottom to top, the fixed layer of the magnetic tunnel junction MTJ1 is connected with the source of the third MOS transistor, and the fixed layer of the magnetic tunnel junction MTJ2 is connected with the source of the fourth MOS transistor; the drain and the gate of the third MOS transistor and the fourth MOS transistor are connected with the read control circuit. The gate of the first MOS transistor is connected with a first input voltage, the gate of the second MOS transistor is connected with a second input voltage, the drain of the first MOS transistor is connected with a fixed voltage VIN1, and the drain of the second MOS transistor is connected with a fixed voltage VIN2; the resistance values of the magnetic tunnel junctions MTJ1 and MTJ2 are adjusted according to the first input voltage and the second input voltage.

2. The SOT-based implementation of a digital AND and OR gate according to claim 1, wherein, The SOT coupling layer conductor is one of platinum, tantalum and tungsten or a combination thereof.

3. The SOT-based implementation of a digital AND and OR gate according to claim 1, wherein, The two magnetic tunnel junctions have different required flip threshold current values.

4. The SOT-based implementation of a digital AND gate and OR gate as claimed in claim 1, wherein, The two magnetic tunnel junctions have the same material and diameter but different heights.

5. The SOT-based implementation of a digital AND and OR gate according to claim 1, wherein, The two magnetic tunnel junctions have the same material and height but different diameters.

6. The SOT-based implementation of a digital AND and OR gate according to claim 1, wherein, The fixed layer and the free layer in the magnetic tunnel junctions MTJ1 and MTJ2 are ferromagnetic materials, the magnetization direction of the fixed layer is fixed and unchangeable, and the magnetization direction of the free layer is affected by the SOT effect; the oxide isolation layer is non-magnetic insulating material.

7. The SOT-based implementation of a digital AND gate and OR gate as claimed in claim 1, wherein, The read control circuit is specifically: one end of a sensitive amplifier SA1 is connected with a drain of a third MOS tube, and the other end is connected with a reference resistor R ref1 ground; one end of a sensitive amplifier SA2 is connected with a drain of a fourth MOS tube, and the other end is connected with a reference resistor R ref2 The gate of the third MOS tube is connected with a fixed voltage C, and the gate of the fourth MOS tube is connected with a fixed voltage D.

8. The SOT-based implementation of a digital AND gate and OR gate as claimed in claim 7, wherein, When the digital AND gate and OR gate are implemented, the third MOS transistor is opened, the remaining MOS transistors are closed, the AND operation result is output through a sensitive amplifier SA1, and when the OR operation is performed, the fourth MOS transistor is opened, the remaining MOS transistors are closed, and the OR operation result is output through a sensitive amplifier SA2.

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