Bidirectional counter and method of generating output data

Abstract

The invention discloses a bidirectional counter and a method for generating output data. The bidirectional counter may include at least one first flip-flop configured to generate at least one first bit and a second bit that is a higher bit of the at least one first bit based on at least one first local clock, the at least one first bit including a least significant bit (LSB) of output data; and a local clock generation circuit configured to generate the at least one first local clock based on an input clock and the at least one first bit in response to an activated upward signal, and generate the at least one first local clock based on the input clock and the at least one inverted first bit in response to the deactivated upward signal.

Description

[0001] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0113194 and Korean Patent Application No. 10-2023-0185066, filed on August 28, 2023 and December 18, 2023, respectively, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entirety by reference. Technical Field

[0002] One or more disclosed example embodiments relate to counters, and more particularly, to bidirectional counters and integrated circuits including bidirectional counters. Background Art

[0003] A counter may refer to a device that stores the number of times a particular event has occurred. For example, a counter may receive a clock and store the number of times a rising edge or a falling edge of the clock has occurred. Counters may be used in a variety of applications, and an integrated circuit manufactured using a semiconductor manufacturing process may include multiple counters. As the clock frequency and integration density of integrated circuits increase, counters with high operating speeds and small areas may be required. Summary of the invention

[0004] One or more example embodiments disclosed provide a bidirectional counter having a high operation speed and a limited area and an integrated circuit including the bidirectional counter.

[0005] According to one aspect of an example embodiment of the invention, there is provided a bidirectional counter configured to generate output data based on an input clock, the bidirectional counter comprising: at least one first trigger configured to generate at least one first bit and a second bit as a higher bit of the at least one first bit based on at least one first local clock, the at least one first bit comprising a least significant bit (LSB) of the output data; and a local clock generating circuit configured to: generate the at least one first local clock based on the input clock and the at least one first bit in response to an activated up signal, and generate the at least one first local clock based on the input clock and at least one inverted first bit corresponding to an inverted version of the at least one first bit in response to a deactivated up signal.

[0006] According to one aspect of the inventive concept, a bidirectional counter configured to generate output data based on an input clock includes: at least one first flip-flop configured to generate a most significant bit (MSB) of output data and at least one first bit lower than the MSB based on at least one first local clock; a first pre-evaluation circuit configured to generate at least one first ripple carry based on the at least one first bit and a second bit lower than the at least one first bit in response to an activated up signal, and to generate the at least one first ripple carry based on an inverted second bit corresponding to an inverted version of the second bit and at least one inverted first bit corresponding to an inverted version of the at least one first bit in response to a deactivated up signal; and a first local clock selection circuit configured to generate the at least one first local clock based on an input clock, a first carry input, and the at least one first ripple carry.

[0007] According to one aspect of the inventive concept, a method for generating increased or decreased output data according to an input clock includes: receiving an up signal; in response to the activated up signal, generating at least one first local clock based on the input clock and at least one first bit, the at least one first bit including the LSB of the output data; in response to the deactivated up signal, generating the at least one first local clock based on the input clock and at least one inverted first bit corresponding to an inverted version of the at least one first bit; and generating the at least one first bit and a second bit as a higher bit of the at least one first bit based on the at least one first local clock. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0009] Figure 1 is a block diagram of a counter according to one or more example embodiments.

[0010] Figure 2 is a block diagram of a counter according to one or more example embodiments.

[0011] Figure 3A and Figure 3B is a timing diagram illustrating the operation of a counter according to an example embodiment.

[0012] Figure 4 is a circuit diagram illustrating a local clock generator according to one or more example embodiments.

[0013] Figure 5A and Figure 5B is a timing diagram illustrating an example of the operation of the first stage of the counter according to example embodiments.

[0014] Figure 6is a circuit diagram illustrating a pre-evaluator according to one or more example embodiments.

[0015] Fig. 7A and Figure 7B is a circuit diagram illustrating an example of a local clock selector according to an example embodiment.

[0016] Fig. 8A and Figure 8B is a timing diagram illustrating an example of the operation of the second stage of the counter according to example embodiments.

[0017] Fig. 9 is a flow chart illustrating the operation of a counter according to one or more example embodiments.

[0018] Fig.10 is a flow chart illustrating the operation of a counter according to one or more example embodiments.

[0019] Fig.11 is a flow chart illustrating the operation of a counter according to one or more example embodiments.

[0020] Fig.12 is a flowchart of a method of manufacturing an integrated circuit according to one or more example embodiments.

[0021] Fig.13 is a block diagram of a system on a chip according to one or more example embodiments. DETAILED DESCRIPTION

[0022] Hereinafter, example embodiments are described with reference to the accompanying drawings.

[0023] Figure 1 1 is a block diagram of a counter 10 according to one or more example embodiments. In some embodiments, the counter 10 may be included in an integrated circuit (IC) manufactured using a semiconductor manufacturing process. Here, unless otherwise stated, it is assumed that the signal is an active-high signal having a logic high level when activated and a logic low level when deactivated, but it should be noted that the embodiments are not limited thereto. As used herein, a logic high may correspond to a positive power supply voltage VDD and may be represented as "1". In addition, a logic low may correspond to a negative power supply voltage VSS and may be represented as "0".

[0024] like Figure 1As shown in , the counter 10 may receive an input clock CK and an up signal UP. The counter 10 may count events based on the input clock CK. For example, the counter 10 may count rising edges or falling edges of the input clock CK, and generate mn-bit output data Q (where m and n are integers greater than 1) having a value corresponding to the count. Here, it is assumed that the counter 10 counts rising edges of the input clock CK, but it should be noted that the embodiment is not limited thereto.

[0025] The counter 10 may operate as an up counter or a down counter according to the up signal UP. For example, the counter 10 may operate as an up counter in response to the activated up signal UP (e.g., "1"), while the counter 10 may operate as a down counter in response to the deactivated up signal UP (e.g., "0"). The counter 10 operating as an up counter or a down counter according to the up signal UP may be referred to as an up-down counter or a bidirectional counter.

[0026] like Figure 1 As shown in , the counter 10 may include a first segment SEG1 to an nth segment SEGn. Each of the first segment SEG1 to the nth segment SEGn may receive an input clock CK and an up signal UP, and generate at least one bit of output data Q. For example, Figure 1 As shown in , the first segment SEG1 can generate m-bit Q[m-1:0] including the least significant bit (LSB) of the output data Q, the second segment SEG2 can generate higher m-bit Q[2m-1:m], and the nth segment SEGn can generate m-bit Q[mn-1:m(n-1)] including the most significant bit (MSB) of the output data Q.

[0027] Each of the first segment SEG1 to the nth segment SEGn may generate a signal provided to the segment adjacent thereto. Figure 1 As shown in , the first segment SEG1 may generate a first signal SIG1 provided to the second segment SEG2. Similarly, the second segment SEG2 may generate a second signal SIG2 provided to the third segment SEG3, and the nth segment SEGn may receive the (n-1)th signal SIGn-1 from the (n-1)th segment SEGn-1.

[0028] The first segment SEG1 generating the m-bit Q[m-1:0] including the LSB of the output data Q may have a different structure from the remaining segments (such as the second segment SEG2 to the n-th segment SEGn) generating higher bits. For example, the first segment SEG1 may generate the m-bit Q[m-1:0] based on the input clock CK and the up signal UP, and each of the second segment SEG2 to the n-th segment SEGn may generate the m-bit based on the signal received from the previous segment and the input clock CK and the up signal UP.

[0029] As described below with reference to the accompanying drawings, the first segment SEG1 may include m flip-flops that generate m-bit Q[m-1:0] and a local clock generator that provides m local clocks to the m flip-flops, respectively. The local clock generator may generate m local clocks in different ways according to the up signal UP while using a simple structure, and thus supports both up counting and down counting. Therefore, the increased area in the counter 10 for implementing up counting and down counting may be minimized, and the counter 10 may have a reduced area. Each of the second segment SEG2 to the nth segment SEGn may pre-evaluate a ripple carry, and generate m local clocks based on the pre-evaluated ripple carry when a carry input is received. Therefore, the output data Q may be updated faster, and the performance of the counter 10 may be improved.

[0030] Figure 2 is a block diagram of a counter 20 according to one or more example embodiments. For example, Figure 2 The block diagram of FIG. 1 shows a counter 20 that generates 16 bits of output data Q and includes four segments (ie, m=4 and n=4) each generating 4 bits of output data Q. Figure 2 Although not shown for ease of illustration, Figure 2 The inverse signal of the signal shown in Figure 2 The signals shown in are generated and transmitted together, and an inverter generating an inverted signal is not shown. For ease of description, a 16-bit counter 20 including first to fourth segments SEG1 to SEG4 will be described below, each of which corresponds to 4 bits, but it is noted that the embodiment is not limited thereto.

[0031] like Figure 2 As shown in , the counter 20 may include first to fourth segments SEG1 to SEG4. Each of the first to fourth segments SEG1 to SEG4 may receive an input clock CK and an up signal UP, and generate 4 bits of output data Q. In addition, each of the second to fourth segments SEG2 to SEG4 may receive a carry input and 1 bit of output data Q from a previous segment. For example, the second segment SEG2 may receive a first carry input CI1 and a fourth bit Q[3] of output data Q from the first segment SEG1, and Figure 1 The first signal SIG1 may include the first carry input CI1 and the fourth bit Q[3]. The third segment SEG3 may receive the second carry input CI2 and the eighth bit Q[7] of the output data Q from the second segment SEG2, and Figure 1 The second signal SIG2 may include the second carry input CI2 and the eighth bit Q[7]. The fourth segment SEG4 may receive the third carry input CI3 and the twelfth bit Q

[11] of the output data Q from the third segment SEG3, and Figure 1The (n-1)th signal SIGn-1 may include the third carry input CI3 and the twelfth bit Q

[11] .

[0032] The first segment SEG1 may include four first flip-flops FF1 and a local clock generator LCG. The four first flip-flops FF1 may receive a 4-bit first local clock LC1 and generate 4-bit Q[3:0] of output data Q according to the first local clock LC1. In some embodiments, each of the four first flip-flops FF1 may be a toggle flip-flop having an output that switches at a rising edge of one bit of the first local clock LC1. Figure 2 As shown in , among 4 bits Q[3:0] of the output data Q, lower 3 bits Q[2:0] may be provided to the local clock generator LCG, and upper 1 bit as the fourth bit Q[3] may be provided to the second segment SEG2.

[0033] The local clock generator LCG may generate a first local clock LC1 based on the input clock CK and the up signal UP. In some embodiments, in response to the activated up signal UP, the local clock generator LCG may generate the first local clock LC1 based on the input clock CK and 3 bits Q[2:0] of the output data Q. In some embodiments, in response to the deactivated up signal UP, the local clock generator LCG may generate the first local clock LC1 based on the input clock CLK and 3 bits QB[2:0] of the inverted output data (referred to herein as QB). The 3 bits QB[2:0] of the inverted output data correspond to the inverted version of the 3 bits Q[2:0] of the output data Q. Refer to Figure 4 An example of describing a local clock generator LCG is shown below. Figure 4 As described above, the local clock generator LCG may include transistors and may be referred to as a local clock generating circuit.

[0034] The second segment SEG2 may include four second flip-flops FF2, a pre-evaluator PE2, and a local clock selector LCS2. The four second flip-flops FF2 may receive the second local clock LC2 and generate 4 bits Q[7:4] of the output data Q in response to the second local clock LC2. In some embodiments, each of the four second flip-flops FF2 may be a switching flip-flop that changes its output at a rising edge of one bit of the second local clock LC2. Figure 2 As shown in , among 4 bits Q[7:4] of the output data Q, lower 3 bits Q[6:4] may be provided to the pre-evaluator PE2, and upper 1 bit as the eighth bit Q[7] may be provided to the third segment SEG3.

[0035] The pre-evaluator PE2 may generate a first ripple carry CA1 based on the up signal UP and the 4-bit Q[6:3] of the output data Q. In some embodiments, in response to the activated up signal UP, the pre-evaluator PE2 may generate a first ripple carry CA1 based on the 4-bit Q[6:3] of the output data Q. In some embodiments, in response to the deactivated up signal UP, the pre-evaluator PE2 may generate a first ripple carry CA1 based on the 4-bit QB[6:3] of the inverted output data QB. Figure 6 An example of a pre-evaluator PE2 is described in more detail. Figure 6 As described, the pre-evaluator PE2 may include a transistor and may be referred to as a pre-evaluator circuit.

[0036] The local clock selector LCS2 may generate the second local clock LC2 and the second carry input CI2 based on the first ripple carry CA1 and the first carry input CI1. Before the first carry input CI1 is activated, the first ripple carry CA1 may be pre-evaluated by the pre-evaluator PE2, and when the activated first carry input CI1 is received, the local clock selector LCS2 may generate the second local clock LC2 based on the first ripple carry CA1. Therefore, the second local clock LC2 may be generated earlier. Fig. 8A and Figure 8B An example of a local clock selector LCS2 is described in more detail. Fig. 8A and Figure 8B As described above, the local clock selector LCS2 may include transistors, and may be referred to as a local clock generating circuit.

[0037] Each of the third segment SEG3 and the fourth segment SEG4 may have the same structure as the second segment SEG2. The third segment SEG3 may include four third flip-flops FF3, a pre-evaluator PE3, and a local clock selector LCS3. The four third flip-flops FF3 may generate 4 bits Q[11:8] of the output data Q based on the third local clock LC3. The pre-evaluator PE3 may generate a second ripple carry CA2 based on the up signal UP and the 4 bits Q[10:7] of the output data Q. The local clock selector LCS3 may generate a third local clock LC3 and a third carry input CI3 based on the second ripple carry CA2 and the second carry input CI2. The fourth segment SEG4 may include four fourth flip-flops FF4, a pre-evaluator PE4, and a local clock selector LCS4. The four fourth flip-flops FF4 may generate 4 bits Q[15:12] of the output data Q based on the fourth local clock LC4. The pre-evaluator PE4 may generate a third ripple carry CA3 based on the up signal UP and the 4 bits Q[14:11] of the output data Q. The local clock selector LCS4 may generate a fourth local clock LC4 based on the third ripple carry CA3 and the third carry input CI3.

[0038] Figure 3A and Figure 3B is a timing diagram illustrating the operation of a counter according to an example embodiment. For example, Figure 3A The timing diagram shows the 4 bits Q[3:0] of the output data Q counting up, and Figure 3B The timing diagram shows 4 bits Q[3:0] of the output data Q in down counting.

[0039] Reference Figure 3A , assuming that there is a dummy bit as "1" lower than the LSB (i.e., Q[0]) of the output data Q, when the lower bits including the dummy bit are all 1, the higher bits may be converted from 0 to 1. For example, at time t11, Q[0] may be converted to 1 due to the dummy bit as 1, and at time t12, Q[1] may be converted to 1 due to the dummy bit as 1 and Q[0]. In addition, at time t13, Q[2] may be converted to 1 due to the dummy bit as 1 and Q[1:0], and at time t14, Q[3] may be converted to 1 due to the dummy bit as 1 and Q[2:0].

[0040] Reference Figure 3B , assuming that there is a dummy bit as 0 lower than the LSB (i.e., Q[0]) of the output data (Q), when the lower bits including the dummy bit are all 0, the higher bits may be converted from 1 to 0. For example, at time t21, Q[0] may be converted to 0 due to the dummy bit as 0, and at time t22, Q[1] may be converted to 0 due to the dummy bit as 0 and Q[0]. In addition, at time t23, Q[2] may be converted to 0 due to the dummy bit as 0 and Q[1:0], and at time t24, Q[3] may be converted to 0 due to the dummy bit as 0 and Q[2:0].

[0041] based on Figure 3A and Figure 3B The timing diagram can be found as follows Figure 4 The bidirectional counter is described by adding only a multiplexer that selects output data Q or inverted output data QB in response to an up signal UP. For example, the multiplexer may select output data Q in response to an activated up signal UP, while selecting inverted output data QB in response to a deactivated up signal UP.

[0042] Figure 4 is a circuit diagram showing a local clock generator 40 according to one or more example embodiments. For example, Figure 4 The circuit diagram shows Figure 2 An example of a local clock generator LCG. Figure 2 As described above, the local clock generator 40 can receive the input clock CK and the up signal UP, and generate a 4-bit first local clock LC1. Figure 4As shown in , the local clock generator 40 may include first to seventh p-channel field effect transistors (PFETs) P11 to P17, first to fourth n-channel FETs (NFETs) N11 to N14, first to fourth inverters INV11 to INV14, and first to third multiplexers MUX11 to MUX13.

[0043] The first to fourth PFETs P11 to P14 may precharge an output node at which the first local clock LC1 is generated in response to the deactivated input clock CK. Figure 4 As shown in , the first PFET P11 may precharge (or pull up) the first bit LC1[0] of the first local clock LC1 to 1 in response to the input clock CK of 0. The second PFET P12 may precharge (or pull up) the second bit LC1[1] of the first local clock LC1 to 1 in response to the input clock CK of 0. The third PFET P13 may precharge (or pull up) the third bit LC1[2] of the first local clock LC1 to 1 in response to the input clock CK of 0. The fourth PFET P14 may precharge (or pull up) the fourth bit LC1[3] of the first local clock LC1 to 1 in response to the input clock CK of 0.

[0044] The first to fourth NFETs N11 to N14 may transmit discharge of an output node at which the first local clock LC1 is generated in response to the activated input clock CK and the outputs of the first to third multiplexers MUX11 to MUX13. Figure 4 As shown in , the first NFET N11 may discharge (or pull down) the first bit LC1[0] of the first local clock LC1 to 0 in response to the input clock CK being 1. When the first bit LC1[0] of the first local clock LC1 is 0, the second NFET N12 may discharge (or pull down) the second bit LC1[1] of the first local clock LC1 in response to the activated output of the first multiplexer MUX11. When the second bit LC1[1] of the first local clock LC1 is 0, the third NFET N13 may discharge (or pull down) the third bit LC1[2] of the first local clock LC1 in response to the activated output of the second multiplexer MUX12. When the third bit LC1[2] of the first local clock LC1 is 0, the fourth NFET N14 may discharge (or pull down) the fourth bit LC1[3] of the first local clock LC1 in response to the activated output of the third multiplexer MUX13.

[0045] The first multiplexer MUX11 to the third multiplexer MUX13 can select the output data Q or the inverted output data QB according to the up signal UP. Figure 4As shown in , the first multiplexer MUX11 can select one of the first bit Q[0] of the output data Q and the first bit QB[0] of the inverted output data QB according to the up signal UP, and generate an output corresponding to the selected bit. The second multiplexer MUX12 can select one of the second bit Q[1] of the output data Q and the second bit QB[1] of the inverted output data QB according to the up signal UP, and generate an output corresponding to the selected bit. The third multiplexer MUX13 can select one of the third bit Q[2] of the output data Q and the third bit QB[2] of the inverted output data QB according to the up signal UP, and generate an output corresponding to the selected bit.

[0046] The fifth PFET P15 to the seventh PFET P17 and the first inverter INV11 to the third inverter INV13 may correspond to three latches. For example, the fifth PFET P15 and the first inverter INV11 may latch the second bit LC1[1] of the first local clock LC1. The sixth PFET P16 and the second inverter INV12 may latch the third bit LC1[2] of the first local clock LC1. The seventh PFET P17 and the third inverter INV13 may latch the fourth bit LC1[3] of the first local clock LC1. The fourth inverter INV14 may generate the first carry input CI1 by inverting the fourth bit LC1[3] of the first local clock LC1. In some embodiments, each of the first inverter INV11 to the fourth inverter INV14 may include a PFET and an NFET connected in series between a node to which a positive power supply voltage VDD is applied and a node to which a negative power supply voltage VSS is applied.

[0047] Figure 5A and Figure 5B is a timing diagram showing an example of the operation of the first segment SEG1 according to an example embodiment. For example, Figure 5A The timing diagram shows the operation of the first segment SEG1 in up counting, and Figure 5B The timing diagram shows the operation of the first segment SEG1 in down counting. In some embodiments, Figure 5A and Figure 5B The operations can be performed by including Figure 4 The first segment SEG1 of the local clock generator 40 is executed in conjunction with Figure 4 describe Figure 5A and Figure 5B operation.

[0048] Reference Figure 5A , the up signal UP may be 1, and the local clock generator 40 may operate based on the 3-bit Q[2:0] of the output data Q. Figure 5AAs shown in , when the input clock CK is 0, the 4 bits LC1[3:0] of the first local clock LC1 may all be 1. When the input clock CK is 0, the first bit LC1[0] of the first local clock LC1 may be 1. When the first bit LC1[0] of the first local clock LC1 is 0 and the first bit Q[0] of the output data Q is 1, the second bit LC1[1] of the first local clock LC1 may be 0. When the lower 2 bits LC1[1:0] of the first local clock LC1 are 0 and the lower 2 bits Q[1:0] of the output data Q are 1, the third bit LC1[2] of the first local clock LC1 may be 0. When the lower 3 bits LC1[2:0] of the first local clock LC1 are 0 and the lower 3 bits Q[2:0] of the output data Q are 1, the fourth bit LC1[3] of the first local clock LC1 may be 0. The 4 bits Q[3:0] of the output data Q may be switched at the rising edges of the 4 bits LC1[3:0] of the first local clock LC1, respectively.

[0049] Reference Figure 5B , the up signal UP may be 0, and the local clock generator 40 may operate based on the 3 bits QB[2:0] of the inverted output data QB. Figure 5B As shown in , when the input clock CK is 0, the 4 bits LC1[3:0] of the first local clock LC1 may all be 1. When the input clock CK is 0, the first bit LC1[0] of the first local clock LC1 may be 1. When the first bit LC1[0] of the first local clock LC1 is 0 and the first bit QB[0] of the inverted output data QB is 1, the second bit LC1[1] of the first local clock LC1 may be 0. When the lower 2 bits LC1[1:0] of the first local clock LC1 are 0 and the lower 2 bits QB[1:0] of the inverted output data QB are 1, the third bit LC1[2] of the first local clock LC1 may be 0. When the lower 3 bits LC1[2:0] of the first local clock LC1 are 0 and the lower 3 bits QB[2:0] of the inverted output data QB are 1, the fourth bit LC1[3] of the first local clock LC1 may be 0. The 4 bits Q[3:0] of the output data Q may be switched at rising edges of the 4 bits LC1[3:0] of the first local clock LC1, respectively.

[0050] Figure 6 is a circuit diagram showing a pre-evaluator 60 according to one or more example embodiments. For example, Figure 6 The circuit diagram shows Figure 2 An example of a pre-evaluator PE2, and included in Figure 2 The pre-evaluators PE2 to PE4 in the second segment SEG2 to the fourth segment SEG4 may have Figure 6 The same structure as shown in FIG. Figure 2As described above, the pre-evaluator 60 may receive the up signal UP and the 4-bit Q[6:3] of the output data Q, and generate the 4-bit first ripple carry CA1[3:0]. Figure 6 As shown in FIG. 1 , the pre-evaluator 60 may include first to seventh PFETs P21 to P27 , first to fourth NFETs N21 to N24 , first to fourth inverters INV21 to INV24 , and first to fourth multiplexers MUX21 to MUX24 .

[0051] In response to the deactivated output of the first multiplexer MUX21, the first to fourth PFETs P21 to P24 may precharge the output node at which the first inverse ripple carry CAB1 is generated. Figure 6 As shown in , the first PFET P21 may precharge (or pull up) the first bit CAB1[0] of the first inverted ripple carry CAB1 to 1 in response to the output of the first multiplexer MUX21 being 0. The second PFET P22 may precharge (or pull up) the second bit CAB1[1] of the first inverted ripple carry CAB1 to 1 in response to the output of the first multiplexer MUX21 being 0. The third PFET P23 may precharge (or pull up) the third bit CAB1[2] of the first inverted ripple carry CAB1 to 1 in response to the output of the first multiplexer MUX21 being 0. The fourth PFET P24 may precharge (or pull up) the fourth bit CAB1[3] of the first inverted ripple carry CAB1 to 1 in response to the output of the first multiplexer MUX21 being 0.

[0052] The first to fourth NFETs N21 to N24 may transmit discharge of an output node at which a first inverse ripple carry CAB1 is generated in response to the activated output of the first to fourth multiplexers MUX21 to MUX24. Figure 6As shown in FIG, the first NFET N21 may discharge (or pull down) the first bit CAB1[0] of the first inverted ripple carry CAB1 to 0 in response to the output of the first multiplexer MUX21 being 1. When the first bit CAB1[0] of the first inverted ripple carry CAB1 is 0, the second NFET N22 may discharge (or pull down) the second bit CAB1[1] of the first inverted ripple carry CAB1 in response to the activated output of the second multiplexer MUX22. When the second bit CAB1[1] of the first inverted ripple carry CAB1 is 0, the third NFET N23 may discharge (or pull down) the third bit CAB1[2] of the first inverted ripple carry CAB1 in response to the activated output of the third multiplexer MUX23. When the third bit CAB1 [ 2 ] of the first inverted ripple carry CAB1 is 0, the fourth NFET N24 may discharge (or pull down) the fourth bit CAB1 [ 3 ] of the first inverted ripple carry CAB1 in response to the activated output of the fourth multiplexer MUX24 .

[0053] The first multiplexer MUX21 to the fourth multiplexer MUX24 can select the output data Q or the inverted output data QB according to the up signal UP. Figure 6 As shown in , the first multiplexer MUX21 can select one of the fourth bit Q[3] of the output data Q and the fourth bit QB[3] of the inverted output data QB according to the up signal UP, and generate an output corresponding to the selected bit. The second multiplexer MUX22 can select one of the fifth bit Q[4] of the output data Q and the fifth bit QB[4] of the inverted output data QB according to the up signal UP, and generate an output corresponding to the selected bit. The third multiplexer MUX23 can select one of the sixth bit Q[5] of the output data Q and the sixth bit QB[5] of the inverted output data QB according to the up signal UP, and generate an output corresponding to the selected bit. The fourth multiplexer MUX24 can select one of the seventh bit Q[6] of the output data Q and the seventh bit QB[6] of the inverted output data QB according to the up signal UP, and generate an output corresponding to the selected bit.

[0054] The fifth PFET P25 to the seventh PFET P27 and the second inverter INV22 to the fourth inverter INV24 may correspond to three latches. For example, the fifth PFET P25 and the second inverter INV22 may latch the second bit CAB1[1] of the first inverted ripple carry CAB1. The sixth PFET P26 and the third inverter INV23 may latch the third bit CAB1[2] of the first inverted ripple carry CAB1. The seventh PFET P27 and the fourth inverter INV24 may latch the fourth bit CAB1[3] of the first inverted ripple carry CAB1. The fourth inverter INV24 may generate the fourth bit CA1[3] of the first ripple carry CA1 by inverting the fourth bit CAB1[3] of the first inverted ripple carry CAB1.

[0055] The first to fourth inverters INV21 to INV24 may generate the first ripple carry CA1 from the first inverted ripple carry CAB1. In some embodiments, each of the first to fourth inverters INV21 to INV24 may include a PFET and an NFET connected in series between a node to which a positive power supply voltage VDD is applied and a node to which a negative power supply voltage VSS is applied.

[0056] Fig. 7A and Figure 7B is a circuit diagram showing an example of a local clock selector according to an example embodiment. For example, Fig. 7A and Figure 7B The circuit diagram shows Figure 2 An example of a local clock selector LCS2, and respectively included in Figure 2 The local clock selectors LCS2 to LCS4 in the second segment SEG2 to the fourth segment SEG4 may each have the same structure. Figure 2 As described above, the local clock selectors 70a and 70b may each generate the second local clock LC2 and the second carry input CI2 based on the first ripple carry CA1 and the first carry input CI1.

[0057] Reference Fig. 7A, the local clock selector 70a may include a first unit circuit 71 to a fourth unit circuit 74 and a carry output circuit 75. The first unit circuit 71 to the fourth unit circuit 74 may each have the same structure and respectively generate 4 bits of the second local clock LC2. The first unit circuit 71 may include a first PFET P31, a second PFET P32, a first NFET N31, a second NFET N32, and a first inverter INV31. The first PFET P31 and the second PFET P32 may be connected in parallel to each other between a node to which a positive power supply voltage VDD is applied and an output node to which a first bit LC2[0] of the second local clock LC2 is output. The first PFET P31 may receive an input clock CK. The second PFET P32 may form a latch with the first inverter INV31 and latch the first bit LC2[0] of the second local clock LC2. The first NFET N31 and the second NFET N32 may be connected in series with each other between an output node to which the first bit LC2[0] of the second local clock LC2 is output and a node to which the first bit CAB1[0] of the first inverted ripple carry CAB1 is applied, and receive the first carry input CI1 and the input clock CK, respectively. In some embodiments, the first NFET N31 and the second NFET N32 may be connected in series with each other. Fig. 7A The different sequences shown are connected in series with each other.

[0058] The second unit circuit 72 may include a third PFET P33, a fourth PFET P34, a third NFET N33, a fourth NFET N34, and a second inverter INV32. The third PFET P33 and the fourth PFET P34 may be connected in parallel to each other between a node to which a positive power supply voltage VDD is applied and an output node to which a second bit LC2[1] of a second local clock LC2 is output. The third PFET P33 may receive an input clock CK. The fourth PFET P34 may form a latch with the second inverter INV32 and latch the second bit LC2[1] of the second local clock LC2. The third NFET N33 and the fourth NFET N34 may be connected in series to each other between an output node to which the second bit LC2[1] of the second local clock LC2 is output and a node to which a second bit CAB1[1] of the first inverted ripple carry CAB1 is applied, and receive a first carry input CI1 and an input clock CK, respectively. In some embodiments, the third NFET N33 and the fourth NFET N34 may be connected in parallel to each other. Fig. 7A The different sequences shown are connected in series with each other.

[0059] The third unit circuit 73 may include a fifth PFET P35, a sixth PFET P36, a fifth NFET N35, a sixth NFET N36, and a third inverter INV33. The fifth PFET P35 and the sixth PFET P36 may be connected in parallel to each other between a node to which a positive power supply voltage VDD is applied and an output node to which a third bit LC2[2] of the second local clock LC2 is output. The fifth PFET P35 may receive an input clock CK. The sixth PFET P36 may form a latch with the third inverter INV33 and latch the third bit LC2[2] of the second local clock LC2. The fifth NFET N35 and the sixth NFET N36 may be connected in series to each other between the output node to which the third bit LC2[2] of the second local clock LC2 is output and a node to which the third bit CAB1[2] of the first inverted ripple carry CAB1 is applied, and receive the first carry input CI1 and the input clock CK, respectively. In some embodiments, the fifth NFET N35 and the sixth NFET N36 may be connected in parallel to each other with respect to the output node to which the third bit LC2[2] of the second local clock LC2 is output and the node to which the third bit CAB1[2] of the first inverted ripple carry CAB1 is applied. Fig. 7A The different sequences shown are connected in series with each other.

[0060] The fourth unit circuit 74 may include a seventh PFET P37, an eighth PFET P38, a seventh NFET N37, an eighth NFET N38, and a fourth inverter INV34. The seventh PFET P37 and the eighth PFET P38 may be connected in parallel to each other between a node to which a positive power supply voltage VDD is applied and an output node to which a fourth bit LC2[3] of the second local clock LC2 is output. The seventh PFET P37 may receive an input clock CK. The eighth PFET P38 may form a latch with the fourth inverter INV34 and latch the fourth bit LC2[3] of the second local clock LC2. The seventh NFET N37 and the eighth NFET N38 may be connected in series to each other between the output node to which the fourth bit LC2[3] of the second local clock LC2 is output and a node to which the fourth bit CAB1[3] of the first inverted ripple carry CAB1 is applied, and receive the first carry input CI1 and the input clock CK, respectively. In some embodiments, the seventh NFET N37 and the eighth NFET N38 may be connected in parallel to each other. Fig. 7A The different sequences shown are connected in series with each other.

[0061] The carry output circuit 75 may include a ninth PFET P39, a ninth NFET N39, and a tenth NFET N40. The ninth PFET P39 and the ninth NFET N39 may be connected in parallel to each other and receive the first inverted carry input CIB1 and the first carry input CI1, respectively. The tenth NFET N40 may be connected between a node at which the second carry input CI2 is generated and a node to which the negative power supply voltage VSS is applied, and receive the first inverted carry input CIB1. Therefore, when the first carry input CI1 is 0, the second carry input CI2 may be equal to the fourth bit CA1[3] of the first ripple carry CA1, and when the first carry input CI1 is 1, the second carry input CI2 may be 0.

[0062] Reference Figure 7B , the local clock selector 70b may include a first unit circuit 71 to a fourth unit circuit 74 and a carry output circuit 75. The first unit circuit 71 to the fourth unit circuit 74 may each have the same structure and respectively generate 4 bits of the second local clock LC2. The first unit circuit 71 may include a first PFET P41, a second PFET P42, a first NFET N41 to a third NFET N43 and a first inverter INV41. The first PFET P41 and the second PFET P42 may be connected in parallel to each other between a node to which a positive power supply voltage VDD is applied and an output node to which a first bit LC2[0] of the second local clock LC2 is output. The first PFET P41 may receive an input clock CK. The second PFET P42 may form a latch with the first inverter INV41 and latch the first bit LC2[0] of the second local clock LC2. The first to third NFETs N41 to N43 may be connected in series with each other between an output node to which the first bit LC2[0] of the second local clock LC2 is output and a node to which the negative power supply voltage VSS is applied, and receive the first carry input CI1, the input clock CK, and the first bit CA1[0] of the first ripple carry CA1, respectively. In some embodiments, the first to third NFETs N41 to N43 may be connected in series with each other between an output node to which the first bit LC2[0] of the second local clock LC2 is output and a node to which the negative power supply voltage VSS is applied. Figure 7B The different sequences shown are connected in series with each other.

[0063] The second unit circuit 72 may include a third PFET P43, a fourth PFET P44, a fourth NFET N44 to a sixth NFET N46, and a second inverter INV42. The third PFET P43 and the fourth PFET P44 may be connected in parallel to each other between a node to which a positive power supply voltage VDD is applied and an output node to which a second bit LC2[1] of a second local clock LC2 is output. The third PFET P43 may receive an input clock CK. The fourth PFET P44 may form a latch with the second inverter INV42, and latch the second bit LC2[1] of the second local clock LC2. The fourth NFET N44 to the sixth NFET N46 may be connected in series to each other between the output node to which the second bit LC2[1] of the second local clock LC2 is output and a node to which a negative power supply voltage VSS is applied, and receive the first carry input CI1, the input clock CK, and the second bit CA1[1] of the first ripple carry CA1, respectively. In some embodiments, the fourth NFET N44 to the sixth NFET N46 may be connected in parallel to each other. Figure 7B The different sequences shown are connected in series with each other.

[0064] The third unit circuit 73 may include a fifth PFET P45, a sixth PFET P46, a seventh NFET N47 to a ninth NFET N49, and a third inverter INV43. The fifth PFET P45 and the sixth PFET P46 may be connected in parallel to each other between a node to which a positive power supply voltage VDD is applied and an output node to which a third bit LC2[2] of the second local clock LC2 is output. The fifth PFET P45 may receive an input clock CK. The sixth PFET P46 may form a latch with the third inverter INV43 and latch the third bit LC2[2] of the second local clock LC2. The seventh NFET N47 to the ninth NFET N49 may be connected in series to each other between the output node to which the third bit LC2[2] of the second local clock LC2 is output and a node to which a negative power supply voltage VSS is applied, and receive the first carry input CI1, the input clock CK, and the third bit CA1[2] of the first ripple carry CA1, respectively. In some embodiments, the seventh NFET N47 to the ninth NFET N49 may be connected in parallel to each other between the output node to which the third bit LC2[2] of the second local clock LC2 is output and the node to which a negative power supply voltage VSS is applied. Figure 7B The different sequences shown are connected in series with each other.

[0065] The fourth unit circuit 74 may include a seventh PFET P47, an eighth PFET P48, a tenth NFET N50 to a twelfth NFET N52, and a fourth inverter INV44. The seventh PFET P47 and the eighth PFET P48 may be connected in parallel to each other between a node to which a positive power supply voltage VDD is applied and an output node to which a fourth bit LC2[3] of the second local clock LC2 is output. The seventh PFET P47 may receive an input clock CK. The eighth PFET P48 may form a latch with the fourth inverter INV44 and latch the fourth bit LC2[3] of the second local clock LC2. The tenth NFET N50 to the twelfth NFET N52 may be connected in series to each other between the output node to which the fourth bit LC2[3] of the second local clock LC2 is output and a node to which a negative power supply voltage VSS is applied, and receive the first carry input CI1, the input clock CK, and the fourth bit CA1[3] of the first ripple carry CA1, respectively. In some embodiments, the tenth NFET N50 to the twelfth NFET N52 may be connected in parallel to each other between the output node to which the fourth bit LC2[3] of the second local clock LC2 is output and the node to which a negative power supply voltage VSS is applied. Figure 7B The different sequences shown are connected in series with each other.

[0066] The carry output circuit 75 may include a ninth PFET P49, a thirteenth NFET N53, and a fourteenth NFET N54. The ninth PFET P49 and the thirteenth NFET N53 may be connected in parallel to each other and receive the first inverted carry input CIB1 and the first carry input CI1, respectively. The fourteenth NFET N54 may be connected between a node at which the second carry input CI2 is generated and a node to which the negative power supply voltage VSS is applied, and receive the first inverted carry input CIB1. Therefore, when the first carry input CI1 is 0, the second carry input CI2 may be equal to the fourth bit CA1[3] of the first ripple carry CA1, and when the first carry input CI1 is 1, the second carry input CI2 may be 0. Hereinafter, reference will be made to Figure 7B The local clock selector 70b is shown in FIG. 1 , but it should be noted that the embodiment is not limited to this.

[0067] Fig. 8A and Figure 8B is a timing diagram showing an example of the operation of the second segment SEG2 according to an example embodiment. For example, Fig. 8A The timing diagram shows the operation of the second segment SEG2 in up counting, and Figure 8B The timing diagram shows the operation of the second segment SEG2 in down counting. In some embodiments, Fig. 8A and Figure 8B The operation can be performed by the second segment SEG2, and the second segment SEG2 includes Figure 6 The pre-evaluator 60 and Figure 7B The local clock selector 70b. Figure 2 , Figure 6 and Figure 7B describe Fig. 8A and Figure 8B The operations shown in .

[0068] Reference Fig. 8A , the up signal UP may be 1, and the pre-evaluator 60 may operate based on the up signal UP and the 4 bits Q[6:3] of the output data Q. Figure 5A As described above, the fourth bit Q[3] of the output data Q may be oscillated by the local clock generator LCG at a period corresponding to 16 times the period of the input clock CK. The 4 bits CA1[3:0] of the first ripple carry CA1 may be 0 due to the 4 bits CAB1[3:0] of the first inverted ripple carry CAB1 being pulled up when the fourth bit Q[3] of the output data Q is 0.

[0069] When the fourth bit Q[3] of the output data Q is 1, the first bit CA1[0] of the first ripple carry CA1 may be 1. When the first bit CAB1[0] of the first inverted ripple carry CAB1 is 0 and the fifth bit Q[4] of the output data Q is 1, the second bit CA1[1] of the first ripple carry CA1 may be 1. When the second bit CAB1[1] of the first inverted ripple carry CAB1 is 0 and the sixth bit Q[5] of the output data Q is 1, the third bit CA1[2] of the first ripple carry CA1 may be 1. When the third bit CAB1[2] of the first inverted ripple carry CAB1 is 0 and the seventh bit Q[6] of the output data Q is 1, the fourth bit CA1[3] may be 1.

[0070] like Fig. 8A As shown in , the first carry input CI1 may include a pulse synchronized with the fourth bit Q[3] of the output data Q. When the input clock CK, the first bit CA1[0] of the first ripple carry CA1, and the first carry input CI1 are 1, the first bit LC2[0] of the second local clock LC2 may be 0. When the input clock CK, the lower 2 bits CA1[1:0] of the first ripple carry CA1, and the first carry input CI1 are 1, the second bit LC2[1] of the second local clock LC2 may be 0. When the input clock CK, the lower 3 bits CA1[2:0] of the first ripple carry CA1, and the first carry input CI1 are 1, the third bit LC2[2] of the second local clock LC2 may be 0. When the input clock CK, the 4 bits CA1[3:0] of the first ripple carry CA1, and the first carry input CI1 are 1, the fourth bit LC2[3] of the second local clock LC2 may be 0. The 4 bits Q[7:4] of the output data Q may be switched at rising edges of the 4 bits LC1[3:0] of the first local clock LC1, respectively.

[0071] Reference Figure 8B, the up signal UP may be 0, and the pre-evaluator 60 may operate based on the up signal UP and the 4 bits QB[6:3] of the inverted output data QB. Figure 5B As described above, the fourth bit QB[3] of the inverted output data QB may be oscillated by the local clock generator LCG at a period corresponding to 16 times the period of the input clock CK. The 4 bits CA1[3:0] of the first ripple carry CA1 may be 0 due to the 4 bits CAB1[3:0] of the first inverted ripple carry CAB1 being pulled up when the 4th bit QB[3] of the inverted output data QB is 0.

[0072] When the fourth bit QB[3] of the inverted output data QB is 1, the first bit CA1[0] of the first ripple carry CA1 may be 1. When the first bit CAB1[0] of the first inverted output data CAB1 is 0 and the fifth bit QB[4] of the inverted output data QB is 1, the second bit CA1[1] of the first ripple carry CA1 may be 1. When the second bit CAB1[1] of the first inverted output data CAB1 is 0 and the sixth bit QB[5] of the inverted output data QB is 1, the third bit CA1[2] of the first ripple carry CA1 may be 1. When the third bit CAB1[2] of the first inverted output data CAB1 is 0 and the seventh bit QB[6] of the inverted output data QB is 1, the fourth bit CA1[3] of the first ripple carry CA1 may be 1.

[0073] like Figure 8B As shown in , the first carry input CI1 may include a pulse synchronized with the fourth bit QB[3] of the inverted output data QB. When the input clock CK, the first bit CA1[0] of the first ripple carry CA1, and the first carry input CI1 are 1, the first bit LC2[0] of the second local clock LC2 may be 0. When the input clock CK, the lower 2 bits CA1[1:0] of the first ripple carry CA1, and the first carry input CI1 are 1, the second bit LC2[1] of the second local clock LC2 may be 0. When the input clock CK, the lower 3 bits CA1[2:0] of the first ripple carry CA1, and the first carry input CI1 are 1, the third bit LC2[2] of the second local clock LC2 may be 0. When the input clock CK, the 4 bits CA1[3:0] of the first ripple carry CA1, and the first carry input CI1 are 1, the fourth bit LC2[3] of the second local clock LC2 may be 0. The 4 bits Q[7:4] of the output data Q may be switched at rising edges of the 4 bits LC1[3:0] of the first local clock LC1, respectively.

[0074] Fig. 9 is a flow chart illustrating the operation of a counter according to one or more example embodiments. Fig. 9 The operation of can be referred to as a method of generating an increased or decreased output data Q according to the input clock CK. Fig. 9 As shown, the method of generating increased or decreased output data Q according to the input clock CK may include a plurality of operations S10 to S50. In some embodiments, Fig. 9 The method can include Figure 4 The local clock generator 40 Figure 2 The first segment SEG1 is executed. Combined with Figure 2 and Figure 4 describe Fig. 9 method.

[0075] Reference Fig. 9 In operation S10, an up signal UP may be received. The up signal UP may indicate an up count or a down count of the first segment SEG1. For example, an up signal UP of 1 may indicate an up count, and an up signal UP of 0 may indicate a down count. In operation S20, it may be determined whether the up signal UP is activated. For example, Fig. 9 As shown in , when the up signal UP is activated, for example, when the up signal UP is "1", operation S30 may be subsequently performed. When the up signal UP is deactivated, for example, when the up signal UP is "0", operation S40 may be subsequently performed.

[0076] In operation S30, the first local clock LC1 may be generated based on at least one first bit of the output data Q. For example, the local clock generator 40 may generate the first local clock LC1 based on the lower 3 bits Q[2:0] of the output data Q. Fig. 9 As shown in , operation S30 may include operations S31 and S32. In operation S31, at least one first bit of the output data Q may be selected. For example, the first multiplexer MUX11 to the third multiplexer MUX13 of the local clock generator 40 may select and output the 3 bits Q[2:0] of the output data Q in response to the activated up signal UP. In operation S32, the first local clock LC1 may be generated. For example, the local clock generator 40 may pull up the first local clock LC1 to 1 based on the input clock CK of 0, and at the same time, when the input clock CK is 1, the bits of the first local clock LC1 may be pulled down respectively in response to the 3 bits Q[2:0] of the output data Q.

[0077] In operation S40, the first local clock LC1 may be generated based on at least one first bit of the inverted output data QB. For example, the local clock generator 40 may generate the first local clock LC1 based on the lower 3 bits QB[2:0] of the inverted output data QB. Fig. 9As shown in , operation S40 may include operations S41 and S42. In operation S41, at least one first bit of the inverted output data QB may be selected. For example, the first multiplexer MUX11 to the third multiplexer MUX13 of the local clock generator 40 may select 3 bits QB[2:0] of the inverted output data QB in response to the deactivated up signal UP and output a result corresponding to the selected 3 bits. In operation S42, a first local clock LC1 may be generated. For example, the local clock generator 40 may pull up the first local clock LC1 to 1 based on the input clock CK of 0, and when the input clock CK is 1, the bits of the first local clock LC1 may be pulled down respectively according to the 3 bits QB[2:0] of the inverted output data QB.

[0078] In operation S50, the second bit and at least one first bit of the output data Q may be generated, and the second bit may be a higher bit of the at least one first bit. For example, the four first flip-flops FF1 may receive the first local clock LC1 generated in operation S30 or operation S40, and generate lower 3 bits Q[2:0] and 1 bit Q[3] of the output data Q.

[0079] Fig.10 is a flow chart illustrating the operation of a counter according to one or more example embodiments. For example, Fig.10 The flow chart shows Figure 2 An example of the operation of the local clock generator LCG or the pre-evaluator PE2. Fig.10 As shown in , the operation of the counter may include operations S01 and S02. In some embodiments, Fig.10 The operation can be performed by Figure 4 A local clock generator 40 or Figure 6 The pre-evaluator 60 performs the combination Figure 4 and Figure 6 describe Fig.10 operation.

[0080] Reference Fig.10 , in operation S01, at least one output node may be precharged simultaneously. In some embodiments, the first PFET P11 to the fourth PFET P14 of the local clock generator 40 may simultaneously precharge the output nodes of the 4 bits LC1[3:0] respectively generating the first local clock LC1 in response to the deactivated input clock CK. Therefore, the 4 bits LC1[3:0] of the first local clock LC1 may be 1. In some embodiments, the first PFET 21 to the fourth PFET P24 of the pre-evaluator 60 may simultaneously precharge the output nodes of the 4 bits CAB1[3:0] respectively generating the first inverted ripple carry CAB1 in response to the deactivated output of the first multiplexer MUX21. Therefore, the 4 bits CA1[3:0] of the first ripple carry CA1 may be 0.

[0081] In operation S02, the discharge of at least one output node may be transmitted. In some embodiments, in response to the activated input clock CK, the first NFET N11 of the local clock generator 40 may discharge the output node generating the first bit LC1[0] of the first local clock LC1. The second NFET N12 to the fourth NFET N14 of the local clock generator 40 may discharge their corresponding output nodes only when all lower bits of the first local clock LC1 are discharged, and the discharge may be transmitted accordingly. In some embodiments, in response to the activated output of the first multiplexer MUX21, the first NFET N21 of the pre-evaluator 60 may discharge the output node generating the first bit CAB1[0] of the first inverted ripple carry CAB1. The second NFET N22 to the fourth NFET N24 of the pre-evaluator 60 may discharge their corresponding output nodes only when all lower bits of the first inverted ripple carry CAB1 are discharged, and the discharge may be transmitted accordingly.

[0082] Fig.11 is a flow chart illustrating the operation of a counter according to one or more example embodiments. Fig.11 The operation is called a method of generating an increased or decreased output data Q according to the input clock CK. Fig.11 As shown in , the method of generating increased or decreased output data Q according to the input clock CK may include a plurality of operations S60 to S90. In some embodiments, Fig.11 The method can be Figure 2 The second segment SEG2 is executed and can be used with Fig. 9 The method is executed in parallel. Figure 2 describe Fig.11 method.

[0083] Reference Fig.11 , in operation S60, a carry input may be received. For example, the pre-evaluator PE2 may receive a first carry input CI1 from the first segment SEG1. In some embodiments, as described above with reference to Figure 4 As described above, the first carry input CI1 may be generated by inverting the MSB (ie, the fourth bit LC1[3]) of the first local clock LC1.

[0084] In operation S70, at least one ripple carry may be generated. For example, the pre-evaluator PE2 may generate a first ripple carry CA1 based on the up signal UP and the 4 bits Q[6:3] of the output data Q. Fig. 8AAs described above, the pre-evaluator PE2 may generate the first ripple carry CA1 based on 4 bits Q[6:3] of the output data Q in response to the activated up signal UP, and may generate the first ripple carry CA1 based on 4 bits QB[6:3] of the inverted output data QB in response to the deactivated up signal UP.

[0085] In operation S80, at least one local clock may be generated. For example, the local clock selector LCS2 may generate the second local clock LC2 based on the first carry input CI1 received in operation S60 and the first ripple carry CA1 generated in operation S70.

[0086] In operation S90 , at least one bit of the output data Q may be generated. For example, the four second flip-flops FF2 may generate 4 bits Q[7:4] of the switched output data Q in response to the second local clock LC2 generated in operation S80 .

[0087] Fig.12 is a flow chart of a method for manufacturing an IC according to one or more example embodiments. In detail, Fig.12 The flowchart of FIG. 1 shows an example of a method of manufacturing an IC including a standard cell. A standard cell is a unit of a layout included in an IC and can be designed to perform a predefined function. Fig.12 , the method of manufacturing an IC may include a plurality of operations S100 to S500 .

[0088] The cell library (or standard cell library) D12 may include information about the standard cell (such as information about functions, characteristics, layout, etc.). In some embodiments, the counter (i.e., bidirectional counter) described above with reference to the drawings may be included in the IC as a standard cell. For example, the cell library D12 may include information about a cell corresponding to the counter described above with reference to the drawings. Therefore, the IC may have a high operating speed and a reduced area.

[0089] Design rules D14 may include requirements that the layout of the IC must comply with. For example, design rules D14 may include requirements for the space between patterns in the same layer, the minimum width of a pattern, the line direction of a wiring layer, etc. In some embodiments, design rules D14 may define a minimum spacing distance on the same trace in a wiring layer.

[0090] In operation S100, a logic synthesis operation for generating netlist data D13 from register transfer level (RTL) data D11 may be performed. For example, a semiconductor design tool (e.g., a logic synthesis tool) may perform logic synthesis by referring to a cell library D12 from RTL data D11 written in a hardware description language (HDL) such as very high speed IC (VHSIC) HDL (VHDL) and Verilog, and generate netlist data D13 including a bitstream or a netlist. The netlist data D13 may correspond to an input of a placement and routing (P&R) as described below.

[0091] In operation S200, standard cells may be placed. For example, a semiconductor design tool (e.g., a P&R tool) may place standard cells used in netlist data D13 with reference to cell library D12. In some embodiments, the semiconductor design tool may place standard cells in rows extending parallel to each other, and the placed standard cells may receive power from power rails extending along the boundaries of the rows.

[0092] In operation S300, the pins of the standard cell may be wired. For example, the semiconductor design tool may generate an interconnection that electrically connects the output pins and input pins of the placed standard cell, and generate layout data D15 that defines the placed standard cell and the generated interconnection. The interconnection may include a via in a via layer and / or a pattern in a wiring layer. In some embodiments, the wiring layer may include a front wiring layer above the gate electrode and a back wiring layer below the gate electrode. The layout data D15 may have a format such as GDSII, and include geometric information of the cell and the interconnection. The semiconductor design tool may refer to the design rule D14 when wiring the pins of the cell. The layout data D15 may correspond to the output of the P&R. A separate operation S300 or both operations S200 and S300 may be referred to as a method for designing an IC.

[0093] In operation S400, an operation of manufacturing a mask may be performed. For example, in photolithography, optical proximity correction (OPC) for correcting distortion (such as refraction) caused by the nature of light may be applied to the layout data D15. A pattern on the mask may be limited to form patterns in a plurality of layers based on the data to which the OPC is applied, and at least one mask (or photomask) for forming patterns in each of the plurality of layers may be manufactured. In some embodiments, the layout of the IC may be limitedly modified in operation S400, and the limited modification of the IC in operation S400 may be a post-processing for optimizing the structure of the IC, which may be referred to as design polishing.

[0094] In operation S500, an operation of manufacturing an IC may be performed. For example, the IC may be manufactured by patterning a plurality of layers using at least one mask manufactured in operation S400. The front end process (FEOL) process may include, for example, planarizing and cleaning the wafer, forming a groove, forming a well, forming a gate electrode, and forming a source and a drain. Individual devices (such as transistors, capacitors, resistors, etc.) may be formed on a substrate by performing a FEOL process. In addition, the back end process (BEOL) process may include, for example, performing silicide of a gate region, a source region, and a drain region, adding a dielectric, performing planarization, forming a hole, adding a metal layer, forming a via, forming a passivation layer, etc. Individual devices (such as transistors, capacitors, resistors, etc.) may be interconnected by performing a BEOL process. In some embodiments, a mid-end process (MEOL) may be performed between the FEOL and BEOL processes, and contacts may be formed on individual devices. Thereafter, the IC may be packaged in a semiconductor package and used as a component in various applications.

[0095] Fig.13 1 is a block diagram of a system on chip (SoC) 130 according to one or more example embodiments. SoC 130 may refer to an IC that integrates components of a computing system or other electronic system. For example, as an example of SoC 130, an application processor (AP) may include a processor and components for other functions. Fig.13 , the SoC 130 may include a core 131 , a digital signal processor (DSP) 132 , a graphics processor (GPU) 133 , an embedded memory 134 , a communication interface 135 , and a memory interface 136 . The components of the SoC 130 may communicate with each other via a bus 137 .

[0096] The components of the SoC 130 may include the counter according to one or more example embodiments described above with reference to the accompanying drawings. Therefore, the components may have a high operating speed and a reduced area, and thus, the performance and efficiency of the SoC 130 may be improved.

[0097] The core 131 may process instructions and control the operation of components included in the SoC 130. For example, by processing a series of instructions, the core 131 may run an operating system and execute an application on the operating system. The DSP 132 may generate useful data by processing a digital signal such as a digital signal provided from the communication interface 135. The GPU 133 may generate data of an image output via a display device based on image data provided from the embedded memory 134 or the memory interface 136, or encode the image data. The embedded memory 134 may store data required for the operation of the core 131, the DSP 132, and the GPU 133. The communication interface 135 may provide an interface for a communication network or one-to-one communication. The memory interface 136 may provide an interface to an external memory of the SoC 130 such as a dynamic random access memory (DRAM) and a flash memory.

[0098] At least one of the components, elements, modules and units described herein may be implemented as various numbers of hardware, software and / or firmware structures that perform the above-mentioned corresponding functions according to one or more example embodiments. For example, at least one of these components, elements and units may use a direct circuit structure (such as a memory, a processor, a logic circuit, a lookup table, etc.) that can perform the corresponding functions through the control of one or more microprocessors or other control devices. In addition, at least one of these components, elements and units may be specifically implemented by a part of a module, a program or a code, and the code contains one or more executable instructions for performing a specified logical function and is executed by one or more microprocessors or other control devices. In addition, at least one of these components, elements and units may also include a processor (such as a central processing unit (CPU), a microprocessor, etc. that performs the corresponding function) or be implemented by a processor (such as a central processing unit (CPU), a microprocessor, etc. that performs the corresponding function). Two or more of these components, elements and units may be combined into a single component, element and unit that performs all operations or functions of the two or more components, elements and units combined. In addition, at least a portion of the function of at least one of these components, elements and units may be performed by another of these components, elements and units. In addition, although the bus is not shown in some block diagrams, the communication between components, elements and units can be performed by the bus. The functional aspects of the above embodiments can be implemented with algorithms executed on one or more processors. In addition, the components, elements or units represented by blocks or processing operations can adopt any number of related technologies for electronic configuration, signal processing and / or control, data processing, etc.

[0099] Although example embodiments have been described in this specification by using specific terms, the terms are only used to describe the example embodiments and are not intended to limit the meaning or scope of the inventive concepts set forth in the claims. Therefore, those skilled in the art will appreciate that various changes and other embodiments may be made therefrom.

[0100] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A bidirectional counter, configured to generate output data based on an input clock, the bidirectional counter comprising: at least one first flip-flop configured to generate at least one first bit and a second bit as a higher bit of the at least one first bit based on at least one first local clock, the at least one first bit including a least significant bit of output data; as well as A local clock generation circuit is configured to: generate the at least one first local clock based on the input clock and the at least one first bit in response to an activated up signal, and generate the at least one first local clock based on the input clock and at least one inverted first bit corresponding to an inverted version of the at least one first bit in response to a deactivated up signal.

2. The bidirectional counter according to claim 1, wherein: The local clock generation circuit includes: at least one multiplexer configured to select the at least one first bit or the at least one inverted first bit based on the up signal, respectively.

3. The bidirectional counter according to claim 2, wherein: The local clock generation circuit includes: at least one first transistor configured to: precharge at least one first output node at which the at least one first local clock is respectively generated based on an input clock; and At least one second transistor is configured to transmit a discharge of the at least one first output node based on an input clock and at least one output of the at least one multiplexer.

4. The bidirectional counter according to claim 1, wherein: The local clock generation circuit comprises: at least one latch configured to latch the at least one first local clock respectively, and Wherein, each of the at least one latch comprises: An inverter configured to receive one of the at least one first local clock; and A p-channel field effect transistor includes a gate connected to the output of the inverter, a source to which a positive power supply voltage is applied, and a drain connected to the input of the inverter.

5. The bidirectional counter according to any one of claims 1 to 4, wherein: The local clock generation circuit is configured to generate a carry input based on the at least one first local clock, and the bidirectional counter further comprises: at least one second flip-flop configured to generate at least one third bit as a higher bit of the second bit based on at least one second local clock; a pre-evaluation circuit configured to generate at least one ripple carry based on the up signal, the second bit, and the at least one third bit; and The local clock selection circuit is configured to generate the at least one second local clock based on the input clock, the carry input and the at least one ripple carry.

6. A bidirectional counter configured to generate output data based on an input clock, the bidirectional counter comprising: at least one first flip-flop configured to: generate a most significant bit of output data and at least one first bit lower than the most significant bit based on at least one first local clock; a first pre-evaluation circuit configured to: generate at least one first ripple carry based on the at least one first bit and a second bit lower than the at least one first bit in response to an activated up signal, and generate the at least one first ripple carry based on an inverted second bit corresponding to an inverted version of the second bit and at least one inverted first bit corresponding to an inverted version of the at least one first bit in response to a deactivated up signal; as well as The first local clock selection circuit is configured to generate the at least one first local clock based on the input clock, the first carry input and the at least one first ripple carry.

7. The bidirectional counter according to claim 6, wherein: The first pre-evaluation circuit includes at least one multiplexer configured to select the second bit and the at least one first bit or the inverted second bit and the at least one inverted first bit, respectively, based on the up signal.

8. The bidirectional counter according to claim 7, wherein: The first pre-evaluation circuit comprises: at least one first transistor configured to: respectively receive at least one output of the at least one multiplexer and respectively precharge at least one first output node, generating at least one inverted first ripple carry corresponding to an inverted version of the at least one first ripple carry at the at least one first output node; and At least one second transistor is configured to receive the at least one output of the at least one multiplexer and transmit the discharge of the at least one first output node, respectively.

9. The bidirectional counter according to claim 6, wherein: The first pre-evaluation circuit includes: at least one latch configured to latch the at least one first ripple carry, respectively, and Wherein, each of the at least one latch comprises: an inverter configured to receive the first ripple carry; and A p-channel field effect transistor includes a gate connected to the output of the inverter, a source to which a positive power supply voltage is applied, and a drain connected to the input of the inverter.

10. The bidirectional counter according to claim 6, wherein: The first local clock selection circuit includes at least one unit circuit corresponding to the at least one first local clock, and Wherein, each of the at least one unit circuit is configured to: generate a first local clock with a logic high among the at least one first local clock when the input clock is logic low, generate a first local clock with a phase inverted from the first ripple carry when the input clock and the first carry input are logic high, and maintain the first local clock when the input clock is logic low.

11. The bidirectional counter according to claim 10, wherein: Each of the at least one unit circuit comprises: a first p-channel field effect transistor connected between a first node to which a positive power supply voltage is applied and a second node to which a first local clock is output, and configured to receive an input clock; a latch connected between the first node and the second node; and The first n-channel field effect transistor and the second n-channel field effect transistor are connected in series with each other between the second node and a third node to which the inverted first ripple carry is applied, and are configured to receive the first carry input and the input clock, respectively, and the inverted first ripple carry corresponds to the inverted version of the first ripple carry.

12. The bidirectional counter according to claim 11, wherein: The latches include: an inverter having an input connected to the second node; and A p-channel field effect transistor includes a gate connected to the output of the inverter, a source connected to the first node, and a drain connected to the second node.

13. The bidirectional counter according to claim 10, wherein: Each of the at least one unit circuit comprises: a first p-channel field effect transistor connected between a first node to which a positive power supply voltage is applied and a second node to which a first local clock is output, and configured to receive an input clock; a latch connected between the first node and the second node; and The first to third n-channel field effect transistors are connected in series between the second node and a third node to which a negative power supply voltage is applied, and are configured to receive a first carry input, an input clock, and a first ripple carry, respectively.

14. The bidirectional counter according to claim 13, wherein: The latches include: an inverter having an input connected to the second node; and A p-channel field effect transistor includes a gate connected to the output of the inverter, a source connected to the first node, and a drain connected to the second node.

15. The bidirectional counter according to any one of claims 6 to 14, further comprising: at least one second flip-flop configured to generate a second bit and at least one third bit lower than the second bit based on at least one second local clock; a second pre-evaluation circuit configured to: generate at least one second ripple carry based on the at least one third bit and a fourth bit lower than the at least one third bit in response to an activated up signal, and generate the at least one second ripple carry based on an inverted fourth bit corresponding to an inverted version of the fourth bit and at least one inverted third bit corresponding to an inverted version of the at least one third bit in response to a deactivated up signal; as well as a second local clock selection circuit configured to generate the at least one second local clock based on the input clock, the second carry input and the at least one second ripple carry, and Wherein the second pre-evaluation circuit is configured to generate a first carry input from the at least one second ripple carry.

16. A method for generating output data, the method comprising: Receive upward signal; generating, in response to the activated up signal, at least one first local clock based on the input clock and at least one first bit, the at least one first bit comprising a least significant bit of the output data; generating the at least one first local clock based on the input clock and at least one inverted first bit corresponding to an inverted version of the at least one first bit in response to the deactivated up signal; as well as The at least one first bit and a second bit which is a higher bit of the at least one first bit are generated based on the at least one first local clock.

17. The method according to claim 16, wherein: The step of generating the at least one first local clock in response to the activated up signal comprises: selecting the at least one first bit based on the activated up signal, respectively, and The step of generating the at least one first local clock in response to the deactivated up signal comprises: selecting the at least one inverted first bit respectively based on the deactivated up signal.

18. The method according to claim 16, wherein: The step of generating the at least one first local clock in response to the activated up signal comprises: simultaneously precharging at least one first output node at which the at least one first local clock is generated based on an input clock; and A discharge of the at least one first output node is transmitted based on an input clock and the at least one first bit.

19. The method according to claim 16, wherein: The step of generating the at least one first local clock in response to the deactivated up signal comprises: simultaneously precharging at least one first output node at which the at least one first local clock is generated based on an input clock; and The discharge of the at least one first output node is transmitted based on the input clock and the at least one inverted first bit.

20. The method according to any one of claims 16 to 19, further comprising: generating a carry input based on the at least one first local clock; generating at least one ripple carry based on the up signal, the second bit, and at least one third bit that is a higher bit than the second bit; generating at least one second local clock based on the input clock, the carry input, and the at least one ripple carry; The at least one third bit is generated based on the at least one second local clock.

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