Cyclic successive approximation analog-to-digital converter of multi-input comparator and quantization method

Abstract

The invention discloses a cyclic successive approximation analog-to-digital converter of a multi-input comparator and a quantization method. The converter comprises a sampling circuit, the multi-input comparator, a residual amplifier, a load capacitor and a decoder. The method comprises the following steps: performing first sampling and conversion processing according to a reference voltage signal to generate a residual voltage signal output code after first sampling; based on a residual amplifier, performing amplification processing on the residual voltage signal output code after the first sampling to obtain an amplified residual voltage signal output code; performing successive sampling and conversion processing on the amplified residual voltage signal output code to obtain a successive sampled residual voltage signal output code; and decoding the successively sampled residual voltage signal output code to obtain an effective residual voltage signal output code. According to the embodiment of the invention, the complexity of the residual amplifier can be reduced, so that the power consumption of the converter is reduced and the performance of the converter is improved. The circuit can be widely applied to the technical field of mixed signal circuits.

Description

Technical Field

[0001] The present application relates to the technical field of mixed signal circuits, and in particular to a cyclic successive approximation analog-to-digital converter of a multi-input comparator and a quantization method. Background Art

[0002] In modern electronic systems, analog-to-digital converters (ADCs) are used as core components to convert continuous analog signals into discrete digital signals. For the implementation of high-precision ADCs, common architecture types mainly include Delta-Sigma ADCs and Noise-Shaping SAR ADCs based on oversampling, as well as SAR ADCs and pipelined ADCs with Nyquist bandwidth. Oversampling ADCs improve resolution through noise shaping functions and digital filtering techniques. Although it helps reduce noise, its dependence on oversampling limits its application at the system level. In contrast, non-oversampling or Nyquist bandwidth high-precision ADC architectures provide greater flexibility.

[0003] One of the existing technical architectures of non-oversampling high-precision ADC is SAR ADC. The typical SAR ADC structure includes CDAC, comparator, sampling circuit and SAR logic. For high-precision SAR ADC, comparator is one of the most critical components. The function of the comparator is to determine the difference between the input signal voltage and the internally generated signal voltage, and output the corresponding digital bit. It is the core of the analog domain to digital domain conversion. Therefore, the noise characteristics of the comparator directly determine the accuracy of the quantization process. Comparator noise usually includes thermal noise, flicker noise (also known as 1 / f noise) and kick-back noise, etc. These noises will cause uncertainty in the comparison results, thereby affecting the accuracy and reliability of the ADC. At present, the reduction of comparator noise is mainly achieved by optimizing the design of the comparator and adding several stages of pre-amplifiers, but it also limits the speed of the comparator. Another technical architecture of non-oversampling high-precision ADC is pipeline ADC, but it is accompanied by high power consumption and complex circuit design requirements, and relies on high-precision comparators or high-performance amplifiers.

[0004] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the invention

[0005] The main purpose of the embodiments of the present application is to propose a cyclic successive approximation analog-to-digital converter with multiple input comparators and a quantization method, which can reduce the complexity of the residual amplifier, thereby reducing the power consumption of the converter and improving the performance of the converter.

[0006] To achieve the above-mentioned purpose, an embodiment of the present application provides a cyclic successive approximation analog-to-digital converter of a multi-input comparator, the converter comprising a sampling circuit, a multi-input comparator, a residual amplifier, a load capacitor and a decoder, the output end of the sampling circuit is connected to the first input end of the multi-input comparator, the first output end of the multi-input comparator is connected to the input end of the residual amplifier, the output end of the residual amplifier is connected to the input end of the load capacitor, the output end of the load capacitor is connected to the second input end of the multi-input comparator, and the second output end of the multi-input comparator is connected to the input end of the decoder, wherein:

[0007] The sampling circuit is used to generate a reference voltage signal;

[0008] The multi-input comparator is used to perform a first sampling and conversion process according to the reference voltage signal to generate a residual voltage signal output code after the first sampling, and perform successive sampling and conversion processes on the amplified residual voltage signal output code to obtain a residual voltage signal output code after successive sampling;

[0009] The residual amplifier is used to amplify the residual voltage signal output code after the first sampling to obtain the amplified residual voltage signal output code;

[0010] The load capacitor is used to store the amplified residual voltage signal output code and transmit it to the multi-input comparator;

[0011] The decoder is used to decode the residual voltage signal output code after the successive sampling to obtain a valid residual voltage signal output code.

[0012] In some embodiments, the multi-input comparator includes a high-order capacitor array, a middle-order capacitor array, and a low-order capacitor array, and the low-order capacitor array, the middle-order capacitor array, and the high-order capacitor array are connected in sequence, wherein:

[0013] The low-bit capacitor array is used to perform a quantization process of the reference voltage signal;

[0014] The mid-capacitor array is used to absorb the amplified comparator offset voltage;

[0015] The high-position capacitor array is used to generate a virtual position of reference.

[0016] In some embodiments, the low-order capacitor array, the middle-order capacitor array, and the high-order capacitor array all participate in a first sampling and conversion process, and the low-order capacitor array and the middle-order capacitor array participate in successive sampling and conversion processes.

[0017] In some embodiments, the residual amplifier includes a trimming network, a switch energy storage capacitor and an inverter amplifier, the trimming network is electrically connected to the switch energy storage capacitor, and the switch energy storage capacitor is electrically connected to the inverter amplifier, wherein:

[0018] The trimming network is used to adjust the capacitance value of the switch energy storage capacitor;

[0019] The switch energy storage capacitor is used to provide a current signal to the inverter amplifier;

[0020] The inverter amplifier is used to amplify the residual voltage signal output code after the first sampling to obtain the amplified residual voltage signal output code.

[0021] In some embodiments, the trimming network includes a capacitor array and a switch array, the capacitor array includes a plurality of capacitors, the switch array includes a plurality of switch pairs, and each of the plurality of switch pairs includes a first switch and a second switch, wherein:

[0022] The upper plates of a plurality of the capacitors are selectively connected to the second end of the first switch, and the lower plates of a plurality of the capacitors are selectively connected to the first end of the second switch;

[0023] The first end of the first switch is selectively connected to the upper plate of the switch energy storage capacitor, and the second end of the second switch is selectively connected to the lower plate of the switch energy storage capacitor.

[0024] In some embodiments, the inverter amplifier includes a first branch switch, a second branch switch, a third branch switch, a first transistor, a second transistor, a third transistor and a fourth transistor, the first branch switch includes a first branch first branch switch and a first branch second branch switch, the second branch switch includes a second branch first branch switch and a second branch second branch switch, the third branch switch includes a third branch first branch switch and a third branch second branch switch, wherein the first end of the first branch first branch switch is connected to a high level, the second end of the first branch first branch switch, the upper plate of the switch energy storage capacitor and the first end of the second branch first branch switch are connected, and the first end of the first branch second branch switch, the lower plate of the switch energy storage capacitor and the first end of the second branch second branch switch are connected. The second end of the second branch switch of the first branch is connected to ground, the second end of the first branch switch of the second branch and the source of the first transistor are connected to the source of the second transistor, the second end of the second branch switch of the second branch and the source of the third transistor are connected to the source of the fourth transistor, the drain of the first transistor and the drain of the third transistor are connected to the first end of the first branch switch of the third branch, the drain of the second transistor and the drain of the fourth transistor are connected to the second end of the second branch switch of the third branch, the second end of the first branch switch of the third branch is connected to the first end of the second branch switch of the third branch and is connected to an enable clock signal, the gate of the first transistor is connected to the gate of the third transistor, and the gate of the second transistor is connected to the gate of the fourth transistor.

[0025] To achieve the above object, another aspect of an embodiment of the present application provides a quantization method for a cyclic successive approximation analog-to-digital converter of a multi-input comparator, the quantization method comprising the following steps:

[0026] Performing a first sampling and conversion process according to the reference voltage signal to generate a residual voltage signal output code after the first sampling;

[0027] Based on the residual amplifier, the residual voltage signal output code after the first sampling is amplified to obtain an amplified residual voltage signal output code;

[0028] The amplified residual voltage signal output code is sampled and converted one by one to obtain a sampled residual voltage signal output code;

[0029] The residual voltage signal output code after the successive sampling is decoded to obtain a valid residual voltage signal output code.

[0030] In some embodiments, the residual amplifier includes a charging stage and an amplification stage.

[0031] In some embodiments, for the charging stage of the residual amplifier, the first branch switch is set to a closed state, the second branch switch is set to an open state, the third branch switch is set to a closed state, the upper board of the switch energy storage capacitor is connected to a power supply, and the lower board of the switch energy storage capacitor is grounded, and the switch energy storage capacitor is charged.

[0032] In some embodiments, for the amplification stage of the residual amplifier, the first branch switch is set to an open state, the second branch switch is set to a closed state, and the third branch switch is set to an open state. The switch energy storage capacitor is used to provide a current signal, and the residual voltage signal output code after the first sampling is amplified to obtain the amplified residual voltage signal output code.

[0033] The embodiments of the present application include at least the following beneficial effects: The present application provides a cyclic successive approximation analog-to-digital converter and a quantization method of a multi-input comparator. After the first SAR conversion is completed, the residual voltage on the CDAC is amplified by a residual amplifier, and the output result is stored on a capacitor and connected to the second pair of inputs of the comparator, and used as an input signal in the second SAR conversion. By increasing the number of input pairs of the comparator, it can be repeatedly expanded to successive SAR conversion. The minimum quantization voltage brought by the segmented SAR conversion and the use of the first SAR conversion result as input data for the successive SAR conversion can reduce the complexity of the residual amplifier, thereby reducing the power consumption of the converter and improving the performance of the converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a structural schematic diagram of a cyclic successive approximation analog-to-digital converter of a multi-input comparator provided in an embodiment of the present application;

[0035] Figure 2 It is a flow chart of a quantization method of a cyclic successive approximation analog-to-digital converter of a multi-input comparator provided in an embodiment of the present application;

[0036] Figure 3 is a schematic diagram of the structure of a residual amplifier provided in an embodiment of the present application;

[0037] Figure 4 It is a schematic diagram of the FFT spectrum output by the converter at a sampling rate of 10 MHz provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are only examples of systems and methods consistent with some aspects of the embodiments of the present application as detailed in the attached claims.

[0039] It is understood that the terms "first", "second", etc. used in this application can be used to describe various concepts in this article, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another concept. For example, without departing from the scope of the embodiment of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determination".

[0040] The terms "at least one", "multiple", "each", "any", etc. used in this application, at least one includes one, two or more, multiple includes two or more, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0042] First of all, it should be noted that in modern electronic systems, analog-to-digital converters (ADCs) are used as core components to convert continuous analog signals into discrete digital signals. Its wide range of applications includes wireless communications, scientific measuring instruments, medical diagnostic equipment, and industrial automation, which place increasingly high standards on signal processing accuracy and speed in these fields. The performance of an ADC is often defined by key indicators such as its resolution, sampling rate, linearity, power consumption, and signal-to-noise ratio, which largely determine the performance and efficiency of the overall system. For the implementation of high-precision ADCs, common architecture types mainly include Delta-Sigma ADCs and Noise-Shaping SAR ADCs based on oversampling, as well as Nyquist bandwidth SAR ADCs and pipelined ADCs. Oversampling ADCs improve resolution through noise shaping functions and digital filtering techniques. Although it helps reduce noise, its dependence on oversampling limits its system-level applications. In contrast, non-oversampling or Nyquist bandwidth high-precision ADC architectures offer greater flexibility.

[0043] One of the technical architectures of the existing non-oversampling high-precision ADC is the SAR ADC. The traditional SAR ADC has been popularized in a wide range of applications due to its simple and effective architecture, low power consumption and moderate speed characteristics. The typical SAR ADC structure includes CDAC, comparator, sampling circuit and SAR logic. The SAR ADC approaches the input signal value bit by bit through the successive approximation algorithm, and its performance is highly dependent on the accuracy of the internal comparator and capacitor array DAC. For high-precision SAR ADC, the comparator is one of the most critical components. The role of the comparator is to determine the difference between the input signal voltage and the internal generated signal voltage, and output the corresponding digital bit, which is the core of the analog domain to digital domain conversion. Therefore, the noise characteristics of the comparator directly determine the accuracy of the quantization process. Comparator noise usually includes thermal noise, flicker noise (also known as 1 / f noise) and kick-back noise, which will cause uncertainty in the comparison result, thereby affecting the accuracy and reliability of the ADC. When the slight changes in the input signal need to be accurately measured, the noise of the comparator may mask or distort these subtle signal changes, causing the ADC to output incorrect digital values. This error is particularly significant for high-precision ADCs. For high-precision SAR ADCs, the comparator noise level is usually required to be within half of the least significant bit (LSB). For example, for a 16-bit high-precision ADC with a 0.9V reference voltage, the differential LSB is only 27.5μV. Conventional single-stage dynamic comparators are difficult to achieve such stringent noise performance. In order to improve the accuracy of the comparator, engineers have taken some measures to reduce the impact of comparator noise. A common method is to optimize the design of the comparator and add several stages of pre-amplifiers to it. However, the multi-stage pre-amplifier itself not only requires a lot of power consumption, but also limits the speed of the comparator, thereby slowing down the overall bandwidth of the system. In recent years, some advanced dynamic amplifier architectures have been introduced as comparator pre-amplifiers. Although they have shown potential in power consumption and speed, the stability and PVT robustness of the dynamic amplifier itself are also difficult problems that must be considered.

[0044] Another widely used technical architecture for non-oversampling high-precision ADCs is the pipeline ADC. In the architecture of the pipeline ADC, the multiplication digital-to-analog converter (MDAC) is the core module and its function is crucial. The MDAC is responsible for partially quantizing the signal in each pipeline stage and generating a residual signal for the next stage. This process enables the pipeline ADC to achieve high throughput and high-precision analog-to-digital conversion. Therefore, the performance of the MDAC directly affects the overall performance of the ADC.

[0045] MDACs are usually composed of two main parts: quantizer and residual amplifier. The quantizer implements a rough analog-to-digital conversion at each stage, which determines the rough digital approximation of the signal at that stage. In this process, the accuracy and speed of the quantizer are critical to the overall performance of the ADC, especially in applications that require high sampling rates and high precision. In recent years, the architecture of quantizers has shown a mixed diversity. Among them, the SAR architecture has been particularly favored as a choice with simple implementation and strong scalability, and pipelined SAR ADCs have become increasingly popular. For high-precision SAR ADCs, a significant advantage of introducing a pipeline structure is that it can greatly relax the restrictions on comparator accuracy. For example, if the same 16-bit accuracy requirement is implemented using an 8-8 two-stage pipeline architecture, only one comparator that meets 8-bit accuracy is required, which can bring amazing improvements to the power consumption and speed of the comparator. However, there are always two sides to everything, and high-precision pipelined SAR ADCs face equally difficult problems, especially the design of the residual amplifier.

[0046] The residual amplifier is responsible for amplifying the residual analog signal difference (i.e., quantization error) and passing it to the next stage for further refined processing. Its design faces many challenges, such as having a high gain to ensure that the residual signal is amplified to a level that can be used for the next stage of processing, while still maintaining low distortion and low noise, which lays the foundation for achieving high resolution of pipeline ADCs. However, high amplification gain is often accompanied by higher power consumption and complex circuit design requirements, so it is necessary to strike a balance between performance and power consumption when designing a residual amplifier. In addition, the circuit characteristics of the residual amplifier, such as linearity, bandwidth, and static offset, also need to be carefully optimized to minimize the impact of error accumulation on the linearity of the entire ADC. For high-precision application scenarios, the design difficulty and power consumption cost of the residual amplifier are no less than those of a high-precision comparator.

[0047] In summary, existing Nyquist bandwidth high-precision ADCs are usually extremely dependent on high-precision comparators or high-performance amplifiers, and the implementation of these two types of modules often requires high circuit and power consumption costs.

[0048] In view of this, a cyclic successive approximation analog-to-digital converter with a multi-input comparator is provided in an embodiment of the present application. After the first SAR conversion (called α-SAR conversion) is completed, the residual voltage on the CDAC is amplified using a residual amplifier, and the output result is stored on a capacitor and connected to the second pair of inputs of the comparator, and used as an input signal in the second SAR conversion (called β-SAR conversion). By increasing the number of input pairs of the comparator, the above process can be repeated and extended to more SAR conversions. In the additional conversion, the CDAC top plate originally connected to the first pair of input pairs no longer has both sampling and binary reference functions, but only provides a binary reference function. CDAC is reset after the residual amplification is completed. During other SAR conversions except α-SAR conversion, each bit capacitor in CDAC will perform different functions: the high-order array will not directly participate in the SAR conversion, but will be used as a Dummy bit for generating a reference; the middle-order array and the low-order array participate in the SAR conversion, wherein the middle-order array mainly plays a role similar to the high-order redundancy in the pipeline SAR ADC, which is used to absorb the amplified comparator offset voltage, and the low-order array performs a complete quantization function like all the bit capacitors of the α-SAR conversion. For high-precision quantization achieved with this architecture, the power consumption and design difficulty of the high-precision comparator can be significantly reduced due to the increase in the minimum quantization voltage brought by the segmented SAR conversion; at the same time, due to the common-mode nature of the multi-input comparator in the transconductance domain addition, the first quantization bit number can be significantly larger than the subsequent quantization, which greatly relaxes the requirements of the residual amplifier. Therefore, through this cyclic multi-step SAR ADC architecture based on multi-input comparators, the cost of high-bit SAR quantization has been significantly reduced.

[0049] In addition, it should be noted that the embodiment of the present invention introduces a residual amplifier with a gain of 16 times, adds an additional input pair of tubes to the comparator, and transforms the original single SAR conversion logic into multiple SAR conversion logic. Since the third and subsequent SAR conversion operation processes are completely consistent with the second SAR conversion, two SAR conversions (α-SAR conversion and β-SAR conversion) are used as examples for explanation below.

[0050] Reference Figure 1 , Figure 1 A structural diagram of a cyclic successive approximation analog-to-digital converter of a multi-input comparator provided by an embodiment of the present invention, referring to Figure 1, the converter includes a sampling circuit, a multi-input comparator, a residual amplifier, a load capacitor and a decoder, the output end of the sampling circuit is connected to the first input end of the multi-input comparator, the first output end of the multi-input comparator is connected to the input end of the residual amplifier, the output end of the residual amplifier is connected to the input end of the load capacitor, the output end of the load capacitor is connected to the second input end of the multi-input comparator, and the second output end of the multi-input comparator is connected to the input end of the decoder, wherein:

[0051] The sampling circuit is used to generate a reference voltage signal;

[0052] The multi-input comparator is used to perform a first sampling and conversion process according to the reference voltage signal to generate a residual voltage signal output code after the first sampling, and perform successive sampling and conversion processes on the amplified residual voltage signal output code to obtain a residual voltage signal output code after successive sampling;

[0053] Specifically, the multi-input comparator includes a high-order capacitor array, a middle-order capacitor array and a low-order capacitor array, and the low-order capacitor array, the middle-order capacitor array and the high-order capacitor array are connected in sequence, wherein the low-order capacitor array is used to perform the quantization process of the reference voltage signal; the middle-order capacitor array is used to absorb the amplified comparator offset voltage; and the high-order capacitor array is used to generate a reference virtual position.

[0054] In addition, it should be noted that, in this embodiment, the low-order capacitor array, the middle-order capacitor array and the high-order capacitor array all participate in the first sampling and conversion process, and the low-order capacitor array and the middle-order capacitor array participate in the successive sampling and conversion process.

[0055] In this embodiment, a multi-input comparator is introduced to support cyclic multi-step successive approximation (SAR) conversion. The multi-input comparator is the core of this architecture, which is usually used to implement addition in the current domain or transconductance domain. For α-SAR conversion (that is, conventional SAR conversion), the signal on the CDAC can be expressed as input V in With codeword D out The addition is realized through the two ends of the capacitor because the capacitor can be regarded as a natural adder. In the β-SAR conversion stage, the amplified α-SAR conversion residual becomes the input of the β-SAR conversion. At this time, the addition does not need to be realized through the sampling circuit at both ends of the capacitor, but is realized at the comparator input with an additional input pair.

[0056] In the β-SAR conversion, the top plate of the CDAC no longer assumes the sampling and binary reference functions at the same time, but is only used to provide the binary reference codeword Dout. After the residual amplification, the CDAC is reset. In the β-SAR stage, each bit capacitor plays a different role: the high-bit capacitor array does not participate in the β-SAR conversion, but is used as a virtual bit to generate the reference; the middle-bit array participates in the β-SAR conversion, playing a role similar to the high-bit redundancy in the pipeline SAR ADC to absorb the amplified comparator offset voltage. The low-bit array performs the full quantization function like all the bit capacitors of the α-SAR.

[0057] This architecture improves the minimum quantization voltage through segmented SAR conversion, thereby significantly reducing the power consumption and design difficulty of high-precision comparators. In addition, due to the common mode characteristics of multi-input comparators in transconductance domain addition, the number of bits in the first quantization can significantly exceed the second quantization. This also reduces the requirements for the residual amplifier accordingly. Through this cyclic multi-step SAR ADC architecture based on multi-input comparators, accurate quantization of high bit numbers can be achieved at a lower cost.

[0058] The schematic diagram of the structure is as follows Figure 1 As shown in the figure, the differential half-side circuit has been omitted, and a two-step SAR conversion is used as an example. The architecture proposed by the present invention is implemented in a 40nm process, and the supply voltage and reference voltage are both 0.9V. Among them, the CDAC used is a segmented bridge form, with a total of 15 binary-sized capacitors, from high to low, C 14 ,C 13 ,C 12 ,…,C0, which includes 3 redundant bits, so a complete SAR conversion can output 12 valid bits. For the two-step SAR conversion, α-SAR performs 15 comparisons completely and provides 12 valid output bits, and β-SAR conversion starts from the 6th bit, performs 9 SAR conversions and provides 4 valid output bits.

[0059] The residual amplifier is used to amplify the residual voltage signal output code after the first sampling to obtain an amplified residual voltage signal output code;

[0060] Specifically, Figure 3 As shown, the residual amplifier includes a trimming network, a switch energy storage capacitor and an inverter amplifier, the trimming network is electrically connected to the switch energy storage capacitor, and the switch energy storage capacitor is electrically connected to the inverter amplifier, wherein the trimming network is used to adjust the capacitance value of the switch energy storage capacitor; the switch energy storage capacitor is used to provide a current signal to the inverter amplifier; the inverter amplifier is used to amplify the residual voltage signal output code after the first sampling to obtain an amplified residual voltage signal output code.

[0061] Among them, it should be noted that the adjustment network includes a capacitor group array and a switch group array, the capacitor group array includes a number of capacitors, the switch group array includes a number of switch pairs, the number of switch pairs each include a first switch and a second switch, the upper plates of the number of capacitors are selectively connected to the second end of the first switch, the lower plates of the number of capacitors are selectively connected to the first end of the second switch, the first end of the first switch is selectively connected to the upper plate of the switch energy storage capacitor, and the second end of the second switch is selectively connected to the lower plate of the switch energy storage capacitor.

[0062] Furthermore, it should be noted that the inverter amplifier includes a first branch switch, a second branch switch, a third branch switch, a first transistor M P1 , the second transistor M P2 , the third transistor M N1 With the fourth transistor M N2 The first branch switch includes a first branch first branch switch S 1,p The second branch switch S of the first branch 1,n The second branch switch includes the second branch first branch switch S 2,p The second branch switch S 2,n The third branch switch includes the third branch first branch switch S 3,a The second branch switch S of the third branch 3,b , wherein the first end of the first branch switch of the first branch is connected to a high level, the second end of the first branch switch of the first branch and the upper plate of the switch energy storage capacitor are connected to the first end of the first branch switch of the second branch, the first end of the second branch switch of the first branch and the lower plate of the switch energy storage capacitor are connected to the first end of the second branch switch of the second branch, the second end of the second branch switch of the first branch is grounded, the second end of the first branch switch of the second branch and the source of the first transistor are connected to the source of the second transistor, the second end of the second branch switch of the second branch and the source of the third transistor are connected to the source of the fourth transistor, the drain of the first transistor and the drain of the third transistor are connected to the first end of the first branch switch of the third branch, the drain of the second transistor and the drain of the fourth transistor are connected to the second end of the second branch switch of the third branch, the second end of the first branch switch of the third branch is connected to the first end of the second branch switch of the third branch and is connected to the enable clock signal, the gate of the first transistor is connected to the gate of the third transistor, and the gate of the second transistor is connected to the gate of the fourth transistor.

[0063] In this embodiment, since the reference level of the β-SAR conversion remains unchanged, the residual amplifier requires a magnification of 16 times. Due to the advantages of the proposed architecture, the residual amplifier has low requirements for linearity and does not need to drive a large CDAC load. Figure 3The floating inverter amplifier (FIA) structure shown in the figure is used as a residual amplifier, which consists of an inverter amplifier and a switch energy storage capacitor C R As a dynamic amplifier, its operation can be divided into the charging stage and the amplification stage. AMP When it is low, FIA is in the charging stage. 1,p , S 1,n Closed, switch S 2,p , S 2,n Disconnect, S 3,a , S 3,b Closed, energy storage capacitor C R The top and bottom plates are connected to power and ground respectively, while the two differential output nodes are set to V CM During the amplification phase, switch S 1,p , S 1,n Disconnect, switch S 2,p , S 2,n Closed, S 3,a , S 3,b Disconnect, C R It powers the circuit like a battery, resulting in a continuous but gradually decaying source-drain current. According to the basic current law, the current through the two capacitor plates must be equal, which makes the output node a symmetrical virtual ground, thereby stabilizing the common-mode output voltage. Due to the common-mode performance requirements of the multi-input comparator as a transconductance addition device, the excellent common-mode output properties of FIA are very suitable for this structure, so there is no need to use an additional common-mode feedback (CMFB) circuit. At the same time, there are N+1 trimming capacitors C t,N ,…,C t,1 ,C t,0 And the corresponding switch pair S t,N<a&b> ,…,S t,1<a&b> ,S t,0<a&b> The trimming network (Trimming Bank) adjusts the FIA ​​equivalent energy storage capacitor C R This ensures the PVT robustness of the open-loop FIA gain.

[0064] The load capacitor is used to store the amplified residual voltage signal output code and transmit it to the multi-input comparator;

[0065] The decoder is used to decode the residual voltage signal output code after successive sampling to obtain a valid residual voltage signal output code.

[0066] In summary, the conventional 16-bit high-precision SAR ADC requires a 16-bit CDAC to be calibrated for capacitance mismatch, and the mismatch calibration of the high-precision pipeline SAR ADC is more complicated because each level of sampling uses a different CDAC. For the architecture proposed in the present invention, although the principle of two SAR conversions is similar to that of the pipeline, only one CDAC is used, so the binary reference level code value generated by the CDAC between the two conversions is completely consistent. At the same time, due to the method of decomposing 16 bits into 12+4, the effective number of bits of the CDAC is only 12 bits, and the unit capacitance value can be selected to be larger than the CDAC unit capacitance used in the conventional 16-bit high-precision SAR ADC, so the calibration difficulty is greatly reduced.

[0067] See also Figure 2 The embodiment of the present application further provides a quantization method of a cyclic successive approximation analog-to-digital converter of a multi-input comparator, which can realize the above-mentioned cyclic successive approximation analog-to-digital converter of a multi-input comparator, and the system includes:

[0068] S100, performing a first sampling and conversion process according to a reference voltage signal to generate a residual voltage signal output code after the first sampling;

[0069] S200, based on a residual amplifier, amplifying the residual voltage signal output code after the first sampling to obtain an amplified residual voltage signal output code;

[0070] It should be noted that, in some embodiments, step S200 may include: S210, for the charging stage of the residual amplifier, setting the first branch switch to a closed state, setting the second branch switch to an open state, setting the third branch switch to a closed state, connecting the upper board of the switch energy storage capacitor to a power supply, grounding the lower board of the switch energy storage capacitor, and charging the switch energy storage capacitor; S220, for the amplification stage of the residual amplifier, setting the first branch switch to an open state, setting the second branch switch to a closed state, setting the third branch switch to an open state, the switch energy storage capacitor is used to provide a current signal, and the residual voltage signal output code after the first sampling is amplified to obtain the amplified residual voltage signal output code.

[0071] S300, performing successive sampling and conversion processing on the amplified residual voltage signal output code to obtain a successive sampled residual voltage signal output code;

[0072] S400, decoding the residual voltage signal output code after successive sampling to obtain a valid residual voltage signal output code;

[0073] In some specific embodiments, sampling is performed first, and then the α-SAR conversion phase (Φ alpha), after 15 comparisons, a 15-bit output code is generated. In this stage, the gate of the second pair of input tubes of the comparator is grounded and regarded as turned off; after the α-SAR conversion is completed, the FIA ​​amplification stage (Φ AMP ), FIA amplifies the residual voltage converted by α-SAR by 16 times and stores it in the load capacitor C L ; After the amplification phase ends, CDAC is briefly reset, and then the load capacitor C L Connect the gate of the second pair of input tubes of the comparator and start the β-SAR stage (Φ beta ), 9 comparisons are performed and a 9-bit output code is generated. After the β-SAR conversion is completed, a total of 26-bit output codes are obtained in a single sampling cycle, and a 16-bit valid output can be obtained after a certain decoding.

[0074] Further, if Figure 4 As shown, the output spectrum of the invented cyclic multi-step successive approximation analog-to-digital converter architecture based on multi-input comparator is shown. The ADC sampling frequency is 10MHz, the input frequency is a sine wave with a peak-to-peak value of 1.6V at 0.547MHz, and the output code value is imported into matlab for FFT testing. The FFT results show that the output SNDR of the ADC within the Nyquist bandwidth of 5MHz is 88.7dB, the effective number of bits (ENOB) is 14.44bit, and the core power consumption is 0.675mW. The quality factor FoMs calculated from this is 187.4dB.

[0075] For comparison, in the industrial world, take the AD7626 chip of Analog Devices (ADI) as an example. This ADC chip is a 16-bit SAR ADC chip with a sampling rate of 10MHz, and it is also the one with the highest bandwidth among the company's 16-bit single-channel precision ADC products. According to the data sheet, the SNR of AD7626 is 91.5dB and the total power consumption is 136mW. Although considering that industrial products often consume considerable power in reference buffers and other stability components, the power consumption of the ADC architecture proposed in the present invention is still very attractive.

[0076] It can be understood that the contents of the above method embodiments are all applicable to the present system embodiments, the functions specifically implemented by the present system embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0077] The preferred embodiments of the present application are described above with reference to the accompanying drawings, but the scope of the rights of the present application is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present application should be within the scope of the rights of the present application.

Claims

1. A cyclic successive approximation analog-to-digital converter with multiple input comparators, characterized in that: The converter comprises a sampling circuit, a multi-input comparator, a residual amplifier, a load capacitor and a decoder, wherein the output end of the sampling circuit is connected to the first input end of the multi-input comparator, the first output end of the multi-input comparator is connected to the input end of the residual amplifier, the output end of the residual amplifier is connected to the input end of the load capacitor, the output end of the load capacitor is connected to the second input end of the multi-input comparator, and the second output end of the multi-input comparator is connected to the input end of the decoder, wherein: The sampling circuit is used to generate a reference voltage signal; The multi-input comparator is used to perform a first sampling and conversion process according to the reference voltage signal to generate a residual voltage signal output code after the first sampling, and perform successive sampling and conversion processes on the amplified residual voltage signal output code to obtain a residual voltage signal output code after successive sampling; The residual amplifier is used to amplify the residual voltage signal output code after the first sampling to obtain the amplified residual voltage signal output code; The load capacitor is used to store the amplified residual voltage signal output code and transmit it to the multi-input comparator; The decoder is used to decode the residual voltage signal output code after the successive sampling to obtain a valid residual voltage signal output code.

2. The converter according to claim 1, characterized in that The multi-input comparator includes a high-order capacitor array, a middle-order capacitor array and a low-order capacitor array, wherein the low-order capacitor array, the middle-order capacitor array and the high-order capacitor array are connected in sequence, wherein: The low-bit capacitor array is used to perform a quantization process of the reference voltage signal; The mid-capacitor array is used to absorb the amplified comparator offset voltage; The high-position capacitor array is used to generate a virtual position of reference.

3. The converter according to claim 2, characterized in that The low-order capacitor array, the middle-order capacitor array and the high-order capacitor array all participate in the first sampling and conversion process, and the low-order capacitor array and the middle-order capacitor array participate in the successive sampling and conversion processes.

4. The converter according to claim 1, characterized in that The residual amplifier includes a trimming network, a switch energy storage capacitor and an inverter amplifier, the trimming network is electrically connected to the switch energy storage capacitor, and the switch energy storage capacitor is electrically connected to the inverter amplifier, wherein: The trimming network is used to adjust the capacitance value of the switch energy storage capacitor; The switch energy storage capacitor is used to provide a current signal to the inverter amplifier; The inverter amplifier is used to amplify the residual voltage signal output code after the first sampling to obtain the amplified residual voltage signal output code.

5. The converter according to claim 4, characterized in that The trimming network includes a capacitor array and a switch array, the capacitor array includes a plurality of capacitors, the switch array includes a plurality of switch pairs, and each of the plurality of switch pairs includes a first switch and a second switch, wherein: The upper plates of a plurality of the capacitors are selectively connected to the second end of the first switch, and the lower plates of a plurality of the capacitors are selectively connected to the first end of the second switch; The first end of the first switch is selectively connected to the upper plate of the switch energy storage capacitor, and the second end of the second switch is selectively connected to the lower plate of the switch energy storage capacitor.

6. The converter according to claim 4, characterized in that The inverter amplifier includes a first branch switch, a second branch switch, a third branch switch, a first transistor, a second transistor, a third transistor and a fourth transistor, the first branch switch includes a first branch switch of the first branch and a second branch switch of the first branch, the second branch switch includes a first branch switch of the second branch and a second branch switch of the second branch, the third branch switch includes a first branch switch of the third branch and a second branch switch of the third branch, wherein the first end of the first branch switch of the first branch is connected to a high level, the second end of the first branch switch of the first branch and the upper plate of the switch energy storage capacitor are connected to the first end of the first branch switch of the second branch, the first end of the second branch switch of the first branch and the lower plate of the switch energy storage capacitor are connected to the first end of the second branch switch of the second branch, The second end of the second branch switch of the first branch is grounded, the second end of the first branch switch of the second branch and the source of the first transistor are connected to the source of the second transistor, the second end of the second branch switch of the second branch and the source of the third transistor are connected to the source of the fourth transistor, the drain of the first transistor and the drain of the third transistor are connected to the first end of the first branch switch of the third branch, the drain of the second transistor and the drain of the fourth transistor are connected to the second end of the second branch switch of the third branch, the second end of the first branch switch of the third branch is connected to the first end of the second branch switch of the third branch and is connected to an enable clock signal, the gate of the first transistor is connected to the gate of the third transistor, and the gate of the second transistor is connected to the gate of the fourth transistor.

7. A quantization method for a cyclic successive approximation analog-to-digital converter of a multi-input comparator, characterized in that: The quantification method comprises the following steps: Performing a first sampling and conversion process according to the reference voltage signal to generate a residual voltage signal output code after the first sampling; Based on the residual amplifier, amplifying the residual voltage signal output code after the first sampling to obtain an amplified residual voltage signal output code; The amplified residual voltage signal output code is sampled and converted one by one to obtain a sampled residual voltage signal output code; The residual voltage signal output code after the successive sampling is decoded to obtain a valid residual voltage signal output code.

8. The method according to claim 7, characterized in that The residual amplifier includes a charging stage and an amplification stage.

9. The method according to claim 8, characterized in that For the charging stage of the residual amplifier, the first branch switch is set to a closed state, the second branch switch is set to an open state, the third branch switch is set to a closed state, the upper board of the switch energy storage capacitor is connected to a power supply, the lower board of the switch energy storage capacitor is grounded, and the switch energy storage capacitor is charged.

10. The method according to claim 8, characterized in that For the amplification stage of the residual amplifier, the first branch switch is set to an open state, the second branch switch is set to a closed state, and the third branch switch is set to an open state. The switch energy storage capacitor is used to provide a current signal, and the residual voltage signal output code after the first sampling is amplified to obtain the amplified residual voltage signal output code.

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