Product code encoding method and device, product code decoding method and device and storage medium

Abstract

The embodiment of the invention provides a coding method, a decoding method, a device and a storage medium of a product code, and the coding method comprises the steps: enabling k1 * p information bits of each p column in a k1 * k2 information bit matrix to correspond to k1 information symbols of one RS code, carrying out the coding to generate n1-k1 check symbols, splicing the n1-k1 check symbols with the information bit matrix, each check symbol comprises p bits to obtain a n1 * k2 first bit matrix, and each check symbol comprises p bits; each k3 bits sequentially distributed in adjacent rows of the first bit matrix correspond to one LDPC code, encoding is carried out to generate n3-k3 check bits, the n3-k3 check bits are sequentially spliced in the same row as each k3 bits, a n1 * n2 second bit matrix is obtained, and the second bit matrix comprises t1 RS codes and t2 LDPC codes. According to the invention, the original LDPC code with short code length can be replaced by the LDPC code with longer code length and stronger error correction capability on the premise of not increasing the code word dimension of the product code, and in addition, the decoding performance is improved.

Description

Technical Field

[0001] The present application relates to the field of coding and decoding technology, and in particular to a method for encoding, a method for decoding, a device and a storage medium of a product code. Background Art

[0002] Channel coding technology corrects errors in transmission signals by adding redundant information, and is one of the core technologies for improving the reliability of communication systems. 5G Low-Density Parity-Codes (5G-LDPC) have excellent performance, but due to the existence of short loops in the parity check matrix, error flattening usually occurs in areas with higher signal-to-noise ratios, that is, the error rate curve suddenly flattens, which is significantly different from the performance in the waterfall area. The error flattening phenomenon of 5G-LDPC codes is a significant obstacle to their application in high-throughput, high-reliability, and low-latency application scenarios of 5G systems.

[0003] Product codes are parallel concatenated codes constructed using two or more codewords. By constructing product codes, interleaving technology is combined with error control, and both random errors and burst errors can be processed simultaneously. Product codes can use a soft-input and soft-output decoder to iteratively exchange soft external information between row component codes and column component codes. This decoding scheme improves decoding performance at the expense of increased computational complexity. Concatenating 5G-LDPC codes with Reed-Solomon (RS) codes can improve the error flooring of 5G-LDPC codes by utilizing the error correction capability of RS codes. There are some limitations in the current RS-LDPC product code scheme, such as performance degradation due to the code rate loss caused by constructing concatenated codes, and error propagation due to insufficient error correction capability of the outer code.

[0004] RS-LDPC product codes are defined over a finite field GF(2 p ) as the outer code, and the LDPC(n2,k2) code defined on the finite field GF(2) as the inner code. The commonly used RS-LDPC product code encoding method is mainly divided into the following two steps. The first step: encode the outer code. Since the RS code is defined on the finite field GF(2 p ), so every p bits correspond to one symbol, and the k1×p information bits in each p column correspond to the k1 information symbol of the RS code, and the encoding generates n1-k1 check symbols to obtain an n1×k2 bit matrix. Step 2: Perform inner code encoding. Since the LDPC code is defined on the finite field GF(2), the k2 information bits in each row are encoded to generate n2-k2 check bits, and the n1×n2 bit matrix is ​​obtained.

[0005] The matrix structure obtained after encoding is as follows Figure 1As shown, each p columns of the information bit part of the matrix are a RS code C1(n1,k1) codeword, and each row is a LDPC code C2(n2,k2) codeword, with a total of k2 / p RS codes and n1 LDPC codes. The code rate R of the product code is the product of the RS code rate R1=k1 / n1 and the LDPC code rate R2=k2 / n2, that is, R=R1×R2. The number of information bits of the product code K=k1×k2, and the number of bits after encoding N=n1×n2.

[0006] In the block structure of product code, the outer code is arranged in the column direction and the inner code is arranged in the row direction. After the inner code decoding is completed, the residual error of an inner code codeword will be dispersed into multiple outer code codewords, so that the residual error is easier to correct, thereby obtaining better decoding performance.

[0007] In the block structure of the RS-LDPC product code word, one LDPC code is arranged in each row in the row direction, which is usually only suitable for using short codes. If an LDPC code with a longer code length is used, the product code will be too long, resulting in excessive transmission delay and excessive consumption of hardware resources in practical applications. Summary of the invention

[0008] At least one embodiment of the present application provides a product code encoding method, decoding method, device and storage medium, which can replace the original LDPC code with a shorter code length with an LDPC code with a longer code length and stronger error correction capability without increasing the codeword dimension of the product code.

[0009] In order to solve the above technical problems, this application is implemented as follows:

[0010] In a first aspect, an embodiment of the present application provides a method for encoding a product code, comprising:

[0011] Corresponding k1×p information bits of each p column in a k1×k2 information bit matrix to k1 information symbols of an RS code, encoding to generate n1-k1 check symbols, and concatenating them with the information bit matrix to obtain a first bit matrix of n1×k2, wherein each of the check symbols includes p bits;

[0012] Corresponding each k3 bits sequentially distributed in adjacent rows of the first bit matrix to one LDPC code, encoding to generate n3-k3 check bits, and sequentially splicing the n3-k3 check bits in the same row as the k3 bits to obtain a n1×n2 second bit matrix, wherein the second bit matrix includes t1 RS codes and t2 LDPC codes;

[0013] Wherein, k1, k2, k3, p, n1, n2, n3 are all positive integers, t1 = k2 / p, t2 = n1×k2 / k3, k2 <k3。

[0014] Optionally, each k3 information is bits distributed in the first bit matrix in an order from left to right and from top to bottom.

[0015] Optionally, sequentially splicing the n3-k3 check bits in the same row as each k3 bits includes:

[0016] In order from left to right and from top to bottom, the n3-k3 check bits are spliced ​​in the same row as each k3 bits, wherein the total number of bits in each row after splicing is n2.

[0017] Optionally, the method further includes: sending the second bit matrix.

[0018] In a second aspect, an embodiment of the present application provides a method for decoding a product code, comprising:

[0019] Receive a first matrix of n1×n2, the first matrix including a second matrix of n1×k2 and a third matrix of n1×(n2-k2), the first matrix corresponding to t2 LDPC codes, each LDPC code corresponding to k3 soft information quantities sequentially distributed in adjacent rows of the second matrix, and n3-k3 soft information quantities sequentially distributed in the third matrix and in the same row as the k3 soft information quantities;

[0020] Performing iterative decoding of the current iteration round on the soft information corresponding to the t2 LDPC codes in the first matrix, respectively, and splicing the decoding results of the t2 LDPC codes into a fourth matrix of n1×n2, wherein the fourth matrix includes a fifth matrix of n1×k2 and a sixth matrix of n1×(n2-k2), the decoding result of each LDPC code includes k3 bits sequentially distributed in adjacent rows of the fifth matrix and n3-k3 check bits sequentially distributed in the sixth matrix and in the same row as the k3 bits, the fifth matrix includes a seventh matrix of k1×k2 and an eighth matrix of (n1-k1)×k2, the fifth matrix corresponds to t1 RS codes, each p column of the fifth matrix corresponds to one RS code, and each p column of the seventh matrix corresponds to k1 information symbols of the RS code, and each p column of the eighth matrix corresponds to n1-k1 check symbols of the RS code;

[0021] Verifying the decoding results of the t2 LDPC codes, and if all the verifications pass, outputting the decoding results of the t2 LDPC codes;

[0022] Wherein, k1, k2, k3, p, n1, n2, n3 are all positive integers, t1 = k2 / p, t2 = n1×k2 / k3, k2 <k3。

[0023] Optionally, the method further includes:

[0024] If the decoding result of any LDPC code fails the verification, the symbols corresponding to the t1 RS codes in the fifth matrix are decoded to obtain the decoding results of the t1 RS codes;

[0025] The decoding results of the t1 RS codes are verified, and if all the verifications pass or the current number of iterations has reached the maximum number of iterations, the decoding results of the t1 RS codes are output.

[0026] Optionally, the method further includes:

[0027] If the decoding result of any RS code fails to pass the verification and the current number of iterations does not reach the maximum number of iterations, the current number of iterations is increased by 1, and the corresponding soft information amount in the first matrix is ​​corrected according to the bits that pass the verification in the decoding result of the RS code, and then the soft information amounts corresponding to the t2 LDPC codes in the first matrix are respectively subjected to the next round of iterative decoding.

[0028] In a third aspect, an embodiment of the present application provides a product code encoding device, including a transceiver and a processor, wherein:

[0029] The processor is configured to:

[0030] Corresponding k1×p information bits of each p column in a k1×k2 information bit matrix to k1 information symbols of an RS code, encoding to generate n1-k1 check symbols, and concatenating them with the information bit matrix to obtain a first bit matrix of n1×k2, wherein each of the check symbols includes p bits;

[0031] Corresponding each k3 bits sequentially distributed in adjacent rows of the first bit matrix to one LDPC code, encoding to generate n3-k3 check bits, and sequentially splicing the n3-k3 check bits in the same row as the k3 bits to obtain a n1×n2 second bit matrix, wherein the second bit matrix includes t1 RS codes and t2 LDPC codes;

[0032] Wherein, k1, k2, k3, p, n1, n2, n3 are all positive integers, t1 = k2 / p, t2 = n1×k2 / k3, k2 <k3。

[0033] Optionally, each k3 information is bits distributed in the first bit matrix in an order from left to right and from top to bottom.

[0034] Optionally, the processor is further used to splice the n3-k3 check bits in the same row as each k3 bits in order from left to right and from top to bottom, wherein the total number of bits in each row after splicing is n2.

[0035] Optionally, the transceiver is used to send the second bit matrix.

[0036] In a fourth aspect, an embodiment of the present application provides a product code encoding device, comprising: a processor, a memory, and a program stored in the memory and executable on the processor, wherein the program, when executed by the processor, implements the steps of the method described in the first aspect.

[0037] In a fifth aspect, an embodiment of the present application provides a decoding device for a product code, including a transceiver and a processor, wherein:

[0038] The transceiver is used to receive a first matrix of n1×n2, wherein the first matrix includes a second matrix of n1×k2 and a third matrix of n1×(n2-k2), wherein the first matrix corresponds to t2 LDPC codes, each LDPC code corresponds to k3 soft information quantities sequentially distributed in adjacent rows of the second matrix, and n3-k3 soft information quantities sequentially distributed in the third matrix and in the same row as the k3 soft information quantities;

[0039] The processor is used to perform iterative decoding of the soft information corresponding to the t2 LDPC codes in the first matrix in the current iteration round, and splice the decoding results of the t2 LDPC codes into a fourth matrix of n1×n2, wherein the fourth matrix includes a fifth matrix of n1×k2 and a sixth matrix of n1×(n2-k2), and the decoding result of each LDPC code includes k3 bits sequentially distributed in adjacent rows of the fifth matrix and n3-k3 proofs sequentially distributed in the sixth matrix and in the same row as the k3 bits. The fifth matrix includes a seventh matrix of k1×k2 and an eighth matrix of (n1-k1)×k2, the fifth matrix corresponds to t1 RS codes, each p columns of the fifth matrix corresponds to an RS code, and each p columns in the seventh matrix correspond to k1 information symbols of the RS code, and each p columns in the eighth matrix correspond to n1-k1 check symbols of the RS code; the decoding results of the t2 LDPC codes are checked, and if all the checks pass, the decoding results of the t2 LDPC codes are output;

[0040] Wherein, k1, k2, k3, p, n1, n2, n3 are all positive integers, t1 = k2 / p, t2 = n1×k2 / k3, k2 <k3。

[0041] Optionally, the processor is further configured to decode symbols corresponding to t1 RS codes in the fifth matrix to obtain decoding results of t1 RS codes if the decoding result of any LDPC code fails verification;

[0042] The decoding results of the t1 RS codes are verified, and if all the verifications pass or the current number of iterations has reached the maximum number of iterations, the decoding results of the t1 RS codes are output.

[0043] Optionally, the processor is also used to increase the current number of iterations by 1 if the decoding result of any RS code fails to pass verification and the current number of iterations does not reach the maximum number of iterations, and correct the corresponding soft information amount in the first matrix based on the verified bits in the decoding result of the RS code, and then perform the next round of iterative decoding on the soft information amounts corresponding to the t2 LDPC codes in the first matrix.

[0044] In a sixth aspect, an embodiment of the present application provides a decoding device for a product code, comprising: a processor, a memory, and a program stored in the memory and executable on the processor, wherein the program, when executed by the processor, implements the steps of the method described in the second aspect.

[0045] In a seventh aspect, an embodiment of the present application provides a computer-readable storage medium, on which a program is stored. When the program is executed by a processor, the steps of the method described above are implemented.

[0046] Compared with the prior art, the encoding method, decoding method, device and storage medium of the product code provided in the embodiments of the present application can replace the original LDPC code with a shorter code length with an LDPC code with a longer code length and stronger error correction capability without increasing the codeword dimension of the product code during encoding; and use the product code iterative decoding algorithm during decoding, with better performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present application. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0048] Figure 1 The structure diagram of RS-LDPC product code of related technology;

[0049] Figure 2 A flow chart of a method for encoding a product code according to an embodiment of the present application;

[0050] Figure 3This is a diagram of the RS-LDPC product code structure obtained by encoding in an embodiment of the present application;

[0051] Figure 4 A flowchart of a decoding method of a product code according to an embodiment of the present application;

[0052] Figure 5 Another flow chart of the decoding method of the product code according to the embodiment of the present application;

[0053] Figure 6 This is a schematic diagram of the FER curve of the RS-LDPC product code under 16QAM of Example 1 of this application;

[0054] Figure 7 This is a schematic diagram of the FER curve of the RS-LDPC product code under 64QAM of Example 1 of this application;

[0055] Figure 8 This is a schematic diagram of the FER curve of the RS-LDPC product code under 16QAM of Example 2 of this application;

[0056] Fig. 9 This is a schematic diagram of the structure of a terminal according to an embodiment of the present application;

[0057] Fig.10 This is a schematic diagram of the structure of a terminal according to another embodiment of the present application;

[0058] Fig.11 A schematic diagram of the structure of a network device according to an embodiment of the present application;

[0059] Fig.12 A schematic diagram of the structure of a network device according to another embodiment of the present application;

[0060] Fig.13 This is a schematic diagram of the structure of a terminal according to another embodiment of the present application;

[0061] Fig.14 This is a schematic diagram of the structure of a network device according to another embodiment of the present application. DETAILED DESCRIPTION

[0062] The exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0063] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and need not be used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable in appropriate circumstances, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, the process, method, system, product or equipment comprising a series of steps or units need not be limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment. "And / or" in the specification and claims represents at least one of the connected objects.

[0064] The following description provides examples and does not limit the scope, applicability, or configuration set forth in the claims. Changes may be made to the functions and arrangements of the elements discussed without departing from the spirit and scope of the present disclosure. Various examples may appropriately omit, replace, or add various procedures or components. For example, the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. In addition, features described with reference to certain examples may be combined in other examples.

[0065] As described in the background technology, RS-LDPC product codes in the prior art are usually only suitable for using short codes. If LDPC codes with longer code lengths are used, the product code length will be too long, resulting in excessive transmission delays and excessive hardware resource consumption in practical applications. In addition, RS-LDPC product codes use a non-iterative decoding algorithm during decoding, and cannot use the information provided by the correct decoding results of the outer code, so there is still room for improvement in decoding performance.

[0066] To solve at least one of the above problems, an embodiment of the present application provides a method for encoding a product code, which can replace the original LDPC code with a shorter code length with an LDPC code with a longer code length and stronger error correction capability without increasing the codeword dimension of the product code.

[0067] Specifically, the embodiment of the present application replaces the LDPC code C2(n2,k2) in each row of the existing solution with the LDPC code C3(n3,k3) with the same code rate but longer code length. In the column direction, t1 RS codes C1(n1,k1) are still encoded, where the RS code is in the finite field GF(2 p ) is defined on the top. In the row direction, the existing scheme encodes n1 LDPC codes C2(n2,k2) codes, while in the embodiment of the present application, t2 LDPC codes C3(n3,k3) codes are encoded, and the information bit part satisfies t1×n1×p=t2×k3. The code rates of C2 and C3 are the same, that is, The code length of C3 is longer than that of C2. The total number of bits n1×n2=t2×n3.

[0068] Please refer to Figure 2 , the encoding method of the product code provided in the embodiment of the present application includes:

[0069] Step 21, correspond the k1×p information bits in each p columns of the k1×k2 information bit matrix to the k1 information symbol of an RS code, encode to generate n1-k1 check symbols, and concatenate them with the information bit matrix to obtain a first bit matrix of n1×k2, wherein each of the check symbols includes p bits.

[0070] Here, first, the outer code C1(n1, k1) of the RS-LDPC product code is encoded in step 21. Since the RS code is in the finite field GF(2 p ), so every p bits correspond to one symbol, and the k1×p information bits of each p column correspond to the k1 information symbols of an RS code, and the encoding generates n1-k1 check symbols to obtain the first bit matrix of n1×k2.

[0071] Step 22, correspond each k3 bits sequentially distributed in adjacent rows of the first bit matrix to one LDPC code, encode to generate n3-k3 check bits, and sequentially splice the n3-k3 check bits in the same row as the k3 bits to obtain a second bit matrix of n1×n2, wherein the second bit matrix includes t1 RS codes and t2 LDPC codes; wherein k1, k2, k3, p, n1, n2, and n3 are all positive integers, t1=k2 / p, t2=n1×k2 / k3, k2 <k3。

[0072] Here, the inner code encoding of the RS-LDPC product code is performed in step 22. The number of information bits of each LDPC code C3(n3,k3) is k3, and n3-k3 check bits are obtained by encoding. The information bits are distributed in adjacent information rows in sequence, and the check bits are also spliced ​​in sequence in the check rows with the same row number as the information row. In this way, after the encoding of t2 LDPC codes C3(n3,k3) is completed, an n1×n2 bit matrix is ​​obtained.

[0073] Specifically, each k3 information is a bit distributed in the first bit matrix in an order from left to right and from top to bottom. The above-mentioned sequential splicing of the n3-k3 check bits in the same row as each k3 bits is to splice the n3-k3 check bits in the same row as each k3 bits in an order from left to right and from top to bottom, wherein the total number of bits in each spliced ​​row is n2.

[0074] The RS-LDPC product code structure obtained by the above encoding method is as follows Figure 3 As shown, it can be seen that the dimension of the matrix is ​​the same as that obtained by the existing encoding method. The bold frame part in the figure represents an LDPC code C3(n3,k3). Each p column of the information bit part of the matrix is ​​an RS code C1(n1,k1) codeword, and there are t1 RS codes and t2 LDPC codes in total.

[0075] It can be seen that through the above steps, the embodiment of the present application can replace the original LDPC code with a shorter code length with an LDPC code with a longer code length and stronger error correction capability without increasing the codeword dimension of the product code.

[0076] After the encoding is completed, the embodiment of the present application may also send the second bit matrix obtained in step 22.

[0077] Based on the above encoding method, the embodiment of the present application also provides a decoding method of a product code, such as Figure 4 As shown, the method includes:

[0078] Step 41, receiving a first matrix of n1×n2, wherein the first matrix includes a second matrix of n1×k2 and a third matrix of n1×(n2-k2), wherein the first matrix corresponds to t2 LDPC codes, each LDPC code corresponds to k3 soft information quantities sequentially distributed in adjacent rows of the second matrix, and n3-k3 soft information quantities sequentially distributed in the third matrix and in the same row as the k3 soft information quantities.

[0079] Step 42, performing iterative decoding of the current iteration round on the soft information corresponding to the t2 LDPC codes in the first matrix, and splicing the decoding results of the t2 LDPC codes into a fourth matrix of n1×n2, wherein the fourth matrix includes a fifth matrix of n1×k2 and a sixth matrix of n1×(n2-k2), the decoding result of each LDPC code includes k3 bits sequentially distributed in adjacent rows of the fifth matrix and n3-k3 check bits sequentially distributed in the sixth matrix and in the same row as the k3 bits, the fifth matrix includes a seventh matrix of k1×k2 and an eighth matrix of (n1-k1)×k2, the fifth matrix corresponds to t1 RS codes, each p column of the fifth matrix corresponds to one RS code, and each p column of the seventh matrix corresponds to k1 information symbols of the RS code, and each p column of the eighth matrix corresponds to n1-k1 check symbols of the RS code;

[0080] Step 43, verifying the decoding results of the t2 LDPC codes, and if all the verifications pass, outputting the decoding results of the t2 LDPC codes;

[0081] Wherein, k1, k2, k3, p, n1, n2, n3 are all positive integers, t1 = k2 / p, t2 = n1×k2 / k3, k2 <k3。

[0082] In step 43, if any of the decoding results of the t2 LDPC codes fails to pass the verification, the symbols corresponding to the t1 RS codes in the fifth matrix are decoded to obtain the decoding results of the t1 RS codes. Then, the decoding results of the t1 RS codes are verified:

[0083] If all checks are passed or the current number of iterations has reached the maximum number of iterations, the decoding results of the t1 RS codes are output;

[0084] If the decoding result of any RS code fails to pass the verification and the current number of iterations does not reach the maximum number of iterations, the current number of iterations is increased by 1, and the corresponding soft information amount in the first matrix is ​​corrected according to the bits that pass the verification in the decoding result of the RS code, and then the process returns to step 42, and the soft information amounts corresponding to the t2 LDPC codes in the first matrix are respectively subjected to the next round of iterative decoding.

[0085] Here, according to the bit that has passed the check in the decoding result of the RS code, the corresponding soft information amount in the first matrix is ​​corrected, which can be specifically: when the value of the bit that has passed the check in the decoding result of the RS code is 0, the soft information amount corresponding to the bit in the first matrix is ​​corrected to the product of a first constant and the absolute value of the soft information amount; when the value of the bit that has passed the check in the decoding result of the RS code is 1, the soft information amount corresponding to the bit in the first matrix is ​​corrected to the product of a second constant and the absolute value of the soft information amount. The first constant is a preset positive number greater than 1, and the second constant is a preset negative number less than -1.

[0086] Figure 5 Another flow chart of the above decoding process is provided, which mainly includes:

[0087] Step 1: First, perform LDPC code decoding. Decode t2 LDPC codes separately: calculate the channel soft quantity L, use the BP decoding algorithm, and use O to calculate the (soft) information quantity of the decoded output. k t2 LDPC code hard decision results are concatenated together to form an n1×n2 matrix, and y LDPC express.

[0088] Step 2: y LDPC Verify. Verify the decoding results of t2 LDPC codes respectively. If they all meet the verification formula of the LDPC code, output the decoding results and end the decoding. If not, perform RS decoding.

[0089] Step 3: Decode the RS code and convert the information bits of the LDPC code output, i.e. the first k2 columns, to the finite field GF(2 p ) to obtain the corresponding k2 / p RS code input information, decode the mapped information into RS code, use BM algorithm for decoding, and use y RS express.

[0090] Step 4: y RS Perform a check. If the check is satisfied or the maximum number of iterations IT is reached, the decoding result is output and the decoding is ended. Otherwise, go to step 5.

[0091] Step 5: y RS The part that meets the checksum is considered to be the correct information record, and the input information of the LDPC code is corrected according to this part of information in the next iteration. Thereby improving the decoding performance. A possible modification is as follows:

[0092]

[0093] Among them, i, j represent the codeword matrix y LDPC The row and column numbers in , 0≤i≤n1-1,0≤j≤k2-1.

[0094] represents the amount of soft information O obtained in the k-1th round of iterative decoding k-1 The rows and columns are the elements of i and j respectively. In the above formula, the first constant is 10, and the second constant is -10.

[0095] The method of the embodiment of the present application is further described below with reference to examples and simulation results.

[0096] Example 1: Use RS(63,57) code and 5G-LDPC(576,288) code to construct RS-LDPC product code. RS(63,57) code is defined on finite field GF(26), and every 6 bits corresponds to one symbol, that is, every 6 columns constitute an RS(63,57) code. 5G-LDPC(576,288) code is defined on GF(2), and each row constitutes a 5G-LDPC(576,288) code. The existing RS-LDPC product code encoding method is used for encoding. The final encoded RS-LDPC product code has 48 RS(63,57) codes in the column direction and 63 5G-LDPC(576,288) codes in the row direction. When encoding using the RS-LDPC product code encoding method of the embodiment of the present application, 5G-LDPC (12096, 6048) codes are used in the row direction, and the RS-LDPC product code still has 48 RS (63, 57) codes in the column direction and 3 5G-LDPC (12096, 6048) codes in the row direction. Without changing the overall dimension of the RS-LDPC product code, the original short LDPC code is replaced with a long LDPC code with a longer code length and stronger error correction capability, which can significantly improve the decoding performance of the RS-LDPC product code.

[0097] The inventor simulated the decoding performance of RS-LDPC product codes under different modulation modes. Simulation parameters: 16QAM / 64QAM modulation; RS code adopts BM decoding algorithm; LDPC code adopts BP decoding algorithm, and the number of iterations is 30.

[0098] Among them, under 16QAM, the existing RS-LDPC product code encoding method and the RS-LDPC product code encoding method proposed in the embodiment of the present application are used for encoding. The FER performance curve of the RS-LDPC product code is as follows: Figure 6 As shown in the figure, when the non-iterative decoding algorithm is used for product code decoding, the FER@10 -3At, the performance gain of the product code constructed using the LDPC (12096, 6048) code can reach a maximum of about 0.9dB compared with the product code constructed using the LDPC (576, 288) code. In addition, using the product code iterative decoding algorithm for decoding, setting the maximum number of iterations to IT = 2, can further obtain a 0.2dB gain. In addition, the inventors also simulated the performance of multi-code block transmission 5G-LDPC codes in the 5G standard with a code length similar to that of the RS-LDPC product code, TBsize = 18432, the number of code blocks CB = 3, and each code block is an LDPC (12288, 6144) codeword. The performance of the RS-LDPC product code encoded using the RS-LDPC product code encoding method proposed in the embodiment of the present application is slightly better than the performance of the multi-code block transmission 5G-LDPC code, and the performance of the RS-LDPC product code using the iterative decoding algorithm is about 0.2dB better than the performance of the multi-code block transmission 5G-LDPC code.

[0099] Under 64QAM, the existing RS-LDPC product code encoding method and the RS-LDPC product code encoding method of the embodiment of the present application are used for encoding. The FER performance curve of the RS-LDPC product code is as follows: Figure 7 As shown in the figure, when the non-iterative decoding algorithm is used for product code decoding, the FER@10 -2 At, the performance gain of the product code constructed using the LDPC (12096, 6048) code can reach a maximum of about 1.0dB compared with the product code constructed using the LDPC (576, 288) code. In addition, using the product code iterative decoding algorithm for decoding, setting the maximum number of iterations to IT = 2, can further obtain a 0.25dB gain. The inventors also simulated the performance of multi-code block transmission 5G-LDPC codes in the 5G standard with a code length similar to that of the RS-LDPC product code, TBsize = 18432, the number of code blocks CB = 3, and each code block is an LDPC (12288, 6144) codeword. The performance of the RS-LDPC product code encoded using the RS-LDPC product code encoding method of the embodiment of the present application is slightly better than that of the multi-code block transmission 5G-LDPC code, and the performance of the RS-LDPC product code using the iterative decoding algorithm is about 0.25dB better than the performance of the multi-code block transmission 5G-LDPC code.

[0100] Example 2: Use RS(255,247) code and 5G-LDPC(576,288) code to construct RS-LDPC product code. RS(255,247) code is defined on finite field GF(28), and every 8 bits corresponds to one symbol, that is, every 8 columns constitute an RS(255,247) code. 5G-LDPC(576,288) code is defined on GF(2), and every row constitutes a 5G-LDPC(576,288) code. The existing RS-LDPC product code encoding method is used for encoding. The final encoded RS-LDPC product code has 36 RS(255,247) codes in the column direction and 255 5G-LDPC(576,288) codes in the row direction. When encoding using the RS-LDPC product code encoding method of the embodiment of the present application, 5G-LDPC (2880, 1440) code and 5G-LDPC (9792, 4896) code are used in the row direction respectively, and the RS-LDPC product code still has 36 RS (255, 247) codes in the column direction. When using the 5G-LDPC (2880, 1440) code, there are 51 5G-LDPC (2880, 1440) codes in the row direction of the product code. When using the 5G-LDPC (9792, 4896) code, there are 15 5G-LDPC (9792, 4896) codes in the row direction of the product code. Without changing the overall dimension of the RS-LDPC product code, replacing the original short LDPC code with a long LDPC code with a longer code length and stronger error correction capability can significantly improve the decoding performance of the RS-LDPC product code.

[0101] The inventor simulated the decoding performance of RS-LDPC product code under 16QAM modulation mode. Simulation parameters: 16QAM modulation; RS code adopts BM decoding algorithm; LDPC code adopts BP decoding algorithm, and the number of iterations is 30.

[0102] The inventors used the existing RS-LDPC product code encoding method and the RS-LDPC product code encoding method of the embodiment of the present application for encoding, and compared the performance of the RS-LDPC product code with an LDPC code block of the same dimension, where the LDPC code block consists of 255 LDPC codes arranged without RS code encoding. The FER performance curve of the RS-LDPC product code is shown in Figure 1. Figure 8 As shown in the figure, the performance of the product code constructed using the LDPC (576, 288) code is about 0.9 dB better than that of the LDPC code block of the same dimension. When both use the non-iterative decoding algorithm to decode the product code, the FER@10 -3At , the performance gain of the product code constructed by using LDPC (2880, 1440) code can reach about 0.5dB compared with the product code constructed by using LDPC (576, 288) code. The performance gain of the product code constructed by using LDPC (9792, 4896) code can reach about 1.1dB compared with the product code constructed by using LDPC (576, 288) code. In addition, using the product code iterative decoding algorithm for decoding, setting the maximum number of iterations to IT = 2, can further obtain a 0.2dB gain.

[0103] From the above, it can be seen that the product code obtained by the existing RS-LDPC product code encoding method arranges one LDPC code in each row in the row direction, which is only suitable for using short codes. If an LDPC code with a longer code length is used, it will lead to the disadvantage that the product code length is too long. The embodiment of the present application arranges a long LDPC code into multiple rows, and replaces the original LDPC code with a shorter code length with an LDPC code with a longer code length and stronger error correction capability without increasing the codeword dimension of the product code. It can realize generalized row and column interleaving according to non-integer row splicing, which is a generalization of serial cascade or conventional row and column RS-LDPC code product cascade. It can realize the integration of 5G transmission and the generalized product cascade of multiple large-block long 5G-LDPC codes.

[0104] In addition, the existing RS-LDPC product code uses a non-iterative decoding algorithm during decoding, and cannot use the information provided by the correct decoding result of the outer code, and there is still room for improvement in decoding performance. The embodiment of the present application corrects the input soft amount of the next iterative LDPC code according to the decoding result of the RS code, and has a maximum gain of about 1.0dB compared to the existing solution.

[0105] In summary, compared with the existing RS-LDPC product code encoding and decoding technology, the embodiments of the present application can replace the original LDPC code with a shorter code length with an LDPC code with a longer code length and stronger error correction capability during encoding without increasing the codeword dimension of the product code; and use the product code iterative decoding algorithm during decoding, with better performance.

[0106] The above describes various methods of the embodiments of the present application. The following further provides devices for implementing the above methods.

[0107] Please refer to Fig. 9 , the embodiment of the present application further provides a product code encoding device, comprising:

[0108] A first encoding module 91 is used to encode the k1×p information bits of each p column in the k1×k2 information bit matrix to correspond to the k1 information symbol of an RS code, generate n1-k1 check symbols, and concatenate them with the information bit matrix to obtain a first bit matrix of n1×k2, wherein each of the check symbols includes p bits;

[0109] A second encoding module 92 is used to correspond every k3 bits sequentially distributed in adjacent rows of the first bit matrix to one LDPC code, encode to generate n3-k3 check bits, and sequentially splice the n3-k3 check bits in the same row as the k3 bits to obtain a second bit matrix of n1×n2, wherein the second bit matrix includes t1 RS codes and t2 LDPC codes;

[0110] Wherein, k1, k2, k3, p, n1, n2, n3 are all positive integers, t1 = k2 / p, t2 = n1×k2 / k3, k2 <k3。

[0111] Optionally, each k3 information is bits distributed in the first bit matrix in an order from left to right and from top to bottom.

[0112] Optionally, sequentially splicing the n3-k3 check bits in the same row as each k3 bits includes:

[0113] In order from left to right and from top to bottom, the n3-k3 check bits are spliced ​​in the same row as each k3 bits, wherein the total number of bits in each row after splicing is n2.

[0114] Optionally, the encoding device further includes:

[0115] A sending module is used to send the second bit matrix.

[0116] It should be noted that the device in this embodiment is a device corresponding to the above-mentioned encoding method, and the implementation methods in the above-mentioned embodiments are all applicable to the embodiments of the device, and can also achieve the same technical effects. The above-mentioned device provided in the embodiment of the present application can implement all the method steps implemented in the above-mentioned method embodiment, and can achieve the same technical effects, and the parts and beneficial effects that are the same as those in the method embodiment in this embodiment will not be specifically repeated here.

[0117] Please refer to Fig.10 , the embodiment of the present application further provides a terminal 1000, including: a transceiver 1001 and a processor 1002;

[0118] The processor 802 is configured to:

[0119] Corresponding k1×p information bits of each p column in a k1×k2 information bit matrix to k1 information symbols of an RS code, encoding to generate n1-k1 check symbols, and concatenating them with the information bit matrix to obtain a first bit matrix of n1×k2, wherein each of the check symbols includes p bits;

[0120] Corresponding each k3 bits sequentially distributed in adjacent rows of the first bit matrix to one LDPC code, encoding to generate n3-k3 check bits, and sequentially splicing the n3-k3 check bits in the same row as the k3 bits to obtain a n1×n2 second bit matrix, wherein the second bit matrix includes t1 RS codes and t2 LDPC codes;

[0121] Wherein, k1, k2, k3, p, n1, n2, n3 are all positive integers, t1 = k2 / p, t2 = n1×k2 / k3, k2 <k3。

[0122] Optionally, each k3 information is bits distributed in the first bit matrix in an order from left to right and from top to bottom.

[0123] Optionally, the above-mentioned processor is also used to splice the n3-k3 check bits in the same row as each k3 bits in order from left to right and from top to bottom, wherein the total number of bits in each row after splicing is n2.

[0124] Optionally, the transceiver 801 is used to send the second bit matrix.

[0125] It should be noted that the device in this embodiment is a device corresponding to the above-mentioned encoding method, and the implementation methods in the above-mentioned embodiments are all applicable to the embodiments of the device, and can also achieve the same technical effects. The above-mentioned device provided in the embodiment of the present application can implement all the method steps implemented in the above-mentioned method embodiment, and can achieve the same technical effects, and the parts and beneficial effects that are the same as those in the method embodiment in this embodiment will not be specifically repeated here.

[0126] Please refer to Fig.11 , the embodiment of the present application further provides a decoding device for a product code, comprising:

[0127] A first receiving module 111 is used to receive a first matrix of n1×n2, wherein the first matrix includes a second matrix of n1×k2 and a third matrix of n1×(n2-k2), wherein the first matrix corresponds to t2 LDPC codes, each LDPC code corresponds to k3 soft information quantities sequentially distributed in adjacent rows of the second matrix, and n3-k3 soft information quantities sequentially distributed in the third matrix and in the same row as the k3 soft information quantities;

[0128] The first decoding module 112 is used to perform iterative decoding of the soft information corresponding to the t2 LDPC codes in the first matrix in the current iteration round, and splice the decoding results of the t2 LDPC codes into a fourth matrix of n1×n2, wherein the fourth matrix includes a fifth matrix of n1×k2 and a sixth matrix of n1×(n2-k2), the decoding result of each LDPC code includes k3 bits sequentially distributed in adjacent rows of the fifth matrix and n3-k3 check bits sequentially distributed in the sixth matrix and in the same row as the k3 bits, the fifth matrix includes a seventh matrix of k1×k2 and an eighth matrix of (n1-k1)×k2, the fifth matrix corresponds to t1 RS codes, each p column of the fifth matrix corresponds to an RS code, and each p column of the seventh matrix corresponds to k1 information symbols of the RS code, and each p column of the eighth matrix corresponds to n1-k1 check symbols of the RS code;

[0129] A first verification module 113 is used to verify the decoding results of the t2 LDPC codes, and output the decoding results of the t2 LDPC codes if all the verifications pass;

[0130] Wherein, k1, k2, k3, p, n1, n2, n3 are all positive integers, t1 = k2 / p, t2 = n1×k2 / k3, k2 <k3。

[0131] Optionally, the decoding device further includes:

[0132] A second decoding module is used for decoding symbols corresponding to t1 RS codes in the fifth matrix to obtain decoding results of t1 RS codes if the decoding result of any LDPC code fails the verification;

[0133] The second verification module is used to verify the decoding results of the t1 RS codes, and output the decoding results of the t1 RS codes if all the verifications pass or the current iteration number has reached the maximum iteration number.

[0134] Optionally, the decoding device further includes:

[0135] An iteration module is used to increase the current iteration number by 1 if the decoding result of any RS code fails to pass the verification and the current iteration number does not reach the maximum iteration number, and to correct the corresponding soft information amount in the first matrix according to the verified bits in the decoding result of the RS code, and then perform the next round of iterative decoding on the soft information amounts corresponding to the t2 LDPC codes in the first matrix.

[0136] It should be noted that the device in this embodiment is a device corresponding to the above decoding method, and the implementation methods in the above embodiments are all applicable to the embodiments of the device, and can also achieve the same technical effects. The above device provided in the embodiment of the present application can implement all the method steps implemented in the above method embodiment, and can achieve the same technical effects, and the parts and beneficial effects that are the same as those in the method embodiment in this embodiment will not be specifically described here.

[0137] Please refer to Fig.12 , the embodiment of the present application further provides a network device 1200, including: a transceiver 1201 and a processor 1202;

[0138] The transceiver 1201 is configured to receive a first matrix of n1×n2, wherein the first matrix includes a second matrix of n1×k2 and a third matrix of n1×(n2-k2), wherein the first matrix corresponds to t2 LDPC codes, each LDPC code corresponds to k3 soft information quantities sequentially distributed in adjacent rows of the second matrix, and n3-k3 soft information quantities sequentially distributed in the third matrix and in the same row as the k3 soft information quantities;

[0139] The processor 1202 is configured to:

[0140] Performing iterative decoding of the current iteration round on the soft information corresponding to the t2 LDPC codes in the first matrix, respectively, and splicing the decoding results of the t2 LDPC codes into a fourth matrix of n1×n2, wherein the fourth matrix includes a fifth matrix of n1×k2 and a sixth matrix of n1×(n2-k2), the decoding result of each LDPC code includes k3 bits sequentially distributed in adjacent rows of the fifth matrix and n3-k3 check bits sequentially distributed in the sixth matrix and in the same row as the k3 bits, the fifth matrix includes a seventh matrix of k1×k2 and an eighth matrix of (n1-k1)×k2, the fifth matrix corresponds to t1 RS codes, each p column of the fifth matrix corresponds to one RS code, and each p column of the seventh matrix corresponds to k1 information symbols of the RS code, and each p column of the eighth matrix corresponds to n1-k1 check symbols of the RS code;

[0141] Verifying the decoding results of the t2 LDPC codes, and if all the verifications pass, outputting the decoding results of the t2 LDPC codes;

[0142] Wherein, k1, k2, k3, p, n1, n2, n3 are all positive integers, t1 = k2 / p, t2 = n1×k2 / k3, k2 <k3。

[0143] The processor 1202 is further configured to:

[0144] If the decoding result of any LDPC code fails the verification, the symbols corresponding to the t1 RS codes in the fifth matrix are decoded to obtain the decoding results of the t1 RS codes;

[0145] The decoding results of the t1 RS codes are verified, and if all the verifications pass or the current number of iterations has reached the maximum number of iterations, the decoding results of the t1 RS codes are output.

[0146] The processor 1202 is further configured to:

[0147] If the decoding result of any RS code fails to pass the verification and the current number of iterations does not reach the maximum number of iterations, the current number of iterations is increased by 1, and the corresponding soft information amount in the first matrix is ​​corrected according to the bits that pass the verification in the decoding result of the RS code, and then the soft information amounts corresponding to the t2 LDPC codes in the first matrix are respectively subjected to the next round of iterative decoding.

[0148] It should be noted that the device in this embodiment is a device corresponding to the above decoding method, and the implementation methods in the above embodiments are all applicable to the embodiments of the device, and can also achieve the same technical effects. The above device provided in the embodiment of the present application can implement all the method steps implemented in the above method embodiment, and can achieve the same technical effects, and the parts and beneficial effects that are the same as those in the method embodiment in this embodiment will not be specifically described here.

[0149] Please refer to Fig.13 The embodiment of the present application also provides a coding device 1300, including a processor 1301, a memory 1302, and a computer program stored in the memory 1302 and executable on the processor 1301. When the computer program is executed by the processor 1301, each process of the above-mentioned product code coding method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be described here.

[0150] Please refer to Fig.14 The embodiment of the present application also provides a network device 1400, including a processor 1401, a memory 1402, and a computer program stored in the memory 1402 and executable on the processor 1401. When the computer program is executed by the processor 1401, each process of the above-mentioned product code decoding method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be described here.

[0151] The embodiment of the present application also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, each process of the above-mentioned product code encoding method and decoding method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it is not repeated here. Among them, the computer-readable storage medium is such as a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, etc.

[0152] It should be noted that, in this article, the terms "include", "include" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0153] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0154] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A method for encoding a product code, characterized in that: include: Corresponding k1×p information bits of each p column in a k1×k2 information bit matrix to k1 information symbols of an RS code, encoding to generate n1-k1 check symbols, and concatenating them with the information bit matrix to obtain a first bit matrix of n1×k2, wherein each of the check symbols includes p bits; Corresponding each k3 bits sequentially distributed in adjacent rows of the first bit matrix to one LDPC code, encoding to generate n3-k3 check bits, and sequentially splicing the n3-k3 check bits in the same row as the k3 bits to obtain a n1×n2 second bit matrix, wherein the second bit matrix includes t1 RS codes and t2 LDPC codes; Wherein, k1, k2, k3, p, n1, n2, n3 are all positive integers, t1 = k2 / p, t2 = n1×k2 / k3, k2 <k3。 2. The method according to claim 1, characterized in that Each k3 information is bits distributed in the first bit matrix in a sequence from left to right and from top to bottom.

3. The method according to claim 2, characterized in that Sequentially splicing the n3-k3 check bits in the same row as each k3 bits, comprising: In order from left to right and from top to bottom, the n3-k3 check bits are spliced ​​in the same row as each k3 bits, wherein the total number of bits in each row after splicing is n2.

4. The method according to claim 1, characterized in that Also includes: The second bit matrix is ​​transmitted.

5. A method for decoding a product code, characterized in that: include: Receive a first matrix of n1×n2, the first matrix including a second matrix of n1×k2 and a third matrix of n1×(n2-k2), the first matrix corresponding to t2 LDPC codes, each LDPC code corresponding to k3 soft information quantities sequentially distributed in adjacent rows of the second matrix, and n3-k3 soft information quantities sequentially distributed in the third matrix and in the same row as the k3 soft information quantities; Performing iterative decoding of the current iteration round on the soft information corresponding to the t2 LDPC codes in the first matrix, respectively, and splicing the decoding results of the t2 LDPC codes into a fourth matrix of n1×n2, wherein the fourth matrix includes a fifth matrix of n1×k2 and a sixth matrix of n1×(n2-k2), the decoding result of each LDPC code includes k3 bits sequentially distributed in adjacent rows of the fifth matrix and n3-k3 check bits sequentially distributed in the sixth matrix and in the same row as the k3 bits, the fifth matrix includes a seventh matrix of k1×k2 and an eighth matrix of (n1-k1)×k2, the fifth matrix corresponds to t1 RS codes, each p column of the fifth matrix corresponds to one RS code, and each p column of the seventh matrix corresponds to k1 information symbols of the RS code, and each p column of the eighth matrix corresponds to n1-k1 check symbols of the RS code; Verifying the decoding results of the t2 LDPC codes, and if all the verifications pass, outputting the decoding results of the t2 LDPC codes; Wherein, k1, k2, k3, p, n1, n2, n3 are all positive integers, t1 = k2 / p, t2 = n1×k2 / k3, k2 <k3。 6. The method according to claim 5, characterized in that Also includes: If the decoding result of any LDPC code fails the verification, the symbols corresponding to the t1 RS codes in the fifth matrix are decoded to obtain the decoding results of the t1 RS codes; The decoding results of the t1 RS codes are verified, and if all the verifications pass or the current number of iterations has reached the maximum number of iterations, the decoding results of the t1 RS codes are output.

7. The method according to claim 6, characterized in that Also includes: If the decoding result of any RS code fails to pass the verification and the current number of iterations does not reach the maximum number of iterations, the current number of iterations is increased by 1, and the corresponding soft information amount in the first matrix is ​​corrected according to the bits that pass the verification in the decoding result of the RS code, and then the soft information amounts corresponding to the t2 LDPC codes in the first matrix are respectively subjected to the next round of iterative decoding.

8. A product code encoding device, characterized in that: comprising a transceiver and a processor, wherein: The processor is configured to: Corresponding k1×p information bits of each p column in a k1×k2 information bit matrix to k1 information symbols of an RS code, encoding to generate n1-k1 check symbols, and concatenating them with the information bit matrix to obtain a first bit matrix of n1×k2, wherein each of the check symbols includes p bits; Corresponding each k3 bits sequentially distributed in adjacent rows of the first bit matrix to one LDPC code, encoding to generate n3-k3 check bits, and sequentially splicing the n3-k3 check bits in the same row as the k3 bits to obtain a n1×n2 second bit matrix, wherein the second bit matrix includes t1 RS codes and t2 LDPC codes; Wherein, k1, k2, k3, p, n1, n2, n3 are all positive integers, t1 = k2 / p, t2 = n1×k2 / k3, k2 <k3。 9. The device according to claim 8, characterized in that Each k3 information is bits distributed in the first bit matrix in a sequence from left to right and from top to bottom.

10. The device according to claim 9, characterized in that The processor is further configured to splice the n3-k3 check bits in the same row as each k3 bits in order from left to right and from top to bottom, wherein the total number of bits in each spliced ​​row is n2.

11. The device according to claim 8, characterized in that The transceiver is used to send the second bit matrix.

12. A product code encoding device, characterized in that: include: A processor, a memory, and a program stored in the memory and executable on the processor, wherein the program implements the steps of the method according to any one of claims 1 to 4 when executed by the processor.

13. A decoding device for a product code, characterized in that: comprising a transceiver and a processor, wherein: The transceiver is used to receive a first matrix of n1×n2, wherein the first matrix includes a second matrix of n1×k2 and a third matrix of n1×(n2-k2), wherein the first matrix corresponds to t2 LDPC codes, each LDPC code corresponds to k3 soft information quantities sequentially distributed in adjacent rows of the second matrix, and n3-k3 soft information quantities sequentially distributed in the third matrix and in the same row as the k3 soft information quantities; The processor is used to perform iterative decoding of the soft information corresponding to the t2 LDPC codes in the first matrix in the current iteration round, and splice the decoding results of the t2 LDPC codes into a fourth matrix of n1×n2, wherein the fourth matrix includes a fifth matrix of n1×k2 and a sixth matrix of n1×(n2-k2), and the decoding result of each LDPC code includes k3 bits sequentially distributed in adjacent rows of the fifth matrix and n3-k3 proofs sequentially distributed in the sixth matrix and in the same row as the k3 bits. The fifth matrix includes a seventh matrix of k1×k2 and an eighth matrix of (n1-k1)×k2, the fifth matrix corresponds to t1 RS codes, each p columns of the fifth matrix corresponds to an RS code, and each p columns in the seventh matrix correspond to k1 information symbols of the RS code, and each p columns in the eighth matrix correspond to n1-k1 check symbols of the RS code; the decoding results of the t2 LDPC codes are checked, and if all the checks pass, the decoding results of the t2 LDPC codes are output; Wherein, k1, k2, k3, p, n1, n2, n3 are all positive integers, t1 = k2 / p, t2 = n1×k2 / k3, k2 <k3。 14. The device according to claim 13, characterized in that The processor is further configured to decode symbols corresponding to t1 RS codes in the fifth matrix to obtain decoding results of t1 RS codes if the decoding result of any LDPC code fails verification; The decoding results of the t1 RS codes are verified, and if all the verifications pass or the current number of iterations has reached the maximum number of iterations, the decoding results of the t1 RS codes are output.

15. The device according to claim 14, characterized in that The processor is also used to increase the current number of iterations by 1 if the decoding result of any RS code fails to pass the verification and the current number of iterations does not reach the maximum number of iterations, and correct the corresponding soft information amount in the first matrix according to the bits that pass the verification in the decoding result of the RS code, and then perform the next round of iterative decoding on the soft information amounts corresponding to the t2 LDPC codes in the first matrix.

16. A decoding device for a product code, characterized in that: include: A processor, a memory, and a program stored in the memory and executable on the processor, wherein when the program is executed by the processor, the steps of the method according to any one of claims 5 to 7 are implemented.

17. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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