Turbo encoding equipment and decoding equipment based on FPGA (Field Programmable Gate Array)

Abstract

The invention belongs to the technical field of data link communication, and particularly discloses a Turbo coding device and decoding device based on an FPGA, and the FPGA of the Turbo coding device is provided with a main control module, a first memory, an interleaving module, a first RSC coding module, a second RSC coding module and a puncturing multiplexing module. A sequence separation module, an iterative decoding module and a main control module are configured on an FPGA (Field Programmable Gate Array) of the Turbo decoding equipment. According to the invention, turbo coding and decoding can be realized based on the FPGA, and by adopting the turbo coding and decoding equipment provided by the invention, the information processing capability of the system can be improved, and meanwhile, the system can be ensured to obtain better bit error rate performance; according to the method, the structure is simple, hardware description language Verilog language can be used, a hardware environment can be built for implementation, and the practicability is high.

Description

Technical Field

[0001] The present application belongs to the field of data link communication technology, and more specifically, to a FPGA-based Turbo encoding device and decoding device. Background Art

[0002] With the continuous development of communication technology, in the field of data links, physical layer communication technology has also attracted more and more widespread attention, especially in information processing. Different information processing methods are different. Information processing content generally includes three aspects of processing: information verification, channel error correction coding and channel interleaving.

[0003] Among them, channel error correction coding is the key to ensure that the information transmission rate is close to the ideal channel capacity. At present, in the field of data link communication technology, in order to ensure that the system has a good bit error rate performance, channel coding and decoding technology is often implemented by turbo coding and decoding. How to implement turbo coding and decoding based on field programmable gate array (FPGA) is a technical problem that needs to be solved urgently in this field. Summary of the invention

[0004] In view of the defects of the prior art, the purpose of this application is to implement turbo encoding and decoding based on FPGA.

[0005] To achieve the above-mentioned purpose, in a first aspect, the present application provides a Turbo coding device based on FPGA, wherein a main control module, a first memory (Meg_RAM), an interleaving module, a first RSC coding module, a second RSC coding module and a puncturing multiplexing module are configured on the FPGA of the Turbo coding device;

[0006] The first memory is used to cache the first information sequence (C k );

[0007] The interleaving module is used to cache the first information sequence, and based on the interleaving address, interleave the first information sequence to obtain the second information sequence (C′ k );

[0008] The first RSC encoding module is used to read the first information sequence from the first memory, and perform Turbo encoding based on the first information sequence to obtain a first system sequence (X k ) and the first check sequence (Z k );

[0009] The second RSC encoding module is used to read the second information sequence from the interleaving module, and perform Turbo encoding based on the second information sequence to obtain a second system sequence (X′ k ) and the second check sequence (Z′ k );

[0010] The puncturing and multiplexing module is used to perform puncturing and multiplexing processing based on the first system sequence, the first check sequence, the second system sequence and the second check sequence to obtain a Turbo coding result;

[0011] The main control module is used to control the working status of each encoding module and control the read and write addresses of each memory in this device.

[0012] In a possible implementation, the interleaving module includes a second memory (ROM) and a third memory (RAM_0);

[0013] The second memory is used for storing the interleaved address;

[0014] The third memory is used to cache the first information sequence, and to perform interleaving mapping on the first information sequence according to the interleaving address to obtain the second information sequence.

[0015] In a possible implementation, the puncturing multiplexing module includes a fourth memory (RAM_1) for caching the first system sequence, a fifth memory (RAM_2) for caching the first check sequence, a sixth memory (RAM_3) for caching the second system sequence, a seventh memory (RAM_4) for caching the second check sequence, and a puncturing multiplexing unit;

[0016] The puncturing and multiplexing unit is used to read the first system sequence, the first check sequence, the second system sequence and the second check sequence from the fourth memory, the fifth memory, the sixth memory and the seventh memory, and perform puncturing and multiplexing on the read sequences to obtain Turbo coding results.

[0017] In a second aspect, the present application provides a Turbo coding method, which is applied to the FPGA-based Turbo coding device described in the first aspect or any possible implementation of the first aspect, and the method includes:

[0018] Acquiring a first information sequence;

[0019] Based on the interleaving address, interleave mapping is performed on the first information sequence to obtain a second information sequence;

[0020] Encoding based on the first information sequence to obtain a first system sequence and a first check sequence; and encoding based on the second information sequence to obtain a second system sequence and a second check sequence;

[0021] Based on the first system sequence, the first check sequence, the second system sequence and the second check sequence, puncturing processing and multiplexing processing are performed to obtain a Turbo coding result.

[0022] In a third aspect, the present application provides a Turbo decoding device based on FPGA, wherein a sequence separation module (decoder_algorithm module), an iterative decoding module (decoder_maxlogmap module) and a main control module are configured on the FPGA of the Turbo decoding device;

[0023] The sequence separation module is used for receiving a third information sequence to be decoded, separating a system sequence and a check sequence from the received third information sequence, and outputting the system sequence and the check sequence to the iterative decoding module;

[0024] The iterative decoding module is used to perform SISO iterative decoding based on the system sequence, the check sequence and the prior information to obtain the Turbo decoding result;

[0025] The main control module is used to control the working status of each decoding module and control the read and write addresses of each memory in this device.

[0026] In a possible implementation, the SISO iterative decoding specifically adopts the Max-Log-MAP algorithm.

[0027] In a fourth aspect, the present application provides a Turbo decoding method, which is applied to the FPGA-based Turbo decoding device described in the third aspect or any possible implementation of the third aspect, and the method includes:

[0028] Acquire a third information sequence to be decoded;

[0029] separating a systematic sequence and a check sequence from a third information sequence;

[0030] Based on the system sequence, check sequence and prior information, SISO iterative decoding is performed to obtain the Turbo decoding result.

[0031] In a fifth aspect, the present application also provides an FPGA-based encoding and decoding system, which includes: an FPGA-based Turbo encoding device and an FPGA-based Turbo decoding device, the Turbo encoding device and the Turbo decoding device are communicatively connected, and an encoding and decoding process of information bits is implemented through the Turbo encoding device and the Turbo decoding device.

[0032] The Turbo coding device is specifically used to: obtain a first information sequence; based on the interleaving address, interleave and map the first information sequence to obtain a second information sequence; encode based on the first information sequence to obtain a first system sequence and a first check sequence; and encode based on the second information sequence to obtain a second system sequence and a second check sequence; perform puncturing and multiplexing based on the first system sequence, the first check sequence, the second system sequence, and the second check sequence to obtain a Turbo coding result;

[0033] The Turbo decoding device is specifically used for: obtaining a third information sequence to be decoded; separating a system sequence and a check sequence from the third information sequence; performing SISO iterative decoding based on the system sequence, the check sequence and prior information to obtain a Turbo decoding result.

[0034] In a possible implementation, a main control module, a first memory, an interleaving module, a first RSC encoding module, a second RSC encoding module and a puncturing multiplexing module are configured on the FPGA of the Turbo encoding device;

[0035] The first memory is used to cache the first information sequence;

[0036] The interleaving module is used to cache the first information sequence, and based on the interleaving address, perform interleaving mapping on the first information sequence to obtain a second information sequence;

[0037] The first RSC encoding module is used to read the first information sequence from the first memory, and perform encoding based on the first information sequence to obtain a first system sequence and a first check sequence;

[0038] The second RSC encoding module is used to read the second information sequence from the interleaving module, and encode based on the second information sequence to obtain a second system sequence and a second check sequence;

[0039] The puncturing and multiplexing module is used to perform puncturing and multiplexing processing based on the first system sequence, the first check sequence, the second system sequence and the second check sequence to obtain a Turbo coding result;

[0040] The main control module is used to control the working status of each encoding module and control the read and write addresses of each memory in this device.

[0041] In a possible implementation, a sequence separation module, an iterative decoding module and a main control module are configured on the FPGA of the turbo decoding device;

[0042] The sequence separation module is used for receiving a third information sequence to be decoded, separating a system sequence and a check sequence from the received third information sequence, and outputting the system sequence and the check sequence to the iterative decoding module;

[0043] The iterative decoding module is used to perform SISO iterative decoding based on the system sequence, the check sequence and the prior information to obtain the Turbo decoding result;

[0044] The main control module is used to control the working status of each decoding module and control the read and write addresses of each memory in this device.

[0045] In general, the above technical solutions conceived by this application have the following beneficial effects compared with the prior art:

[0046] (1) By configuring a main control module, a first memory (Meg_RAM), an interleaving module, a first RSC encoding module, a second RSC encoding module and a puncturing and multiplexing module on the FPGA of a turbo coding device, a first information sequence can be obtained, and then the first information sequence is interleaved and mapped based on the interleaving address to obtain a second information sequence, and then encoding is performed based on the first information sequence to obtain a first system sequence and a first check sequence; and encoding is performed based on the second information sequence to obtain a second system sequence and a second check sequence, and then puncturing and multiplexing are performed based on the first system sequence, the first check sequence, the second system sequence and the second check sequence to obtain a coding result, so that turbo coding can be implemented based on FPGA.

[0047] (2) By configuring a sequence separation module (decoder_algorithm module), an iterative decoding module (decoder_maxlogmap module) and a main control module on the FPGA of the turbo decoding device, a third information sequence to be decoded can be obtained, and then a system sequence and a check sequence can be separated from the third information sequence, and then SISO iterative decoding is performed based on the system sequence, the check sequence and the prior information to obtain a decoding result, so that turbo decoding can be realized based on the FPGA.

[0048] (3) The turbo encoding and decoding device provided by this application can improve the information processing capability of the system and ensure that the system obtains better bit error rate performance; this application has a simple structure and can use the hardware description language Verilog to build a hardware environment for implementation, which has high practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 It is a structural diagram of a Turbo codec device based on FPGA provided in an embodiment of the present application;

[0050] Figure 2 is a structural block diagram of a Turbo encoder provided in an embodiment of the present application;

[0051] Figure 3 is a block diagram of the overall implementation of the encoder provided in the embodiment of the present application;

[0052] Figure 4 is a flow chart of the Turbo encoder provided in an embodiment of the present application;

[0053] Figure 5 It is a decoding iteration block diagram provided in an embodiment of the present application;

[0054] Figure 6 is a flow chart of a Turbo decoder provided in an embodiment of the present application;

[0055] Figure 7 This is an overall implementation block diagram of the decoder provided in an embodiment of the present application. DETAILED DESCRIPTION

[0056] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0057] The terms "first", "second", etc. in the specification and claims herein are used to distinguish different objects rather than to describe a specific order of objects. For example, a first memory and a second memory are used to distinguish different memories rather than to describe a specific order of memories.

[0058] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0059] In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more than two. For example, multiple processing units refer to two or more processing units, etc.; multiple elements refer to two or more elements, etc.

[0060] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application.

[0061] Figure 1 is a schematic diagram of the structure of a Turbo codec device based on FPGA provided in an embodiment of the present application, such as Figure 1 As shown, a main control module, a first memory (Meg_RAM), an interleaving module, a first RSC encoding module, a second RSC encoding module and a puncturing multiplexing module are configured on the FPGA of the Turbo encoding device;

[0062] The first memory is used to cache the first information sequence (C k );

[0063] The interleaving module is used to cache the first information sequence, and based on the interleaving address, interleave the first information sequence to obtain the second information sequence (C′ k );

[0064] The first RSC encoding module is used to read the first information sequence from the first memory, and perform Turbo encoding based on the first information sequence to obtain a first system sequence (X k ) and the first check sequence (Z k );

[0065] The second RSC encoding module is used to read the second information sequence from the interleaving module, and perform Turbo encoding based on the second information sequence to obtain a second system sequence (X′ k ) and the second check sequence (Z′ k );

[0066] The puncturing and multiplexing module is used to perform puncturing and multiplexing processing based on the first system sequence, the first check sequence, the second system sequence and the second check sequence to obtain a Turbo coding result;

[0067] The main control module is used to control the working status of each encoding module and control the read and write addresses of each memory in this device.

[0068] It can be understood that by configuring the main control module, the first memory (Meg_RAM), the interleaving module, the first RSC encoding module, the second RSC encoding module and the puncturing and multiplexing module on the FPGA of the Turbo encoding device, the first information sequence can be obtained, and then the first information sequence is interleaved and mapped based on the interleaving address to obtain the second information sequence, and then encoding is performed based on the first information sequence to obtain the first system sequence and the first check sequence; and encoding is performed based on the second information sequence to obtain the second system sequence and the second check sequence, and then puncturing and multiplexing are performed based on the first system sequence, the first check sequence, the second system sequence and the second check sequence to obtain the encoding result, so that turbo encoding can be implemented based on FPGA.

[0069] like Figure 1 As shown, a sequence separation module (decoder_algorithm module), an iterative decoding module (decoder_maxlogmap module) and a main control module are configured on the FPGA of the Turbo decoding device;

[0070] The sequence separation module is used for receiving a third information sequence to be decoded, separating a system sequence and a check sequence from the received third information sequence, and outputting the system sequence and the check sequence to the iterative decoding module;

[0071] The iterative decoding module is used to perform SISO iterative decoding based on the system sequence, the check sequence and the prior information to obtain the Turbo decoding result;

[0072] The main control module is used to control the working status of each decoding module and control the read and write addresses of each memory in this device.

[0073] In a possible implementation, the SISO iterative decoding specifically adopts the Max-Log-MAP algorithm.

[0074] The Max-Log-MAP algorithm is a specific implementation method for Turbo decoding. It estimates the most likely transmitted information by processing the received signal based on the principle of maximum a posteriori probability. It is a simplified version of the Log-MAP algorithm with lower complexity and better performance. The basic contents of the Max-Log-MAP algorithm are as follows: (1) Initialization: assign an initial likelihood ratio (LLR) to each information bit, which is usually set to the initial log-likelihood ratio of the received signal; (2) Forward and backward recursion: use forward and backward recursion to calculate the probability of each state, where the probability refers to the probability when the state is true; (3) Branch metric calculation: the branch metric is calculated based on the received signal and prior information, reflecting the possibility of transitioning from one state to another; (4) Output likelihood ratio update: update the likelihood ratio of each information bit based on the forward and backward recursion results and the branch metric.

[0075] SISO iterative decoding is the core of Turbo decoding. Its iterative process includes: in each decoder component, using the Max-Log-MAP algorithm to calculate the likelihood ratio of the information bit; using the output of one decoder component as the prior information of another decoder component for the next iteration; iterating multiple times until the stop condition is met (such as reaching the maximum number of iterations or the decoding performance reaches a preset threshold). After multiple iterations, the final decoding result is output.

[0076] It can be understood that by configuring a sequence separation module (decoder_algorithm module), an iterative decoding module (decoder_maxlogmap module) and a main control module on the FPGA of the turbo decoding device, the third information sequence to be decoded can be obtained, and then the system sequence and the check sequence can be separated from the third information sequence, and then based on the system sequence, the check sequence and the prior information, SISO iterative decoding is performed to obtain the decoding result, and turbo decoding can be realized based on the FPGA.

[0077] Therefore, by configuring a main control module, a first memory (Meg_RAM), an interleaving module, a first RSC encoding module, a second RSC encoding module and a puncturing multiplexing module on the FPGA of a turbo encoding device, and by configuring a sequence separation module (decoder_algorithm module), an iterative decoding module (decoder_maxlogmap module) and a main control module on the FPGA of a turbo decoding device, turbo encoding and decoding can be implemented based on FPGA. The turbo encoding and decoding device provided by the present application can improve the system information processing capability and ensure that the system obtains a good bit error rate performance; the present application has a simple structure and can use the hardware description language Verilog language to build a hardware environment for implementation, and has high practicality.

[0078] The following is an illustrative description of the FPGA-based Turbo encoding device and decoding device provided by the present application with reference to several examples.

[0079] This application adopts Figure 2 The encoder structure shown in FIG. 1 shows that two recursive systematic convolutional codes (RSC) are cascaded in parallel in the Turbo code encoder, and an interleaver and a deinterleaver are used in the encoder. Figure 2 D represents a delay device. The RSC encoder of this application uses an 8-state recursive systematic convolutional code with coefficients of [13, 15] as a component code, and the number of storage levels m=3.

[0080] The overall implementation block diagram of the encoder is as follows Figure 3 As shown, in this application, Turbo coding is to encode data frame 0 or 1, so there is no need to consider the problem of fixed point. The whole coding process includes five modules, main control module, Interleave module, RSC_1 coding module, RSC_2 coding module, delete multiplexing module, etc.

[0081] The overall working process of the encoder is that the main control module receives the input information sequence C kAfter the frame header type is judged as a valid signal, the input information bits are divided into two signals and cached in two RAMs respectively. One signal is directly cached in the memory Meg_RAM, and the other signal is cached in the memory RAM_0. Then the interleaving address stored in the ROM is extracted (when interleaving processing is required later, the interleaving address stored in the ROM will be directly called). Among them, the process of writing the information sequence into the RAM is called the information storage state. When the information sequence input is completed, the encoder working state changes from the information storage state to the precoding state. When working in the precoding state, the main control module gives the RAM read address to read the information sequence from the RAM, and the input sequence mapped by the interleaving address becomes C′ k , and finally the two information sequences C k , C′ k The RSC_encoder1 / 2 (component encoder RSC module) are input respectively for formal encoding. At this time, the encoder's working state also changes from the pre-coding state to the encoding state. The coding sequence output by the RSC encoding module is in the form of (system sequence, check sequence), and the coding sequence is cached in the post-stage RAM. Then, the 4-way coding sequences obtained by the two encoders are read out from the RAM and sent to the subsequent delete multiplexing module. Then, puncture and delete are performed according to the bit rate selection (data output selection), and the processed result is output as the encoding result of the turbo code encoder. The above entire encoding process is as follows: Figure 4 shown.

[0082] The main control module takes the lead and controls the entire turbo encoding workflow, including controlling the status information of each encoding module and the read and write addresses of each memory module.

[0083] The Interleave module calculates the interleaved information sequence according to the interleaving address given by the main control module and outputs it to the RSC_2 encoding module, and stores the interleaving address in the ROM.

[0084] The RSC_1 / 2 encoding module receives the uninterleaved data and the interleaved data respectively, processes them bit by bit, and outputs the system sequence X k , X′ k , check sequence Z k , Z′ k .

[0085] Specifically, the RSC_1 / 2 encoding module processes the received information sequence bit by bit, wherein after the RSC_1 encoding module receives the original information sequence, it first calculates the system sequence and the check sequence when the information sequence is not fully received according to the input sequence encoding structure. At this time, the system sequence is equal to the input information sequence, and the check sequence is generated based on the shift register + modulo 2 processing structure connected by the generating polynomial. When the information sequence is fully received, the tail bit calculation is performed. According to the tail bit encoding structure, the system sequence at this time is generated based on the shift register + modulo 2 processing structure connected by the feedback polynomial, and the check sequence is generated based on the shift register + modulo 2 processing structure connected by the feedforward polynomial. The hardware implementation method of the shift register + modulo 2 processing structure is: first perform a bitwise AND operation to realize the connection between the polynomial and the shift register, and then perform a reduced XOR operation on the result to realize the modulo 2 operation. The RSC_2 encoding module has the same encoding process as the RSC_1 encoding module, except that the input of the RSC_2 encoding module is the interleaved information sequence, and finally the 4-way encoding sequence obtained by the two encoders is sent to the subsequent delete multiplexing module.

[0086] The delete multiplexing module performs puncturing and deletion (data selection output) according to different bit rates to obtain the final encoding result of the turbo code encoder.

[0087] Specifically, the delete multiplexing module receives the system sequence and check sequence output by the RSC_1 / 2 encoding module and stores them in the dual-port RAM, and then sends the read address to the memory under the control of the main control module according to different code rates, and converts the parallel data into serial output under the control of the clock cycle according to the address.

[0088] Combine the following Figure 3 and Figure 4 , a detailed description of the specific working process of the encoder of this application is given.

[0089] Step 1, the main control module is in an idle waiting state, waiting for the input of encoded data;

[0090] Step 2: After the input of the coding information is detected, the main control module controls the RAM memory to receive the data, starts the write mode, and starts the write count at the same time, until the last data is written, and then jumps to step 3;

[0091] Step 3, the main control module enables the Interleave module;

[0092] Step 4: The Interleave module calculates the interleaving address according to a given formula and transmits it to the main control module;

[0093] Step 5: The main control module enables the memory read signal, turns on the read count, and reads out the data address in sequence. The main control module controls the incremental sequential address generated by the original information and the interleaving address generated by the Interleave module according to the formula to be input into the Meg_RAM and RAM_0 memories respectively;

[0094] Step 6, the main control module enables the RSC_1 / 2 encoding module;

[0095] Step 7, the memories Meg_RAM and RAM_0 output the non-interleaved data and the interleaved data according to the received increasing sequence addresses and the recursively generated interleaved addresses, and the RSC_1 / 2 encoding module receives the non-interleaved data and the interleaved data from the memories Meg_RAM and RAM_0 respectively and performs RSC encoding;

[0096] Step 8, the main control module controls the RAM memory to receive data, turns on the write mode, turns on the write count, and stores the RSC-encoded codeword sequence into the post-stage RAM until the last codeword is written, and then jumps to step 9;

[0097] Step 9, the main control module enables the memory read signal, turns on the read count, sequentially reads out the data address in the RAM, and enables the redundancy removal multiplexing module at the same time;

[0098] Step 10: The main control module controls the puncturing and multiplexing module to select different puncturing rules according to the bit rate to select and output data, and the encoding process ends here.

[0099] Regarding the decoder design, considering the difficulty of hardware implementation, the Turbo decoding in this application is implemented using the Max-Log-MAP algorithm, using SISO (Soft Input Soft Output) iterative decoding. The entire decoding (decoding) iterative structure is as follows Figure 5 The entire decoding process is divided into three modules: decoder_algorithm module, decoder_maxlogmap module, and main control module.

[0100] SISO decoder 1 and SISO decoder 2 have the same structure. They decode according to the logarithmic probability ratio of the codewords during the decoding process. The SISO decoder has three inputs (system sequence, check sequence, and prior information) and two outputs (soft information output and external information, where the soft information output is used as a valid output only after the iteration is completed and used for hard decision).

[0101] For a certain codeword, SISO decoder 1 takes the received information bit, the check bit corresponding to the output of component encoder 1 and the prior information given by SISO decoder 2 as input, and after decoding, outputs the prior information required by SISO decoder 2. Similarly, SISO decoder 2 decodes with the received interleaved information bit, the check bit corresponding to the output of component encoder 2 and the prior information given by SISO decoder 1.

[0102] Iterate over the decoded structure box Figure 5 The entire decoding workflow is as follows: Assume that the input of SISO decoder 1 is the system sequence y in the received sequence s The first check sequence y 1p and the prior information sequence Le 21 The input of SISO decoder 2 is the system sequence y in the received sequence. s interleaving, the second check sequence y 2p and the prior information sequence Le 12 For the first iteration, the prior information Le is input to SISO decoder 1 21 Set to 0. After SISO decoder 1 completes decoding, it outputs the reliability information sequence Le 12 , for Le 12 After reordering according to the mapping function, it is passed to SISO decoder 2. Here, the interleaver is exactly the same as the interleaver in the encoding. For SISO decoder 2, its processing process is similar to SISO decoder 1, the difference is that its output is deinterleaved instead of interleaved. In the decoding of Turbo codes, a number of iterations is often specified to stop the decoder and output the log-likelihood ratio of the information bit. In some applications, the decoding is also terminated by a stopping criterion. Finally, it will pass through a hard decision circuit to output the estimated value of the information bit, so that the decoding is completed.

[0103] Since the encoder needs to return to the initial zero state after encoding, the tail code is added. If the code length is K, the length of the input sequence and output sequence of the SISO decoder are both L=K+m, (m=4). This means that when SISO decoder 1 and SISO decoder 2 are transmitting reliability information during decoding, the corresponding tail bits must be cleared. In other words, the interleaver (or deinterleaver) needs to interleave (or deinterleave) the first K symbols in the reliability information, and then all the last m symbols are cleared to zero and passed to the next level decoder as its prior information input.

[0104] The decoder_algorithm module receives the input information sequence, QPP interleaving address, number of decoding iterations and decoding algorithm module selection flag, separates the system sequence and check sequence from the received sequence, and then sends them as input to the iterative decoding MAX-LOG-MAP module, iterates the two decoders to complete the decoding operation, and the actual algorithm selection is determined by the input algorithm module selection flag.

[0105] The decoder_maxlogmap module calculates the branch metric, forward metric, and backward metric, and then uses the calculated three parts to calculate the log-likelihood ratio LLR according to the formula, and repeats it in turn until the number of decoding iterations is reached. Finally, the data output after the iteration is deinterleaved and hard-determined for the last time and then output as the decoding result. The above decoding process is as follows Figure 6 shown.

[0106] Exemplarily, the decoder_maxlogmap module takes the tailed system sequence, check sequence and prior information as input, and for loops from 1 to the sequence length to calculate the branch metric and the forward component, and then reversely calculates, loops from the sequence length to 1, calculates the backward component, and then calculates the log-likelihood ratio LLR according to the formula based on the calculated three parts, and at the same time calculates the external information as the output of the decoding module, and iterates the prior information for the next decoder, and repeats this cycle to complete the decoding.

[0107] Combine the following Figure 6 and Figure 7 , a detailed description of the specific working process of the decoder of this application is given.

[0108] Step 1, the main control module is in an idle waiting state, waiting for the input of data to be decoded;

[0109] Step 2, the main control module enables the decoder_algorithm module;

[0110] Step 3: The decoder_algorithm module receives the input sequence, QPP interleaving address, decoding iteration number and decoding algorithm selection flag from the upstream module, and separates the system sequence X from the received sequence. k Sum check sequence Z k , Z′ k ;

[0111] Step 4: The main control module controls the RAM memory to receive data, turns on the write mode, and turns on the write count until the last data is written, then jumps to step 5, where the system sequence X k Need to be interleaved to get X′ k Add 0 at the end and store it in RAM_6;

[0112] Step 5: The main control module enables the memory read signal, turns on the read count, and reads out the data address sequentially.

[0113] Step 6, the main control module enables the decoder_maxlogmap module;

[0114] Step 7, before the first iterative decoding, the decoder initializes the prior information sequence Le of SISO decoder 1 21 , set it to 0;

[0115] Step 8: After the decoder_maxlogmap module receives the tailed system sequence, check sequence and prior information, it performs the first decoding;

[0116] Step 9, according to the formula, the branch metric and the forward component value are calculated, the main control module controls the RAM memory to receive data, turns on the write mode, and turns on the write count, and stores it in the subsequent RAM until the last data is written, and then jumps to step 10;

[0117] Step 10, the main control module enables the memory read signal, turns on the read count, and reads out the data address in reverse order;

[0118] Step 11, the memory outputs the corresponding branch metric value according to the reverse decreasing address, and then calculates the backward component;

[0119] Step 12, based on the branch metric, the forward component value and the backward component, calculate the log likelihood ratio LLR according to the formula;

[0120] Step 13, the main control module controls the RAM memory to receive data, turns on the write mode, turns on the write count, and stores the log-likelihood ratio LLR calculation result in the post-stage RAM until the last data is written, and then jumps to step 14;

[0121] Step 14, the memory outputs the log-likelihood ratio according to the reverse decreasing address, and calculates the external information as the output of the decoding module, and iterates the prior information of the next decoder, and repeats this cycle until the set number of iterations is reached, and jumps to step 15, otherwise, jumps to step 9;

[0122] Step 15, the data output after the iteration is deinterleaved and hard-decided for the last time, and the decoding process ends here.

[0123] It is understandable that the turbo code encoding and decoding device provided by the present application has a simple structure, and the hardware description language Verilog can be used to complete the turbo code encoding and decoding through FPGA hardware implementation, and the FPGA implementation project is embedded in the control system (host computer) and FPGA joint test platform for performance testing, which has high practicality. At the same time, in the decoder design of the present application, the principle of time-sharing and block-based multiplexing parallel decoding is adopted within a single iteration, which can further reduce the decoding complexity while reducing resource usage.

[0124] The present application also provides an encoding and decoding system based on FPGA, which includes: an FPGA-based Turbo encoding device and an FPGA-based Turbo decoding device, the Turbo encoding device and the Turbo decoding device are communicatively connected, and an encoding and decoding process of information bits is implemented through the Turbo encoding device and the Turbo decoding device.

[0125] The Turbo coding device is specifically used to: obtain a first information sequence; based on the interleaving address, interleave and map the first information sequence to obtain a second information sequence; encode based on the first information sequence to obtain a first system sequence and a first check sequence; and encode based on the second information sequence to obtain a second system sequence and a second check sequence; perform puncturing and multiplexing based on the first system sequence, the first check sequence, the second system sequence, and the second check sequence to obtain a Turbo coding result;

[0126] The Turbo decoding device is specifically used for: obtaining a third information sequence to be decoded; separating a system sequence and a check sequence from the third information sequence; performing SISO iterative decoding based on the system sequence, the check sequence and prior information to obtain a Turbo decoding result.

[0127] It should be understood that the various numerical numbers involved in the embodiments of the present application are only used for the convenience of description and are not used to limit the scope of the embodiments of the present application.

[0128] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A Turbo encoding device based on FPGA, characterized in that: A main control module, a first memory, an interleaving module, a first RSC encoding module, a second RSC encoding module and a puncturing multiplexing module are configured on the FPGA of the turbo encoding device; The first memory is used to cache the first information sequence; The interleaving module is used to cache the first information sequence, and based on the interleaving address, perform interleaving mapping on the first information sequence to obtain a second information sequence; The first RSC encoding module is used to read the first information sequence from the first memory, and perform encoding based on the first information sequence to obtain a first system sequence and a first check sequence; The second RSC encoding module is used to read the second information sequence from the interleaving module, and encode based on the second information sequence to obtain a second system sequence and a second check sequence; The puncturing and multiplexing module is used to perform puncturing and multiplexing processing based on the first system sequence, the first check sequence, the second system sequence and the second check sequence to obtain a Turbo coding result; The main control module is used to control the working status of each encoding module and control the read and write addresses of each memory in this device.

2. The FPGA-based Turbo encoding device according to claim 1, characterized in that: The interleaving module includes a second memory and a third memory; The second memory is used for storing the interleaved address; The third memory is used to cache the first information sequence, and to perform interleaving mapping on the first information sequence according to the interleaving address to obtain the second information sequence.

3. The FPGA-based Turbo encoding device according to claim 1, characterized in that: The puncturing multiplexing module comprises: a fourth memory for caching the first system sequence, a fifth memory for caching the first check sequence, a sixth memory for caching the second system sequence, a seventh memory for caching the second check sequence and a puncturing multiplexing unit; The puncturing and multiplexing unit is used to read the first system sequence, the first check sequence, the second system sequence and the second check sequence from the fourth memory, the fifth memory, the sixth memory and the seventh memory, and perform puncturing and multiplexing on the read sequences to obtain Turbo coding results.

4. A Turbo coding method, characterized in that: Applied to the FPGA-based Turbo encoding device according to any one of claims 1 to 3, the method comprises: Acquiring a first information sequence; Based on the interleaving address, interleave mapping is performed on the first information sequence to obtain a second information sequence; Encoding based on the first information sequence to obtain a first system sequence and a first check sequence; and encoding based on the second information sequence to obtain a second system sequence and a second check sequence; Based on the first system sequence, the first check sequence, the second system sequence and the second check sequence, puncturing processing and multiplexing processing are performed to obtain a Turbo coding result.

5. A Turbo decoding device based on FPGA, characterized in that: A sequence separation module, an iterative decoding module and a main control module are configured on the FPGA of the turbo decoding device; The sequence separation module is used for receiving a third information sequence to be decoded, separating a system sequence and a check sequence from the received third information sequence, and outputting the system sequence and the check sequence to the iterative decoding module; The iterative decoding module is used to perform SISO iterative decoding based on the system sequence, the check sequence and the prior information to obtain the Turbo decoding result; The main control module is used to control the working status of each decoding module and control the read and write addresses of each memory in this device.

6. The FPGA-based Turbo decoding device according to claim 5, characterized in that: The SISO iterative decoding specifically adopts the Max-Log-MAP algorithm.

7. A Turbo decoding method, characterized in that: Applied to the FPGA-based Turbo decoding device as claimed in claim 5 or 6, the method comprises: Acquire a third information sequence to be decoded; separating a systematic sequence and a check sequence from a third information sequence; Based on the system sequence, check sequence and prior information, SISO iterative decoding is performed to obtain the Turbo decoding result.

8. A coding and decoding system based on FPGA, characterized in that: include: A Turbo encoding device based on FPGA and a Turbo decoding device based on FPGA, the Turbo encoding device and the Turbo decoding device are communicatively connected; The Turbo encoding device is specifically used for: Acquiring a first information sequence; Based on the interleaving address, interleave mapping is performed on the first information sequence to obtain a second information sequence; Encoding is performed based on the first information sequence to obtain a first system sequence and a first check sequence; and performing encoding based on the second information sequence to obtain a second system sequence and a second check sequence; Based on the first system sequence, the first check sequence, the second system sequence and the second check sequence, perform puncturing processing and multiplexing processing to obtain a Turbo coding result; The Turbo decoding device is specifically used for: Acquire a third information sequence to be decoded; separating a systematic sequence and a check sequence from a third information sequence; Based on the system sequence, check sequence and prior information, SISO iterative decoding is performed to obtain the Turbo decoding result.

9. The FPGA-based encoding and decoding system according to claim 8, characterized in that: A main control module, a first memory, an interleaving module, a first RSC encoding module, a second RSC encoding module and a puncturing multiplexing module are configured on the FPGA of the turbo encoding device; The first memory is used to cache the first information sequence; The interleaving module is used to cache the first information sequence, and based on the interleaving address, perform interleaving mapping on the first information sequence to obtain a second information sequence; The first RSC encoding module is used to read the first information sequence from the first memory, and perform encoding based on the first information sequence to obtain a first system sequence and a first check sequence; The second RSC encoding module is used to read the second information sequence from the interleaving module, and encode based on the second information sequence to obtain a second system sequence and a second check sequence; The puncturing and multiplexing module is used to perform puncturing and multiplexing processing based on the first system sequence, the first check sequence, the second system sequence and the second check sequence to obtain a Turbo coding result; The main control module is used to control the working status of each encoding module and control the read and write addresses of each memory in this device.

10. The FPGA-based encoding and decoding system according to claim 8, characterized in that: A sequence separation module, an iterative decoding module and a main control module are configured on the FPGA of the turbo decoding device; The sequence separation module is used for receiving a third information sequence to be decoded, separating a system sequence and a check sequence from the received third information sequence, and outputting the system sequence and the check sequence to the iterative decoding module; The iterative decoding module is used to perform SISO iterative decoding based on the system sequence, the check sequence and the prior information to obtain the Turbo decoding result; The main control module is used to control the working status of each decoding module and control the read and write addresses of each memory in this device.

Images