A transceiver integrated detection system based on CMUT sensor

Abstract

The present invention discloses a transceiver-integrated detection system based on a CMUT sensor, comprising: a DC bias voltage supply module for providing bias voltage for the CMUT sensor; a system power supply module for providing power; a PC host computer terminal for generating host computer data; a data communication module for transmitting host computer data; an FPGA selection signal control module for receiving host computer data and processing and distributing it; a high-voltage pulse circuit generation module for selecting and activating corresponding n-channel high-voltage pulse excitation signals based on the selection signal; a time-division multiplexing circuit module for expanding the n-channel high-voltage pulse excitation signals to 2n channels; an LC impedance matching module for matching specific transducers; a secondary amplification echo signal amplification module; and an analog-to-digital conversion module for quantizing the echo data after the secondary amplification. The present invention can achieve multi-channel synchronous driving of an array CMUT sensor, while suppressing crosstalk between different channels and delays caused by different path lengths.

Description

Technical Field

[0001] The present invention belongs to the field of ultrasonic technology, and in particular relates to a multi-channel ultrasonic transmitting system based on a CMUT (Capacitive Micromachined Ultrasonic Transducer) sensor. Background Art

[0002] Ultrasonic testing is a nondestructive testing method that is primarily categorized as biomedical ultrasound and industrial testing, based on differences in the test object, imaging method, and equipment architecture. In the biomedical field, ultrasonic testing has become an indispensable technique. Compared to traditional CT, X-ray, and MRI imaging, ultrasound offers advantages in acquiring data on organ structure and morphology, such as no radiation risk and real-time performance, significantly improving diagnostic accuracy and safety.

[0003] In the field of biomedical ultrasound, due to the increasing complexity of application scenarios, the diversification of object-oriented technologies, and the massive amount of data processing, there are greater demands on the frequency, bandwidth, and volume of its key component, the transducer. At the same time, advances in micromachining processes for MEMS (Micro-Electro-Mechanical Systems) have driven the development of CMUTs. CMUTs not only overcome the difficulty of coupling between piezoelectric materials and air, but also offer advantages such as high energy conversion efficiency, high reception sensitivity, wide bandwidth, high detection accuracy, and ease of arraying. Therefore, fully leveraging the advantages of CMUTs in bioultrasound testing and designing a multi-channel transmission system that matches the CMUT probe is particularly important.

[0004] Existing ultrasonic flaw detection system circuits typically only support single-point detection of the object being inspected, not multi-point detection. In real-world applications, achieving multi-point detection of the same object requires a multi-point, simultaneously driven ultrasonic transmission system that can match a CMUT linear or planar array. However, existing multi-channel drive circuits are not only complex and bulky, but also prone to significant crosstalk between the signals of the various pulse transmission circuits, negatively impacting signal integrity.

[0005] In summary, it is necessary to develop a transmitting system that matches the multi-array capacitive ultrasonic micromachined transducer, design an impedance matching circuit that matches the CMUT probe, solve the problem of signal interference between each ultrasonic pulse, and at the same time, design a circuit system to achieve low delay between channels, and the control system has a high-precision delay control algorithm, which is of great significance for ultrasonic driving and detection. Summary of the Invention

[0006] The purpose of the present invention is to overcome the shortcomings of the existing technology and propose a transceiver integrated detection system based on CMUT sensors, aiming to achieve multi-channel synchronous driving of array CMUT sensors, and suppress the mutual crosstalk between different channels and the delay caused by different path lengths.

[0007] In order to achieve the above object, the technical solutions specifically adopted by the present invention are as follows:

[0008] A transceiver-integrated detection system based on a CMUT sensor comprises: a DC bias voltage supply module for providing a bias voltage for the CMUT sensor; a system power supply module for providing power to the entire circuit system; a PC host computer terminal for generating data transmitted by a host computer; a data communication module for transmitting the data transmitted by the host computer to an FPGA system; an FPGA selection signal control module for receiving the data transmitted by the host computer and processing the distribution of the host computer data; a high-voltage pulse circuit generation module for selecting and enabling corresponding n-channel high-voltage pulse excitation signals according to the selection signal generated by the FPGA selection signal control module; a time-division multiplexing circuit module for expanding the n-channel high-voltage pulse excitation signals to 2n channels; an LC impedance matching module for matching specific transducers; an echo signal amplification module for receiving echo data and performing secondary amplification; and an analog-to-digital conversion module for quantizing the echo data after the secondary amplification.

[0009] Furthermore, the DC bias voltage supply module uses the LM5022 chip as the main control, loads a 30V input voltage, decouples it through capacitor filtering, and inputs it to the main control chip. The output voltage is based on current mode control, through resistor voltage division and SEPIC voltage regulation, and through MOS tube control of current size and output shutdown to achieve boost voltage regulation and voltage output. The voltage output terminal is connected to capacitor filtering and supplied to the CMUT sensor through a matching circuit to provide a stable supply of 100V bias voltage.

[0010] Furthermore, the external part of the system power supply module is supplied with ±30V voltage by a voltage-stabilizing power supply module. The first part is directly connected to the high-voltage pulse circuit generation module by the ±30V voltage to control the size of the excitation signal. The system is configured with a voltage supply system of ±30V to ±40V, which can reach a maximum of ±40V excitation high-voltage pulse signal. The 30V voltage is loaded into the LM25085 chip, and the switching power supply is used to achieve voltage division and voltage stabilization, and the output voltage is obtained through N-MOS, and then the current required by the system is obtained through the inductor L2, and the output voltage is converted from 30V to 12V.

[0011] Furthermore, the 12V voltage obtained in the voltage supply system is obtained through the TP54302 switching chip, and a 5V input voltage is obtained by resistive voltage division and inductive current control. The ±5V voltage is obtained through the design of the ICL7660 switching power supply chip, and is supplied to the multi-channel multiplexing chip of the post-circuit. Then, the input 12V power supply voltage is obtained through the TPS62130 chip to obtain the power supply voltage part required by the FPGA system, including 3.3V, 3.15V, 1.9V, 1.8V, 1.5V, 1.2V and 1V, to meet the power supply requirements of different parts of the system.

[0012] Furthermore, the PC host computer sets specific required data, including serial port channel, serial port transmission current, baud rate, signal frequency, number of signals, etc., through the host computer interface and generates a data stream. 80-bit wide data is sent in a packed data frame format, and the data is packed in a frame header and frame footer format to generate the host computer transmission data.

[0013] Furthermore, the data communication module transmits data to the FPGA using a serial communication method.

[0014] Furthermore, the FPGA sending digital control module includes an FPGA serial port data receiving module, a data cache FPGA data classification module, a MAX14808 high-voltage drive circuit control module, and a MAX14866 signal multi-channel multiplexing control module.

[0015] Furthermore, the high-voltage pulse circuit generation module uses the MAX14808 main control chip as the main control module of the system. The port of a single MAX14808 chip connected to the FPGA consists of 20 IO ports, of which 4 are divided into 4 current control ports and a mode selection port. The power supply is +30VPP and -30VPP. Then the entire system outputs 8 positive and negative pulse signals with a duty cycle of 50%. The entire system uses a total of 4 high-voltage pulse excitation chips and generates 64 pulse excitation signals.

[0016] Furthermore, the time-division multiplexing circuit module uses the MAX14866 main control chip as the main control module of the system. The port for a single MAX14808 chip to access the FPGA consists of 6 ports, including clock, chip select, set, and MISO and MOSI interfaces for SPI communication. Then the input signal is connected to its input port from the front MAX14808 chip output port, ultimately realizing 64 output signals. The module is powered by +5V voltage and +3V3 voltage.

[0017] Furthermore, the LC impedance matching module is targeted at the signal sending circuit part, and the input impedance is closer to the probe impedance. The matching network has a wider frequency response and is suitable for high-frequency signals.

[0018] Furthermore, impedance matching includes the following steps:

[0019] Step 1: In the LC tuning network, design and calculate the CMUT equivalent circuit resistance and CMUT equivalent circuit series resonant frequency according to the CMUT structural parameters;

[0020] Step 2: Using the Smith chart, combined with the reactance of the CMUT equivalent circuit and the series resonant frequency of the CMUT equivalent circuit, adjust the inductance of the tuning inductor L and the capacitance of the tuning capacitor C so that the overall reactance of the CMUT equivalent circuit and the LC tuning network is 0 and the resistance is 50Ω±5Ω. This gives the final parameters for the inductance of the inductor L and the capacitance of the tuning capacitor C.

[0021] Furthermore, the echo signal amplification module includes a TIA transimpedance amplifier circuit, an LNA in-phase proportional amplifier circuit, and a BPF bandpass filter, to achieve two-stage amplification and filtering of high-frequency weak echo signals.

[0022] Furthermore, the echo signal passes through the TIA, LNA, and BPF circuits and then undergoes ADC conversion in the analog-to-digital conversion module. The analog-to-digital conversion module is mainly controlled by the AFE5832 chip, which integrates multiple functions such as signal attenuator, amplifier, filter, and analog-to-digital conversion. In addition, time division multiplexing is used internally to achieve 32-channel data reception with 16 channels.

[0023] The present invention implements a self-crossing control algorithm for the LVDS data receiving part, which can achieve stable data reception. Compared with the prior art, the present invention has the following characteristics and beneficial effects:

[0024] (1) Design an impedance matching circuit that matches the CMUT probe to ensure and realize that the CMUT can operate stably and resonantly under a certain voltage.

[0025] (2) Compared with the traditional driving circuit, the realized 64-channel driving circuit has higher integration and smaller size, which is conducive to portable design. It adopts a modular design and has complete overall functions.

[0026] (3) In terms of control algorithm, at a frequency of 250MHz, the delay accuracy can reach 1ns. The layout utilizes the layout of equal-length differential lines, which greatly reduces the delay error. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Other features, objects and advantages of the present invention will become more apparent upon reading the detailed description of non-limiting embodiments with reference to the following drawings:

[0028] Figure 1 FPGA system block diagram in an embodiment of the present invention;

[0029] Figure 2 A system power supply module in an embodiment of the present invention;

[0030] Figure 3 A DC bias voltage supply module in an embodiment of the present invention;

[0031] Figure 4 Supply circuits for some systems in embodiments of the present invention;

[0032] Figure 5 Supply circuits for some systems in embodiments of the present invention;

[0033] Figure 6 The MAX14808 high-voltage pulse generation module hardware circuit in the embodiment of the present invention;

[0034] Figure 7 It is the hardware circuit of the MAX14866 signal multi-channel time division multiplexing circuit module in the embodiment of the present invention;

[0035] Figure 8 is the impedance matching Smith diagram in an embodiment of the present invention; DETAILED DESCRIPTION

[0036] The present invention is described in detail below in conjunction with specific embodiments. The following examples will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other.

[0037] The embodiment of the present invention provides a transceiver integrated detection system based on a CMUT sensor, which mainly includes: a PC host terminal, an FPGA system, a DC bias voltage supply module, a system power supply module, and an LC impedance matching module; specifically:

[0038] In the embodiment of the present invention, a PC host computer and an FPGA system are provided to match the circuit port. Figure 1 As shown, the PC host interface sets the required data, including serial port channel, serial port transmission current, baud rate, signal frequency, signal number, and other data, and generates a data stream. 80-bit wide data is sent using a packed data frame, with a frame header of 0xAA and a frame footer of 0xFF generating the host transmission data. The host transmission data includes various information such as drive signal frequency, drive signal length, drive signal shutdown control, and drive signal delay parameter settings, thereby achieving the data transmission part of the host computer.

[0039] The FPGA system includes a power supply module, a serial port data transmission module, a data cache DDR3 module, a USB3.0 echo data receiving module, an echo digital control module, a transmission digital control module, a MAX14808 high-voltage pulse generation module, a MAX14866 signal multi-channel time division multiplexing circuit module, a hardware circuit analog signal amplification module, a bandpass filter, an ADC analog signal to digital signal module and a data LVDS receiving module. Among them, the MAX14808 high-voltage pulse generation module hardware circuit is combined with the Figure 6 The MAX14808 main control chip serves as the main control module of the system. The port of a single MAX14808 chip connected to the FPGA consists of 20 IO ports, of which 4 are current control ports and mode selection ports. The power supply is +30VVPP and -30VPP. Then the entire system outputs 8 positive and negative pulse signals with a duty cycle of 50%. The entire system uses a total of 4 high-voltage pulse excitation chips and generates 64 pulse excitation signals.

[0040] MAX14866 signal multi-channel time division multiplexing circuit module hardware circuit combination Figure 7 As shown in the figure, the MAX14866 main control chip serves as the main control module of the system. The port for a single MAX14808 chip to access the FPGA consists of 6 ports, including clock, chip select, set, and MISO and MOSI interfaces for SPI communication. The input signal is then connected to its input port from the output port of the front MAX14808 chip, ultimately realizing 64 output signals. The module is powered by +5V and +3V3 voltages.

[0041] During operation, the PC host generates host transmission data and transmits it to the FPGA system via the data communication module. The FPGA system receives the host transmission data, processes it in the transmission digital control module, and distributes it to the MAX14808 high-voltage pulse generation module. The MAX14808 high-voltage pulse generation module selects and activates the corresponding n-channel high-voltage pulse excitation signal based on the selection signal generated by the echo digital control module. The MAX14866 signal multi-channel time-division multiplexing circuit module then expands the n-channel high-voltage pulse excitation signal to 2n channels. Simultaneously, the high-voltage pulse wave generated by the MAX14808, the de-energized CMUT ultrasonic transducer, and the ultrasonic wave generated by the CMUT ultrasonic transducer encounter defects and reflect the ultrasonic signal, forming an echo signal. The echo signal is processed in sequence by the hardware circuit analog signal amplification module, bandpass filter, and ADC analog signal to digital signal conversion module, and then transmitted to the echo digital control module via the data LVDS receiving module. After processing by the echo digital control module, it is transmitted to the PC host via the USB3.0 echo data receiving module. The data communication module transmits the data to the FPGA via serial communication.

[0042] The system power supply module of the present invention is combined with Figure 2 Description: The external voltage is supplied by the voltage-stabilized power supply module with ±30V voltage. The first part is directly connected to the high-voltage pulse circuit generation module by the ±30V voltage to control the size of the excitation signal. The system is configured with a voltage supply system of ±30V to ±40V, which can reach a maximum of ±40V excitation high-voltage pulse signal. The 30V voltage is loaded into the LM25085 chip, and the output voltage is obtained through the switching power supply design by voltage division and stabilization and N-MOS. Then, the current required by the system is obtained through inductor 2, and the output voltage is converted from 30V to 12V. The converted 12V voltage continues to pass through the TP54302 switching chip, and obtains a 5V input voltage by means of resistor voltage division and inductor current control. The ±5V voltage is obtained through the design of the ICL7660 switching power supply chip, which is used to supply the multi-channel multiplexing chip of the post-circuit. The input 12V power supply voltage then passes through the TPS62130 chip to obtain the power supply voltage required by the FPGA system, including 3.3V, 3.15V, 1.9V, 1.8V, 1.5V, 1.2V and 1V, to meet the power supply requirements of different parts of the system.

[0043] Figure 3 The DC bias voltage supply module is used to drive the CMUT sensor. The LM5022 chip is used as the main control chip. The 30V input voltage is loaded, decoupled through capacitor filtering, and input to the main control chip. The output voltage is based on current mode control, and is stabilized by resistor voltage division and SEPIC. The MOS tube controls the current size and output shutdown to achieve boost and voltage output. The voltage output terminal is connected to the capacitor filter and the matching circuit is used to supply the CMUT sensor with a stable bias voltage of 100V.

[0044] Combining impedance matching circuit and Smith circle Figure 8 , wherein the LC impedance matching module of the present invention includes the following steps when performing impedance matching,

[0045] Step 1: In the LC tuning network, according to the equivalent circuit principle, the CMUT equivalent circuit can be constructed based on the CMUT structural parameters. The CMUT film loss and mechanical loss can be equivalent to the resistance R m =π×R 2 ×Z rad , where R represents the film radius, Z rad Represents the acoustic impedance of the medium; the mass of the CMUT film is equivalent to the inductance L m =1.84π×R 2 ×h×ρ, h represents the equivalent height of the composite film, ρ represents the equivalent density of the composite film; the capacitance of the CMUT physical structure is equivalent to the capacitance ε0 represents the acoustic dielectric constant, g0 represents the cavity height, x represents the average displacement of the film collapse, h 薄膜材料 Indicates the corresponding height of different film materials, ε 薄膜材料 Represents the relative dielectric constant of different film materials; CMUT film stiffness equivalent capacitance c0 represents the equivalent capacitance of the CMUT physical structure, Q represents the charge, C0 ′ It represents the derivative of the equivalent capacitance with respect to the average displacement of the film collapse.

[0046] Step 2: Using the Smith chart, combined with the impedance and series resonant frequency of the CMUT equivalent circuit, adjust the inductance of the tuning inductor L and the capacitance of the tuning capacitor C so that the overall reactance of the CMUT equivalent circuit and the LC tuning network is zero and the resistance is 50Ω ± 5Ω. This yields the final inductance of the inductor L and the capacitance of the tuning capacitor C. 50Ω is the standard input impedance of the RF transmission band.

[0047] According to the above description, the overall workflow of the present invention is as follows: First, the PC generates the data required for emitting ultrasonic waves and sends the data to the FPGA system through serial port communication. The data is processed by the FPGA chip and generates differential control signals that can excite the MAX14808 high-voltage pulse chip and the MAX14866-channel time-division multiplexing chip. Finally, the chip generates positive and negative pulse excitation signals with adjustable frequency of 0KHz-6.5535MHz, adjustable excitation duration, adjustable repeated excitation interval, adjustable excitation delay duration, and excitation delay accuracy of up to 1ns, and excitation voltage of up to ±30V to ±40V. This signal can drive the 64-channel CMUT chip and generate ultrasonic waves. When the ultrasonic signal passes through different media, a reflection effect will be generated. The reflected ultrasonic wave passes through the secondary amplification circuit, thereby generating an analog signal that can be recognized by the AFE5832 analog-to-digital chip. The converted signal is communicated via USB3.0 and sent back to the host computer for signal processing. The above is the overall workflow of the system.

[0048] Based on the above description, those skilled in the art should have a clear understanding of the multi-channel transceiver integrated detection system based on CMUT sensors of the present invention.

[0049] In summary, the present invention designs an impedance matching circuit that matches the CMUT probe, ensuring stable resonant operation of the CMUT under a certain voltage. Compared with traditional drive circuits, this circuit offers higher integration and a smaller overall size, favoring portable designs. Furthermore, it can achieve a delay signal with an accuracy of 1ns, and uses equal-length wiring for better signal transmission synchronization and coordination, thereby improving both performance and integration.

[0050] The above shows and describes the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions are merely preferred examples of the present invention and are not intended to limit the present invention. Various changes and improvements may be made to the present invention without departing from the spirit and scope of the present invention. Such changes and improvements fall within the scope of the present invention. The scope of protection claimed in the present invention is defined by the appended claims and their equivalents.

Claims

1. A transceiver integrated detection system based on a CMUT sensor, characterized by: The system includes: A DC bias voltage supply module is used to provide bias voltage for the CMUT sensor; System power supply module, used to provide power for the entire circuit system; PC host computer side, used to generate data for host computer transmission; A data communication module is used to transmit data from the host computer to the FPGA system using a serial communication method; An FPGA system is equipped with an FPGA strobe signal control module, a high-voltage pulse circuit generation module, and a time-division multiplexing circuit module, wherein the FPGA strobe signal control module is used to receive the host computer data and process and distribute it; the high-voltage pulse circuit generation module is used to select and activate corresponding n-channel high-voltage pulse excitation signals according to the strobe signal generated by the FPGA strobe signal control module; and the time-division multiplexing circuit module is used to expand the n-channel high-voltage pulse excitation signals to 2n channels. The time-division multiplexing circuit module uses the MAX14866 main control chip as the main control module of the system. The port for a single MAX14808 chip to access the FPGA consists of 6 ports, including clock, chip select, set, and MISO and MOSI interfaces for SPI communication. Then, the input signal is connected to its input port from the output port of the front MAX14808 chip, ultimately realizing 64 output signals. The module is powered by +5V voltage and +3V3 voltage; LC impedance matching module, used to match specific transducers; Echo signal amplification module, used to receive echo data and perform secondary amplification; The analog-to-digital conversion module is used to quantify the echo data after secondary amplification.

2. The CMUT sensor-based integrated transceiver detection system according to claim 1, characterized in that: The DC bias voltage supply module uses the LM5022 chip as the main control, loads a 30V input voltage, decouples it through capacitor filtering, and inputs it to the main control chip. The output voltage is based on current mode control, through resistor voltage division and SEPIC voltage regulation, and through MOS tube control of current size and output shutdown to achieve boost and voltage regulation and output voltage. The voltage output terminal is connected to capacitor filtering and supplies the CMUT sensor through a matching circuit to provide a stable supply of 100V bias voltage.

3. The CMUT sensor-based integrated transceiver detection system according to claim 1, characterized in that: The external part of the system power supply module is supplied with ±30V voltage by a voltage-stabilizing power supply module. The first part is directly connected to the high-voltage pulse circuit generation module by the ±30V voltage to control the size of the excitation signal. The system is configured with a voltage supply system of ±30V to ±40V. The 30V voltage is loaded into the LM25085 chip, and the switching power supply is used to achieve voltage division and voltage stabilization. The output voltage is obtained through N-MOS, and then the current size required by the system is obtained through the inductor L2, and the output voltage is converted from 30V to 12V.

4. The CMUT sensor-based integrated transceiver detection system according to claim 3, characterized in that: The 12V voltage obtained in the voltage supply system is obtained through the TP54302 switching chip, and a 5V input voltage is obtained by resistor voltage division and inductor current control. The ±5V voltage is obtained through the design of the ICL7660 switching power supply chip, which is supplied to the multi-channel multiplexing chip of the post-circuit. Then, the input 12V power supply voltage is obtained through the TPS62130 chip to obtain the power supply voltage part required by the FPGA system, including 3.3V, 3.15V, 1.9V, 1.8V, 1.5V, 1.2V and 1V, to meet the power supply requirements of different parts of the system.

5. The CMUT sensor-based integrated transceiver detection system according to claim 1, characterized in that: The PC host computer side sets the specific required data, including serial port channel, serial port sending current, baud rate, signal frequency, number of signals, and generates a data stream. It uses a packaged data frame to send 80-bit wide data, and uses a frame header and frame footer to package data to generate host computer transmission data.

6. The CMUT sensor-based integrated transceiver detection system according to claim 1, characterized in that: The FPGA digital transmission control module includes an FPGA serial port data receiving module, a data buffer FPGA data classification module, a MAX14808 high-voltage drive circuit control module, and a MAX14866 signal multi-channel multiplexing control module.

7. The CMUT sensor-based integrated transceiver detection system according to claim 1, characterized in that: The high-voltage pulse circuit generation module uses the MAX14808 main control chip as the main control module of the system. The port of a single MAX14808 chip connected to the FPGA consists of 20 IO ports, of which 4 are divided into 4 current control ports and a mode selection port. The power supply is +30VPP and -30VPP. Then the entire system outputs 8 positive and negative pulse signals with a duty cycle of 50%. The entire system uses a total of 4 high-voltage pulse excitation chips and generates 64 pulse excitation signals.

8. The CMUT sensor-based integrated transceiver detection system according to claim 1, characterized in that: The LC impedance matching module includes the following steps when performing impedance matching: Step 1: In the LC tuning network, design and calculate the CMUT equivalent circuit resistance and CMUT equivalent circuit series resonant frequency based on the CMUT structural parameters; Step 2: Using the Smith chart, combined with the reactance of the CMUT equivalent circuit and the series resonant frequency of the CMUT equivalent circuit, adjust the inductance of the tuning inductor L and the capacitance of the tuning capacitor C so that the overall reactance of the CMUT equivalent circuit and the LC tuning network is 0 and the resistance is 50Ω±5Ω. This gives the final parameters for the inductance of the inductor L and the capacitance of the tuning capacitor C.

9. The CMUT sensor-based integrated transceiver detection system according to claim 1, characterized in that: The echo signal amplification module includes a TIA transimpedance amplifier circuit, an LNA in-phase proportional amplifier circuit, and a BPF bandpass filter, which realizes secondary amplification and filtering of high-frequency weak echo signals.

10. The CMUT sensor-based integrated transceiver detection system according to claim 1, characterized in that: The analog-to-digital conversion module uses the AFE5832 chip as the main control module, which integrates a signal attenuator, amplifier, filter, and ADC conversion channel. Through internal time division multiplexing, 32-channel data reception can be achieved with 16 channels.

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