Signal processing architecture of electro-optical front-end reconnaissance system

Abstract

The invention relates to the technical field of electronic reconnaissance signal processing, in particular to a signal processing architecture of an electro-optical front-end reconnaissance system, which comprises a digital-to-analog conversion module for sampling an input radio-frequency signal and converting the input radio-frequency signal into a digital signal; the time-frequency conversion module is used for converting time domain information of the digital signal into frequency domain information; the frequency domain analysis module obtains frequency domain parameters by using a peak detection algorithm, a bandwidth detection algorithm and a defuzzification algorithm based on phase remainder matching; the frequency conversion filtering module is used for moving the digital signal to zero frequency and filtering the digital signal according to a frequency domain parameter to obtain mixed and filtered IQ data; and the time domain analysis module is responsible for analyzing the IQ data through the GO-CAFAR threshold detection circuit to obtain a time domain parameter of the signal, and outputting the IQ data, the frequency domain parameter and the time domain parameter to terminal equipment. According to the architecture, the transmission pressure of frequency domain reconnaissance signals can be reduced, and the frequency resolution and sensitivity of a system are improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of electronic reconnaissance signal processing, and in particular to a signal processing architecture of an electro-optical front-end reconnaissance system. Background Art

[0002] In recent years, electronic reconnaissance technology has also undergone major changes, and the electromagnetic environment is considered to be a unique field. The electromagnetic spectrum resources in the modern environment are extremely complex and crowded. The electromagnetic radiation covering multiple elements such as the command and control system, detection system, reactance system, communication system and guidance system is extremely complex and fiercely confrontational, which also puts higher requirements on the signal processing of the electronic reconnaissance system. The signal processing of the electronic reconnaissance system can be divided into two parts based on the type of processing parameters, namely time domain parameter processing and frequency domain parameter processing. The time domain parameter processing is mainly to obtain the pulse amplitude, pulse repetition period, pulse width and arrival time of the target signal, and the frequency domain parameter processing includes the measurement of signal carrier frequency, bandwidth, modulation type and other parameters.

[0003] Traditional signal processing technologies for electronic reconnaissance systems include digital channelization technology and FFT technology (Fast Fourier Transform system). Digital channelization technology builds digital filter groups with different center frequencies and bandwidths on FPGA, and outputs corresponding frequency information according to the center frequency and bandwidth of the filter group. This technology has strong anti-interference ability and high sensitivity, but its frequency resolution is limited. If a higher frequency resolution is to be achieved, the number and order of digital filters need to be increased, which will increase the computational complexity and bring a great burden to hardware resources. FFT technology builds a complex multiplier on FPGA to perform butterfly operations on the input data sequence to obtain the frequency domain information of the signal. This technology can process the input signal in a pipeline, has a high computing speed and excellent real-time performance, but obtaining a higher frequency resolution requires more FFT points, which will occupy a large amount of FPGA storage resources and computing resources, thereby reducing the overall hardware performance.

[0004] For an electro-optical front-end reconnaissance receiver with instantaneous, ultra-wideband electromagnetic interception capabilities, the electromagnetic signals in the environment are folded and compressed into the first repetition frequency interval of the optical frequency comb, which requires the signal processing architecture to have higher frequency resolution and sensitivity to meet the requirements for parsing frequency folded signals. In order to further analyze the modulation type and individual characteristics of the electromagnetic signal, the IQ data after mixing and filtering needs to be transmitted to the terminal processing device through the network port, which places higher requirements on the data transmission and storage capabilities of the signal processing architecture. Traditional signal processing architectures are difficult to simultaneously meet the requirements of sensitivity, resource occupancy, and frequency resolution. The low data transmission capacity also makes it impossible to transmit IQ data in real time to the terminal device for subsequent analysis and processing. Therefore, improving and upgrading the signal processing architecture of the electro-optical front-end reconnaissance system is an urgent problem to be solved. Summary of the invention

[0005] In view of this, an embodiment of the present application proposes a signal processing architecture for an electro-optical front-end reconnaissance system, which can reduce the transmission pressure of the signal for frequency domain reconnaissance, reasonably optimize the hardware resource occupancy rate, and further enhance the interception probability while improving the system frequency resolution and sensitivity.

[0006] In the first aspect, the embodiment of the present application proposes a signal processing architecture of an electro-optical front-end reconnaissance system, and the signal processing architecture includes: an analog-to-digital conversion module, a time-frequency conversion module, a frequency domain analysis module, a variable frequency filtering module and a time domain analysis module, the time-frequency conversion module is respectively connected to the analog-to-digital conversion module and the frequency domain analysis module, the variable frequency filtering module is respectively connected to the analog-to-digital conversion module, the frequency domain analysis module and the time domain analysis module, the analog-to-digital conversion module, the time-frequency conversion module, the time domain analysis module and the variable frequency filtering module are all implemented on the FPGA, and the frequency domain analysis module is implemented on the DSP; the digital-to-analog conversion module is responsible for the input RF signal The module is responsible for sampling and converting the digital signal into a digital signal; the time-frequency conversion module is responsible for converting the time domain information of the digital signal into frequency domain information; the frequency domain analysis module is responsible for obtaining the frequency domain parameters by using the peak detection algorithm, the bandwidth detection algorithm, and the deambiguation algorithm based on the phase residue matching; the variable frequency filtering module is responsible for moving the digital signal to zero frequency and filtering it according to the frequency domain parameters to obtain the mixed and filtered IQ data; the time domain analysis module is responsible for analyzing the IQ data through the GO-CAFAR threshold detection circuit to obtain the time domain parameters of the signal, and outputting the IQ data, frequency domain parameters and time domain parameters to the terminal device.

[0007] In some optional embodiments, the digital-to-analog conversion module is implemented on the FPGA through an ADC chip.

[0008] In some optional embodiments, the time-frequency conversion module is implemented by building a 256-point FFT on the FPGA, using a pipeline structure to sample and calculate the digital signal, and converting the time domain information of the digital signal into frequency domain information.

[0009] In some optional embodiments, the frequency domain analysis module is implemented on the DSP, the center frequency and bandwidth are obtained through the peak detection algorithm and the bandwidth detection algorithm, and the frequency folded signal is analyzed by the deambiguation algorithm based on phase residue matching to obtain the RF signal frequency before compression.

[0010] In some optional embodiments, the frequency conversion filtering module is implemented by building a mixer and a bandpass filter in the FPGA, moving the digital signal to zero frequency and filtering the digital signal according to the center frequency, bandwidth and RF signal frequency before compression to obtain IQ data after mixing and filtering.

[0011] In some optional embodiments, the time domain analysis module is implemented by building a GO-CAFAR threshold detection circuit in an FPGA. The GO-CAFAR threshold detection circuit analyzes the time domain information of the IQ data and obtains the pulse amplitude, period and pulse width, and finally completes the measurement of the center frequency, bandwidth, pulse amplitude, pulse repetition period and pulse width of the RF signal, and transmits the IQ data, frequency domain parameters and time domain parameters to the terminal device through the network port for subsequent processing.

[0012] The signal processing architecture of an electro-optical front-end reconnaissance system proposed in the embodiment of the present application overcomes the problems of the traditional electronic reconnaissance signal processing architecture that it is difficult to simultaneously have resource occupancy, frequency resolution, and high IQ data transmission pressure, etc., through FFT technology, matched filtering technology, and frequency domain analysis algorithm design. This signal processing architecture is perfectly suitable for reconnaissance receivers based on frequency folded signals. It has a high frequency resolution and can effectively meet the requirements for frequency folded signal analysis, reducing signal storage pressure and transmission pressure. It can transmit the mixed and filtered IQ data to the terminal device in real time for subsequent analysis and processing, optimizing the overall hardware performance. Compared with traditional channelization technology, this signal processing architecture saves 10% of hardware resources, while improving the system frequency resolution and sensitivity, it can further improve the probability of interception, and has strong universal applicability.

[0013] In the second aspect, an embodiment of the present application proposes a signal processing method for an electro-optical front-end reconnaissance system, which is implemented based on the signal processing architecture of an electro-optical front-end reconnaissance system as described above, and the method includes the following steps: sampling the input RF signal and converting it into a digital signal; converting the time domain information of the digital signal into frequency domain information; obtaining the frequency domain parameters of the digital signal using a peak detection algorithm, a bandwidth detection algorithm, and a deambiguation algorithm based on phase residue matching; moving the digital signal to zero frequency, and filtering the digital signal according to the frequency domain parameters to obtain mixed and filtered IQ data; performing time domain analysis on the IQ data through a GO-CAFAR threshold detection circuit to obtain the time domain parameters of the signal, and outputting the IQ data, frequency domain parameters and time domain parameters to the terminal device.

[0014] In a third aspect, an embodiment of the present application proposes an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute a signal processing method for an electro-optical front-end reconnaissance system as described in the second aspect above.

[0015] In a fourth aspect, an embodiment of the present application proposes a computer-readable storage medium storing a computer program, which, when executed by a processor, can implement a signal processing method for an electro-optical front-end reconnaissance system as described in the second aspect above.

[0016] It can be understood that the beneficial effects of the second to fourth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the related technologies, the drawings required for use in the embodiments of the present application or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 It is a structural schematic diagram of a signal processing architecture of an electro-optical front-end reconnaissance system provided in an embodiment of the present application;

[0019] Figure 2 It is a structural schematic diagram of an electro-optical front-end reconnaissance system provided in one embodiment of the present application;

[0020] Figure 3It is a structural schematic diagram of a circuit board of a signal processing architecture of an electro-optical front-end reconnaissance system provided in one embodiment of the present application;

[0021] Figure 4 is a flowchart of a signal processing method of an electro-optical front-end reconnaissance system provided in another embodiment of the present application;

[0022] Figure 5 It is a structural schematic diagram of an electronic device provided in another embodiment of the present application. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below in conjunction with the accompanying drawings. In the various embodiments of the present application, many technical details are proposed in order to make the reader better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can also be implemented. The division of the following embodiments is only for the convenience of description, and the specific implementation mode of the present application should not constitute any limitation. The various embodiments can be combined with each other and referenced to each other under the premise of no contradiction.

[0024] An embodiment of the present application proposes a signal processing architecture for an electro-optical front-end reconnaissance system. The implementation details of the signal processing architecture for an electro-optical front-end reconnaissance system proposed in this embodiment are described in detail below. The signal processed in this embodiment is particularly suitable for a reconnaissance receiver based on frequency folding. The following content is only provided for the convenience of understanding the implementation details and is not necessary for the implementation of this solution. The specific structure of the signal processing architecture for an electro-optical front-end reconnaissance system proposed in this embodiment is as follows: Figure 1 As shown, the signal processing architecture includes: an analog-to-digital conversion module 11, a time-frequency conversion module 12, a frequency domain analysis module 13, a variable frequency filtering module 14 and a time domain analysis module 15.

[0025] The time-frequency conversion module 12 is connected to the analog-to-digital conversion module 11 and the frequency domain analysis module 13 respectively, and the frequency conversion filtering module 14 is connected to the analog-to-digital conversion module 11, the frequency domain analysis module 13 and the time domain analysis module 15 respectively. The analog-to-digital conversion module 11, the time-frequency conversion module 12, the time domain analysis module 14 and the frequency conversion filtering module 15 are all implemented on the FPGA, and the frequency domain analysis module 13 is implemented on the DSP.

[0026] In a specific implementation, the external RF signal enters the digital-to-analog conversion module 11, which is responsible for sampling the input RF signal and converting it into a digital signal, and inputting the digital signal into the time-frequency conversion module 12 and the frequency conversion filter module 14 respectively. After receiving the digital signal, the time-frequency conversion module 12 is responsible for converting the time domain information of the digital signal into frequency domain information, and providing the frequency domain information to the frequency domain analysis module 13. The frequency domain analysis module 13 is responsible for processing the frequency domain information using the peak detection algorithm, the bandwidth detection algorithm, and the defuzzification algorithm based on the phase residue matching, obtaining the frequency domain parameters and providing them to the frequency conversion filter module 14. The frequency conversion filter module 14 is responsible for moving the digital signal to zero frequency and filtering it according to the frequency domain parameters to obtain the mixed and filtered IQ data, and inputting the IQ data into the time domain analysis module 15. The time domain analysis module 15 is responsible for performing time domain analysis on the IQ data through the GO-CAFAR threshold detection circuit, obtaining the time domain parameters of the signal, and outputting the IQ data, frequency domain parameters and time domain parameters to the external terminal device.

[0027] In one example, the circuit structure of the electro-optical front-end reconnaissance system can be as follows: Figure 2 As shown, the structure of the circuit board of the signal processing architecture of the electro-optical front-end reconnaissance system can be as follows Figure 3 As shown in the figure, the highly integrated signal processing architecture processes the RF signal sent by the front end, and finally outputs the IQ data and time-frequency parameters to the back-end device. The highly integrated signal processing architecture takes up very little space and can meet the lightweight and miniaturization requirements of the electro-optical front-end reconnaissance system.

[0028] In one example, the digital-to-analog conversion module is implemented on the FPGA through an ADC chip.

[0029] In one example, the time-frequency conversion module is implemented by building a 256-point FFT (complex multiplier of butterfly operation) on the FPGA. The time-frequency conversion module uses a pipeline structure to sample and calculate the digital signal to convert the time domain information of the digital signal into frequency domain information.

[0030] In one example, the frequency domain analysis module is implemented on the DSP. The frequency domain analysis module obtains the center frequency and bandwidth of the signal through the peak detection algorithm and the bandwidth detection algorithm, and uses the defuzzification algorithm based on phase residue matching to analyze the frequency folded signal to obtain the frequency of the RF signal before compression. The center frequency, bandwidth and frequency of the RF signal before compression are the frequency domain parameters analyzed by the frequency domain analysis module.

[0031] In one example, the frequency conversion filtering module is implemented by building a mixer and a bandpass filter in an FPGA. The frequency conversion filtering module moves the digital signal to zero frequency and filters the digital signal according to the center frequency, bandwidth, and RF signal frequency before compression to obtain IQ data after mixing and filtering.

[0032] In one example, the time domain analysis module is implemented by building a GO-CAFAR threshold detection circuit in an FPGA. The time domain analysis module analyzes the time domain information of the IQ data through the GO-CAFAR threshold detection circuit and obtains time domain parameters including but not limited to pulse amplitude, period and pulse width. Finally, the center frequency, bandwidth, pulse amplitude, pulse repetition period and pulse width of the RF signal are measured, and the IQ data, frequency domain parameters and time domain parameters are transmitted to the terminal device (back-end device) through the network port for subsequent processing.

[0033] In one example, the selected FPGA model is XC7K410T-2FFG900I, and the selected DSP model is FT-M6678N. The entire signal processing architecture uses a total of 1204 multipliers, 19 BUFGs, 27765 LUTs and 582 BRAMs. The FPGA resource utilization rate is 70%, and the signal processing time is about 100μs to 250μs. Compared with traditional channelization technology, it saves 10% of hardware resources.

[0034] This embodiment, through FFT technology, matched filtering technology and frequency domain analysis algorithm design, overcomes the problems of traditional electronic reconnaissance signal processing architecture that it is difficult to simultaneously have resource occupancy, frequency resolution, IQ data transmission pressure and other issues. This signal processing architecture can be perfectly applied to reconnaissance receivers based on frequency folded signals, has a high frequency resolution, can effectively meet the requirements for frequency folded signal analysis, reduces signal storage pressure and transmission pressure, can transmit the mixed and filtered IQ data to the terminal device in real time for subsequent analysis and processing, and optimizes the overall hardware performance. Compared with traditional channelization technology, this signal processing architecture saves 10% of hardware resources, while improving the system frequency resolution and sensitivity, it can further improve the probability of interception, and has strong universal applicability.

[0035] It is worth mentioning that all modules involved in this embodiment are logic modules. In practical applications, a logic unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, in order to highlight the innovative part of this application, this embodiment does not introduce units that are not closely related to solving the technical problems proposed by this application, but this does not mean that there are no other units in this embodiment.

[0036] Another embodiment of the present application proposes a signal processing method for an electro-optical front-end reconnaissance system, which is specifically implemented based on the signal processing architecture of an electro-optical front-end reconnaissance system as described above. The implementation details of the signal processing method for an electro-optical front-end reconnaissance system proposed in this embodiment are described in detail below. The following content is only for the convenience of understanding the implementation details, and is not necessary for the implementation of this example. The specific process of the signal processing method for an electro-optical front-end reconnaissance system proposed in this embodiment is as follows: Figure 4 As shown, including:

[0037] Step 21, sampling the input radio frequency signal and converting it into a digital signal.

[0038] Step 22: Convert the time domain information of the digital signal into frequency domain information.

[0039] Step 23, using a peak detection algorithm, a bandwidth detection algorithm, and a deambiguation algorithm based on phase residue matching to obtain frequency domain parameters of the digital signal.

[0040] Step 24, shift the digital signal to zero frequency, and filter the digital signal according to the frequency domain parameters to obtain IQ data after mixing and filtering.

[0041] Step 25, analyze the IQ data through the GO-CAFAR threshold detection circuit to obtain the time domain parameters of the signal, and output the IQ data, frequency domain parameters and time domain parameters to the terminal device

[0042] The step division of the above methods is only for clear description. When implemented, they can be combined into one step or some steps can be split and decomposed into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this application; adding insignificant modifications to the algorithm or process or introducing insignificant designs without changing the core design of the algorithm and process are all within the scope of protection of this application.

[0043] It is not difficult to find that this embodiment is a method embodiment corresponding to the above embodiment, and this embodiment can be implemented in conjunction with the above embodiment. The relevant technical details and technical effects mentioned in the above embodiment are still valid in this embodiment, and in order to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied in the above embodiment.

[0044] Another embodiment of the present application provides an electronic device, whose specific structure is as follows: Figure 5As shown, it includes: at least one processor 31; and a memory 32 that is communicatively connected to the at least one processor 31; wherein the memory 32 stores instructions that can be executed by the at least one processor 31, and the instructions are executed by the at least one processor 31 so that the at least one processor 31 can execute a signal processing method for an electro-optical front-end reconnaissance system as described in the above-mentioned method embodiments.

[0045] Among them, the memory and the processor are connected in a bus manner, and the bus can include any number of interconnected buses and bridges, and the bus can connect various circuits of one or more processors and memories together. The bus can also connect various other circuits such as peripheral devices, voltage regulators and power management circuits, which are well known in the art and will not be further described in this article. The bus interface is responsible for providing an interface between the bus and the transceiver. The transceiver can be one component or multiple components, such as multiple receivers and transmitters, providing a unit for communicating with various other devices on a transmission medium. The data processed by the processor is transmitted on a wireless medium through an antenna, and further, the antenna also receives data and transmits the data to the processor.

[0046] The processor is responsible for managing the bus and general processing, and can also provide various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory can be used to store data used by the processor when performing operations.

[0047] Another embodiment of the present application provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it can implement a signal processing method for an electro-optical front-end reconnaissance system as described in the above method embodiments.

[0048] That is, those skilled in the art can understand that all or part of the steps in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a program, and the program is stored in a storage medium, including several instructions for making a device (which can be a single-chip microcomputer, chip, etc.) or a processor execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes, but is not limited to: U disk, mobile hard disk, ROM (Read-Only Memory), RAM (Random Access Memory), disk or optical disk and other media that can store program codes.

[0049] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present application, and in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present application.

Claims

1. A signal processing architecture for an electro-optical front-end reconnaissance system, characterized in that: The signal processing architecture includes: an analog-to-digital conversion module, a time-frequency conversion module, a frequency domain analysis module, a variable frequency filtering module and a time domain analysis module, the time-frequency conversion module is respectively connected to the analog-to-digital conversion module and the frequency domain analysis module, the variable frequency filtering module is respectively connected to the analog-to-digital conversion module, the frequency domain analysis module and the time domain analysis module, the analog-to-digital conversion module, the time-frequency conversion module, the time domain analysis module and the variable frequency filtering module are all implemented on the FPGA, and the frequency domain analysis module is implemented on the DSP; The digital-to-analog conversion module is responsible for sampling the input RF signal and converting it into a digital signal; The time-frequency conversion module is responsible for converting the time domain information of the digital signal into frequency domain information; The frequency domain analysis module is responsible for obtaining frequency domain parameters using peak detection algorithm, bandwidth detection algorithm, and deambiguation algorithm based on phase residue matching; The frequency conversion filter module is responsible for moving the digital signal to zero frequency and filtering it according to the frequency domain parameters to obtain the mixed and filtered IQ data; The time domain analysis module is responsible for analyzing the IQ data through the GO-CAFAR threshold detection circuit, obtaining the time domain parameters of the signal, and outputting the IQ data, frequency domain parameters and time domain parameters to the terminal device.

2. The signal processing architecture of the electro-optical front-end reconnaissance system according to claim 1, characterized in that: The digital-to-analog conversion module is implemented on the FPGA through the ADC chip.

3. The signal processing architecture of the electro-optical front-end reconnaissance system according to claim 2, characterized in that: The time-frequency conversion module is implemented by building a 256-point FFT on the FPGA, using a pipeline structure to sample and calculate the digital signal, and converting the time domain information of the digital signal into frequency domain information.

4. The signal processing architecture of the electro-optical front-end reconnaissance system according to claim 3, characterized in that: The frequency domain analysis module is implemented on the DSP. The center frequency and bandwidth are obtained through the peak detection algorithm and the bandwidth detection algorithm. The frequency folding signal is analyzed by the deambiguation algorithm based on phase residue matching to obtain the RF signal frequency before compression.

5. The signal processing architecture of the electro-optical front-end reconnaissance system according to claim 4, characterized in that: The frequency conversion filtering module is implemented by building a mixer and a bandpass filter in the FPGA, which moves the digital signal to zero frequency and filters the digital signal according to the center frequency, bandwidth and RF signal frequency before compression to obtain IQ data after mixing and filtering.

6. The signal processing architecture of the electro-optical front-end reconnaissance system according to claim 5, characterized in that: The time domain analysis module is realized by building a GO-CAFAR threshold detection circuit in the FPGA. The GO-CAFAR threshold detection circuit analyzes the time domain information of the IQ data and obtains the pulse amplitude, period and pulse width. Finally, the center frequency, bandwidth, pulse amplitude, pulse repetition period and pulse width of the RF signal are measured, and the IQ data, frequency domain parameters and time domain parameters are transmitted to the terminal device through the network port for subsequent processing.

7. A signal processing method for an electro-optical front-end reconnaissance system, characterized in that: Based on the signal processing architecture of an electro-optical front-end reconnaissance system according to any one of claims 1 to 6, the method comprises: Sample the input RF signal and convert it into a digital signal; Convert the time domain information of digital signals into frequency domain information; The frequency domain parameters of the digital signal are obtained by using the peak detection algorithm, the bandwidth detection algorithm, and the defuzzification algorithm based on phase residue matching; Move the digital signal to zero frequency, and filter the digital signal according to the frequency domain parameters to obtain the mixed and filtered IQ data; The IQ data is analyzed by the GO-CAFAR threshold detection circuit to obtain the time domain parameters of the signal, and the IQ data, frequency domain parameters and time domain parameters are output to the terminal device.

8. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; Wherein, the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the signal processing method of the electro-optical front-end reconnaissance system as described in claim 7.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, it can implement the signal processing method of an electro-optical front-end reconnaissance system as claimed in claim 7.

Images