High-precision circuit board and manufacturing method thereof

Abstract

The application discloses a high-precision circuit board and a preparation method thereof. The preparation method comprises the following steps: obtaining a preset circuit diagram; setting a plurality of conductive layer groups according to the preset circuit diagram; wherein the conductive layers forming the same blind hole or buried hole are one conductive layer group, and the adjacent conductive layers without forming the blind hole or the buried hole are one conductive layer group; each conductive layer group comprises a core plate; the conductive layers are laminated and placed, the adhesive layers are placed between the core plates of the same group or between the core plate and the conductive layers, and the auxiliary layers are placed between the different conductive layer groups; the laminated and placed conductive layers, the adhesive layers and the auxiliary layers are compressed, and the auxiliary layers are stripped after the compression, so that the conductive layer groups form the sub-plates; holes are drilled at the preset positions of the sub-plates to form the through holes; the sub-plates are laminated and placed, and the adhesive layers are placed between the adjacent sub-plates; and the laminated and placed sub-plates and the adhesive layers are compressed. By adopting the technical scheme, the alignment degree and the warping problem caused by the asymmetric structure of the sub-plates compressed respectively can be solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of printed circuit board, and particularly to a high-precision circuit board and a preparation method thereof. BACKGROUND

[0002] The stepped gold finger product is widely used, which can be applied not only to the conventional memory storage field, but also to the current trend of AI server acceleration card product, and is a very important product in the current mainstream market. The top three server groups in the world are all developing such products to quickly occupy the AI server acceleration card market.

[0003] The structure of the stepped gold finger printed circuit board for the AI server acceleration card product is mainly 18 layers, which is composed of 8 core boards and 2 copper foil layers. Due to the need of product design, there are buried holes or blind holes. The conventional method is to press and form multiple sub-boards respectively, then form through holes in the sub-boards, and then press and form multiple sub-boards to form the final required 18 conductive layers, and make the through holes of the sub-boards form buried holes or blind holes. Inevitably, there is an asymmetric structure of copper foil and core board in the pressing process of the sub-boards. Due to the asymmetry of the core board and the copper foil, the sub-boards are not consistent in heating and shrinking in the pressing machine, which will inevitably cause serious misalignment and warping problems, which will make it impossible to meet the high alignment requirement, thereby limiting the development and development of the AI server acceleration card product. SUMMARY

[0004] The present application provides a high-precision circuit board and a preparation method thereof to solve the technical problems of misalignment and warping caused by the asymmetric structure of the sub-boards caused by separate pressing.

[0005] According to one aspect of the present application, a preparation method of a high-precision circuit board is provided, the high-precision circuit board comprising at least one blind hole or buried hole;

[0006] The preparation method comprises:

[0007] obtaining a preset circuit diagram of the high-precision circuit board;

[0008] According to the preset circuit diagram, a plurality of conductive layer groups are set; wherein the adjacent conductive layers forming the same blind hole or buried hole are one conductive layer group, and the adjacent conductive layers not forming the blind hole or buried hole are one conductive layer group; the conductive layer group comprises a core board provided with two conductive layers;

[0009] stacking each conductive layer, placing an adhesive layer between the core boards in the same group or between the core board and the conductive layer, and placing an auxiliary layer between different adjacent conductive layer groups;

[0010] Laminating the stacked conductive layer, the adhesive layer, and the auxiliary layer, and peeling off the auxiliary layer after lamination, so that the conductive layer group forms a sub-board;

[0011] Drilling a hole at a preset position of at least one of the sub-boards to form a through hole;

[0012] stacking the sub-boards and placing the adhesive layer between different and adjacent sub-boards;

[0013] The sub-board and the adhesive layer are laminated and laminated to form the through hole into the blind hole or the buried hole.

[0014] Optionally, at least part of the conductive layer group includes a single conductive layer.

[0015] Optionally, the uppermost and lowermost conductive layer groups include an odd number of conductive layers;

[0016] According to the preset circuit diagram, multiple conductive layer groups are set, including:

[0017] According to the preset circuit diagram, a plurality of conductive layer groups are divided; wherein, the side close to the adjacent conductive layer group in the top and bottom conductive layer groups is the single conductive layer, and / or, the side away from the adjacent conductive layer group in the top and bottom conductive layer groups is the core board.

[0018] Optionally, the uppermost and lowermost conductive layer groups include an odd number of conductive layers;

[0019] According to the preset circuit diagram, multiple conductive layer groups are set, including:

[0020] According to the preset circuit diagram, a plurality of conductive layer groups are divided; wherein, the side of the topmost and bottommost conductive layer groups away from the adjacent conductive layer group is the single conductive layer, and / or, the side of the topmost and bottommost conductive layer groups close to the adjacent conductive layer group is the core board.

[0021] Optionally, the auxiliary layer includes the single conductive layer;

[0022] The uppermost and / or lowermost conductive layer group includes an odd number of conductive layers;

[0023] According to the preset circuit diagram, multiple conductive layer groups are set, including:

[0024] According to the preset circuit diagram, a plurality of conductive layer groups are divided; wherein, one of the uppermost layer in the uppermost conductive layer group and the lowermost layer in the lowermost conductive layer group is the single conductive layer, and the other is the core board;

[0025] stacking each of the conductive layers, and placing a bonding layer between the core plates of the same group or between the core plates and the conductive layers, and placing an auxiliary layer between different and adjacent groups of the conductive layers, comprising:

[0026] stacking each of the conductive layers, and placing a bonding layer between the core plates of the same group or between the core plates and the conductive layers, and placing the auxiliary layer between different and adjacent groups of the conductive layers, and further placing the auxiliary layer above the uppermost group of the conductive layers or below the lowermost group of the conductive layers, so that the upper and lower edge conductive layers in all the conductive layers are the single-layer conductive layers.

[0027] Optionally, the conductive layer comprises a copper layer; and the auxiliary layer comprises at least one copper foil.

[0028] Optionally, the auxiliary layer comprises two copper foils.

[0029] placing an auxiliary layer between different and adjacent groups of the conductive layers, comprising:

[0030] placing two copper layers between different and adjacent groups of the conductive layers, the smooth surface of the copper foil facing the adjacent group of the conductive layers, and the rough surface of the copper foil facing the inner side of the auxiliary layer.

[0031] Optionally, the auxiliary layer comprises two copper foils, and the bonding layer is located between the two copper foils.

[0032] Optionally, the thickness of the copper foil is d; and 12um≤d≤70um.

[0033] According to another aspect of the present application, there is provided a high-precision circuit board prepared by the method for preparing a high-precision circuit board according to any one of the above.

[0034] The technical solution of the present application can increase the thickness of the board in one pressing process, and can also include some conductive layers that should be exposed to the outer layer in the pressing process in the middle position of the film layer structure, thereby improving the uniformity of heating in the pressing process, making it easier to control the expansion and contraction generated in the pressing process, and effectively reducing the layer deviation and warping generated in the pressing process. In addition, pressing different conductive layer groups in the same process makes the consistency of the film layer expansion and contraction data of different conductive layer groups better, which is conducive to improving the alignment accuracy and simplifying the subsequent expansion and contraction adjustment process, and can effectively solve the technical problems of alignment accuracy and warping caused by asymmetric structure when each conductive layer group is pressed separately. The embodiments of the present application can effectively solve the preparation problem of AI server acceleration cards, thereby promoting the rapid development of AI server acceleration card technology in the future.

[0035] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 This is a flow chart of a method for preparing a high-precision circuit board provided by an embodiment of the present invention;

[0038] Figure 2 This is a schematic diagram of the film layer structure of a preset circuit diagram of a high-precision circuit board provided by an embodiment of the invention;

[0039] Figure 3 This is a schematic diagram of a film layer structure in a stacked arrangement provided by an embodiment of the present invention;

[0040] Figure 4 Schematic diagram of the film structure of a laminated sub-plate provided by an embodiment of the present invention;

[0041] Figure 5 This is a schematic diagram of a film layer structure in another stacking arrangement provided by an embodiment of the present invention;

[0042] Figure 6 This is a schematic diagram of a film layer structure in another stacking arrangement provided by an embodiment of the present invention;

[0043] Figure 7 This is a schematic diagram of a film layer structure in another stacking arrangement provided by an embodiment of the present invention;

[0044] Figure 8 This is a schematic diagram of a film layer structure in another stacking arrangement provided by an embodiment of the present invention;

[0045] Figure 9 This is a schematic diagram of a film layer structure in another stacking arrangement provided by an embodiment of the present invention;

[0046] Figure 10 This is a schematic diagram of a film layer structure in another stacking arrangement provided by an embodiment of the present invention;

[0047] Figure 11 This is a schematic diagram of a membrane layer structure in another stacking arrangement provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0048] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0049] It should be noted that the terms "including" and "having" and any variations thereof in the specification and claims of the present invention and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or are inherent to these processes, methods, products or apparatuses.

[0050] Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work shall fall within the scope of protection of the present invention. The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention.

[0051] Figure 1 This is a flow chart of a method for preparing a high-precision circuit board provided by an embodiment of the present invention, with reference to Figure 1 , the preparation method comprises:

[0052] S1001. Obtain a preset circuit diagram of a high-precision circuit board.

[0053] Among them, the high-precision circuit board of the embodiment of the present invention can be applied to AI server acceleration card products, and can also be applied to computer system boards, mainboards and other products. Specifically, it can be a stepped gold finger printed circuit board, but is not limited to this.

[0054] The preset circuit diagram includes the circuit patterns of each film layer in the high-precision circuit board, as well as the positions of blind holes and / or buried holes and their connection relationships. For example, taking the high-precision circuit board including 18 layers (L1-L18) of conductive layers 10 as an example, Figure 2 This is a schematic diagram of the film structure of a preset circuit diagram of a high-precision circuit board provided by an embodiment of the invention, with reference to Figure 2 The preset circuit diagram shows the structure of each film layer, the location of blind holes and / or buried holes and their connection relationship, and also shows the bonding layer 102, which can bond and insulate the adjacent conductive layers 10. In addition, the preset circuit diagram can also show the circuit pattern of each film layer structure ( Figure 2 not shown).

[0055] S1002. According to a preset circuit diagram, a plurality of conductive layer groups are set; wherein, adjacent conductive layers that need to form the same blind hole or buried hole are one conductive layer group, and adjacent conductive layers that do not need to form blind holes or buried holes are one conductive layer group; each conductive layer group includes a core board provided with two conductive layers.

[0056] Exemplary, reference Figure 2 , the first conductive layer group 01 and the second conductive layer group 02 can be divided according to the film layer schematic diagram of the preset circuit diagram. The conductive layer groups (01, 02) can include multiple core boards 22, and the core boards 22 include a substrate layer 20 and conductive layers 10 located on both sides of the substrate layer. In addition, the conductive layer groups (01, 02) can also include a single conductive layer 11. In an optional embodiment, the conductive layer 10 can be a copper layer, and the single conductive layer 11 can be a copper foil.

[0057] In an optional embodiment, multiple conductive layer groups are provided according to a preset circuit diagram, including: dividing the multiple conductive layer groups according to the preset circuit diagram, and forming a preset circuit on the conductive layer 10 located within the conductive layer group. After forming the preset circuit, the circuit surface may be browned to increase the bonding strength between the conductive layer 10 and the adhesive layer 102 during the subsequent lamination process.

[0058] Among them, the preset circuits of different conductive layers 10 may be different, and the conductive layers located on the surface of the conductive layer group (such as the first layer L1, the seventh layer L7, the eighth layer L8, and the eighteenth layer L18) may temporarily not form preset circuits to avoid damage to the preset circuits on the surface of the conductive layer group during the pressing process.

[0059] S1003. Stack the conductive layers, place adhesive layers between the core plates in the same group or between the core plates and the conductive layers, and place auxiliary layers between different and adjacent conductive layer groups.

[0060] For example, Figure 3 Schematic diagram of a film layer structure in a stacked arrangement according to an embodiment of the present invention. Figure 3 As shown, an adhesive layer 102 is placed between each conductive layer structure (core board 22, single conductive layer 11) in the same conductive layer group, and an auxiliary layer 30 is placed between different conductive layer groups.

[0061] The adhesive layer 102 can be a prepreg, also known as a PP sheet, which softens and melts at high temperatures and solidifies upon cooling, bonding adjacent film layers. The auxiliary layer 30 must be removable and should not introduce contaminants during the lamination and lamination process. Auxiliary layers 30 include, but are not limited to, copper foil, aluminum sheet, steel plate, and copper-clad laminate. Auxiliary layer 30 can be a thick, molded metal material that provides a certain degree of hardness during lamination, helping to minimize post-lamination misalignment and warping.

[0062] S1004 , laminating the stacked conductive layer, adhesive layer, and auxiliary layer, and peeling off the auxiliary layer after lamination, so that the conductive layer group forms a sub-board.

[0063] Specifically, a suitable preset temperature can be selected based on the material of the adhesive layer 102, and the stacked conductive layer, adhesive layer, and auxiliary layer can be heated and a certain pressure can be applied to convert the adhesive layer 102 from a solid state to a molten state, thereby bonding the adjacent film layer structures (core plate 22, single-layer conductive layer 11). The adhesive layer 102 is not provided between different conductive layer groups, so the different conductive layer groups are not bonded.

[0064] For example, Figure 4 This is a schematic diagram of the film structure of a laminated sub-plate provided by an embodiment of the present invention, with reference to Figure 3 and Figure 4 After the first conductive layer group 01 is pressed together, a first sub-board 91 can be formed. After the second conductive layer group 02 is pressed together, a second sub-board 92 can be formed. Before pressing together, an auxiliary layer 30 is placed between the first conductive layer group 01 and the second conductive layer group 02. On the one hand, this can prevent the first sub-board 91 and the second sub-board 92 formed after pressing from being tightly attached and difficult to separate. On the other hand, this can prevent the pulling force during the separation process of the first sub-board 91 and the second sub-board 92 from damaging or bending the first sub-board 91 and / or the second sub-board 92, thereby preventing unnecessary losses.

[0065] In an optional embodiment, before laminating the stacked conductive layers, adhesive layers and auxiliary layers, the conductive layers 10 in each conductive layer group can be fixed together by riveting. For example, the conductive layers 10 of the L1-L7 layers can be fixed together, and the conductive layers 10 of the L8-L18 layers can be fixed together to reduce the displacement of the film layers during the lamination process.

[0066] S1005 , drilling a hole at a preset position of at least one daughter board to form a through hole.

[0067] For example, continue to refer to Figure 4 , a through hole can be formed in the daughter board by mechanical drilling, and then copper is plated in the through hole and resin plugged ( Figure 4 After plugging the hole, copper can be applied to the surface to prepare the pad ( Figure 4 After plugging the vias, a predetermined circuit can be formed on a portion of the conductive layer 10 located on the surface (e.g., the seventh layer L7 and the eighth layer L8). After forming the predetermined circuit, the circuit surface can be browned to increase the bonding strength between the conductive layer 10 and the adhesive layer 102 during the subsequent lamination process.

[0068] S1006 , stacking the sub-boards and placing adhesive layers between different and adjacent sub-boards.

[0069] Exemplarily, Figure 5 is another schematic diagram of the film layer structure provided by the embodiment of the present application, which is another layer-stacking mode. Figure 5 As shown, the second layer-stacking needs to place the adhesive layer 102 between the sub-panels (91, 92) to bond the first sub-panel 91 and the second sub-panel 92 together after subsequent pressing.

[0070] S1007, pressing the layer-stacked sub-panels and the adhesive layer to make the through holes into blind holes or buried holes.

[0071] Exemplarily, after pressing and bonding the first sub-panel 91 and the second sub-panel 92 together, the preset circuit can be formed on the conductive layers 10 (for example, the first layer L1 and the eighteenth layer L18) located on the surface.

[0072] It should be noted that the figure only exemplarily shows that two conductive layer groups are needed to form the high-precision circuit board, and in other embodiments, the high-precision circuit board can also be formed by pressing three or more conductive layer groups to form multiple sub-panels, and then pressing again after forming through holes in the sub-panels, wherein when the sub-panels at the middle position are provided with through holes, the buried holes of the high-precision circuit board can be formed after pressing again (not shown in the figure).

[0073] It should also be noted that the figure only exemplarily shows that the high-precision circuit board includes 18 conductive layers, and in other embodiments, the high-precision circuit board can also include less than 18 or more than 18 conductive layers, which is not limited by the embodiments of the present application.

[0074] In an optional embodiment, a gold finger can also be formed on the edge of one side or both sides of the surface of the sub-panels before or after pressing the sub-panels, and the gold finger can be correctly aligned and connected with the connector of other devices or circuit boards.

[0075] In the embodiments of the present application, by pressing different conductive layer groups in the same process, the thickness of the board pressed at one time can be increased, and part of the conductive layers (for example, L7 and L8 of Figures 2-5 ) that should be exposed to the outer layer during the pressing process can be included in the middle position of the film layer structure, which increases the uniformity of heating during the pressing process, makes the expansion and contraction generated during the pressing process easier to control, and effectively reduces the layer deviation and warping generated during the pressing; in addition, pressing different conductive layer groups in the same process makes the consistency of the film layer expansion and contraction data of different conductive layer groups better, which is conducive to improving the alignment accuracy and simplifying the subsequent expansion and contraction adjustment process.

[0076] It should be noted that the conductive layer groups are exemplarily shown as Figures 2-5For example, during the lamination process, the outermost layers of the first conductive layer group 01 and the second conductive layer group 02 still have an asymmetric structure with the single conductive layer 11 at the top and the core board 22 at the bottom. However, through the preparation method of the high-precision circuit board provided by the embodiment of the present invention, the first conductive layer group 01 and the second conductive layer group 02 are pressed together in the same process, which improves the heating uniformity of each film layer, and can effectively reduce the layer deviation and warping of the core board 22 at the bottom of the first conductive layer group 01 and the layer deviation and warping of the single conductive layer 11 at the top of the second conductive layer group 02; pressing the first conductive layer group 01 and the second conductive layer group 02 in the same process improves the expansion and contraction consistency of different conductive layer groups, and can also simplify or even omit the expansion and contraction coordination of the core board 22 at the bottom of the first conductive layer group 01 and the single conductive layer 11 at the top of the second conductive layer group 02, which can effectively solve the technical problems of alignment and warping caused by the asymmetric structure when each conductive layer group is pressed together separately. The embodiments of the present invention can effectively solve the preparation difficulties of AI server accelerator cards, thereby promoting the rapid development of AI server accelerator card technology in the future.

[0077] Optional, Figure 6 This is a schematic diagram of a film layer structure in another stacking arrangement provided by an embodiment of the present invention, such as Figure 6 As shown, each conductive layer group includes an even number of conductive layers 10, and each conductive layer group does not include a single conductive layer 11. This creates a symmetrical structure for each conductive layer group, facilitating stress balance among the film layers in the first conductive layer group 01 and the second conductive layer group 02 during the high-temperature, high-pressure lamination process, further reducing post-lamination layer deviation and warping.

[0078] However, the situation where each conductive layer group includes an even number of conductive layers 10 and each conductive layer group does not include a single conductive layer 11 is only applicable to special cases. In actual applications, at least some conductive layer groups include a single conductive layer 11, and the structural asymmetry of the conductive layer group still needs to be considered.

[0079] Optional, Figure 7 This is a schematic diagram of a film layer structure in another stacking arrangement provided by an embodiment of the present invention, such as Figure 7 As shown, the topmost and bottommost conductive layer groups include an odd number of conductive layers 10; multiple conductive layer groups are set according to a preset circuit diagram, including: dividing multiple conductive layer groups according to a preset circuit diagram; wherein, the side close to the adjacent conductive layer group in the topmost and bottommost conductive layer groups is a single conductive layer 11, and / or, the side away from the adjacent conductive layer group in the topmost and bottommost conductive layer groups is a core board 22.

[0080] For example, when the conductive layer group includes an odd number of conductive layers 10, it is inevitable to set a single conductive layer 11 in the conductive layer group. In a feasible embodiment, the single conductive layer 11 can be set at a position close to other conductive layer groups. For example, the single conductive layer 11 can be set at the bottom layer of the top first conductive layer group 01, and / or, at the top layer of the bottom second conductive layer group 02. In this way, when multiple conductive layer groups are pressed together in the same process, the single-layer conductive layer 11 that is prone to layer deviation and warping can be placed in the middle position, which is beneficial to improving the heating uniformity and expansion and contraction uniformity of the single-layer conductive layer 11 during the pressing process, thereby effectively reducing the layer deviation and warping of the single-layer conductive layer 11; in addition, when multiple conductive layer groups are pressed together in the same process, the top layer (first layer L1) and the bottom layer (eighteenth layer L18) are both core boards 22, making the top layer (first layer L1) and the bottom layer (eighteenth layer L18) symmetrical, which is beneficial to reducing the layer deviation and warping of the top layer (first layer L1) and / or the bottom layer (eighteenth layer L18).

[0081] In a feasible embodiment, the single conductive layer 11 may be arranged at a position away from other conductive layer groups. Figure 8 This is a schematic diagram of a film layer structure in another stacking arrangement provided by an embodiment of the present invention, such as Figure 8 As shown, the topmost and bottommost conductive layer groups include an odd number of conductive layers 10; multiple conductive layer groups are set according to a preset circuit diagram, including: dividing multiple conductive layer groups according to a preset circuit diagram; wherein, the side away from the adjacent conductive layer group in the topmost and bottommost conductive layer groups is a single conductive layer 11, and / or, the side close to the adjacent conductive layer group in the topmost and bottommost conductive layer groups is a core board 22.

[0082] For example, the single conductive layer 11 may be disposed at the topmost layer of the topmost first conductive layer group 01 and / or at the bottommost layer of the bottommost second conductive layer group 02. In this way, the topmost layer (first layer L1) and the bottommost layer (eighteenth layer L18) may be symmetrical, which helps to reduce layer deviation and warping of the topmost layer (first layer L1) and / or the bottommost layer (eighteenth layer L18).

[0083] However, due to different practical needs, it may not be possible to make the top layer (the first layer L1) and the bottom layer (the eighteenth layer L18) symmetrical during lamination. Figure 9 This is a schematic diagram of a film layer structure in another stacking arrangement provided by an embodiment of the present invention, such as Figure 9As shown, the topmost and / or bottommost conductive layer groups include an odd number of conductive layers 10; setting multiple conductive layer groups according to a preset circuit diagram includes: dividing multiple conductive layer groups according to the preset circuit diagram; wherein one of the topmost layer in the topmost conductive layer group and the bottommost layer in the bottommost conductive layer group is a single conductive layer 11, and the other is a core board 22. The auxiliary layer 30 may include a single conductive layer 11. Before laminating multiple conductive layer groups at one time, in addition to placing the auxiliary layer 30 (i.e., a single conductive layer 11) between different and adjacent conductive layer groups, the auxiliary layer 30 (i.e., a single conductive layer 11) may also be placed above the topmost conductive layer group or below the bottommost conductive layer group, so that the upper and lower edge conductive layers 10 of all conductive layers 10 are single conductive layers 11.

[0084] For example, based on special design requirements, it is necessary to ensure that the top layer of the combination of the first conductive layer group 01 and the second conductive layer group 02 is a single conductive layer 11, and the bottom layer is a core board 22. In this case, the single conductive layer 11 can be used as the auxiliary layer 30. When stacking the various film layer structures, in addition to placing the auxiliary layer 30 (i.e., the single conductive layer 11) between the conductive layer groups, the auxiliary layer 30 (i.e., the single conductive layer 11) can also be placed below the bottom conductive layer 10 (i.e., the eighteenth layer L18) of the second conductive layer group 02. In this way, the bottom auxiliary layer 30 (i.e., the single conductive layer 11) can simulate the symmetrical structure of the top layer (the first layer L1) to reduce layer deviation and warping after lamination.

[0085] Optionally, the conductive layer includes a copper layer; and the auxiliary layer includes at least one layer of copper foil.

[0086] For example, one or more layers of copper foil can be placed between different conductive layer groups. The thickness of a single layer of copper foil can range from 12µm to 70µm. Using copper foil as an auxiliary layer, on the one hand, its material properties make it easier to peel after lamination. On the other hand, the conductive layer and the auxiliary layer of copper foil on the surface of the conductive layer group are made of the same material. Even if peeling fails, impurities from other materials will not be introduced, which helps improve product yield.

[0087] In an optional embodiment, the auxiliary layer includes two layers of copper foil; placing the auxiliary layer between different and adjacent conductive layer groups includes: placing two copper layers between different and adjacent conductive layer groups, with the smooth surface of the copper foil facing the adjacent conductive layer group, and the rough surface of the copper foil facing the inner side of the auxiliary layer.

[0088] For example, Figure 10 This is a schematic diagram of a film layer structure in another stacking arrangement provided by an embodiment of the present invention, such as Figure 10As shown, the polished surface of the copper foil in the lower layer of the auxiliary layer 30 can face the topmost conductive layer 10 (eighth layer L8) of the second conductive layer group 02, and the polished surface of the copper foil in the upper layer of the auxiliary layer 30 can face the bottommost conductive layer 10 (seventh layer L7) of the first conductive layer group 01. In this way, during the lamination process, the rough, matte surfaces of the two copper foils in the auxiliary layer 30 can adhere to each other, while the polished surfaces of the copper foils can contact the conductive layer 10 of the conductive layer group (01 or 02), facilitating subsequent peeling.

[0089] In addition, placing two layers of copper foil between adjacent conductive layer groups (01 and 02) is also beneficial for simulating a symmetrical structure of the conductive layer groups (01 and 02) to reduce layer deviation and warping during the lamination process.

[0090] For example, continue to refer to Figure 10 The top layer of the first conductive layer group 01 is a single conductive layer 11, such as copper foil, and the bottom layer of the first conductive layer group 01 is a core board 22. The first conductive layer group 01 is an asymmetric structure; the bottom layer of the second conductive layer group 02 is a single conductive layer 11, such as copper foil, and the top layer of the second conductive layer group 02 is a core board 22. The second conductive layer group 02 is also an asymmetric structure. By placing two layers of copper foil between the first conductive layer group 01 and the second conductive layer group 02, the upper copper foil in the auxiliary layer 30 can simulate the symmetrical structure of the uppermost copper foil in the first conductive layer group 01, and the lower copper foil in the auxiliary layer 30 can simulate the symmetrical structure of the lowermost copper foil in the second conductive layer group 02. During the lamination process, the upper copper foil in the first conductive layer group 01 and the auxiliary layer 30 form a symmetrical structure, and the lower copper foil in the second conductive layer group 02 and the auxiliary layer 30 form a symmetrical structure. During the high-temperature and high-pressure lamination process, the stress of each film layer in the first conductive layer group 01 and the second conductive layer group 02 is balanced, which helps to further reduce layer deviation and warping after lamination.

[0091] In yet another optional embodiment, the auxiliary layer includes two layers of copper foil and an adhesive layer located between the two layers of copper foil.

[0092] For example, Figure 11 This is a schematic diagram of a film layer structure in another stacking arrangement provided by an embodiment of the present invention, such as Figure 11As shown, two layers of copper foil and an adhesive layer located between the two layers of copper foil are placed between adjacent conductive layer groups, wherein the number of adhesive layers can be set according to actual needs. An adhesive layer 102 is provided in the auxiliary layer 30. The adhesive layer softens and melts at high temperatures. During the lamination process, it can buffer the bonding between the conductive layer 10 in the conductive layer group and the adhesive layer 102, which is conducive to the adhesive layer 102 filling the line gap of the conductive layer 10 and improving the coating effect. It is particularly suitable for the case where the conductive layer 10 in the conductive layer group is relatively thick. It avoids the situation where the conductive layer 10 in the conductive layer group is too thick and the adhesive layer 102 cannot fill the gap and can only contact the surface of the conductive layer 10. It can effectively solve the problem of easy delamination of the conductive layer 10 in the conductive layer group.

[0093] Based on the same inventive concept, the present invention also provides a high-precision circuit board. The high-precision circuit board provided by the embodiment of the present invention can be prepared using the method for preparing a high-precision circuit board provided by any embodiment of the present invention. Therefore, the high-precision circuit board provided by the embodiment of the present invention also has the beneficial effects of the method for preparing a high-precision circuit board provided by the embodiment of the present invention. For matters not fully described in this embodiment, please refer to the above description of the method for preparing a high-precision circuit board, and will not be repeated here.

[0094] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0095] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A method for preparing a high-precision circuit board, characterized in that: The high-precision circuit board includes at least one blind hole or buried hole; The preparation method comprises: Obtaining a preset circuit diagram of the high-precision circuit board; According to the preset circuit diagram, a plurality of conductive layer groups are provided; wherein, adjacent conductive layers that need to form the same blind via or buried via constitute one conductive layer group; each conductive layer group comprises a core board provided with two conductive layers; The conductive layers are stacked, and a bonding layer is placed between the core plates of the same conductive layer group or between the core plate and the conductive layer, and an auxiliary layer is placed between different and adjacent conductive layer groups; wherein the auxiliary layer is a cladding metal material; Laminating the stacked conductive layer, the adhesive layer, and the auxiliary layer, and peeling off the auxiliary layer after lamination, so that the conductive layer group forms a sub-board; Drilling a hole at a preset position of at least one of the sub-boards to form a through hole; stacking the sub-boards and placing the adhesive layer between different and adjacent sub-boards; The sub-board and the adhesive layer are laminated and laminated to form the through hole into the blind hole or the buried hole.

2. The method for preparing a high-precision circuit board according to claim 1, wherein: At least part of the conductive layer group includes a single conductive layer.

3. The method for preparing a high-precision circuit board according to claim 2, characterized in that: The uppermost and lowermost conductive layer groups include an odd number of conductive layers; According to the preset circuit diagram, multiple conductive layer groups are set, including: According to the preset circuit diagram, a plurality of conductive layer groups are divided; wherein, the side close to the adjacent conductive layer group in the top and bottom conductive layer groups is the single conductive layer, and / or, the side away from the adjacent conductive layer group in the top and bottom conductive layer groups is the core board.

4. The method for preparing a high-precision circuit board according to claim 2, wherein: The uppermost and lowermost conductive layer groups include an odd number of conductive layers; According to the preset circuit diagram, multiple conductive layer groups are set, including: According to the preset circuit diagram, a plurality of conductive layer groups are divided; wherein, the side of the topmost and bottommost conductive layer groups away from the adjacent conductive layer group is the single conductive layer, and / or, the side of the topmost and bottommost conductive layer groups close to the adjacent conductive layer group is the core board.

5. The method for preparing a high-precision circuit board according to claim 2, wherein: The auxiliary layer includes the single conductive layer; The uppermost and / or lowermost conductive layer group includes an odd number of conductive layers; According to the preset circuit diagram, multiple conductive layer groups are set, including: According to the preset circuit diagram, a plurality of conductive layer groups are divided; wherein, one of the uppermost layer in the uppermost conductive layer group and the lowermost layer in the lowermost conductive layer group is the single conductive layer, and the other is the core board; The conductive layers are stacked, a bonding layer is placed between the core plates in the same group or between the core plates and the conductive layers, and an auxiliary layer is placed between different and adjacent conductive layer groups, comprising: The conductive layers are stacked, and an adhesive layer is placed between the core plates in the same group or between the core plates and the conductive layers. The auxiliary layer is placed between different and adjacent conductive layer groups. The auxiliary layer is also placed above the top conductive layer group or below the bottom conductive layer group, so that the upper and lower edge conductive layers in all the conductive layers are single-layer conductive layers.

6. The method for preparing a high-precision circuit board according to claim 1, wherein: The conductive layer includes a copper layer; the auxiliary layer includes at least one layer of copper foil.

7. The method for preparing a high-precision circuit board according to claim 6, characterized in that: The auxiliary layer includes two layers of copper foil; Placing an auxiliary layer between different and adjacent conductive layer groups, comprising: Two copper layers are placed between different and adjacent conductive layer groups, with the shiny surface of the copper foil facing the adjacent conductive layer group and the matte surface of the copper foil facing the inner side of the auxiliary layer.

8. The method for preparing a high-precision circuit board according to claim 6, wherein: The auxiliary layer includes two layers of copper foil and the adhesive layer located between the two layers of copper foil.

9. The method for preparing a high-precision circuit board according to any one of claims 6 to 8, characterized in that: The thickness of the copper foil is d, wherein 12um≤d≤70um.

10. A high-precision circuit board, characterized in that: The high-precision circuit board is prepared by the method for preparing the high-precision circuit board according to any one of claims 1 to 9.

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