Semiconductor device and method of manufacturing the same, electronic device

Abstract

A semiconductor device, a manufacturing method thereof, and an electronic device, the manufacturing method of the semiconductor device comprising: forming, along a thickness direction of a substrate, a stack structure of a sacrificial layer and a conductive layer alternately arranged in sequence on the substrate, a lattice mismatch degree of the sacrificial layer and the conductive layer being less than or equal to 0.5%; forming, in the stack structure, a groove extending along a direction perpendicular to the substrate by patterned etching, the groove exposing a side wall of the conductive layer and a side wall of the sacrificial layer; performing selective etching on the exposed side wall of the sacrificial layer to remove the sacrificial layer, form a cavity, and retain the conductive layer, the cavity exposing at least part of a side surface of the conductive layer; filling the cavity and the groove with an insulating layer; removing part of the insulating layer to form a channel, the channel exposing at least part of the side surface of the conductive layer; and forming, in sequence, a gate insulating layer and a gate electrode on the exposed side surface of the conductive layer.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to, but are not limited to, semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. BACKGROUND

[0002] With the continuous development of semiconductor technology, the critical dimension of semiconductor devices is increasingly reduced, and the types and quantities of devices contained in a single chip are also increased. In order to obtain higher storage capacity, lower leakage, and higher integration, a new structure and simple semiconductor device design have become a demand. SUMMARY

[0003] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0004] Embodiments of the present disclosure provide a manufacturing method of a semiconductor device, comprising:

[0005] forming, along a thickness direction of a substrate, a stack structure of a sacrificial layer and a conductive layer arranged alternately and successively on the substrate, a lattice mismatch degree of the sacrificial layer and the conductive layer being less than or equal to 0.5%;

[0006] forming, by patterned etching, a groove extending along a direction perpendicular to the substrate in the stack structure, the groove exposing a sidewall of the conductive layer and a sidewall of the sacrificial layer;

[0007] selectively etching the exposed sidewall of the sacrificial layer to remove the sacrificial layer, forming a cavity and retaining the conductive layer, the cavity exposing at least part of a side surface of the conductive layer;

[0008] filling the cavity and the groove with an insulating layer;

[0009] removing part of the insulating layer to form a channel, the channel exposing at least part of the side surface of the conductive layer;

[0010] forming, successively, a gate insulating layer and a gate electrode surrounding the conductive layer on the exposed side surface of the conductive layer.

[0011] In an exemplary embodiment, the material of the sacrificial layer is aluminum gallium arsenide, and the material of the conductive layer is gallium arsenide.

[0012] In an exemplary embodiment, the material of the sacrificial layer is gallium arsenide, and the material of the conductive layer is aluminum gallium arsenide.

[0013] In an exemplary embodiment, the sum of the thickness of the sacrificial layer and the thickness of the adjacent conductive layer is greater than or equal to 20 nanometers and less than or equal to 100 nanometers.

[0014] In an example embodiment, the stack structure includes n layers of sacrificial layers and n layers of conductive layers, n is a natural number greater than or equal to 2, the layers of the stack structure close to the substrate are sacrificial layers, and the layers of the stack structure far from the substrate are conductive layers.

[0015] In an example embodiment, after the selective etching of the sidewalls of the exposed sacrificial layers and the removal of the sacrificial layers to form cavities, the method further includes:

[0016] forming an epitaxial layer on the exposed side of the conductive layer;

[0017] Alternatively, after the removal of part of the insulating layer to form a channel, the method further includes:

[0018] forming an epitaxial layer on the exposed side of the conductive layer.

[0019] In an example embodiment, the thickness of the epitaxial layer is less than or equal to 5 nanometers and greater than or equal to 0.1 nanometer.

[0020] In an example embodiment, the thickness of the epitaxial layer is greater than 5 nanometers.

[0021] In an example embodiment, the material of the epitaxial layer is silicon.

[0022] In an example embodiment, after the formation of the gate insulating layer and the gate electrode on the exposed side of the conductive layer in sequence, the method further includes:

[0023] by patterned etching, removing one end of each of the conductive layers to form a plurality of strip-shaped grooves;

[0024] by a deposition process, forming a bit line in each of the strip-shaped grooves, and each of the bit lines is connected to the corresponding conductive layer.

[0025] In an example embodiment, after the formation of the bit line in each of the strip-shaped grooves by the deposition process, the method further includes:

[0026] by patterned etching, removing the insulating layer corresponding to one end of the conductive layer far from the bit line to expose the one end of the conductive layer;

[0027] by a deposition process, forming a capacitor dielectric layer and a second capacitor electrode on the one end of the conductive layer in sequence, so that the one end of the conductive layer forms a first capacitor electrode.

[0028] The disclosure embodiments also provide a semiconductor device manufactured by the manufacturing method of any one of the preceding semiconductor devices, and the semiconductor device includes at least a plurality of transistors arranged on a substrate and in the thickness direction of the substrate in sequence.

[0029] The transistor includes a channel, a gate electrode surrounding the sidewall of the channel, a gate insulating layer arranged between the channel and the gate electrode, a first electrode and a second electrode; the first electrode is connected to the second electrode through the channel, and the first electrode, the channel and the second electrode are an integrated structure and include the same conductive material.

[0030] In an exemplary embodiment, a buffer layer is further included, and the buffer layer is disposed on a side of the substrate facing the transistor.

[0031] In an exemplary embodiment, the same conductive material is gallium arsenide or aluminum gallium arsenide.

[0032] In an exemplary embodiment, an epitaxial layer is further included, and the epitaxial layer is at least disposed between the channel and the gate insulating layer.

[0033] An embodiment of the present disclosure further provides an electronic device comprising the aforementioned semiconductor device.

[0034] The manufacturing method of the semiconductor device in the embodiment of the present disclosure increases or eliminates the critical thickness value of the stacking structure due to lattice mismatch by making the lattice mismatch between the sacrificial layer and the conductive layer less than or equal to 0.5%. The sacrificial layer and the conductive layer can be stacked in multiple layers by epitaxy, thereby increasing the number of stacked layers in the stacking structure, improving the integration of the semiconductor device, and ensuring the lattice quality of the sacrificial layer and the conductive layer, avoiding the lattice mismatch between the sacrificial layer and the conductive layer due to the large number of stacked layers in the stacking structure, affecting the lattice quality of the sacrificial layer and the conductive layer, and reducing the performance of the conductor device.

[0035] The manufacturing method of the semiconductor device of the embodiment of the present application is to use the material of the sacrificial layer as aluminum gallium arsenide (Al x Ga 1-x As), and the conductive layer is made of gallium arsenide (GaAs), which greatly reduces the lattice mismatch between the sacrificial layer and the conductive layer. This lattice mismatch can be ignored during the epitaxial growth of the sacrificial layer and the conductive layer, allowing the sacrificial layer and the conductive layer to be superimposed in infinite layers.

[0036] In the manufacturing method of the semiconductor device of the embodiment of the present application, the etching selectivity ratio of the sacrificial layer to the conductive layer changes with the aluminum (Al) content in the sacrificial layer. The etching selectivity ratio of the sacrificial layer to the conductive layer can be controlled by controlling the aluminum (Al) content in the sacrificial layer. Thus, in the subsequent etching process, a hydrogen fluoride (HF) solution can be used as an etching solution to selectively etch and remove the sacrificial layer while retaining the conductive layer.

[0037] The manufacturing method of the semiconductor device of the embodiment of the present application uses gallium arsenide (GaAs) as the conductive layer, so that the conductive layer has the characteristics of low static power consumption and high driving current. The biggest problem of gallium arsenide material relative to Si material is that the interface state density is too high, and in the field of high-speed high-frequency devices, it has been proved that the interface state density of gallium arsenide (GaAs) material can be reduced to 10^11 eV -1 cm -2 by some processes, so as to ensure the performance of the device.

[0038] The manufacturing method of the semiconductor device of the embodiment of the present application uses silicon as the substrate and gallium arsenide (GaAs) as the conductive layer, and the penetration dislocation density of the conductive layer and the sacrificial layer can be reduced by epitaxy of the buffer layer, for example, the penetration dislocation density of hetero-epitaxy gallium arsenide (GaAs) material on silicon (001) can be reduced to 10^6 cm -2 .

[0039] The manufacturing method of the semiconductor device of the embodiment of the present application uses gallium arsenide (GaAs) as the conductive layer, improves the electron mobility of the conductive layer, and makes the semiconductor device have higher on-current (I on ).

[0040] The manufacturing method of the semiconductor device of the embodiment of the present application uses gallium arsenide (GaAs) as the conductive layer, improves the conductivity of the conductive layer, makes the channel formed by the conductive layer have higher channel conductance, and reduces the energy consumption of the semiconductor device.

[0041] The manufacturing method of the semiconductor device of the embodiment of the present application uses gallium arsenide (GaAs) layer to integrate part of peripheral circuits, so that the working frequency of the semiconductor device can be improved, for example, the working frequency of the semiconductor device as a sensitive amplifier can be improved.

[0042] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art from the description, or can be learned by practice of the present application. The objects and advantages of the present application can be realized and obtained by means of the structures particularly pointed out in the description and the appended drawings.

[0043] Other aspects can become apparent to those of ordinary skill in the art upon reading and understanding the attached figures and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0044] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, and do not constitute a limitation on the technical solutions.

[0045] Figure 1 A schematic view of a semiconductor device provided for an exemplary embodiment along a direction parallel to the substrate is shown;

[0046] Figure 2 for Figure 1 a cross-sectional view taken along the a-a' direction;

[0047] Figure 3 a schematic view of a semiconductor device after forming a stack structure in a manufacturing process of the semiconductor device according to an exemplary embodiment;

[0048] Figure 4a a schematic view of a semiconductor device after forming a recess in a manufacturing process of the semiconductor device according to an exemplary embodiment;

[0049] Figure 4b for Figure 4a a cross-sectional view taken along the a-a' direction;

[0050] Figure 5 a schematic view of a semiconductor device after forming a cavity in a manufacturing process of the semiconductor device according to an exemplary embodiment;

[0051] Figure 6a a schematic view of a semiconductor device after forming a first insulating layer and a second insulating layer in a manufacturing process of the semiconductor device according to an exemplary embodiment;

[0052] Figure 6b for Figure 6a a cross-sectional view taken along the a-a' direction;

[0053] Figure 7a a schematic view of a semiconductor device after forming a gate insulating layer and a gate electrode in a manufacturing process of the semiconductor device according to an exemplary embodiment;

[0054] Figure 7b for Figure 7a a cross-sectional view taken along the a-a' direction;

[0055] Figure 8a a schematic view of a semiconductor device after forming a first bit line and a second bit line in a manufacturing process of the semiconductor device according to an exemplary embodiment;

[0056] Figure 8b for Figure 8a a cross-sectional view taken along the a-a' direction;

[0057] Figure 9a a schematic view of a semiconductor device according to another exemplary embodiment along a direction parallel to a substrate;

[0058] Figure 9b for Figure 9a a cross-sectional view taken along the a-a' direction;

[0059] Figure 10 a schematic view of a semiconductor device after forming an epitaxial layer in a manufacturing process of the semiconductor device according to an exemplary embodiment; Figure 1 ​

[0060] Figure 11 FIG. 6 is a diagram illustrating a semiconductor device manufacturing process according to an exemplary embodiment. Figure 2 . DETAILED DESCRIPTION

[0061] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The features of the embodiments of the present disclosure and the embodiments can be combined with each other unless they conflict.

[0062] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the same meaning as those understood by a person of ordinary skill in the art to which the present disclosure belongs.

[0063] The embodiments of the present disclosure are not necessarily limited to the shapes or values shown in the drawings, and the shapes and sizes of the components shown in the drawings can be changed as needed. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values shown in the drawings.

[0064] In the present disclosure, ordinal numbers such as "first", "second", "third", and the like are set in order to avoid confusion of components, and do not represent any order, number, or importance.

[0065] In the present disclosure, in order to facilitate the description, words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the components with reference to the drawings, and are only for the convenience of describing the present specification and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be construed as limiting the present disclosure. The positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words described in the disclosure, and can be appropriately replaced according to the situation.

[0066] In the present disclosure, unless explicitly defined and limited otherwise, the terms "mount", "connected", and "connection" should be interpreted broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate, or the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0067] In this disclosure, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and the source electrode (a source electrode terminal, a source region, or a source electrode), and a current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to a region through which a current mainly flows.

[0068] In this disclosure, it can be that the first electrode is the drain electrode and the second electrode is the source electrode, or it can be that the first electrode is the source electrode and the second electrode is the drain electrode. In the case of using a transistor having opposite polarity or in the case of changing the direction of current in circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes exchanged with each other. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be exchanged with each other.

[0069] In this disclosure, "electrically connected" includes a case where constituent elements are connected together through an element having some electrical action. The element having some electrical action is not particularly limited as long as it can perform transmission and reception of an electrical signal between the connected constituent elements. Examples of the element having some electrical action include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0070] In this disclosure, "parallel" means approximately parallel or almost parallel, such as a state where the angle formed by two straight lines is -10° or more and 10° or less, and thus also includes a state where the angle is -5° or more and 5° or less. In addition, "perpendicular" means approximately perpendicular, such as a state where the angle formed by two straight lines is 80° or more and 100° or less, and thus also includes a state where the angle is 85° or more and 95° or less.

[0071] In this disclosure, "film" and "layer" can be exchanged with each other. For example, "a conductive layer" can be sometimes replaced with "a conductive film". Similarly, "an insulating film" can be sometimes replaced with "an insulating layer".

[0072] In this disclosure, "A and B are provided in the same layer" means that A and B are formed at the same time by one patterning process. "A orthographic projection is within the range of B orthographic projection" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0073] In this disclosure, "A and B are of an integral structure" can mean that there is no clear boundary or gap, or a clear boundary surface, in the microstructure. Generally, a film layer formed by patterning on another film layer is of an integral structure. For example, A and B are of an integral structure formed by using the same material and by one patterning process.

[0074] The present disclosure provides a semiconductor device manufacturing method, comprising:

[0075] forming, along a thickness direction of a substrate, a stack structure comprising a plurality of pairs of a sacrificial layer and a conductive layer, the pairs of the sacrificial layer and the conductive layer being arranged alternately and successively, a lattice mismatch degree of the sacrificial layer and the conductive layer being less than or equal to 0.5%;

[0076] forming, by patterned etching, a groove in the stack structure, the groove exposing a sidewall of the conductive layer and a sidewall of the sacrificial layer;

[0077] selectively etching the exposed sidewall of the sacrificial layer to remove the sacrificial layer, forming a cavity and retaining the conductive layer, the cavity exposing at least a part of a side surface of the conductive layer;

[0078] filling the cavity and the groove with an insulating layer;

[0079] removing part of the insulating layer to form a passage, the passage exposing at least a part of the side surface of the conductive layer;

[0080] forming, successively, a gate insulating layer and a gate electrode on the exposed side surface of the conductive layer.

[0081] The semiconductor device of the present disclosure is illustrated below by some exemplary embodiments.

[0082] Figure 1 A schematic view of a semiconductor device provided by an exemplary embodiment along a direction parallel to a substrate direction is shown in FIG. 1. Figure 1 As shown in FIG. 1, the semiconductor device can comprise a transistor, a capacitor, a bit line extending along a direction parallel to a substrate direction, and a word line extending along a direction perpendicular to the substrate direction. Figure 1 A cross-sectional view along a-a' direction is shown in FIG. 2. In an exemplary embodiment, as shown in FIG. 2, the semiconductor device can comprise a transistor, a capacitor, a bit line extending along a direction parallel to a substrate direction, and a word line extending along a direction perpendicular to the substrate direction. Figure 2 As shown in FIG. 2, the semiconductor device can comprise a transistor, a capacitor, a bit line extending along a direction parallel to a substrate direction, and a word line extending along a direction perpendicular to the substrate direction. Figure 3 As shown in FIG. 2, the semiconductor device can comprise a transistor, a capacitor, a bit line extending along a direction parallel to a substrate direction, and a word line extending along a direction perpendicular to the substrate direction.

[0083] In an example embodiment, the transistor comprises a channel 73, a first electrode 74, a second electrode 75, a gate electrode 71, and a gate insulating layer 72. The first electrode 74 and the second electrode 75 are located on opposite sides of the channel 73 in a first direction D1. A first end of the first electrode 74 is connected to the channel 73, and a second end of the first electrode 74 is connected to a bit line. A first end of the second electrode 75 is connected to the channel 73, and a second end of the second electrode 75 is connected to a capacitor. The gate insulating layer 72 is disposed between the gate electrode 71 and the channel 73, and the gate electrode 71 surrounds the sidewall of the channel 73 through the gate insulating layer 72.

[0084] In an example embodiment, the capacitor comprises a first capacitor electrode 91, a second capacitor electrode 92, and a capacitor dielectric layer 93 disposed between the second capacitor electrode 92 and the first capacitor electrode 91. The first capacitor electrode 91 is connected to the second end of the second electrode 75.

[0085] In an example embodiment, the first electrode 74, the channel 73, the second electrode 75, and the first capacitor electrode 91 are of an integral structure and comprise the same conductive material, i.e., the first electrode 74, the channel 73, the second electrode 75, and the first capacitor electrode 91 are different regions of a conductive layer arranged in sequence along the first direction D1.

[0086] In practical applications, the integral structure can be understood as a conductive line or line shape, a part of the conductive line is surrounded by the gate insulating layer and the gate electrode, and the remaining part has one end connected to the bit line as the first electrode and the other end connected to the second electrode and the first capacitor electrode.

[0087] In an example embodiment, a buffer layer is further included, and the buffer layer is disposed on a side of the substrate facing the transistor.

[0088] In an example embodiment, the same conductive material is gallium arsenide or aluminum gallium arsenide.

[0089] In an example embodiment, an epitaxial layer is further included, and the epitaxial layer is disposed at least between the channel and the gate insulating layer.

[0090] The technical scheme of the embodiment is further illustrated by a manufacturing process of the memory of the embodiment. The "patterning process" in the embodiment includes deposition of a film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist, and the like, which are mature manufacturing processes in the related art. The "lithography process" in the embodiment includes coating of a film layer, mask exposure, and development, which are mature manufacturing processes in the related art. Deposition can use known processes such as sputtering, evaporation, chemical vapor deposition, coating can use known coating processes, and etching can use known methods, which are not specifically limited herein. In the description of the embodiment, it needs to be understood that "film" refers to a film layer of a certain material made on a substrate by deposition or coating process. If the "film" does not need to be subjected to the patterning process or the lithography process during the entire manufacturing process, the "film" can also be referred to as a "layer". If the "film" needs to be subjected to the patterning process or the lithography process during the entire manufacturing process, it is referred to as a "film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the lithography process includes at least one "pattern".

[0091] In an example embodiment, the semiconductor device can be any of the semiconductor devices described above, and the manufacturing process of the semiconductor device can include:

[0092] Step 101, forming a stack structure.

[0093] The forming of the stack structure includes: forming a buffer layer 2 on a substrate 1; then, forming the sacrificial layers 31 and the conductive layers 32 arranged alternately in sequence on the buffer layer 2, and the sacrificial layers 31 and the conductive layers 32 arranged alternately in sequence form a stack structure 3, as shown in Figure 4a

[0094] In an example embodiment, the lattice mismatch degree of the sacrificial layers 31 and the conductive layers 32 is less than or equal to 0.5%.

[0095] The embodiment of the application increases the thickness critical value of the stack structure due to the lattice mismatch by making the lattice mismatch degree of the sacrificial layers 31 and the conductive layers 32 less than or equal to 0.5%, can use the epitaxial method to stack the sacrificial layers 31 and the conductive layers 32 in multiple layers, thereby increasing the number of periods of the stack structure and improving the integration of the semiconductor device; and ensures the crystal quality of the sacrificial layers 31 and the conductive layers 32 in the stack structure, avoiding the performance degradation of the semiconductor device.

[0096] In an example embodiment, the material of the sacrificial layers 31 can be aluminum gallium arsenide (AlGaAs), and the material of the conductive layers 32 can be gallium arsenide (GaAs).

[0097] ​The material of the sacrificial layer 31 is aluminum gallium arsenide (AlGaAs), and the material of the conductive layer 32 is gallium arsenide (GaAs), so that the lattice mismatch degree of the sacrificial layer 31 and the conductive layer 32 is 0.14%, which can be ignored in the epitaxy process of the sacrificial layer 31 and the conductive layer 32, so that the sacrificial layer 31 and the conductive layer 32 can be stacked infinitely.

[0098] The etching selectivity ratio of the sacrificial layer 31 and the conductive layer 32 changes with the content of aluminum (Al) in the sacrificial layer 31, and the etching selectivity ratio of the sacrificial layer 31 and the conductive layer 32 can be controlled by controlling the content of aluminum (Al) in the sacrificial layer 31, so that in the subsequent etching process, hydrogen fluoride (HF) solution can be used as the etching liquid to selectively etch and remove the sacrificial layer 31, and the conductive layer 32 is reserved.

[0099] The manufacturing method of the semiconductor device provided in the embodiment of the present application uses gallium arsenide (GaAs) as the conductive layer, so that the conductive layer has the characteristics of low static power consumption and high driving current.

[0100] The manufacturing method of the semiconductor device provided in the embodiment of the present application uses silicon as the substrate and gallium arsenide (GaAs) as the conductive layer, and the epitaxy of the buffer layer can be used to transition and reduce the threading dislocation density of the conductive layer and the sacrificial layer. For example, the threading dislocation density of the gallium arsenide (GaAs) material hetero-epitaxied on silicon (001) can be reduced to 10^6 cm -2 .

[0101] The manufacturing method of the semiconductor device provided in the embodiment of the present application uses gallium arsenide (GaAs) as the conductive layer, which improves the electron mobility of the conductive layer, so that the semiconductor device has a higher on-current (I on ).

[0102] The manufacturing method of the semiconductor device provided in the embodiment of the present application uses gallium arsenide (GaAs) as the conductive layer, which improves the conductivity of the conductive layer, so that the channel formed by the conductive layer has a higher channel conductance, and the energy consumption of the semiconductor device is reduced.

[0103] The manufacturing method of the semiconductor device provided in the embodiment of the present application integrates part of the peripheral circuit by using the gallium arsenide (GaAs) layer, which can improve the working frequency of the semiconductor device, for example, the working frequency of the semiconductor device as a sensitive amplifier.

[0104] In an example embodiment, the stack structure 3 can include n layers of the sacrificial layers 31 and n layers of the conductive layers 32, which are arranged alternately along the thickness direction of the substrate 1. Wherein, n is a natural number greater than or equal to 2, for example, n can be 2, 3, 4, 5, 6, etc. The film layer close to the substrate 1 side in the stack structure 3 can be the sacrificial layer 31, and the film layer away from the substrate 1 side in the stack structure 3 can be the conductive layer 32.

[0105] In an example embodiment, the thickness of the sacrificial layer 31 and the thickness of the adjacent conductive layer 32 are greater than or equal to 20 nanometers and less than or equal to 100 nanometers, that is, the sum of the thickness of one sacrificial layer 31 and the thickness of one adjacent conductive layer 32 is greater than or equal to 20 nanometers and less than or equal to 100 nanometers. For example, the thickness of the sacrificial layer 31 can be greater than or equal to 30 nm and less than or equal to 60 nm, and the thickness of the conductive layer 32 can be greater than or equal to 10 nm and less than or equal to 30 nm.

[0106] The manufacturing method of the semiconductor device of the example embodiment of the present application avoids the thickness of the adjacent sacrificial layer and the conductive layer being too thin or too thick by making the sum of the thickness of the adjacent sacrificial layer and the conductive layer greater than or equal to 20 nanometers and less than or equal to 100 nanometers, thereby facilitating subsequent processes.

[0107] In some embodiments, the stack structure can include n+1 layers of sacrificial layers and n layers of conductive layers, or the stack structure can include n layers of sacrificial layers and n+1 layers of conductive layers, which will not be described here in the example embodiment of the present disclosure.

[0108] In an example embodiment, the buffer layer 2 can be formed by a high-low temperature combined growth method, a superlattice dislocation filtering layer method, or a patterned substrate assisted method.

[0109] In an example embodiment, the sacrificial layer 31 and the conductive layer 32 can be formed by epitaxy.

[0110] In an example embodiment, the substrate 1 can be a semiconductor substrate, such as a silicon substrate, and of course can be any substrate that can satisfy the epitaxial growth of the stack structure.

[0111] Step 102, forming a recess.

[0112] In an example embodiment, taking the stack structure 3 including 2 layers of sacrificial layers 31 and 2 layers of conductive layers 32 as an example, the preparation process of the subsequent semiconductor device is described. Wherein, the film layer close to the substrate 1 side in the stack structure 3 is the sacrificial layer 31, and the film layer away from the substrate 1 side in the stack structure 3 can be the conductive layer 32.

[0113] In an example embodiment, forming the recesses comprises: on the basis of the substrate 1 on which the aforementioned pattern is formed, forming two recesses 5 in the stack structure 3 by means of a patterned etching, such as a dry etching process, so that the conductive layer 32 in the stack structure 3 comprises a main body 321 and a plurality of branches 322 which are connected to the main body 321 crosswise.

[0114] In an example embodiment, in a direction parallel to the substrate 1, the main body 321 of the conductive layer 32 is in the shape of a long strip and extends along the second direction D2; the plurality of branches 322 of the conductive layer 32 are in the shape of long strips and extend along the first direction D1, and the plurality of branches 322 are arranged at intervals along the second direction D2 and are all connected to the main body 321 perpendicularly.

[0115] In an example embodiment, in a direction parallel to the substrate 1, the two recesses 5 are both in the shape of rectangles and both extend along the first direction D1 and are arranged at intervals along the second direction D2. In a direction perpendicular to the substrate 1, the recesses 5 extend along the direction perpendicular to the substrate 1, and the recesses 5, from the surface of the stack structure 3 away from the substrate 1, successively penetrate the conductive layer 32 and the sacrificial layer 31 in the stack structure 3 and extend to the surface of the buffer layer 2, the bottom of the recess 5 being the surface of the buffer layer 2 corresponding to the recess 5, and the sidewall of the recess 5 exposing part of the sidewall of the conductive layer 32 and part of the sidewall of the sacrificial layer 31 in the stack structure 3.

[0116] Subsequently, by means of a patterned etching, a trench is formed in the stack structure 3 on opposite sides of the first direction D1, and a support layer 4 is formed in the trench. In a direction parallel to the substrate 1, the support layer 4 extends along the second direction D2, the support layer 4 is located on opposite sides of the recess 5 in the first direction D1 and is connected to one side of the recess 5 in the first direction D1, that is, the side of the support layer 4 can serve as one side of the recess 5 in the first direction D1; the opposite ends of the conductive layer 32 in the stack structure 3 in the first direction D1 are respectively connected to the support layer 4, and the support layer 4 is used to support the conductive layer 32 in subsequent processes to prevent the conductive layer 32 from collapsing; as shown in Figure 4b and Figure 5 The first direction D1 and the second direction D2 are both parallel to the plane on which the substrate 1 is located, and the first direction D1 and the second direction D2 intersect, for example, the first direction D1 and the second direction D2 are perpendicular.

[0117] In an example embodiment, the material of the support layer 4 can be silicon nitride.

[0118] Step 103, forming a cavity.

[0119] In an exemplary embodiment, forming the cavities includes: on the basis of the substrate 1 with the aforementioned pattern, using an etching solution to selectively etch the sidewall of each layer of the sacrificial layer 31 exposed by the groove 5, etching to remove the sacrificial layer 31 and retain the conductive layer 32, so that the area where each layer of the sacrificial layer 31 is removed forms a cavity 33 extending along the direction parallel to the substrate 1, and each layer of the cavity 33 exposes the upper side and the lower side of the conductive layer 32, as shown in Figure 6a FIG. 3. The upper side is the surface of the conductive layer 32 away from the substrate 1, and the lower side is the surface of the conductive layer 32 close to the substrate 1.

[0120] In an exemplary embodiment, the etching solution can include a hydrogen fluoride (HF) solution.

[0121] Step 104, forming a first insulating layer and a second insulating layer.

[0122] In an exemplary embodiment, forming the first insulating layer and the second insulating layer includes: on the basis of the substrate 1 with the aforementioned pattern, depositing an insulating film in each layer of the cavity and the groove 5, so that the insulating film filling each layer of the cavity forms the first insulating layer 61, and the insulating film filling the groove 5 forms the second insulating layer 62; and then, through a polishing process, polishing the surface of the second insulating layer 62 away from the substrate 1 to be flat, as shown in Figure 6b and Figure 7a .

[0123] In an exemplary embodiment, the material of the insulating film can include silicon oxide (SiOx), so that the material of the first insulating layer 61 and the second insulating layer 62 both includes silicon oxide (SiOx).

[0124] In an exemplary embodiment, the insulating film can be deposited by a chemical vapor deposition method or an atomic layer deposition method.

[0125] Step 105, forming a gate insulating layer and a gate electrode.

[0126] In an exemplary embodiment, forming a gate insulating layer and a gate electrode includes: on the basis of the substrate 1 having the aforementioned pattern formed thereon, forming a channel in each first insulating layer 61 and second insulating layer 62 by patterned etching to expose the side walls of the multiple branches 322 of each conductive layer 32, the channel surrounding the side walls of the multiple branches 322 of each conductive layer 32 to form a ring structure extending along the first direction D1, and the channel exposing the side walls of the multiple branches 322 of the corresponding conductive layer 32; subsequently, forming a gate insulating layer 72 and a gate electrode 71 in the channel in sequence, the gate insulating layer 72 surrounding the side walls of the multiple branches 322 of each conductive layer 32, the gate electrode 71 surrounding the side walls of the multiple branches 322 of each layer through the gate insulating layer 72, the gate electrode 71 being insulated from the side walls of the multiple branches 322 of each layer by the gate insulating layer 72, and the multiple branches 322 of the conductive layer 32 corresponding to the gate electrode 71 forming a channel 73; subsequently, filling the gap in the channel with an insulating material, such as Figure 7b and Figure 8a shown.

[0127] In an exemplary embodiment, the gate electrodes 71 corresponding to each conductive layer 32 may be connected together to form a word line extending in a direction perpendicular to the substrate 1 .

[0128] In one exemplary embodiment, the gate insulating layer 72 and the gate electrode 71 may be formed by an atomic layer deposition method.

[0129] Step 106 : forming a first bit line and a second bit line.

[0130] The formation of the first bit line and the second bit line includes: on the basis of the substrate 1 formed with the aforementioned pattern, removing a portion of the area located in the main body of the conductive layer 32 by patterned etching to form a strip groove; then, forming the first bit line 81 and the second bit line 82 in each strip groove by an atomic layer deposition process, and forming a third insulating layer 63 between the first bit line 81 and the second bit line 82; forming the first electrode 74 in the area where multiple branches of each layer of the conductive layer 32 are located between the first bit line 81 and the gate electrode 71; the first bit line 81 is connected to the first electrode 74 of the conductive layer 32 located on the side away from the substrate 1 in the stack structure, and the second bit line 82 is connected to the first electrode 74 of the conductive layer 32 located on the side close to the substrate 1 in the stack structure, and the third insulating layer 63 separates the first bit line 81 from the second bit line 82, as shown in FIG. Figure 8b and Figure 1 shown.

[0131] In an exemplary embodiment, in a direction parallel to the substrate 1 , the first bit line 81 is in the shape of a long strip and extends along the second direction D2 . The first bit line 81 is arranged in the same layer as the conductive layer 32 on the side away from the substrate 1 in the stacked structure and is connected to the first electrode 74 of the conductive layer 32 .

[0132] In an example embodiment, the third insulating layer 63 is elongated in a direction parallel to the substrate 1 and extends along the second direction D2. The third insulating layer 63 is located between the first bit line 81 and the second bit line 82, and is arranged in the same layer as the first bit line 81.

[0133] In an example embodiment, the second bit line 82 is elongated in a direction parallel to the substrate 1 and extends along the second direction D2. The second bit line 82 is located on a side of the third insulating layer 63 away from the first bit line 81. In a direction perpendicular to the substrate 1, the second bit line 82 includes a main body portion extending along a direction perpendicular to the substrate 1 and a connecting portion extending along a direction parallel to the substrate 1. The first end of the connecting portion is arranged in the same layer as the first electrode 74 of the conductive layer 32 located on the side close to the substrate 1 in the stack structure, and is connected to the first electrode 74. The second end of the connecting portion extends in the opposite direction of the first direction D1 and is connected to the first end of the main body portion. The second end of the main body portion extends along a direction perpendicular to the substrate 1, is arranged in the same layer as the third insulating layer 63 and the first bit line 81, and is separated from the first bit line 81 by the third insulating layer 63.

[0134] In step 107, a capacitor is formed.

[0135] The formation of the capacitor includes: on the basis of the substrate 1 with the aforementioned pattern, removing the first insulating layer and the second insulating layer corresponding to the ends of the plurality of branches of the conductive layer 32 away from the first bit line 81 and the second bit line 82 by patterned etching, to expose the ends of the plurality of branches; and then sequentially forming a capacitor dielectric layer 93 and a second capacitor electrode 92 on the exposed plurality of branches, the exposed plurality of branches forming a first capacitor electrode 91, and the plurality of branches located in the region of the gate electrode 71 and the first capacitor electrode 91 forming a second electrode 75, as shown in FIGS. 1C and 1D. Figure 2 and Figure 1 The first electrode 74, the channel 73, the second electrode 75, and the gate electrode 71 form a transistor, and the first capacitor electrode 91 and the second capacitor electrode 92 form a capacitor.

[0136] In an example embodiment, the second capacitor electrode 92 surrounds the sidewall of the first capacitor electrode 91 through the capacitor dielectric layer 93, forming a ring structure extending along a direction parallel to the substrate.

[0137] In an example embodiment, different regions of the plurality of branches of the conductive layer 32 form the first electrode 74, the channel 73, the second electrode 75, and the first capacitor electrode 91.

[0138] The first electrode 74, the channel 73, the second electrode 75 and the first capacitor electrode 91 are formed by the same conductive layer 32 material, and form an integrated structure, which simplifies the production process, reduces the production cost, and is easy to manufacture.

[0139] In some embodiments, the present disclosure provides a semiconductor device manufacturing method, and the semiconductor device manufacturing method of the present disclosure is different from Figure 1 The semiconductor device manufacturing method shown in the difference is that, in step 101, the material of the sacrificial layer 31 can be gallium arsenide (GaAs), and the material of the conductive layer 32 can be aluminum gallium arsenide (AlGaAs). In step 102, the sacrificial layer 31 can be selectively etched and removed by an etching solution, and the conductive layer 32 is reserved. The etching solution includes a mixture of citric acid and hydrogen peroxide.

[0140] In some embodiments, the present disclosure provides a semiconductor device, and the semiconductor device of the present disclosure is different from Figure 2 and Figure 9a The difference between the semiconductor device of the present disclosure and Figure 1 and 9b As shown in the semiconductor device of the present disclosure further includes an epitaxial layer 11, and the epitaxial layer 11 is arranged on at least the sidewall of the channel 73 and between the channel 73 and the gate insulating layer 72.

[0141] In an exemplary embodiment, the epitaxial layer 11 is arranged on the sidewall of the integrated structure formed by the first electrode 74, the channel 73, the second electrode 75 and the first capacitor electrode 91, and the epitaxial layer 11 and the orthogonal projection of the integrated structure on the substrate overlap.

[0142] In an exemplary embodiment, the epitaxial layer 11 surrounds the sidewall of the channel 73 and forms a ring structure extending along the direction parallel to the substrate.

[0143] In an exemplary embodiment, the material of the epitaxial layer 11 can include silicon.

[0144] In an exemplary embodiment, the thickness of the epitaxial layer 11 is less than or equal to 5 nanometers and greater than or equal to 0.1 nanometers.

[0145] In an exemplary embodiment, the semiconductor device manufacturing method of the present disclosure is different from Figure 10 The semiconductor device manufacturing method of the present disclosure is different from the semiconductor device manufacturing method shown in the difference, and after step 103 and before step 104, the semiconductor device manufacturing method of the present disclosure further includes forming an epitaxial layer.

[0146] The forming of the epitaxial layer includes: on the basis of the substrate 1 with the aforementioned pattern, a silicon thin film is deposited on the exposed branches of the conductive layer in the cavity and the groove by an atomic layer deposition process, so that the silicon thin film forms an epitaxial layer 11, and the epitaxial layer 11 covers part of the sidewalls of the branches, as shown in Figure 1 .

[0147] In an exemplary embodiment, the manufacturing method of the semiconductor device of the embodiments of the present disclosure is different from the manufacturing method of the semiconductor device shown in Figure 11 , in that step 105, the gate insulating layer and the gate electrode are formed.

[0148] The forming of the gate insulating layer and the gate electrode includes: on the basis of the substrate with the aforementioned pattern, a channel exposing the sidewalls of the branches of the conductive layer 32 in each layer is formed in the first insulating layer 61 and the second insulating layer 62 by patterned etching, the channel surrounds the sidewalls of the branches of the conductive layer 32 in each layer, forms an annular structure extending along the first direction D1, and exposes the sidewalls of the branches of the conductive layer 32 in each layer corresponding to the channel; then, a silicon thin film is deposited on the exposed sidewalls of the branches by an epitaxial process, so that the silicon thin film forms an epitaxial layer 11; then, the gate insulating layer 72 and the gate electrode 71 are sequentially formed in the channel, the gate insulating layer 72 surrounds the sidewalls of the branches of the conductive layer 32 in each layer through the epitaxial layer 11, the gate electrode 71 surrounds the sidewalls of the branches of each layer through the gate insulating layer 72 and the epitaxial layer 11, the gate electrode 71 is insulated from the sidewalls of the branches of each layer through the gate insulating layer 72, and the area of the branches of the conductive layer 32 corresponding to the gate electrode 71 forms a channel 73; then, the gap of the channel is filled with an insulating material, as shown in Figure 9a .

[0149] In the semiconductor device of the embodiments of the present disclosure, the epitaxial layer 11 is arranged on the sidewalls of the channel 73 and overlaps the orthogonal projection of the channel 73 on the substrate, and the epitaxial layer 11 does not overlap the orthogonal projection of the first electrode 74, the second electrode 75 and the first capacitor electrode 91 on the substrate.

[0150] In the semiconductor device of the embodiments of the present disclosure, the epitaxial layer can optimize the interface of the conductive layer 32, improve the disadvantage that the material of the conductive layer 32 does not have a stable oxide, reduce the interface state of the conductive layer 32, improve the mobility of the carriers of the conductive layer 32, and reduce the off current, thereby improving the electrical properties of the semiconductor device.

[0151] In some embodiments, the embodiments of the present disclosure provide a semiconductor device, and the semiconductor device of the embodiments of the present disclosure is different from the semiconductor device shown in ​ and 9bThe difference of the semiconductor device shown is that the thickness of the epitaxial layer of the semiconductor device of the embodiment of the present disclosure is greater than or equal to 3 nanometers, the epitaxial layer of the semiconductor device of the embodiment of the present disclosure can be used as a channel, and the conductive layer can be used as a support layer, thereby improving the compatibility of the semiconductor device.

[0152] The embodiment of the present disclosure also provides a manufacturing method of a semiconductor device, comprising:

[0153] forming, along the thickness direction of the substrate, a stack structure of sequentially and alternately arranged sacrificial layers and conductive layers on the substrate, the lattice mismatch degree of the sacrificial layers and the conductive layers being less than or equal to 0.5%;

[0154] forming, by patterned etching, a groove extending along a direction perpendicular to the substrate in the stack structure, the groove exposing the sidewall of the conductive layer and the sidewall of the sacrificial layer;

[0155] selectively etching the exposed sidewall of the sacrificial layer to remove the sacrificial layer, forming a cavity, and retaining the conductive layer, the cavity exposing at least part of the side surface of the conductive layer;

[0156] filling the cavity and the groove with an insulating layer;

[0157] removing part of the insulating layer to form a channel, the channel exposing at least part of the side surface of the conductive layer;

[0158] forming, on the exposed side surface of the conductive layer, a gate insulating layer and a gate electrode in sequence.

[0159] In an exemplary embodiment, the material of the sacrificial layer is aluminum gallium arsenide, and the material of the conductive layer is gallium arsenide.

[0160] In an exemplary embodiment, the material of the sacrificial layer is gallium arsenide, and the material of the conductive layer is aluminum gallium arsenide.

[0161] In an exemplary embodiment, the stack structure comprises n layers of sacrificial layers and n layers of conductive layers, n is a natural number greater than or equal to 2, the film layer close to the substrate side in the stack structure is a sacrificial layer, and the film layer away from the substrate side in the stack structure is a conductive layer.

[0162] In an exemplary embodiment, after selectively etching the exposed sidewall of the sacrificial layer to remove the sacrificial layer and form a cavity, the method further comprises:

[0163] forming an epitaxial layer on the exposed side surface of the conductive layer;

[0164] Alternatively, after removing part of the insulating layer to form a channel, the method further comprises:

[0165] forming an epitaxial layer on the side of the exposed conductive layer.

[0166] In an exemplary embodiment, the thickness of the epitaxial layer is less than or equal to 5 nanometers, and greater than or equal to 0.1 nanometers.

[0167] In an exemplary embodiment, the thickness of the epitaxial layer is greater than 5 nanometers.

[0168] In an exemplary embodiment, the material of the epitaxial layer is silicon.

[0169] In an exemplary embodiment, after sequentially forming a gate insulating layer and a gate electrode on the side of the exposed conductive layer, further comprising:

[0170] by patterned etching, removing one end of each of the conductive layers to form a strip-shaped slot;

[0171] by a deposition process, forming a bit line in the strip-shaped slot, the bit line being connected to the corresponding conductive layer.

[0172] In an exemplary embodiment, after forming a bit line in the strip-shaped slot by a deposition process, further comprising:

[0173] by patterned etching, removing the insulating layer corresponding to the one end of the conductive layer away from the bit line to expose the one end of the conductive layer;

[0174] by a deposition process, sequentially forming a capacitor dielectric layer and a second capacitor electrode on the one end of the conductive layer, so that the one end of the conductive layer forms a first capacitor electrode.

[0175] The embodiments of the present disclosure also provide an electronic device comprising a semiconductor device manufactured by the method of manufacturing a semiconductor device of any of the preceding embodiments. The electronic device can be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply, or the like. The storage device can include a memory in a computer, and the like, which is not limited herein.

[0176] Although the embodiments of the present disclosure are as described above, the content described is only the embodiments adopted for the purpose of facilitating the understanding of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure. The patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method comprises: forming, along a thickness direction of a substrate, a stack structure of alternating layers of a sacrificial layer and a conductive layer on the substrate, a lattice mismatch degree of the sacrificial layer and the conductive layer being less than or equal to 0.5%; forming, by patterned etching, a groove in the stack structure extending along a direction perpendicular to the substrate, the groove exposing a sidewall of the conductive layer and a sidewall of the sacrificial layer; selectively etching the exposed sidewall of the sacrificial layer to remove the sacrificial layer, form a cavity, and retain the conductive layer, the cavity exposing at least a portion of a side surface of the conductive layer; filling the cavity and the groove with an insulating layer; removing a portion of the insulating layer to form a channel, the channel exposing at least a portion of the side surface of the conductive layer; forming, on the exposed side surface of the conductive layer, a gate insulating layer and a gate electrode in sequence around the conductive layer.

2. The method of manufacturing a semiconductor device according to claim 1, wherein The material of the sacrificial layer is aluminum gallium arsenide, and the material of the conductive layer is gallium arsenide.

3. The method of manufacturing a semiconductor device according to claim 1, wherein The material of the sacrificial layer is gallium arsenide, and the material of the conductive layer is aluminum gallium arsenide.

4. The method of manufacturing a semiconductor device according to Claim 1, wherein The sum of the thickness of the sacrificial layer and the thickness of the adjacent conductive layer is greater than or equal to 20 nanometers and less than or equal to 100 nanometers.

5. The method of manufacturing a semiconductor device according to Claim 1, wherein The stack structure comprises n layers of sacrificial layers and n layers of conductive layers, n being a natural number greater than or equal to 2, the film layer near the substrate in the stack structure being a sacrificial layer, and the film layer away from the substrate in the stack structure being a conductive layer.

6. The method of manufacturing a semiconductor device according to any one of claims 1 to 5, wherein After selectively etching the exposed sidewall of the sacrificial layer to remove the sacrificial layer, forming a cavity, and retaining the conductive layer, the method further comprises: forming an epitaxial layer on the exposed side surface of the conductive layer; Alternatively, after removing a portion of the insulating layer to form a channel, the method further comprises: forming an epitaxial layer on the exposed side surface of the conductive layer.

7. The method of manufacturing a semiconductor device according to claim 6, wherein The thickness of the epitaxial layer is less than or equal to 5 nanometers and greater than or equal to 0.1 nanometer.

8. The method of manufacturing a semiconductor device according to claim 6, wherein The thickness of the epitaxial layer is greater than 5 nanometers.

9. The method of manufacturing a semiconductor device according to Claim 6, wherein The material of the epitaxial layer is silicon.

10. The method of manufacturing a semiconductor device according to any one of claims 1 to 5, wherein After forming, on the exposed side surface of the conductive layer, a gate insulating layer and a gate electrode in sequence around the conductive layer, the method further comprises: removing one end of each of the conductive layers by patterned etching to form a plurality of strip-shaped grooves; forming bit lines in each of the strip-shaped grooves by a deposition process, each of the bit lines being connected to the corresponding conductive layer.

11. The method of manufacturing a semiconductor device according to Claim 10, wherein After forming bit lines in each of the strip-shaped grooves by a deposition process, the method further comprises: removing the insulating layer corresponding to the one end of the conductive layer away from the bit line by patterned etching to expose the one end of the conductive layer; forming, on the one end of the conductive layer, a capacitor dielectric layer and a second capacitor electrode in sequence by a deposition process, so that the one end of the conductive layer forms a first capacitor electrode.

12. A semiconductor device, characterized by comprising: The semiconductor device is manufactured by the method of any one of claims 1 to 11, and the semiconductor device comprises at least a plurality of transistors arranged in sequence along a thickness direction of a substrate. The transistor comprises a channel, a gate electrode surrounding a sidewall of the channel, a gate insulating layer arranged between the channel and the gate electrode, a first electrode and a second electrode; the first electrode is connected with the second electrode through the channel, the first electrode, the channel and the second electrode are of an integrated structure and comprise a same conductive material.

13. The semiconductor device of claim 12, wherein, A buffer layer is further included, and the buffer layer is arranged on a side of the substrate facing the transistor.

14. The semiconductor device of claim 12, wherein, The same conductive material is gallium arsenide or aluminum gallium arsenide.

15. The semiconductor device of claim 12, wherein, An epitaxial layer is further included, and the epitaxial layer is arranged at least between the channel and the gate insulating layer.

16. An electronic device, comprising: The semiconductor device comprises the transistor as claimed in any one of claims 12 to 15.

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