Semiconductor device, memory system, and method of manufacturing semiconductor device

Abstract

The embodiment of the invention provides a semiconductor device, a memory system and a manufacturing method of the semiconductor device. The semiconductor device comprises a plurality of semiconductor columns which are arranged in an array along a first direction and a second direction, and the adjacent semiconductor columns in the first direction are respectively provided with first side walls which are opposite to each other; the conductive shielding layer is located on the outer side of the first side wall and extends in the second direction; the filling layer is positioned between the conductive shielding layers; wherein the first direction is perpendicular to the second direction.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor device, a memory system, and a method for manufacturing a semiconductor device. Background Art

[0002] In recent years, in order to improve the storage density of semiconductor memory, the size of memory cells has been continuously reduced. However, as the size of memory cells decreases, the coupling effect of adjacent memory cells intensifies, and due to process limitations, it is difficult to improve the electrical performance caused by the coupling effect. Summary of the invention

[0003] The present application provides a semiconductor device, a memory system, and a method for manufacturing a semiconductor device that can at least partially solve the above-mentioned problems existing in the related art or other problems in the art.

[0004] In a first aspect, some embodiments of the present application provide a semiconductor device. The semiconductor device includes: a plurality of semiconductor pillars arranged in an array along a first direction and a second direction, wherein adjacent semiconductor pillars in the first direction respectively have first side walls opposite to each other; a conductive shielding layer located outside the first side wall and extending along the second direction; and a filling layer located between the conductive shielding layers; wherein the first direction is perpendicular to the second direction.

[0005] In some embodiments, the thickness of the conductive shielding layer in the first direction is substantially the same.

[0006] In some embodiments, the semiconductor device further includes a first oxide layer located between the first sidewall and the conductive shielding layer.

[0007] In some embodiments, the conductive shielding layer includes: a first adhesive layer located on a surface of the first oxide layer and extending along the second direction; and a first metal layer located on a surface of the first adhesive layer and extending along the second direction.

[0008] In some embodiments, the semiconductor device has a first region and a second region arranged along a second direction, the second region is located on both sides of the first region, the conductive shielding layer extends in the first region and the second region, and in a third direction, the size of the conductive shielding layer in at least one second region is larger than its size in the first region, and the third direction is perpendicular to the first direction and the second direction.

[0009] In some embodiments, the semiconductor device further includes: a first contact structure located in the second region and connected to the conductive shielding layer.

[0010] In some embodiments, the semiconductor pillar has a second sidewall opposite to the first sidewall, and the semiconductor device further includes: a gate oxide layer located on a surface of the second sidewall; and a gate layer located on a surface of the gate oxide layer and extending along the second direction.

[0011] In some embodiments, the gate layer includes: a second adhesion layer located on a surface of the gate oxide layer and extending along a second direction; and a second metal layer located on a surface of the second adhesion layer and extending along the second direction.

[0012] In some embodiments, ends of the plurality of semiconductor pillars arranged along the first direction are connected to each other.

[0013] In a second aspect, some embodiments of the present application provide a memory system, which includes: a memory device, including a semiconductor device as mentioned in any of the above embodiments; and a controller, coupled to the memory device, for controlling the memory device to store data.

[0014] In a third aspect, some embodiments of the present application provide a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes: forming a first trench extending along a first direction from a first side of a semiconductor layer, and filling the first trench with an insulating material; forming a second trench and a third trench extending along a second direction from the first side, the second trench and the third trench are arranged alternately, and the first direction is perpendicular to the second direction; forming a conductive shielding layer on the inner side of the second trench, and forming a filling layer on the inner side of the conductive shielding layer; and forming a gate oxide layer and a gate layer in the third trench.

[0015] In some embodiments, in the first direction, the size of the second groove is smaller than the size of the third groove; wherein, forming the second groove and the third groove extending along the second direction from the first side includes: forming the second groove and the initial third groove extending along the second direction from the first side, wherein, in the first direction, the size of the second groove is equal to the size of the initial third groove; and increasing the size of the initial third groove in the first direction through an etching process to form the third groove.

[0016] In some embodiments, sequentially forming a gate oxide layer and a gate layer in the third trench includes: forming a barrier layer at the bottom of the third trench; forming a gate oxide layer on the sidewalls of the third trench; forming an initial gate layer on the surface of the gate oxide layer and the surface of the barrier layer; removing a portion of the initial gate layer located on the surface of the barrier layer to disconnect the initial gate layer; and removing a portion of the initial gate layer close to the first side to form a gate layer.

[0017] In some embodiments, forming a conductive shielding layer inside the second trench and forming a filling layer inside the conductive shielding layer includes: forming an initial conductive shielding layer inside the second trench; and removing a portion of the initial conductive shielding layer close to the first side.

[0018] In some embodiments, the manufacturing method further includes: removing a portion of the initial conductive shielding layer from a second side of the semiconductor layer opposite to the first side to form the conductive shielding layer.

[0019] In some embodiments, the semiconductor layer has a first region and a second region arranged along a second direction, and the second region is located on both sides of the first region; wherein, removing a portion of the initial conductive shielding layer from a second side of the semiconductor layer opposite to the first side includes: removing a portion of the initial conductive shielding layer located in the first region from the second side to form a conductive shielding layer; and filling the space formed after removing a portion of the initial conductive shielding layer with insulating material.

[0020] In some embodiments, the manufacturing method further includes: forming a first contact structure connected to the conductive shielding layer in the second region.

[0021] In some embodiments, before forming the initial conductive shielding layer inside the second trench, the manufacturing method further includes: forming a first oxide layer on an inner wall of the second trench.

[0022] According to at least one embodiment of the present application, the semiconductor device, memory system and method for manufacturing a semiconductor device provided by the present application, because the conductive shielding layer is a thin layer structure and the filling layer is located on the inner side of the conductive shielding layer, the conductive shielding layer can have a relatively uniform thickness in the D1 direction, and can also ensure the size matching of the conductive shielding layer and the gate layer in the D3 direction. In addition, the filling layer can reduce the risk of damage to adjacent structures, which is beneficial to improving the yield and electrical performance of the final product. On the other hand, the conductive shielding layer with a thin layer structure is easier to implement in terms of process, and has more advantages in iterative miniaturization capabilities. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings, in which:

[0024] Figure 1A and Figure 1B They are respectively cross-sectional schematic diagrams of the semiconductor device provided by the embodiments of the present application taken on different planes perpendicular to the third direction;

[0025] Figure 1C The semiconductor device provided by the embodiment of the present application is Figure 1A or Figure 1B A schematic cross-sectional view taken along line AA' is shown;

[0026] Figure 2 is a block diagram of a system having a memory system provided by an embodiment of the present application;

[0027] Figure 3 is a schematic flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0028] FIG. 4A to FIG. 13 is a schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present application; and

[0029] FIG. 14A to FIG. 17 It is a schematic diagram of the structure of a semiconductor device during the manufacturing process provided by another embodiment of the present application. DETAILED DESCRIPTION

[0030] In order to better understand the present application, a more detailed description will be made of various aspects of the present application with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0031] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first adhesive layer discussed in this application may also be referred to as the second adhesive layer, and vice versa.

[0032] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0033] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0034] Unless otherwise specified, all words (including engineering terms and scientific and technological terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0035] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments in this application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method recorded in this application are not necessarily limited to the recorded order, but can be performed in any order or in parallel.

[0036] In addition, when "connect" or "couple" is used in the present application, it can indicate direct contact or indirect contact between corresponding components, unless otherwise clearly defined or inferred from the context. The present application will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0037] An embodiment of the present application provides a semiconductor device. Figure 1A and Figure 1B They are respectively schematic cross-sectional views of the semiconductor device provided by the embodiments of the present application taken on different planes perpendicular to the third direction (D3). Figure 1C The semiconductor device provided by the embodiment of the present application is Figure 1A or Figure 1B The cross-sectional schematic diagram shown is taken along the line AA'. Figure 1A and Figure 1B They are Figure 1C The semiconductor device shown is a cross-sectional view taken along the D3 direction. The semiconductor device may be a memory device or a part of a memory device. For example, the memory device may be a dynamic random access memory (DRAM). In a DRAM memory, each memory cell generally includes a transistor and a capacitor.

[0038] It should be noted that, hereinafter, the D1 direction, the D2 direction, and the D3 direction in each of the drawings illustrate the spatial relationship of the components in the semiconductor device. For example, the D3 direction is the extension direction of the semiconductor column, and the D1 direction and the D2 direction are two directions that intersect (e.g., are perpendicular) to each other on a plane that intersects (e.g., is perpendicular) to the extension direction. For example, the D1 direction is the bit line direction, and the D2 direction is the word line direction. The same concept will be used throughout this application to describe the spatial relationship of the components in the semiconductor device.

[0039] like Figure 1A and Figure 1CAs shown, the semiconductor device 100 includes a plurality of semiconductor pillars (e.g., 111a) arranged in an array along the D1 direction and the D2 direction. For example, each semiconductor pillar (e.g., 111a) extends along the D3 direction. As will be described in detail below, the semiconductor pillars (e.g., 111a) can be formed using a semiconductor substrate, and the extension direction (e.g., D3 direction) of the semiconductor pillars (e.g., 111a) can be perpendicular to the plane extension direction of the semiconductor substrate.

[0040] In some embodiments, the semiconductor pillar (e.g., 111a) has a first sidewall 112 and a second sidewall 113 opposite to each other in the D1 direction. The semiconductor device 100 may further include a gate oxide layer 114. The gate oxide layer 114 is located on the surface of the second sidewall 113. For example, the gate oxide layer 114 extends continuously along the D2 direction and is located on the surface of the second sidewall 113 of a row of semiconductor pillars (e.g., 111a) arranged along the D2 direction. For example, the material of the gate oxide layer 114 may include silicon oxide (SiO2), silicon oxynitride (SiO x N y ) or any other suitable insulating oxide material or materials.

[0041] In some embodiments, the semiconductor device 100 may further include a gate layer 115 located on a surface of the gate oxide layer 114. The gate layer 115 extends along the direction D2 (eg, continuously extends). Figure 1C , the gate layer 115 may include a second adhesive layer 116 and a second metal layer 117 attached to each other. The second adhesive layer 116 may be located on the surface of the gate oxide layer 114 and extend along the D2 direction (for example, continuously extend). The second metal layer 117 may be located on the surface of the second adhesive layer 116 and extend along the D2 direction (for example, continuously extend). In other words, the second adhesive layer 116 is located between the second metal layer 117 and the gate oxide layer 114. The second adhesive layer 116 helps to improve the bonding performance between the second metal layer 117 and the gate oxide layer 114. For example, the material of the second adhesive layer 116 may include one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or any other suitable material. For example, the material of the second metal layer 117 may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), or any other suitable metal material. In other examples, the gate layer 115 may not have a composite structure, but may be composed of a conductive material, and the present application does not make specific restrictions on this.

[0042] According to the above description, in some embodiments, a semiconductor column (e.g., 111a), and a gate oxide layer 114 and a gate layer 115 covering a portion of the second side wall 113 of the semiconductor column (e.g., 111a) can constitute a transistor. In the transistor, the semiconductor column (e.g., 111a) serves as a channel, the gate layer 115 corresponds to a portion of the second side wall 113 of the semiconductor column (e.g., 111a) as a gate, and the two ends of the semiconductor column (e.g., 111a) in the extension direction serve as a source and a drain, respectively. Since the extension direction (e.g., D3 direction) of the semiconductor column (e.g., 111a) is perpendicular to the plane extension direction of the semiconductor substrate, the transistor can also be called a vertical channel transistor. Vertical channel transistors can effectively reduce the plane occupied area and improve storage density. In this case, the gate layer 115 extending in the D2 direction can be used as a word line to control a row of storage cells arranged along the D2 direction.

[0043] In some embodiments, ends of a plurality of semiconductor pillars (eg, 111a) arranged along the D1 direction are connected to each other. For example, ends of a plurality of semiconductor pillars (eg, 111a) arranged along the D1 direction are connected to the same bit line.

[0044] In some embodiments, a first isolation structure 118 is provided between adjacent gate layers 115 in the D1 direction. For example, the material of the first isolation structure 118 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. Figure 1A As shown, the transistors adjacent to each other in the direction D1 are mirror-symmetric with respect to the first isolation structure 118 .

[0045] Continue to refer Figure 1A and Figure 1C, the first side walls 112 of two semiconductor pillars (e.g., 111a and 111b) adjacent in the D1 direction face each other. In one (e.g., 111a) of the two semiconductor pillars (e.g., 111a and 111b) and another semiconductor pillar (e.g., 111c) adjacent thereto in the D1 direction, the second side walls 113 also face each other. The semiconductor device 100 further includes a conductive shielding layer 121 and a filling layer 125. The conductive shielding layer 121 is located outside the first side wall 112 of the semiconductor pillar (e.g., 111a or 111b) and extends (e.g., continuously) along the D2 direction. For example, the conductive shielding layer 121 is substantially parallel to the first side wall 112 of the semiconductor pillar (e.g., 111a or 111b). The filling layer 125 is located between the conductive shielding layers 121. For example, the material of the conductive shielding layer 121 may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material. For example, the material of the filling layer 125 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. For example, the thickness of the conductive shielding layer 121 in the D1 direction is substantially the same (eg, the error is within ±10%).

[0046] In some embodiments, Figure 1A As shown, from a direction perpendicular to D3, the conductive shielding layer 121 may be roughly annular. For example, the first end of the conductive shielding layer 121 in the D3 direction is open, and the second end in the D3 direction is at least partially open. The filling layer 125 may be located inside the annular conductive shielding layer 121.

[0047] According to the above description, in some embodiments, the conductive shielding layer 121 can control the transistor from the back side of the transistor channel (the side of the channel where the gate is not set), for example, by applying a ground voltage to the conductive shielding layer 121 to improve the coupling effect between a row of memory cells arranged along the D2 direction and another row of memory cells.

[0048] In some exemplary embodiments, the positions of the conductive shielding layer and the filling layer are all replaced by conductive materials. However, due to process limitations, gaps will appear in the conductive shielding layer during the formation of such a conductive shielding layer, making it difficult to ensure the thickness uniformity of the conductive shielding layer in the D1 direction, and it is also difficult to ensure the size matching of the conductive screen layer and the gate layer in the D3 direction. In addition, due to the presence of gaps in the conductive shielding layer, the process of etching the conductive shielding layer will damage the adjacent structures, thereby affecting the yield and electrical performance. On the other hand, with the continuous miniaturization of semiconductor devices, it will become more difficult to form a conductive shielding layer composed entirely of conductive materials.

[0049] According to the semiconductor device provided by the embodiment of the present application, since the conductive shielding layer is a thin layer structure and the filling layer is located on the inner side of the conductive shielding layer, the conductive shielding layer can have a relatively uniform thickness in the D1 direction, and the size matching of the conductive shielding layer and the gate layer in the D3 direction can be ensured. In addition, the filling layer can reduce the risk of damage to adjacent structures, which is beneficial to improving the yield and electrical performance of the final product. On the other hand, the conductive shielding layer with a thin layer structure is easier to implement in terms of process, and has more advantages in iterative miniaturization capabilities.

[0050] In some embodiments, the semiconductor device 100 may further include a first oxide layer 124. The first oxide layer 124 may be located between the first sidewall 112 of the semiconductor pillar (eg, 111a) and the conductive shielding layer 121. For example, the material of the first oxide layer 124 may include silicon oxide (SiO2), silicon oxynitride (SiO x N y ) or any other suitable insulating oxide material. Figure 1A , viewed from a direction perpendicular to D3, the first oxide layer 124 may be roughly annular and surround the outer periphery of the conductive shielding layer 121. In this embodiment, the first oxide layer 124 is disposed between the first sidewall 112 of the semiconductor pillar (e.g., 111a) and the conductive shielding layer 121, which helps to improve the control effect of the conductive shielding layer 121.

[0051] In some embodiments, Figure 1CAs shown, the conductive shielding layer 121 may include a first adhesive layer 122 and a first metal layer 123 attached to each other. The first adhesive layer 122 may be located on the surface of the first oxide layer 124 and extend along the D2 direction (e.g., continuously extend). The first metal layer 123 may be located on the surface of the first adhesive layer 122 and extend along the D2 direction (e.g., continuously extend). In other words, the first adhesive layer 122 is located between the first metal layer 123 and the first oxide layer 124. The first adhesive layer 122 helps to improve the bonding performance between the first metal layer 123 and the first oxide layer 124. For example, the material of the first adhesive layer 122 may include one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or any other appropriate material. For example, the material of the first metal layer 123 may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), or any other appropriate metal material. In other examples, the conductive shielding layer 121 may not have a composite structure, but may be composed of a conductive material, which is not specifically limited in this application.

[0052] In some embodiments, Figure 1B and Figure 1C As shown, the semiconductor device 100 may include a first area 101 and a second area 102 arranged along the D2 direction, wherein the second area 102 is located on both sides of the first area 101. For example, at least part of the first area 101 may be a storage area, and the second area 102 may be a connection area. The conductive shielding layer 121 extends (for example, continuously extends) in the first area 101 and the second area 102. In the D3 direction, the size of the conductive shielding layer 121 located in at least one second area 102 is larger than its size located in the first area 101. For example, the second end of the conductive shielding layer 121 in the D3 direction is open in the part located in the first area 101. The second end is open in the part located in one second area 102, and is closed in the part located in another second area 102. In this embodiment, the conductive shielding layer 121 has different sizes in the D3 direction, which can take into account the size matching of the conductive shielding layer 121 and the gate layer 115 in the D3 direction, while realizing the lead-out of the conductive shielding layer 121 in the D3 direction.

[0053] In some embodiments, Figure 1CAs shown, the semiconductor device 100 may further include a first contact structure 126. The first contact structure 126 is located in the second region 102 and is connected to the conductive shielding layer 121. For example, the first contact structure 126 extends along the D3 direction to the portion of the conductive shielding layer 121 located in the second region 102 to directly contact the conductive shielding layer 121, thereby achieving connection between the first contact structure 126 and the conductive shielding layer 121. For example, the material of the first contact structure 126 may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO) or any other appropriate conductive material. In this embodiment, the first contact structure 126 uses the portion of the conductive shielding layer 121 located in the second region 102 to have a larger size in the D3 direction, and leads the conductive shielding layer 121 out from the D3 direction, which is more friendly to the preparation process of the first contact structure 126.

[0054] An embodiment of the present application also provides a memory system. Figure 2 is a block diagram of a system with a memory system provided in an embodiment of the present application.

[0055] like Figure 2 As shown, the system 200 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (the electronic device has the memory system 210 located therein). Figure 2 As shown, the system 200 may include a host 220 and a memory system 210. The memory system 210 has one or more memory devices 211 and a controller 212. The host 220 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). The host 220 may be configured to send or receive data to and from the memory device 211.

[0056] In some embodiments, the controller 212 is coupled to the memory device 211 and the host 220, and is configured to control the memory device 211. For example, the controller 212 may be configured to control operations such as read, erase, and program of the memory device 211. The controller 212 may also manage data stored in the memory device 211 and communicate with the host 220. For example, the controller 212 may communicate with an external device (e.g., the host 220) according to a specific communication protocol.

[0057] An embodiment of the present application also provides a method for manufacturing a semiconductor device. Figure 3 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application. Figure 3 As shown, a method 300 for manufacturing a semiconductor device (hereinafter referred to as manufacturing method 300 ) may include the following steps.

[0058] S310 , forming a first trench extending along a first direction from a first side of the semiconductor layer, and filling the first trench with an insulating material.

[0059] S320 , forming second grooves and third grooves extending along the second direction from the first side, wherein the second grooves and the third grooves are arranged alternately.

[0060] S330 , forming a conductive shielding layer inside the second trench, and forming a filling layer inside the conductive shielding layer.

[0061] S340, forming a gate oxide layer and a gate layer in the third trench.

[0062] According to the manufacturing method of the semiconductor device provided by this embodiment, since the conductive shielding layer is a thin layer structure and a filling layer is formed on the inner side of the conductive shielding layer, the conductive shielding layer can have a relatively uniform thickness in the D1 direction, and the difficulty of controlling the etching process can be reduced in the process of removing the initial conductive shielding layer from the first side and / or the second side, which is conducive to ensuring the size matching of the conductive shielding layer finally formed with the gate layer in the D3 direction. In addition, since a filling layer is formed on the inner side of the conductive shielding layer, the risk of damaging the adjacent structure can be reduced in the process of etching the initial conductive shielding layer, which is conducive to improving the yield and electrical performance of the final product. On the other hand, compared with filling the second groove with a conductive material to form a conductive shielding layer, by forming a conductive shielding layer with a thin layer structure, the process is easier to implement, and the iterative miniaturization capability is more advantageous.

[0063] FIG. 4A to FIG. 13 Schematic diagram of the structure of the semiconductor device in the manufacturing process provided by the embodiment of the present application. For example, each intermediate structure of the semiconductor device in the manufacturing process of the embodiment can be based on Figure 3 The manufacturing method shown is formed. FIG. 4A to FIG. 13The above steps S310 to S340 are explained by way of example.

[0064] Figure 4A and Figure 4B An intermediate structure 400a including a semiconductor layer 431, a first dielectric layer 432 and a second dielectric layer 433 is shown. Figure 4A is a schematic top view of the intermediate structure 400a. Figure 4B It is along Figure 4A A schematic cross-sectional view taken along line BB' is shown. Figure 5A and Figure 5B The intermediate structure 400b is shown after forming the first trench and filling the insulating material 435. Figure 5A is a schematic top view of the intermediate structure 400b. Figure 5B It is along Figure 5A It should be noted that in order to more clearly show the spatial relationship between the components in the intermediate structure 400b, Figure 5A The first dielectric layer 432 and the second dielectric layer 433 are omitted in the figure, and the same illustration method is used for each top view schematic diagram below.

[0065] In step S310, Figure 4A and Figure 4B As shown, in some embodiments, the semiconductor layer 431 may be a semiconductor substrate. For example, the material of the semiconductor substrate may be silicon (Si), germanium (Ge), gallium arsenide (GaAs) or indium phosphide (InP). For another example, the semiconductor substrate may be a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) substrate, etc.

[0066] In some embodiments, the material of the first dielectric layer 432 may include silicon oxide (SiO2), and the material of the second dielectric layer 433 may include silicon nitride (Si3N4). In some examples, the first dielectric layer 432 and the second dielectric layer 433 may be sequentially formed on the semiconductor layer 431 using a thin film deposition process of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In other examples, the first dielectric layer 432 may be formed on the semiconductor layer 431 using a dry oxidation method or a wet oxidation method.

[0067] like Figure 5A and Figure 5BAs shown, in some embodiments, the semiconductor layer 431 may be patterned from the first side (e.g., the front side of the semiconductor layer 431) by photolithography and etching (e.g., dry etching and / or wet etching) processes to form a first trench (not shown) extending in the D1 direction, and at the same time, a semiconductor wall 434 extending in the D1 direction is formed. For example, the second dielectric layer 433 may be used as a hard mask layer for etching the semiconductor layer 431. The semiconductor wall 434 and the unetched semiconductor layer 431 are arranged vertically in the D1 direction. Since the semiconductor wall 434 is formed by etching the semiconductor layer 431, the semiconductor wall 434 is made of the same material as the semiconductor layer 431. Further, a thin film deposition process of CVD, PVD, ALD, or any combination thereof may be used to fill the first trench with an insulating material 435, so that the semiconductor walls 434 are insulated and isolated by the insulating material 435.

[0068] Fig. 6A and Figure 6B The intermediate structure 400c is shown after forming the second trench 436 and the initial third trench 437'. Fig. 6A is a schematic top view of the intermediate structure 400c. Figure 6B It is along Fig. 6A A schematic cross-sectional view taken along line CC' is shown. Fig. 7A and Figure 7B The intermediate structure 400d is shown after the first sacrificial material 438 is filled in the second trench 436 and the initial third trench 437'. Fig. 7A is a schematic top view of the intermediate structure 400d. Figure 7B It is along Fig. 7A A schematic cross-sectional view taken along line CC' is shown. Fig. 8A and Figure 8B The intermediate structure 400e is shown after the second trench 436 and the third trench 437 are formed. Fig. 8A is a schematic top view of the intermediate structure 400e. Figure 8B It is along Fig. 8A A schematic cross-sectional view taken along line CC' is shown.

[0069] In step S320, Fig. 8A and Figure 8B As shown, in some embodiments, a photolithography and etching (eg, dry etching and / or wet etching) process can be used to etch the semiconductor wall 434 and the insulating material 435 (see FIG. 4 ) formed on the semiconductor layer 431 from the first side. Figure 5A and Figure 5B) is patterned to form a second trench 436 and a third trench 437 extending in the D2 direction, and a plurality of semiconductor pillars 411 arranged in an array along the D1 direction and the D2 direction are formed. The second trench 436 and the third trench 437 are arranged alternately in the D1 direction. The semiconductor pillars 411 and the unetched semiconductor layer 431 are arranged vertically in the D1 direction. Since the semiconductor pillars 411 are formed by etching the semiconductor layer 431, the semiconductor pillars 411 and the semiconductor layer 431 are made of the same material. For example, the depths of the second trench 436 and the third trench 437 are less than the depths of the semiconductor wall 434 (refer to Figure 5A and Figure 5B ) in the direction D3. Thus, the ends of the semiconductor pillars 411 arranged along the direction D1 and close to the semiconductor layer 431 can be connected to each other through the semiconductor walls 434 that are not etched.

[0070] In some embodiments, the semiconductor layer 431 may include a first region 401 and a second region 402 arranged along the D2 direction, wherein the second region 402 is located on both sides of the first region 401. For example, at least a portion of the first region 401 may be a storage region, and the second region 402 may be a connection region. The second trench 436 and the third trench 437 extend in the first region 401 and the second region 402 on both sides.

[0071] In some embodiments, the dimension of the second trench 436 in the D1 direction may be smaller than the dimension of the third trench 437 in the D1 direction. For example, the second trench 436 and the third trench 437 having the above-mentioned dimension relationship may be formed by the method described below.

[0072] like Fig. 6A and Figure 6B As shown, the semiconductor wall 434 and the insulating material 435 (see FIG. 1 ) formed on the semiconductor layer 431 may be etched from the first side by photolithography and etching (eg, dry etching and / or wet etching). Figure 5A and Figure 5B ) is patterned to form a second trench 436 and an initial third trench 437' extending along the D2 direction. The second trench 436 and the initial third trench 437' are alternately arranged in the D1 direction, and the size of the second trench 436 in the D1 direction may be equal to the size of the initial third trench 437' in the D1 direction.

[0073] like Fig. 7A and Figure 7BAs shown, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to fill the second trench 436 and the initial third trench 437' with the first sacrificial material 438. For example, the first sacrificial material 438 may include polysilicon (Poly), carbon (Carbon), spin-on-carbon (SOC), spin-on-dielectric material (Spin-on-Dielectric) or any other appropriate sacrificial material.

[0074] In some embodiments, a mask layer (e.g., a photoresist layer and / or a hard mask layer) may be covered on the top surface of the initial third trench 437' filled with the first sacrificial material 438, and then the first sacrificial material 438 in the second trench 436 may be etched back to form a third dielectric layer 439 (see Fig. 8A and Figure 8B ). For example, the material of the third dielectric layer 439 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. For example, the material of the third dielectric layer 439 may be the same as that of the second dielectric layer 433.

[0075] In some embodiments, an etching (eg, dry etching and / or wet etching) process may be used to remove the first sacrificial material 438 in the initial third trench 437' and increase the size of the initial third trench 437' in the D1 direction to form a third trench 437 having a larger size in the D1 direction (see FIG. Fig. 8A and Figure 8B ). Optionally, in the process of increasing the size of the initial third trench 437' in the D1 direction, the size of the initial third trench 437' in the D3 direction may also increase. For example, the third dielectric layer 439 may protect the first sacrificial material 438 in the second trench 436 from being etched and maintain the size of the second trench 436 in the D1 direction. Optionally, after forming the third trench 437, an etching process (e.g., dry etching and / or wet etching) may be used to remove the first sacrificial material 438 and the third dielectric layer 439 in the second trench 436.

[0076] Fig.9A and Fig. 9B The intermediate structure 400f after forming the barrier layer 440 is shown. Fig.9A 400f is a top view of the intermediate structure. Fig. 9B It is along Fig.9A A schematic cross-sectional view taken along line CC' is shown. Fig. 10A and Fig. 10BThe intermediate structure 400g is shown after the gate oxide layer 414, the first oxide layer 424, the initial gate layer 415' and the initial conductive shielding layer 421' are formed. Fig. 10A It is a schematic cross-sectional view of the intermediate structure 400g taken on a plane perpendicular to the D2 direction. Fig. 10B It is along Fig. 10A A schematic cross-sectional view taken along line DD' is shown. Fig.11A and Fig. 11B The intermediate structure 400h is shown after forming the gate layer 415 and removing a portion of the initial conductive shielding layer 421' from the first side. Fig.11A It is a schematic cross-sectional view of the intermediate structure 400h taken in a direction perpendicular to D3. Fig. 11B It is along Fig.11A A schematic cross-sectional view taken along line CC' is shown. Fig. 12A and Fig. 12B The intermediate structure 400i is shown after the conductive shielding layer 421 is formed. Fig. 12A It is a schematic cross-sectional view of the intermediate structure 400i taken on a plane perpendicular to the D3 direction. Fig. 12B It is along Fig. 12A A schematic cross-sectional view taken along line AA' is shown.

[0077] Combine the following 9A to 12B Steps S330 and S340 are described with examples.

[0078] In steps S330 and S340, Fig.9A and Fig. 9B As shown, in some embodiments, when the third trench 437 is in an unfilled state, a barrier layer 440 may be formed at the bottom of the third trench 437 by using a thin film deposition process and an etching (e.g., dry etching and / or wet etching) process. Specifically, a material for forming the barrier layer 440 may be filled in the third trench 437 by using a thin film deposition process of CVD, PVD, ALD, or any combination thereof. Optionally, a chemical mechanical planarization (CMP) process may be used for planarization. Next, a wet etching process may be used to etch back the material filled in the third trench 437 to form the barrier layer 440 at the bottom of the third trench 437. For example, by controlling the parameters of the wet etching process (e.g., etching time, etchant material, or etching rate, etc.), a preset distance may be provided between the top surface of the barrier layer 440 (e.g., the surface facing the notch direction of the third trench 437) and the bottom surface of the second trench 436 in the D3 direction.

[0079] In some embodiments, the material of the barrier layer 440 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. For example, the barrier layer 440 may be composed of a single material or multiple materials, which is not limited in the present application. Optionally, the first sacrificial material 438 and the third dielectric layer 439 (see Fig. 8A and Figure 8B ) may be removed after forming the barrier layer 440. For example, while removing the third dielectric layer 439, the second dielectric layer 433 (refer to Figure 8B ) are also removed.

[0080] In some embodiments, Fig. 10A and Fig. 10B As shown, a gate oxide layer 414 may be formed on the sidewall of the third trench 437 by a dry oxidation method or a wet oxidation method. Optionally, when the second trench 436 is also in an unfilled state, during the process of forming the gate oxide layer 414, for example, the same dry oxidation method or wet oxidation method may be used to form a first oxide layer 424 on the inner wall of the second trench 436. As another option, the first sacrificial material 438 and the third dielectric layer 439 (see FIG. 4 ) in the second trench 436 are formed. Fig. 8A and Figure 8B ) is removed after the gate oxide layer 414 is formed, the first oxide layer 424 can be prevented from being formed on the inner wall of the second trench 436 during the process of forming the gate oxide layer 414. Fig. 10A and Fig. 10B, a thin film deposition process of CVD, PVD, ALD or any combination thereof may be used to sequentially form an adhesion layer 441 and a metal layer 442 on the inner side of the second trench 436 (e.g., the inner wall of the second trench 436 or the surface of the first oxide layer 424), the surface of the gate oxide layer 414, the surface of the barrier layer 440, and the surface of the first dielectric layer 432. The adhesion layer 441 and the metal layer 442 formed on the surface of the gate oxide layer 414 and the surface of the barrier layer 440 may serve as an initial gate layer 415', and the adhesion layer 441 and the metal layer 442 formed on the inner side of the second trench 436 (e.g., the inner wall of the second trench 436 or the surface of the first oxide layer 424) may serve as an initial conductive shielding layer 421'. For example, the material of the adhesion layer 441 may include one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or any other appropriate material. For example, the material of the metal layer 442 may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), or any other suitable metal material. In other examples, the adhesion layer 441 and the metal layer 442 may be replaced by a conductive material, which is not specifically limited in the present application.

[0081] In some embodiments, Fig.11A and Fig. 11B As shown, a punch etch process may be used to remove the initial gate layer 415' (see Fig. 10A and Fig. 10B ) is located on a portion of the surface of the barrier layer 440 to disconnect the initial gate layer 415'. For example, the cut that disconnects the initial gate layer 415' extends continuously along the D2 direction. In other words, from the D3 direction, the annular initial gate layer 415' is open at the first end near the semiconductor layer 431. Next, a thin film deposition process of CVD, PVD, ALD or any combination thereof can be used to form a first isolation structure 418 on the inner side of the initial gate layer 415', and in this process, a filling layer 425 can be formed on the inner side of the initial conductive shielding layer 421'. Optionally, a CMP process can be used for planarization to remove, for example, portions of the adhesion layer 441 and the metal layer 442 located on the surface of the first dielectric layer 432.

[0082] In some embodiments, an etching (e.g., dry etching and / or wet etching) process may be used to remove a portion of the initial gate layer 415' close to the first side to form the gate layer 415. For example, the gate layer 415 is reduced in size in the D3 direction compared to the initial gate layer 415'. In this process, the same etching (e.g., dry etching and / or wet etching) process may be used to remove a portion of the initial conductive shielding layer 421' close to the first side. For example, the initial conductive shielding layer 421' after removal is reduced in size in the D3 direction. For example, for the two end surfaces of the gate layer 415 and the initial conductive shielding layer 421' close to the first side in the D3 direction, the two end surfaces may be made substantially flush (e.g., within an error of ±10%) according to the actual control requirements of the transistor, or the end surface of the initial conductive shielding layer 421' may be made lower than the end surface of the gate layer 415, and the present application does not impose specific restrictions on this. It should be noted that the process of removing a portion of the initial gate layer 415 ′ close to the first side and a portion of the initial conductive shielding layer 421 ′ close to the first side may be achieved by different etching processes, and the present application does not impose any specific limitation on this.

[0083] In some embodiments, the second isolation structure 419 may be formed by an etching process (e.g., dry etching and / or wet etching) and a thin film deposition process. For example, the second isolation structure 419 is located in the second region 402. For example, the material of the second isolation structure 419 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. The second isolation structure 419 is used to disconnect the gate layer 415 located on both sides of the gate layer 415 in the D1 direction into two parts, so that the semiconductor pillar 411 located in the first area 401 is controlled by the disconnected part of the gate layer 415.

[0084] In some embodiments, any known process method in the art may be used to form a capacitor connection structure and a capacitor (not shown) connected to the end surface of the semiconductor pillar 411 away from the semiconductor layer 431. For example, the capacitor and the transistor may constitute a memory cell of a DRAM memory.

[0085] In some embodiments, Fig.11A and Fig. 11B The intermediate structure 400h is shown flipped 180° to allow subsequent processing from the second side of the semiconductor layer 431 (eg, the back side of the semiconductor layer 431). FIG. 12A to FIG. 12BAs shown, the semiconductor layer 431 may first be planarized from the second side of the semiconductor layer 431 by using a CMP process. Then, a portion of the initial conductive shielding layer 421' is removed from the second side of the semiconductor layer 431, for example, by using an etching (for example, dry etching and / or wet etching) process to form a conductive shielding layer 421. Exemplarily, the portion of the initial conductive shielding layer 421' removed may include: a portion of the initial conductive shielding layer 421' close to the second side and located in the first region 401, and a portion of the initial conductive shielding layer 421' close to the second side and located in one of the second regions 402. For example, among the initial conductive shielding layers 421' arranged in the direction D1, a portion of the odd-numbered initial conductive shielding layers 421' is removed from the second region 402 on the left, and a portion of the even-numbered initial conductive shielding layers 421' is removed from the second region 402 on the right. For another example, in the initial conductive shielding layer 421' arranged in the direction D1, a portion of the entire initial conductive shielding layer 421' is removed from the second region 402 located on the left, or a portion of the entire initial conductive shielding layer 421' is removed from the second region 402 located on the right. In the process of removing a portion of the initial conductive shielding layer 421' from the second side to form the conductive shielding layer 421, the barrier layer 440 can be used to protect the gate layer 415 from being damaged. Next, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to fill the space formed after removing a portion of the initial conductive shielding layer 421' with an insulating layer material, thereby forming the third isolation structure 420. For example, the material of the third isolation structure 420 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material or materials.

[0086] In some embodiments, compared to the initial conductive shielding layer 421 ′, Fig. 12B The portion of the conductive shielding layer 421 shown in the first region 401 is further reduced in size in the D3 direction. For example, for the two end surfaces of the gate layer 415 and the conductive shielding layer 421 close to the second side in the D3 direction, the two end surfaces can be made substantially flush (for example, with an error within ±10%) according to the actual control requirements of the transistor, or the end surface of the conductive shielding layer 421 can be made lower than the end surface of the gate layer 415, and the present application does not impose specific restrictions on this.

[0087] In some embodiments, the manufacturing method 300 may further include a step of forming a first contact structure. Fig.13The semiconductor device 400 after forming the first contact structure 426 is shown. According to the above description, the conductive shielding layer 421 can be led out from the D3 direction by using the portion of the conductive shielding layer 421 located in the second region 402 and the first contact structure 426. For example, an etching (e.g., dry etching and / or wet etching) process can be used to form a contact hole (corresponding to the outer contour of the first contact structure 426) extending to the portion of the conductive shielding layer 421 located in the second region 402 from the second side. For example, the contact hole can expose the conductive shielding layer 421. Then, a thin film deposition process such as CVD, PVD, ALD or any combination thereof can be used to fill the contact hole with one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO) or any other suitable conductive materials to form the first contact structure 426. In this embodiment, by utilizing the characteristic that the conductive shielding layer 421 has a larger size in the direction D3 in the second region 402 , the first contact structure 426 can have a smaller extension distance in the direction D3 , thereby reducing the difficulty in manufacturing the first contact structure 426 .

[0088] In this embodiment, since the conductive shielding layer is a thin layer structure and a filling layer is formed on the inner side of the conductive shielding layer, the conductive shielding layer can have a relatively uniform thickness in the D1 direction, and the difficulty of controlling the etching process can be reduced in the process of removing the initial conductive shielding layer from the first side and / or the second side, which is beneficial to ensure the size matching of the conductive shielding layer finally formed with the gate layer in the D3 direction. In addition, since a filling layer is formed on the inner side of the conductive shielding layer, the risk of damaging the adjacent structure can be reduced in the process of etching the initial conductive shielding layer, which is beneficial to improving the yield and electrical performance of the final product. On the other hand, compared to filling the second groove with a conductive material to form a conductive shielding layer, by forming a conductive shielding layer with a thin layer structure, the process is easier to implement, and the iterative miniaturization capability is more advantageous.

[0089] FIG. 14A to FIG. 17 1 is a schematic diagram of the structure of a semiconductor device in a manufacturing process according to another embodiment of the present application. For example, each intermediate structure of the semiconductor device in the manufacturing process of this embodiment can be based on Figure 3 The manufacturing method shown is formed. Among them, steps S310 and S320 are basically the same as those in the previous embodiment, and the present application will not repeat them here. FIG. 14A to FIG. 17 Steps S330 and S340 are explained by way of example.

[0090] Fig.14A and Fig. 14BThe intermediate structure 500g is shown after forming the gate oxide layer 514, the first oxide layer 524, the initial gate layer 515' and the initial conductive shielding layer 521'. Fig.14A It is a schematic cross-sectional view of the intermediate structure 500g taken in a direction perpendicular to D2. Fig. 14B It is along Fig.14A A schematic cross-sectional view taken along line DD' is shown. Fig.15A and Fig. 15B The intermediate structure 500h is shown after a portion of the initial gate layer 515' and a portion of the initial conductive shielding layer 521' are removed from the first side. Fig.15A is a schematic cross-sectional view of the intermediate structure 500h taken on a plane perpendicular to the D3 direction. Fig. 15B It is along Fig.15A A schematic cross-sectional view taken along line CC' is shown. Fig.16A and Fig. 16B The intermediate structure 500i is shown after the gate layer 515 and the conductive shielding layer 521 are formed. Fig.16A It is a schematic cross-sectional view of the intermediate structure 500i taken on a plane perpendicular to the D3 direction. Fig. 16B It is along Fig.16A A schematic cross-sectional view taken along line AA' is shown.

[0091] In steps S330 and S340, Fig.14A and Fig. 14B As shown, in some embodiments, the third trench 537 is in an unfilled state, and a gate oxide layer 514 can be first formed on the inner wall of the third trench 537 by a dry oxidation method or a wet oxidation method. Optionally, when the second trench 536 is also in an unfilled state, during the process of forming the gate oxide layer 514, for example, the same dry oxidation method or wet oxidation method can be used to form a first oxide layer 524 on the inner wall of the second trench 536. As another option, the first sacrificial material 438 and the third dielectric layer 439 (see FIG. 4 ) in the second trench 536 are formed. Fig. 8A and Figure 8B ) is removed after the gate oxide layer 514 is formed, the formation of the first oxide layer 524 on the inner wall of the second trench 536 can be avoided during the process of forming the gate oxide layer 514.

[0092] Next, continue to refer to Fig.14A and Fig. 14B, a thin film deposition process of CVD, PVD, ALD or any combination thereof may be used to sequentially form an adhesion layer 541 and a metal layer 542 on the inner side of the second trench 536 (e.g., the inner wall of the second trench 536 or the surface of the first oxide layer 524), the surface of the gate oxide layer 514, and the surface of the first dielectric layer 532. The adhesion layer 541 and the metal layer 542 formed on the surface of the gate oxide layer 514 may serve as an initial gate layer 515', and the adhesion layer 541 and the metal layer 542 formed on the inner side of the second trench 536 (e.g., the inner wall of the second trench 536 or the surface of the first oxide layer 524) may serve as an initial conductive shielding layer 521'. For example, the material of the adhesion layer 541 may include one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or any other appropriate material. For example, the material of the metal layer 542 may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), or any other appropriate metal material. In other examples, the adhesive layer 541 and the metal layer 542 may be replaced by a conductive material, which is not specifically limited in the present application.

[0093] In some embodiments, Fig.15A and Fig. 15B As shown, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to form a first isolation structure 518 inside the initial gate layer 515', and in this process, a filling layer 525 may be formed inside the initial conductive shielding layer 521'. Optionally, a CMP process may be used for planarization to remove, for example, portions of the adhesion layer 541 and the metal layer 542 located on the surface of the first dielectric layer 532.

[0094] In some embodiments, an etching (e.g., dry etching and / or wet etching) process may be used to remove a portion of the initial gate layer 515' close to the first side. In this process, the same etching (e.g., dry etching and / or wet etching) process may be used to remove a portion of the initial conductive shielding layer 521' close to the first side. For example, for the two end surfaces of the initial gate layer 515' and the initial conductive shielding layer 521' close to the first side in the D3 direction, the two end surfaces may be made substantially flush (e.g., within an error of ±10%), or the end surface of the initial conductive shielding layer 521' may be made lower than the end surface of the initial gate layer 515', and the present application does not impose specific restrictions on this. It should be noted that the process of removing a portion of the initial gate layer 515' close to the first side and a portion of the initial conductive shielding layer 521' close to the first side may be achieved by different etching processes, and the present application does not impose specific restrictions on this.

[0095] In some embodiments, Fig.15A and Fig. 15BThe intermediate structure 500h is shown flipped 180° to allow subsequent processing from a second side of the semiconductor layer 531 (eg, the back side of the semiconductor layer 531). FIG. 16A to FIG. 16B As shown, the semiconductor layer 531 may first be planarized from the second side of the semiconductor layer 531 by using a CMP process. Then, a portion of the initial conductive shielding layer 521' is removed from the second side of the semiconductor layer 531, for example, by using an etching (e.g., dry etching and / or wet etching) process to form the conductive shielding layer 521, and a portion of the initial gate layer 515' is removed to disconnect the initial gate layer 515' in the D1 direction, thereby forming the gate layer 515. Exemplarily, the portion of the initial conductive shielding layer 521' removed may include: a portion of the initial conductive shielding layer 521' close to the second side and located in the first region 501, and a portion of the initial conductive shielding layer 521' close to the second side and located in one of the second regions 502.

[0096] Next, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to fill the space formed after removing a portion of the initial gate layer 515' and the initial conductive shielding layer 521' with an insulating layer material, thereby forming a third isolation structure 520. For example, the material of the third isolation structure 520 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material or materials.

[0097] In some embodiments, compared to the initial conductive shielding layer 521 ′, Fig. 16B The portion of the conductive shielding layer 521 shown in the first region 501 is further reduced in size in the D3 direction. For example, for the two end surfaces of the gate layer 515 and the conductive shielding layer 521 close to the second side in the D3 direction, the two end surfaces can be made substantially flush (for example, with an error within ±10%) according to the actual control requirements of the transistor, or the end surface of the conductive shielding layer 521 can be made lower than the end surface of the gate layer 515, and the present application does not impose specific restrictions on this.

[0098] In some embodiments, the manufacturing method 300 may further include a step of forming a first contact structure. Fig.17The semiconductor device 500 after forming the first contact structure 526 is shown. According to the above description, the conductive shielding layer 521 can be led out from the D3 direction by using the portion of the conductive shielding layer 521 located in the second region 502 and the first contact structure 526. For example, an etching (for example, dry etching and / or wet etching) process can be used to form a contact hole (corresponding to the outer contour of the first contact structure 526) extending to the portion of the conductive shielding layer 521 located in the second region 502 from the second side. For example, the contact hole can expose the conductive shielding layer 521. Then, a thin film deposition process such as CVD, PVD, ALD or any combination thereof can be used to fill the contact hole with one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO) or any other suitable conductive materials to form the first contact structure 526. In this embodiment, by utilizing the characteristic that the conductive shielding layer 521 has a larger size in the direction D3 in the second region 502 , the first contact structure 526 can have a smaller extension distance in the direction D3 , thereby reducing the difficulty in manufacturing the first contact structure 526 .

[0099] In this embodiment, the conductive shielding layer has a relatively uniform thickness in the D1 direction, and can reduce the difficulty of controlling the etching process, which is conducive to ensuring the size matching of the conductive shielding layer and the gate layer in the D3 direction. In addition, the risk of damage to the adjacent structure can be reduced during the etching of the initial conductive shielding layer, which is conducive to improving the yield and electrical performance of the final product. On the other hand, by forming a conductive shielding layer with a thin layer structure, the process is easier to implement, and the iterative miniaturization capability is more advantageous.

[0100] The above description is only an implementation method of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor device, characterized in that: include: A plurality of semiconductor pillars are arranged in an array along a first direction and a second direction, wherein the semiconductor pillars adjacent to each other in the first direction respectively have first side walls opposite to each other; a conductive shielding layer, located outside the first side wall and extending along the second direction; as well as A filling layer, located between the conductive shielding layers; The first direction is perpendicular to the second direction.

2. The semiconductor device according to claim 1, wherein The thickness of the conductive shielding layer in the first direction is substantially the same.

3. The semiconductor device according to claim 1, wherein The invention also includes a first oxide layer located between the first sidewall and the conductive shielding layer.

4. The semiconductor device according to claim 3, wherein: The conductive shielding layer comprises: A first adhesive layer, located on a surface of the first oxide layer and extending along the second direction; and The first metal layer is located on the surface of the first adhesive layer and extends along the second direction.

5. The semiconductor device according to claim 1, wherein The semiconductor device has a first region and a second region arranged along the second direction, the second region is located on both sides of the first region, the conductive shielding layer extends in the first region and the second region, and in a third direction, the size of the conductive shielding layer in at least one of the second regions is larger than its size in the first region, and the third direction is perpendicular to the first direction and the second direction.

6. The semiconductor device according to claim 5, wherein: Also includes: The first contact structure is located in the second region and connected to the conductive shielding layer.

7. The semiconductor device according to claim 1, wherein The semiconductor column has a second sidewall opposite to the first sidewall, and the semiconductor device further includes: a gate oxide layer, located on a surface of the second side wall; The gate layer is located on the surface of the gate oxide layer and extends along the second direction.

8. The semiconductor device according to claim 7, wherein: The gate layer comprises: a second adhesive layer, located on a surface of the gate oxide layer and extending along the second direction; and The second metal layer is located on the surface of the second adhesive layer and extends along the second direction.

9. The semiconductor device according to claim 1, wherein: Ends of the plurality of semiconductor pillars arranged along the first direction are connected to each other.

10. A memory system, characterized in that: Also includes: A memory comprising a semiconductor device as claimed in any one of claims 1 to 9; as well as The controller is coupled to the memory and is used to control the memory to store data.

11. A method for manufacturing a semiconductor device, characterized in that: include: forming a first trench extending along a first direction from a first side of the semiconductor layer, and filling the first trench with an insulating material; forming a second groove and a third groove extending along a second direction from the first side, the second grooves and the third grooves are arranged alternately, and the first direction is perpendicular to the second direction; forming a conductive shielding layer inside the second groove, and forming a filling layer inside the conductive shielding layer; and A gate oxide layer and a gate layer are formed in the third trench.

12. The manufacturing method according to claim 11, wherein: In the first direction, the size of the second groove is smaller than the size of the third groove; Wherein, forming a second groove and a third groove extending along a second direction from the first side comprises: forming the second trench and a preliminary third trench extending in the second direction from the first side, wherein in the first direction, a size of the second trench is equal to a size of the preliminary third trench; and By means of an etching process, a dimension of the initial third trench in the first direction is increased to form the third trench.

13. The manufacturing method according to claim 11, wherein: Sequentially forming a gate oxide layer and a gate layer in the third trench comprises: forming a barrier layer at the bottom of the third trench; forming the gate oxide layer on the sidewalls of the third trench; forming an initial gate layer on a surface of the gate oxide layer and a surface of the barrier layer; removing a portion of the initial gate layer located on the surface of the barrier layer to disconnect the initial gate layer; A portion of the initial gate layer close to the first side is removed to form the gate layer.

14. The manufacturing method according to claim 11 or 13, wherein: Forming a conductive shielding layer inside the second groove, and forming a filling layer inside the conductive shielding layer comprises: forming an initial conductive shielding layer inside the second trench; and A portion of the initial conductive shielding layer adjacent to the first side is removed.

15. The manufacturing method according to claim 14, wherein: Also includes: A portion of the initial conductive shielding layer is removed from a second side of the semiconductor layer opposite to the first side to form the conductive shielding layer.

16. The manufacturing method according to claim 15, wherein: The semiconductor layer comprises a first region and a second region arranged along the second direction, wherein the second region is located at two sides of the first region; Wherein, removing a portion of the initial conductive shielding layer from a second side of the semiconductor layer opposite to the first side comprises: From the second side, removing a portion of the initial conductive shielding layer located in the first region to form the conductive shielding layer; and The space formed after removing a portion of the initial conductive shielding layer is filled with an insulating material.

17. The manufacturing method according to claim 16, wherein: Also includes: In the second region, a first contact structure connected to the conductive shielding layer is formed.

18. The manufacturing method according to claim 14, wherein: Before forming an initial conductive shielding layer inside the second trench, the method further includes: A first oxide layer is formed on the inner wall of the second trench.

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