Semiconductor element structure with air gap and preparation method thereof

Abstract

A semiconductor device structure includes a semiconductor substrate, a first fin structure, a first source / drain structure, and a bit line contact. The first fin structure protrudes from the semiconductor substrate and has a first sidewall, a second sidewall, and an upper surface connecting the first sidewall to the second sidewall. The first source / drain structure is disposed over the first fin structure and covers the upper surface of the first fin structure, a portion of the first sidewall, and a portion of the second sidewall. The bit line contact is disposed over the first source / drain structure. The bit line contact includes a barrier layer in contact with the first source / drain structure and a conductive layer disposed over the barrier layer.

Description

Technical Field

[0001] This application claims priority to U.S. patent application No. 18 / 241,057 (i.e., the priority date is "August 31, 2023"), the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a semiconductor device structure and a method for preparing the semiconductor device structure, and more particularly to a semiconductor device structure having an air gap between adjacent source / drain structures and a method for preparing the semiconductor device structure. Background Art

[0003] Due to its simple structure, dynamic random access memory (DRAM) can provide more memory cells per unit chip area than other types of memory, such as static random access memory (SRAM). Dynamic random access memory is composed of multiple dynamic random access memory cells, each of which includes a capacitor for storing information and a transistor coupled to the capacitor to regulate when the capacitor is charged or discharged. During a read operation, the word line (WL) is asserted to turn on the transistor. The enabled transistor allows a sense amplifier to read the voltage across the capacitor via the bit line (BL). During a write operation, the data to be written is provided on the BL while WL is asserted.

[0004] In order to meet the demand for greater memory storage, the size of DRAM memory cells continues to decrease, resulting in a significant increase in the packaging density of such DRAMs. However, as DRAM memory cell size requirements dictate continued reductions in size, capacitive coupling is becoming an increasingly significant issue resulting in increased parasitic capacitance. As a result, the speed of the DRAM memory cell is undesirably reduced, and the performance of the overall device is negatively affected.

[0005] The above “prior art” description only provides background technology, does not admit that the above “prior art” description reveals the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the invention

[0006] An embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a semiconductor substrate, a first fin structure, a first source / drain structure, and a bit line contact point. The first fin structure protrudes from the semiconductor substrate and has a first sidewall, a second sidewall, and an upper surface connecting the first sidewall to the second sidewall. The first source / drain structure is arranged above the first fin structure and covers the upper surface of the first fin structure, a portion of the first sidewall, and a portion of the second sidewall. The bit line contact point is arranged above the first source / drain structure. The bit line contact point includes a barrier layer in contact with the first source / drain structure; and a conductive layer arranged above the barrier layer.

[0007] An embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a first fin structure, a first source / drain structure, a second source / drain structure, a third source / drain structure, a first word line and a second word line. The first fin structure is disposed on a semiconductor substrate and includes a first channel region, a second channel region and other regions. The first source / drain structure, the second source / drain structure and the third source / drain structure are disposed above the first fin structure. The first word line is disposed between the first source / drain structure and the second source / drain structure, and crosses the first channel region of the first fin structure from a top view of the semiconductor device structure. The second word line is disposed between the second source / drain structure and the third source / drain structure, and crosses the second channel region of the first fin structure from a top view. A width of the first channel region is equal to a width of the second channel region, and the width of the first channel region is less than a width of the other regions of the first fin structure.

[0008] Another embodiment of the present disclosure provides a method for preparing a semiconductor device structure. The preparation method includes forming a first fin structure and a second fin structure above a semiconductor substrate; forming an isolation structure above the semiconductor substrate, wherein the first fin structure and the second fin structure protrude from the isolation structure; partially removing the first fin structure and the second fin structure to form a first recessed portion of the first fin structure and a second recessed portion of the second fin structure; epitaxially growing a first source / drain structure above the first recessed portion and epitaxially growing a second source / drain structure above the second recessed portion, wherein the first source / drain structure is separated from the second source / drain structure by a first opening; partially removing the isolation structure through the first opening to form a second opening, wherein the first opening and the second opening are a continuous space; forming a contact etch A stop layer is formed over the first source / drain structure and the second source / drain structure so that an air gap is formed and sealed in the first opening and the second opening; an interlayer dielectric structure is formed over the contact etch stop layer; a portion of the interlayer dielectric structure over the first source / drain structure and a portion of the contact etch stop layer over the first source / drain structure are removed to form a third opening, wherein the third opening exposes the first source / drain structure; an anisotropic deposition process is performed to deposit a barrier layer in the third opening, wherein the barrier layer includes a lower portion in contact with the first source / drain structure and a side portion in contact with the dielectric structure; and a conductive layer is formed over the barrier layer, wherein the barrier layer and the conductive layer are configured to become a bit line contact.

[0009] According to some embodiments of the present disclosure, embodiments of a semiconductor device structure are provided. The semiconductor device structure includes a first word line spanning a first fin structure and a second fin structure, a first source / drain structure located above the first fin structure, and a second source / drain structure located above the second fin structure. The first source / drain structure and the second source / drain structure are formed adjacent to the first word line, and an air gap is formed between the first and second source / drain structures. Therefore, the capacitance between adjacent source / drain structures (i.e., the first and second source / drain structures) can be reduced. As a result, the operating speed of the semiconductor device structure can be increased, and the overall device performance can be improved.

[0010] The above has outlined the technical features and advantages of the present disclosure in a fairly broad manner, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purpose as the present disclosure. It should also be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] When with Figure 1 When read together, various aspects of the present disclosure can be best understood from the following detailed description. It should be understood that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the size of various features can be arbitrarily increased or reduced for clarity of discussion.

[0012] Figure 1 is a top view schematically illustrating a semiconductor device structure according to some embodiments of the present disclosure.

[0013] Figure 2 is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along Figure 1 The semiconductor device structure along the section line II' in FIG.

[0014] Figure 3 It is a schematic flow chart illustrating a method for preparing a semiconductor device structure according to some embodiments of the present disclosure.

[0015] Figure 4 is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along Figure 1 The section line II' in FIG. 1 forms an intermediate stage of the semiconductor device structure.

[0016] Figure 5 is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along Figure 1 The section line II' in FIG. 1 forms an intermediate stage of the semiconductor device structure.

[0017] Figure 6 is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along Figure 1 The section line II' in FIG. 1 forms an intermediate stage of the semiconductor device structure.

[0018] Figure 7 is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along Figure 1 The section line II' in FIG. 1 forms an intermediate stage of the semiconductor device structure.

[0019] Figure 8 is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along Figure 1 The section line II' in FIG. 1 forms an intermediate stage of the semiconductor device structure.

[0020] Fig. 9 is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along Figure 1 The section line II' in FIG. 1 forms an intermediate stage of the semiconductor device structure.

[0021] Fig.10 is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along Figure 1 The section line II' in FIG. 1 forms an intermediate stage of the semiconductor device structure.

[0022] Fig.11 is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along Figure 1 The section line II' in FIG. 1 forms an intermediate stage of the semiconductor device structure.

[0023] Fig.12 is a schematic cross-sectional view illustrating the semiconductor device structure according to some other embodiments of the present disclosure.

[0024] Fig.13 FIG. 4 is a top view schematically illustrating the semiconductor device structure according to some different embodiments of the present disclosure.

[0025] The reference numerals are described as follows:

[0026] 10: Preparation method

[0027] 100: Semiconductor component structure

[0028] 101: Semiconductor substrate

[0029] 103: Patterned dielectric layer

[0030] 105: Patterned mask layer

[0031] 108a: Opening

[0032] 108b: Opening

[0033] 111a~111c: Fin structure

[0034] 111a' to 111c': Depression

[0035] 113: Isolation Structure

[0036] 113': Depression isolation structure

[0037] 113”: Isolation structure

[0038] 113p1: protrusion

[0039] 113p2: protrusion

[0040] 121a~121o:Source / drain structure

[0041] 124a1: First opening

[0042] 124b1: First opening

[0043] 124a2: Second opening

[0044] 124b2: Second opening

[0045] 131: Contact Etch Stop Layer

[0046] 134a~134b:Air gap

[0047] 141: Interlayer dielectric structure

[0048] 148a: Contact opening

[0049] 148b: Contact opening

[0050] 149a: Opening

[0051] 149d: Opening

[0052] 151a~151d: Bit line contact points

[0053] 161a~161d:Character line

[0054] 171a~171f: Deep trench capacitors

[0055] 200: Semiconductor component structure

[0056] 251: Barrier layer

[0057] 251a~251d:Barrier layer

[0058] 252: Bit line contact

[0059] 252a: Conductive layer

[0060] 252b: Conductive layer

[0061] 252d: Conductive layer

[0062] 300: Semiconductor component structure

[0063] 311a: Fin structure

[0064] 311b: Fin structure

[0065] 311c: Fin structure

[0066] CH1~CH6: Channel area

[0067] P: Highest point

[0068] S1: Upper surface

[0069] S2: Interface

[0070] S11: Steps

[0071] S13: Steps

[0072] S15: Steps

[0073] S17: Steps

[0074] S19: Steps

[0075] S21: Steps

[0076] SW1: Sidewall

[0077] SW2: Sidewall

[0078] W1: Thickness

[0079] W2: Thickness

[0080] Wm1: Maximum width

[0081] Wm2: Maximum width DETAILED DESCRIPTION

[0082] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, in the description, the first component is formed on the second component, which may include an embodiment in which the first and second components are in direct contact, and may also include an embodiment in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in many examples. The purpose of these repetitions is to simplify and clarify, and unless otherwise specified in the text, they do not themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0083] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0084] Figure 1FIG. 1 is a top view schematically illustrating a semiconductor device structure 100 according to some embodiments of the present disclosure. Figure 1 As shown, according to some embodiments, the semiconductor device structure 100 includes a plurality of fin structures 111a, 111b and 111c, which are active regions of the semiconductor device structure 100. The fin structures 111a, 111b and 111c are parallel to each other and extend along the X direction. It should be understood that in this embodiment, the semiconductor device structure 100 is a dynamic random access memory (DRAM).

[0085] Furthermore, according to some embodiments, Figure 1 As shown, the semiconductor device structure 100 further includes a plurality of word lines 161a, 161b, 161c, and 161d. The word lines 161a to 161d are parallel to each other and extend along the Y direction. In some embodiments, the word line 161a extends across the gate structure of the fin structures 111a to 111c.

[0086] In addition, in some embodiments, the fin structures 111a to 111c include a plurality of recessed portions that are exposed (ie, not covered) by the word lines 161a to 161d. Figure 1 As shown, source / drain (S / D) structures 121a, 121b, 121c, 121d and 121e are disposed above the recessed portions of the fin structure 111a, source / drain structures 121f, 121g, 121h, 121i and 121j are disposed above the recessed portions of the fin structure 111b, and source / drain structures 121k, 121l, 121m, 121n and 121o are disposed above the recessed portions of the fin structure 111c. It should be understood that in order to simplify the diagram, Figure 1 Only some of the recessed portions of the fin structures 111a, 111b, and 111c are shown. For example, the source / drain structure 121c is disposed above the recessed portion 111a' of the fin structure 111a, the source / drain structure 121g is disposed above the recessed portion 111b' of the fin structure 111b, and the source / drain structure 121m is disposed above the recessed portion 111c' of the fin structure 111c.

[0087] The semiconductor device structure 100 also includes bit line contacts 151a, 151b, 151c, and 151d disposed above the source / drain structures 121c, 121f, 121j, and 121m, respectively, and the deep trench capacitors 171a, 171b, 171c, 171d, 171e, and 171f are covered by the word lines 161a to 161d. In some embodiments, each of the bit line contacts 151a, 151b, 151c, and 151d has a circular profile from a top view. In some embodiments, the bit line contacts 151a to 151d are used to electrically connect the underlying source / drain structures 121c, 121f, 121j, and 121m to the overlying bit lines. For simplicity and clarity, the bit line contacts 151a to 151d are shown in FIG. Figure 1 The upper bit lines are not shown.

[0088] In some embodiments, deep trench capacitor 171a is located at the intersection of word line 161a and fin structure 111a, deep trench capacitor 171b is located at the intersection of word line 161d and fin structure 111a, deep trench capacitor 171c is located at the intersection of word line 161b and fin structure 111b, deep trench capacitor 171d is located at the intersection of word line 161c and fin structure 111b, deep trench capacitor 171e is located at the intersection of word line 161a and fin structure 111c, and deep trench capacitor 171f is located at the intersection of word line 161d and fin structure 111c. In some embodiments, each of deep trench capacitors 171a to 171f is embedded in one of fin structures 111a to 111c. In addition, deep trench capacitors 171a to 171f may extend to semiconductor substrate 101 (e.g., below fin structures 111a to 111c) below fin structures 111a to 111c. Figure 2 shown).

[0089] It should be understood that according to some embodiments, reference Figure 1 Source / drain structures 121a to 121e are above the recessed portion of the mid-fin structure 111a, the source / drain structures 121a and 121e are virtual source / drain structures and are not electrically connected to other elements or components, the source / drain structure 121b is electrically connected to the deep trench capacitor 171a, the source / drain structure 121c is electrically connected to the bit line above via the bit line contact point 151a, and the source / drain structure 121d is electrically connected to the deep trench capacitor 171b.

[0090] Furthermore, according to some embodiments, reference Figure 1Source / drain structures 121f to 121j above the recessed portion of the mid-fin structure 111b, the source / drain structure 121f is electrically connected to the upper bit line via the bit line contact 151b, the source / drain structure 121g is electrically connected to the deep trench capacitor 171c, the source / drain structure 121h is a virtual source / drain structure and is not electrically connected to other elements or components, the source / drain structure 121i is electrically connected to the deep trench capacitor 171d, and the source / drain structure 121j is electrically connected to the upper bit line via the bit line contact 151c.

[0091] In addition, the layout of the source / drain structures 121k to 121o above the recessed portion of the fin structure 111c is similar to the layout of the source / drain structures 121a to 121e. Figure 1 As shown, the source / drain structures 121k and 121o are virtual source / drain structures and are not electrically connected to other elements or components, the source / drain structure 121l is electrically connected to the deep trench capacitor 171e, the source / drain structure 121m is electrically connected to the upper bit line via the bit line contact 151d, and the source / drain structure 121n is electrically connected to the deep trench capacitor 171f.

[0092] Figure 2 is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along Figure 1 The semiconductor device structure 100 is shown along the section line II' in FIG. According to some embodiments, Figure 2 As shown, an isolation structure 113 ″ is disposed above the semiconductor substrate 101 , and the recessed portions 111 a ′, 111 b ′ and 111 c ′ of the fin structures 111 a , 111 b and 111 c protrude from the isolation structure 113 ″.

[0093] In some embodiments, the source / drain structures 121c, 121h, and 121m are disposed above the recessed portions 111a', 111b', and 111c', a contact etch stop layer (CESL) 131 is formed to cover the source / drain structures 121c, 121h, 121m and the isolation structure 113", and a plurality of air gaps are formed between adjacent source / drain structures. For example, Figure 1 and Figure 2 As shown, according to some embodiments, air gap 134a is formed between source / drain structures 121c and 121h, and air gap 134b is formed between source / drain structures 121h and 121m.

[0094] Although only three source / drain structures 121c, 121h, 121m and three recessed portions 111a', 111b', 111c' of the fin structures 111a, 111b, 111c of the semiconductor device structure 100 are shown, it should be understood that the structures and configurations of other source / drain structures and other recessed portions of the fin structure may be similar to or the same as the source / drain structures 121c, 121h, 121m and the recessed portions 111a', 111b', 111c'.

[0095] In some embodiments, each of the air gaps 134a and 134b is surrounded by the contact etching stop layer 131 and is Figure 2 , and the air gaps 134a and 134b are partially covered by the source / drain structures 121c, 121h, and 121m. In some embodiments, the air gap 134a has a highest point P, and the source / drain structure 121c has a maximum width Wm1, wherein the portion of the source / drain structure 121c having the maximum width Wm1 is located above the highest point P of the air gap 134a. In some embodiments, the recessed portion 111a' of the fin structure 111a has an upper surface S1 and an interface S2, wherein the upper surface S1 is located higher than a portion of the air gap 134a having a maximum width Wm2, and the interface S2 is located at the interface S2 between the isolation structure 113" and the source / drain structure 121c and is located higher than the portion of the air gap 134a having the maximum width Wm2. The details of the air gap 134b may be similar to or the same as the details of the air gap 134a, and will not be repeated here.

[0096] In addition, an interlayer dielectric (ILD) structure 141 is disposed above the CESL 131, and bit line contacts 151a and 151d are formed to penetrate the ILD structure 141 and the CESL 131 to directly contact the source / drain structures 121c and 121m, respectively. Figure 1 and Figure 2 Only two air gaps 134a and 134b are shown in FIG. 1 , but the semiconductor device structure 100 may include more than two air gaps. For example, the source / drain structures 121b and 121g (see FIG. 1 ) may be provided with a plurality of air gaps. Figure 1 It should be understood that the air gap can be arranged between adjacent source / drain structures along the Y direction, and the Y direction is parallel to the longitudinal direction of the word lines 161a to 161d.

[0097] Figure 3 1 is a flow chart illustrating a method 10 for manufacturing a semiconductor device structure 100 according to some embodiments of the present disclosure, and the method 10 includes steps S11, S13, S15, S17, S19 and S21. Figures 4 to 10 Detailed description Figure 3 Steps S11 to S21.

[0098] Figure 4 is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along Figure 1 The section line II′ in FIG. 1 forms an intermediate stage of the semiconductor device structure 100 .

[0099] like Figure 4 As shown, a semiconductor substrate 101 is provided. The semiconductor substrate 101 may be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, the semiconductor substrate 101 may include elemental semiconductor materials, compound semiconductor materials and / or alloy semiconductor materials. Examples of elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium and / or diamond. Examples of compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide. Examples of alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP.

[0100] In some embodiments, the semiconductor substrate 101 includes an epitaxial layer. For example, the semiconductor substrate 101 has an epitaxial layer covering a bulk semiconductor. In some embodiments, the semiconductor substrate 101 is a semiconductor-on-insulator substrate, which may include a substrate, a buried oxide layer above the substrate, and a semiconductor layer above the buried oxide layer, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate may be manufactured using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods.

[0101] In some embodiments, a dielectric layer (not shown) is disposed on the semiconductor substrate 101, a mask layer (not shown) is disposed on the dielectric layer, and a patterned photoresist layer (not shown) is disposed on the mask layer. The manufacturing technology of the patterned photoresist layer may include a deposition process and a patterning process.

[0102] The deposition process for forming the patterned photoresist layer may include a chemical vapor deposition (CVD) process, a high density plasma chemical vapor deposition (HDPCVD) process, a spin coating process, a sputtering process or other suitable processes. The patterning process for forming the patterned photoresist layer may include a lithography process and an etching process. The lithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing and drying (e.g., hard baking). The etching process may include a dry etching process or a wet etching process.

[0103] In addition, the dielectric layer can be a buffer layer between the semiconductor substrate 101 and the mask layer. In some embodiments, when the mask layer is removed, the dielectric layer is used as a stop layer. The dielectric layer may include silicon oxide. The mask layer may include silicon oxide, silicon nitride, silicon oxynitride or other applicable materials. The manufacturing technology of the dielectric layer and the mask layer may include multiple deposition processes, and the deposition process may include a CVD process, a HDPCVD process, a spin coating process, a sputtering process or other applicable processes.

[0104] like Figure 4 As shown, according to some embodiments, after forming the patterned photoresist layer, the patterned photoresist layer is used as a mask to pattern the dielectric layer and the mask layer, thereby obtaining a patterned dielectric layer 103 and a patterned mask layer 105. Next, the patterned photoresist layer is removed.

[0105] Next, an etching process is performed on the semiconductor substrate 101 using the patterned dielectric layer 103 and the patterned mask layer 105 as a mask to form the fin structures 111a, 111b and 111c. The corresponding steps are shown as follows: Figure 3 The step S11 in the manufacturing method 10 is shown. The etching process may be a dry etching process or a wet etching process. After the etching process for forming the fin structures 111a to 111c, the fin structures 111a to 111c are separated by the openings 108a and 108b.

[0106] In some embodiments, the semiconductor substrate 101 is etched by a dry etching process. The dry etching process includes using a fluorine-based etching gas, such as SF6, C x F y , NF3 or a combination thereof. The etching process may be a time-controlled process and may continue until the fin structures 111a to 111c reach a predetermined height. In some embodiments, each of the fin structures 111a to 111c has a width that gradually increases from the upper portion to the lower portion.

[0107] Figure 5 is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along Figure 1 The section line II' in FIG. 1 forms an intermediate stage of the semiconductor device structure.

[0108] According to some embodiments, after forming the fin structures 111a to 111c, an insulating material (not shown) is formed to cover the fin structures 111a to 111c, the patterned dielectric layer 103, and the patterned mask layer 105 above the semiconductor substrate 101. In other words, according to some embodiments, the openings 108a and 108b are filled with the insulating material. In some embodiments, the insulating material includes silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), or other low-k dielectric materials. The insulating material can be deposited by a CVD process, a spin-on-glass process, or other suitable processes.

[0109] Next, the insulating material is thinned or planarized to expose the upper surface of the patterned mask layer 105. In some embodiments, the insulating material is thinned by a chemical mechanical polishing (CMP) process. Next, the patterned dielectric layer 103 and the patterned mask layer 105 are removed.

[0110] like Figure 5 As shown, according to some embodiments, after removing the patterned dielectric layer 103 and the patterned mask layer 105, an upper portion of the insulating material is removed to form an isolation structure 113. The corresponding steps are shown as Figure 3 The step S13 in the manufacturing method 10 is shown. The isolation structure 113 may be a shallow trench isolation (STI) structure surrounding the fin structures 111a to 111c. In some embodiments, the lower portions of the openings 108a and 108b are filled with the isolation structure 113, and the openings 114a and 114b are disposed above the isolation structure 113 and between the adjacent fin structures 111a, 111b, and 111c.

[0111] In some embodiments, some portions of the fin structures 111a to 111c are embedded in the isolation structure 113. In some embodiments, lower portions of the fin structures 111a to 111c are surrounded by the isolation structure 113, while upper portions of the fin structures 111a to 111c protrude from the isolation structure 113. The isolation structure 113 is used to prevent electrical interference or crosstalk.

[0112] Figure 6 is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along Figure 1 The section line II′ in FIG. 1 forms an intermediate stage of the semiconductor device structure 100 .

[0113] According to some embodiments, Figure 6 As shown, after the isolation structure 113 is formed, the word lines 161a to 161d (refer to Figure 1) is disposed across the fin structures 111a to 111c and extends over the isolation structure 113, and partially removes a plurality of portions of the fin structures 111a to 111c exposed (i.e., not covered) by the word lines 161a to 161d to form recessed portions of the fin structures, such as the recessed portion 111a' of the fin structure 111a, the recessed portion 111b' of the fin structure 111b, and the recessed portion 111c' of the fin structure 111c. The corresponding steps are shown as Figure 3 Step S15 in the preparation method 10 shown.

[0114] In some embodiments, the word lines 161a to 161d are multiple gate structures arranged across the fin structures 111a to 111c. During this step, multiple virtual gate structures are formed on the word lines 161a to 161d. After the contact etching stop layer 131 and the interlayer dielectric structure 141 are formed in the subsequent process, the virtual gate structure will be replaced by a gate structure (i.e., a metal gate structure).

[0115] In some embodiments, portions of the fin structures 111a, 111b, and 111c adjacent to the word lines 161a to 161d are recessed to form recessed portions (e.g., recessed portions 111a', 111b', 111c') at both sides of the fin structures 111a, 111b, and 111c. In some embodiments, upper portions of the isolation structure 113 are removed during the recessing of the fin structures 111a, 111b, and 111c, so that the recessed portions 111a', 111b', and 111c' protrude from a recessed isolation structure 113'.

[0116] In some embodiments, the recessed isolation structure 113' has a protrusion 113p1 adjacent to the recessed portions 111a', 111b', and 111c' of the fin structures 111a, 111b, and 111c, and the protrusion 113p1 has a concave surface. In some embodiments, the recessed portions 111a', 111b', and 111c' have an upper surface S1 and a sidewall SW1 exposed (i.e., not covered) by the recessed isolation structure 113'.

[0117] Figure 7 is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along Figure 1 The section line II′ in FIG. 1 forms an intermediate stage of the semiconductor device structure 100 .

[0118] Next, source / drain structures 121a to 121o are epitaxially grown over the recessed portions of the fin structures 111a, 111b, and 111c. Figure 7As shown, the source / drain structures 121c, 121h and 121m are disposed above the recessed portions 111a', 111b' and 111c' of the fin structures 111a to 111c. The corresponding steps are shown as follows: Figure 3 Step S17 in the manufacturing method 10 shown. It should be understood that in some embodiments, the source / drain structures 121a to 121o are separated from each other. That is, the source / drain structures 121a to 121o are not connected to each other or are not merged together.

[0119] In some embodiments, Figure 7 As shown, according to some embodiments, the source / drain structure 121c is separated from the source / drain structure 121h by a first opening 124a1, and the source / drain structure 121h is separated from the source / drain structure 121m by another first opening 124b1. In some embodiments, the upper boundaries of the first openings 124a1 and 124b1 are defined to be aligned with the position of the maximum width of the adjacent source / drain structure, such as the maximum value of Wm1 of the source / drain structure 121c, and a width of each of the first openings 124a1 and 124b1 increases from the upper portion to the lower portion. In addition, a dotted line extending from the upper boundaries of the first openings 124a1 and 124b1 also divides the source / drain structure 121c into an upper portion and a lower portion. The lower portion 121c of the source / drain structure covers the upper surface S1 and a portion of the sidewall SW1. The upper portion of the source / drain structure 121c has a triangular profile, i.e. Figure 7 The main side is coupled to the lower portion of the source / drain structure 121c, and the sub-sides have the same length.

[0120] In some embodiments, a strained material is grown on the recessed portions of the fin structures 111a, 111b, and 111c by an epitaxial (epi) process to form source / drain structures 121a to 121o. In addition, the lattice constant of the strained material may be different from the lattice constant of the semiconductor substrate 101. In some embodiments, the material of the source / drain structures 121a to 121o includes Ge, SiGe, InAs, InGaAs, InSb, GaAs, GaSb, InAlP, InP, or the like.

[0121] Figure 8 is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along Figure 1 The section line II′ in FIG. 1 forms an intermediate stage of the semiconductor device structure 100 .

[0122] like Figure 8As shown, according to some embodiments, after the epitaxial growth of the source / drain structures 121a to 121o, the upper portion of the recessed isolation structure 113' is removed to form an isolation structure 113", which is a remaining portion of the recessed isolation structure 113'. In some embodiments, the recessed isolation structure 113' is partially removed through the first openings 124a1 and 124b1 to form second openings 124a2 and 124b2 in the isolation structure 113". The corresponding steps are shown as Figure 3 Step S19 in the preparation method 10 shown.

[0123] In some embodiments, the partial removal of the recessed isolation structure 113' includes a wet etching process, a dry etching process, or a combination thereof. After the etching process, second openings 124a2 and 124b2 are formed below the first openings 124a1 and 124b1, and between the protrusions 113p2 of the isolation structure 113", wherein the protrusion 113p2 is located below the protrusion 113p1. In some embodiments, a width of each of the second openings 124a2 and 124b2 decreases from the top to the bottom. Furthermore, the protrusion 113p2 of the isolation structure 113" has a sidewall SW2 exposed by the second openings 124a2 and 124b2.

[0124] Fig. 9 is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along Figure 1 The section line II′ in FIG. 1 forms an intermediate stage of the semiconductor device structure 100 .

[0125] Next, a contact etch stop layer 131 is disposed over the source / drain structures 121a to 121o so that a plurality of air gaps are formed and sealed in the first and second openings. For example, according to some embodiments, the air gaps 134a and 134b are formed as follows: Fig. 9 The corresponding steps are shown as Figure 3 Step S21 in the preparation method 10 shown.

[0126] In some embodiments, a contact etching stop layer 131 is formed to cover the sidewall SW2 of the isolation structure 113″, wherein the sidewall SW2 is exposed by the second openings 124a2 and 124b2, and the contact etching stop layer 131 also covers the sidewalls of the source / drain structures 121a to 121o. As a result, Fig. 9 In the cross-sectional view of FIG. 1 , the air gaps 134a and 134b are surrounded by the contact etch stop layer 131. In some embodiments, the contact etch stop layer 131 includes silicon nitride, silicon oxynitride and / or other applicable materials. Furthermore, according to some embodiments, the manufacturing technology of the contact etch stop layer 131 includes plasma enhanced CVD, low pressure CVD, atomic layer deposition (ALD) or other applicable processes.

[0127] In some embodiments, each of the air gaps 134a and 134b has a highest point P, a leftmost point, and a rightmost point. The highest point P is lower than the upper portion of the source / drain structure 121c and higher than the upper surface S1 of the fin structure 111a. The leftmost point is flush with the rightmost point. In addition, the leftmost point and the rightmost point are lower than the upper surface S1 and a highest point of the protrusion 113p1 of the isolation structure 113″.

[0128] After the contact etch stop layer 131 is formed, the interlayer dielectric structure 141 is disposed above the contact etch stop layer 131. It should be understood that in the present embodiment, since the air gaps 134a and 134b are sealed by the contact etch stop layer 131, the interlayer dielectric structure 141 is not deposited into the air gaps 134a and 134b. In some embodiments, the interlayer dielectric structure 141 includes multiple layers made of multiple dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric materials and / or other applicable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorosilicate glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, polyparaxylene, bibenzocyclobutene (BCB) and polyimide. In addition, the manufacturing technology of the interlayer dielectric structure 141 may include CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating or other applicable processes.

[0129] Fig.10 is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along Figure 1 The section line II′ in FIG. 1 forms an intermediate stage of the semiconductor device structure 100 .

[0130] After forming the interlayer dielectric structure 141, the interlayer dielectric structure 141 and the contact etching stop layer 131 are partially removed to form a plurality of contact openings exposing the underlying source / drain structures, which are designed to be electrically connected to the bit lines formed subsequently. Fig.10 As shown, according to some embodiments, contact openings 148a and 148b are formed to expose the source / drain structures 121c and 121m, respectively. In some embodiments, the interlayer dielectric structure 141 and the contact etching stop layer 131 are partially removed by an etching process such as a dry etching process.

[0131] Next, bit line contacts 151a to 151d are formed in a plurality of contact openings surrounded by the contact etch stop layer 131 and the interlayer dielectric structure 141, for example, according to some embodiments, such as Figure 2 The bit line contacts 151a to 151d are shown in a cross-sectional view.

[0132] In some embodiments, each of the bit line contacts 151a to 151d includes multiple layers. In some embodiments, the material of the bit line contacts 151a to 151d includes polysilicon, tungsten (W), aluminum (Al), copper (Cu), nickel (Ni), cobalt (Co), cobalt silicide, titanium silicide, tantalum silicide, nickel silicide, copper silicide, tungsten silicide, molybdenum silicide, other suitable conductive materials or combinations thereof.

[0133] In addition, in some embodiments, deep trench capacitors 171a to 171f are formed after forming fin structures 111a to 111c. In some embodiments, deep trench capacitors 171a to 171f are formed before forming dummy gate structures, which are used to form word lines 161a to 161d. In some embodiments, semiconductor device structure 100 is a DRAM, and bit line contacts 151a to 151d are used to form vertical electrical connections between the underlying source / drain structures and the overlying bit lines.

[0134] Embodiments of semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure 100 includes word lines 161a to 161d arranged across fin structures 111a to 111c, source / drain structures 121a to 121o arranged above recessed portions (e.g., recessed portions 111a', 111b', and 111c') of the fin structures 111a to 111c and adjacent to the word lines 161a to 161d, and air gaps (e.g., air gaps 134a and 134b) formed between adjacent source / drain structures (e.g., source / drain structures 121c, 121h, and 121m) along a direction parallel to the longitudinal direction of the word lines 161a to 161d. Since the air gaps are formed between adjacent source / drain structures and the air gaps extend into adjacent recessed portions of the fin structures 111a to 111c, the capacitance between adjacent source / drain structures can be reduced. As a result, the operating speed of the semiconductor device structure 100 can be increased, and the overall device performance can be improved.

[0135] The semiconductor device structure 100 is provided for the purpose of illustration, and the present disclosure is not limited thereto. For example, in other embodiments, the bit line contacts 151a to 151d of the semiconductor device structure 100 may be replaced by other structures, such as Fig.12 A semiconductor device structure 200 is shown.

[0136] Please refer to Fig.11 and Fig.12 . Fig.11 is a schematic cross-sectional view illustrating an intermediate stage of forming a semiconductor device structure 200 according to some other embodiments of the present disclosure. Fig.12 is a schematic cross-sectional view illustrating a semiconductor device structure 200 according to some other embodiments of the present disclosure.

[0137] In some embodiments, the bit line contacts may be formed prior to applying Figures 4 to 10 The semiconductor device structure 200 is formed by the formation shown. Therefore, for the sake of brevity, the details of the formation of the bit line contacts of the semiconductor device structure 200 are omitted.

[0138] exist Fig.11 In the embodiment, a barrier layer 251a and a barrier layer 251d are formed in the contact opening 148a and the contact opening 148d, respectively. Although only the barrier layer 251a and the barrier layer 251d are described, it should be understood that the barrier layer 251b and the barrier layer 251c are also formed in the contact opening 148b and the contact opening 148c, respectively.

[0139] The barrier layer 251a is identical to the barrier layer 251d, and therefore, for the sake of brevity, only the barrier layer 251 is discussed below. In some embodiments, the barrier layer 251a is formed to cover the sidewalls of the contact opening 148a and the exposed surface of the source / drain structure 121c. In other words, a portion of the contact opening 148a is filled with the barrier layer 251a, and thus the contact opening 148a is shrunk to an opening 149a. Similarly, after the barrier layer 251d is formed, the contact opening 148d is shrunk to an opening 149d.

[0140] The barrier layer 251a includes a lower portion and two side portions. The lower portion contacts the source / drain structure 121c and the contact etching stop layer 131, and each side portion contacts the interlayer dielectric structure 141. In some embodiments, a thickness W1 of the lower portion is different from a thickness W2 of the side portion. In some embodiments, the thickness W1 is greater than the thickness W2.

[0141] In some embodiments, the barrier layer 251 a includes titanium (Ti), titanium nitride (TiN), or a combination thereof.

[0142] In some embodiments, the barrier layer 251a is formed by an anisotropic deposition process such that the thickness W1 is greater than the thickness W2. In some embodiments, the anisotropic deposition process for forming the barrier layer 251a includes a physical vapor deposition (PVD) process.

[0143] After the barrier layers 251 a to 251 d are formed, conductive layers 252 a to 252 d are formed in the openings 149 a to 149 d , respectively.

[0144] like Fig.12As shown, the openings 149a and 149d are completely filled with the conductive layer 252a and 252d respectively. The conductive layer 252a is separated from the source / drain structure 121c and the interlayer dielectric structure 141, and the conductive layer 252d is separated from the source / drain structure 121d and the interlayer dielectric structure 141.

[0145] In some embodiments, the conductive layer 252a and the conductive layer 252d include tungsten (W).

[0146] The barrier layer 251a and the conductive layer 252b together form a bit line contact 252. In some embodiments, the bit line contact 252 is a non-void contact. In some embodiments, the non-void contact has better electrical conductivity than the void contact. Therefore, when the semiconductor device structure 200 has a non-void contact for transmitting electronic signals, the semiconductor device structure 200 can have better performance.

[0147] Please refer to Fig.13 . Fig.13 FIG. 3 is a top view schematically illustrating a semiconductor device structure 300 according to some different embodiments of the present disclosure.

[0148] Except for the configuration of the fin structure, the semiconductor device structure 300 is similar to Figure 1 The semiconductor device structure 100 is shown. Fig.13 As shown, the semiconductor device structure 300 includes fin structures 311a, 311b and 311c that are different from the fin structures 111a, 111b and 111c of the semiconductor device structure 100. It should be understood that other elements of the semiconductor device structure 300 are the same as those of the semiconductor device structure 100.

[0149] In various embodiments, each channel region of the fin structures 311 a , 311 b , and 311 c has a width narrower than other regions of the fin structures 311 a , 311 b , and 311 c .

[0150] In some embodiments, from a top view of the semiconductor element structure 300, the channel region CH1 and the channel region CH2 of the fin structure 311a are narrower than other regions of the fin structure 311a; therefore, the channel region CH1 and the channel region CH2 of the fin structure 311a are narrower than other regions of the fin structure 311a; the channel region CH3 and the channel region CH4 of the fin structure 311b are narrower than other regions of the fin structure 311b; and the channel region CH5 and the channel region CH6 of the fin structure 311c are narrower than other regions of the fin structure 311c.

[0151] Although the semiconductor device structures 200 and 300 described above have different features, the semiconductor device structure 200 may include features of the semiconductor device structure 300 , and the semiconductor device structure 300 may include properties of the semiconductor device structure 200 .

[0152] An embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a semiconductor substrate, a first fin structure, a first source / drain structure, and a bit line contact point. The first fin structure protrudes from the semiconductor substrate and has a first sidewall, a second sidewall, and an upper surface connecting the first sidewall to the second sidewall. The first source / drain structure is arranged above the first fin structure and covers the upper surface of the first fin structure, a portion of the first sidewall, and a portion of the second sidewall. The bit line contact point is arranged above the first source / drain structure. The bit line contact point includes a barrier layer in contact with the first source / drain structure; and a conductive layer arranged above the barrier layer.

[0153] An embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a first fin structure, a first source / drain structure, a second source / drain structure, a third source / drain structure, a first word line and a second word line. The first fin structure is disposed on a semiconductor substrate and includes a first channel region, a second channel region and other regions. The first source / drain structure, the second source / drain structure and the third source / drain structure are disposed above the first fin structure. The first word line is disposed between the first source / drain structure and the second source / drain structure, and crosses the first channel region of the first fin structure from a top view of the semiconductor device structure. The second word line is disposed between the second source / drain structure and the third source / drain structure, and crosses the second channel region of the first fin structure from a top view. A width of the first channel region is equal to a width of the second channel region, and the width of the first channel region is less than a width of the other regions of the first fin structure.

[0154] Another embodiment of the present disclosure provides a method for preparing a semiconductor device structure. The preparation method includes forming a first fin structure and a second fin structure above a semiconductor substrate; forming an isolation structure above the semiconductor substrate, wherein the first fin structure and the second fin structure protrude from the isolation structure; partially removing the first fin structure and the second fin structure to form a first recessed portion of the first fin structure and a second recessed portion of the second fin structure; epitaxially growing a first source / drain structure above the first recessed portion and epitaxially growing a second source / drain structure above the second recessed portion, wherein the first source / drain structure is separated from the second source / drain structure by a first opening; partially removing the isolation structure through the first opening to form a second opening, wherein the first opening and the second opening are a continuous space; forming a contact etch A stop layer is formed over the first source / drain structure and the second source / drain structure so that an air gap is formed and sealed in the first opening and the second opening; an interlayer dielectric structure is formed over the contact etch stop layer; a portion of the interlayer dielectric structure over the first source / drain structure and a portion of the contact etch stop layer over the first source / drain structure are removed to form a third opening, wherein the third opening exposes the first source / drain structure; an anisotropic deposition process is performed to deposit a barrier layer in the third opening, wherein the barrier layer includes a lower portion in contact with the first source / drain structure and a side portion in contact with the dielectric structure; and a conductive layer is formed over the barrier layer, wherein the barrier layer and the conductive layer are configured to become a bit line contact.

[0155] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements may be made without departing from the spirit and scope of the present disclosure as defined in the claims. For example, many of the above processes may be implemented in different ways, and other processes or combinations thereof may be used to replace many of the above processes.

[0156] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A semiconductor device structure, comprising: a semiconductor substrate; A first fin structure protrudes from the semiconductor substrate and has a first sidewall, a second sidewall, and an upper surface connecting the first sidewall to the second sidewall; a first source / drain structure disposed above the first fin structure and covering the upper surface of the first fin structure, a portion of the first sidewall, and a portion of the second sidewall; as well as A bit line contact is disposed above the first source / drain structure and includes: a barrier layer in contact with the first source / drain structure; as well as A conductive layer is disposed above the barrier layer.

2. The semiconductor device structure as claimed in claim 1, wherein the first source / drain structure comprises a lower portion and an upper portion above the lower portion; wherein the lower portion covers the upper surface of the first fin structure, the portion of the first sidewall, and the portion of the second sidewall; The upper portion has a triangular profile, wherein the upper portion has a main side coupled to the lower portion and two sub-sides surrounding the triangular profile having the main side, wherein the two sub-sides have the same length. 3 . The semiconductor device structure as claimed in claim 2 , wherein the barrier layer is in contact with the two sub-sides. 4 . The semiconductor device structure as claimed in claim 2 , wherein the first source / drain structure has a maximum width, and the maximum width is equal to a length of the main side.

5. The semiconductor device structure according to claim 4, further comprising: a second fin structure protruding from the semiconductor substrate, wherein the second fin structure is arranged parallel to the first fin structure; as well as a second source / drain structure disposed above the second fin structure; as well as An isolation structure is formed between the first fin structure and the second fin structure, wherein the isolation structure includes a plurality of protrusions contacting the first source / drain structure and the second source / drain structure.

6. The semiconductor device structure according to claim 5, further comprising: a contact etching stop layer, contacting the two sub-sides of the upper portion of the first source / drain structure, the lower portion of the first source / drain structure, the isolation structure, the second source / drain structure and the barrier layer; as well as An air gap is disposed between the first fin structure and the second fin structure, wherein the air gap is surrounded by the contact etching stop layer and sealed by the contact etching stop layer. The semiconductor device structure as claimed in claim 6 , wherein the air gap has a pentagonal profile. 8 . The semiconductor device structure as claimed in claim 6 , wherein a highest point of the air gap is lower than the upper portion of the first source / drain structure, and the highest point of the air gap is higher than the upper surface of the first fin structure. 9 . The semiconductor device structure as claimed in claim 6 , wherein the air gap has a leftmost point and a rightmost point flush with the leftmost point, wherein the leftmost point and the rightmost point are lower than the upper surface of the first fin structure. 10 . The semiconductor device structure as claimed in claim 9 , wherein a highest point of the plurality of protrusions of the isolation structure is higher than the leftmost point and the rightmost point of the air gap.

11. The semiconductor device structure according to claim 6, further comprising: an interlayer dielectric structure disposed above the contact etch stop layer and in contact with the barrier layer; The second source / drain structure is separated from the interlayer dielectric structure.

12. The semiconductor device structure according to claim 6, further comprising: a first word line, viewed from a top view of the semiconductor device structure, crossing the first fin structure and the second fin structure; as well as a second word line, viewed from the top view of the semiconductor device structure, crossing the first fin structure and the second fin structure; wherein the first word line is parallel to the second word line; From the top view, the first source / drain structure, the second source / drain structure and the air gap are disposed between the first word line and the second word line.

13. The semiconductor device structure as claimed in claim 1, wherein the barrier layer comprises: Two side parts; as well as a lower portion, connecting one of the side portions to the other side portion; A thickness of the lower portion is greater than a thickness of the two side portions.

14. A method for preparing a semiconductor element structure, comprising: forming a first fin structure and a second fin structure above a semiconductor substrate; forming an isolation structure above the semiconductor substrate, wherein the first fin structure and the second fin structure protrude from the isolation structure; Partially removing the first fin structure and the second fin structure to form a first recessed portion of the first fin structure and a second recessed portion of the second fin structure; epitaxially growing a first source / drain structure above the first recess and epitaxially growing a second source / drain structure above the second recess, wherein the first source / drain structure is separated from the second source / drain structure by a first opening; Partially removing the isolation structure through the first opening to form a second opening, wherein the first opening and the second opening are a continuous space; forming a contact etch stop layer over the first source / drain structure and the second source / drain structure so that an air gap is formed and sealed in the first opening and the second opening; forming an interlayer dielectric structure over the contact etch stop layer; Removing a portion of the interlayer dielectric structure above the first source / drain structure and a portion of the contact etch stop layer above the first source / drain structure to form a third opening, wherein the third opening exposes the first source / drain structure; Performing an anisotropic deposition process to deposit a barrier layer in the third opening, wherein the barrier layer includes a lower portion contacting the first source / drain structure and a side portion contacting the interlayer dielectric structure; as well as A conductive layer is formed over the barrier layer, wherein the barrier layer and the conductive layer are configured to form a bit line contact. 15 . The method for fabricating a semiconductor device structure as claimed in claim 14 , wherein a thickness of the lower portion of the barrier layer is greater than a thickness of the side portion of the barrier layer. 16 . The method for fabricating a semiconductor device structure as claimed in claim 14 , wherein before the first source / drain structure is epitaxially grown, an upper surface and a sidewall of the first recess protrude from the isolation structure. 17 . The method for fabricating a semiconductor device structure as claimed in claim 14 , wherein a width of the first opening increases from an upper portion of the first opening to a lower portion of the first opening, and a width of the second opening decreases from an upper portion of the second opening to a lower portion of the second opening. 18 . The method for manufacturing a semiconductor device structure as claimed in claim 14 , wherein a sidewall of the isolation structure is exposed in the second opening. 19 . The method for fabricating a semiconductor device structure as claimed in claim 18 , wherein the contact etching stop layer extends into the first opening and the second opening, and the sidewall of the isolation structure is covered by the contact etching stop layer.

20. The method for preparing a semiconductor device structure according to claim 14, further comprising: A first word line and a second word line are formed across the first fin structure and the second fin structure, wherein the first source / drain structure, the second source / drain structure and the air gap are located between the first word line and the second word line.

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