Semiconductor structure and preparation method thereof, storage device and storage system

Abstract

The invention discloses a semiconductor structure and a preparation method thereof, a storage device and a storage system. The semiconductor structure includes: a first chip including a first peripheral circuit and a second peripheral circuit connected to each other; the second chip is located on one side of the first chip in the first direction, and the second chip comprises a first storage array; the first chip comprises a first storage array, the second chip comprises a second storage array, the first storage array and the second storage array are different in type, the first peripheral circuit is connected with the first storage array, and the second peripheral circuit is connected with the second storage array. The storage device comprises a plurality of semiconductor structures, the plurality of semiconductor structures are sequentially stacked along a first direction, and first chips of two adjacent semiconductor structures are connected with each other.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of semiconductor technology, and in particular, to semiconductor structures and methods for preparing the same, storage devices, and storage systems. Background Art

[0002] Solid State Drives (SSDs) have the advantages of fast read and write speed, low power consumption and high stability, and are widely used in electronic devices such as laptops. SSDs usually include a control chip, a dynamic random access memory chip (DRAM) and a NAND chip. The DRAM chip and the NAND chip are independently packaged and connected to the control chip through transmission lines.

[0003] Currently, how to further improve the performance of SSD is one of the technical problems that technical personnel in this field need to solve urgently. Summary of the invention

[0004] The semiconductor structure and its manufacturing method, storage device and storage system provided in the embodiments of the present application can solve or partially solve the above-mentioned deficiencies in the prior art or other deficiencies in the prior art.

[0005] The semiconductor structure provided according to the first aspect of the present application includes:

[0006] A first chip includes a first peripheral circuit and a second peripheral circuit connected to each other;

[0007] A second chip, located at one side of the first chip along a first direction, the second chip comprising a first storage array; and

[0008] The third chip includes a second storage array, the first storage array and the second storage array are of different types, the first peripheral circuit is connected to the first storage array, and the second peripheral circuit is connected to the second storage array.

[0009] The storage device provided according to the second aspect of the present application includes: a plurality of semiconductor structures described in the first aspect of the present application, wherein the plurality of semiconductor structures are stacked in sequence along a first direction, and the first chips of two adjacent semiconductor structures are connected to each other.

[0010] According to the third aspect of the present application, the storage system includes: a controller and the storage device described in the second aspect of the present application, wherein the controller is coupled to the storage device and is used to control the storage device to store data.

[0011] The method for preparing a semiconductor structure according to the fourth aspect of the present application includes:

[0012] forming a first chip including a first peripheral circuit and a second peripheral circuit connected to each other;

[0013] forming a second chip including the first memory array;

[0014] forming a third chip including a second memory array; and

[0015] The first chip, the second chip and the third chip are bonded together so that the first peripheral circuit is connected to the first storage array, and the second peripheral circuit is connected to the second storage array.

[0016] The semiconductor structure provided in the embodiment of the present application disassembles the first storage array and the first peripheral circuit corresponding to the first storage array, disassembles the second storage array and the second peripheral circuit corresponding to the second storage array, integrates the first peripheral circuit and the second peripheral circuit with similar process technology on the same chip, i.e., the first chip, and manufactures the first storage array and the second storage array with greatly different process technology on two chips, i.e., the second chip and the third chip, respectively. Not only can the peripheral circuit realize logical control of the corresponding storage array, reading of stored data and other operations by connecting the first storage array with the first peripheral circuit and connecting the second storage array with the second peripheral circuit, but the first peripheral circuit and the second peripheral circuit are integrated on the same chip and can be directly contacted and connected, eliminating additional data transmission lines and reducing data transmission losses, thereby improving data interaction speed and transmission bandwidth utilization.

[0017] The storage device provided in the embodiments of the present application can reduce the footprint of the entire storage device by stacking multiple semiconductor structures together along a first direction, and can also reduce subsequent packaging costs.

[0018] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present application, nor is it intended to limit the scope of the present application. Other features of the present application will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Other features, purposes and advantages of the present application will become more apparent by reading the detailed description of the non-limiting embodiments made with reference to the following drawings. The drawings are used to better understand the present solution and do not constitute a limitation of the present application. In the drawings:

[0020] Figure 1 is a schematic diagram of an electronic device according to one embodiment of the present application;

[0021] Figure 2 is a schematic top view of a solid state drive according to an embodiment of the present application;

[0022] Figure 3 is a schematic structural diagram of a solid state drive according to an embodiment of the present application;

[0023] Figure 4 is a three-dimensional schematic diagram of a semiconductor structure according to one embodiment of the present application;

[0024] Figure 5 is a three-dimensional schematic diagram of a semiconductor structure according to another embodiment of the present application;

[0025] Figure 6 is a three-dimensional schematic diagram of a semiconductor structure according to another embodiment of the present application;

[0026] Figure 7 is a schematic structural diagram of a storage device according to one embodiment of the present application;

[0027] Figure 8 is a schematic structural diagram of a storage device according to another embodiment of the present application;

[0028] Fig. 9 is a schematic structural diagram of a wiring layer according to an embodiment of the present application; and

[0029] Fig.10 is a flow chart of a method for preparing a semiconductor structure according to one embodiment of the present application.

[0030] Reference numerals:

[0031] 100. semiconductor structure; 110. first chip; 111. first peripheral circuit;

[0032] 112. a second peripheral circuit; 120. a second chip; 121. a first storage array;

[0033] 122, wiring layer; 123, dielectric layer; 124, solder mask layer; 125, metal routing;

[0034] 130, a third chip; 131, a second storage array; 141, a first bonding layer;

[0035] 142. a first bonding contact; 143. a second bonding contact; 144. a second bonding layer;

[0036] 145. third bonding contact; 146. fourth bonding contact; 200. packaging substrate;

[0037] 300, plastic package; 410, first wire; 420, second wire; 500, solder ball;

[0038] 600, electronic device; 610, host; 620, storage system; 621, control chip;

[0039] 622, cache chip; 623, flash memory chip; 630, solid state drive;

[0040] 631, DRAM chip; 632, NAND chip; 633, circuit board;

[0041] 634. Connector. DETAILED DESCRIPTION

[0042] In order to better understand the present application, a more detailed description will be made of various aspects of the present application with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0043] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature region, but do not represent any limitation on the features, and especially do not represent any order of precedence.

[0044] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0045] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0046] Unless otherwise specified, all words (including engineering terms and scientific and technological terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0047] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method described in the present application are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0048] In addition, in the present application, the term "layer" refers to a material portion including an area with a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is less than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of a continuous structure. A layer may extend horizontally, vertically and / or along an inclined surface. A layer may include multiple sublayers. In addition, in the present application, when "connected" or "coupled" is used, it may indicate direct contact or indirect contact between corresponding parts, unless otherwise clearly defined or inferred from the context.

[0049] Figure 1 FIG. 6 is a schematic diagram of an electronic device 600 according to one embodiment of the present application. The electronic device 600 may be, but is not limited to, a mobile phone, a desktop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a virtual reality device, an augmented reality device, or other devices with a memory. Figure 1As shown, the electronic device 600 includes a host 610 and a storage system 620. The host 610 may be a processor of the electronic device 600, such as a central processing unit (CPU) or a system-on-a-Chip (SoC). The storage system 620 includes a plurality of storage chips and a control chip 621. The control chip 621 is coupled to the storage chip and the host 610. The host 610 is configured to send data to the storage chip or receive data from the storage chip. The control chip 621 is configured to manage the data stored in the storage chip and communicate with the host 610. Among them, at least one storage chip among the plurality of storage chips may be a cache chip 622, and at least one storage chip may be a flash memory chip 623. Among them, the control chip 621 may be designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or a data storage device for electronic devices such as personal calculators, digital cameras, mobile phones, etc. In addition, the control chip 621 can also be designed to operate in a high duty cycle environment SSD (Solid State Drives) or embedded multimedia card (eMMC), which is used as a data storage device for mobile devices such as smart phones and tablet computers. Figure 2 and Figure 3 As shown, the control chip 621, the cache chip 622 and the flash memory chip 623 are integrated on the circuit board 633 of the SSD. The control chip 621 is used to reasonably allocate the load of data on each flash memory chip 623 and transfer all data. The cache chip 622 is used to assist the control chip 621 in data processing, and the flash memory chip 623 is used to store data. Among them, the cache chip 622 generally adopts a dynamic random access memory chip (Dynamic Random Access Memory, DRAM), and the flash memory chip 623 generally adopts a NAND chip 632. In addition, the SSD may also include a connector 634 that couples the SSD with the host 610.

[0050] like Figure 3As shown, the control chip 621, DRAM chip 631 and NAND chip 632 are each independently packaged and connected to the circuit board 633 of the SSD through solder balls, and the DRAM chip 631 and the NAND chip 632 are connected to the control chip 621 through the transmission line of the circuit board 633. This connection method makes it impossible for the DRAM chip 631 and the NAND chip 632 to directly transmit data, and the data transmission path between the DRAM chip 631 and the NAND chip 632 is too long, resulting in a large data transmission delay, which affects the utilization of the transmission bandwidth, resulting in a limited data exchange speed, and further resulting in the performance of the DRAM chip 631 and the NAND chip 632 cannot be fully utilized.

[0051] Based on this, in order to solve at least some of the above problems, such as Figure 4 and Figure 5 As shown, an embodiment of the present application provides a semiconductor structure 100, which includes a first chip 110, a second chip 120 and a third chip 130. The first chip 110 includes a first peripheral circuit 111 and a second peripheral circuit 112 connected to each other, the second chip 120 is located at one side of the first chip 110 along a first direction (z direction), the second chip 120 includes a first memory array 121, the third chip 130 includes a second memory array 131, the first memory array 121 and the second memory array 131 are of different types, the first peripheral circuit 111 is connected to the first memory array 121, and the second peripheral circuit 112 is connected to the second memory array 131.

[0052] Since the first memory array 121 and the second memory array 131 are of different types, the process technology of the first memory array 121 and the second memory array 131 is usually quite different, while the first peripheral circuit 111 and the second peripheral circuit 112 are both peripheral circuits, and the process technology of the two is usually similar, so that the first peripheral circuit 111 and the second peripheral circuit 112 can be formed on the same chip. Based on this, in the embodiment of the present application, the first storage array 121 and the first peripheral circuit 111 corresponding to the first storage array 121 are disassembled, and the second storage array 131 and the second peripheral circuit 112 corresponding to the second storage array 131 are disassembled, and the first peripheral circuit 111 and the second peripheral circuit 112 with similar process are integrated on the same chip, namely the first chip 110, and the first storage array 121 and the second storage array 131 with greatly different process are respectively made into two chips, namely the second chip 120 and the third chip 130. Not only can the peripheral circuit realize the logic control of the corresponding storage array and the reading of the stored data by the connection between the first storage array 121 and the first peripheral circuit 111 and the connection between the second storage array 131 and the second peripheral circuit 112, but also the first peripheral circuit 111 and the second peripheral circuit 112 are integrated on the same chip and can be directly contacted and connected, which saves additional data transmission lines and reduces data transmission losses, thereby improving the data interaction speed and the utilization rate of the transmission bandwidth.

[0053] like Figure 4 and Figure 5 As shown, the first chip 110, the second chip 120 and the third chip 130 can be bonded and connected. The bonding positions of the first chip 110, the second chip 120 and the third chip 130 are affected by the relative sizes of the three chips.

[0054] For example, Figure 5As shown, if the area of ​​the first chip 110 is greater than the sum of the areas of the second chip 120 and the third chip 130, in other words, on a plane perpendicular to the first direction (z direction), the projections of the second chip 120 and the third chip 130 fall into the projection of the first chip 110, then the second chip 120 and the third chip 130 can be located on the same side of the first chip 110 and arranged in sequence along a second direction (x direction) perpendicular to the first direction, and the second chip 120 and the third chip 130 can be directly bonded to the first chip 110 respectively. In order to shorten the data transmission path between the first memory array 121 and the first peripheral circuit 111 and the data transmission path between the second memory array 131 and the second peripheral circuit 112, the first memory array 121 and the second memory array 131 can be arranged corresponding to the first peripheral circuit 111 and the second peripheral circuit 112 respectively, in other words, on a plane perpendicular to the first direction, the projection of the second chip 120 at least partially overlaps with the projection of the first peripheral circuit 111, and the projection of the third chip 130 at least partially overlaps with the projection of the second peripheral circuit 112. Thus, the first memory array 121 can be directly bonded to the first peripheral circuit 111 to achieve data transmission communication between the first memory array 121 and the first peripheral circuit 111, and the second memory array 131 can be directly bonded to the second peripheral circuit 112 to achieve data transmission communication between the second memory array 131 and the second peripheral circuit 112. As an example, Figure 5 As shown, the area of ​​the first peripheral circuit 111 is larger than the area of ​​the first storage array 121, and the area of ​​the second peripheral circuit 112 is smaller than the area of ​​the second storage array 131. In other words, on a plane perpendicular to the first direction, the projection of the first storage array 121 falls into the projection of the first peripheral circuit 111, and the projection of the second peripheral circuit 112 falls into the projection of the second storage array 131.

[0055] It should be noted that the second chip 120 and the third chip 130 can be directly bonded to the first chip 110, or can be bonded based on a bonding layer. Compared with other methods, the direct bonding method can make the first chip 110 and the second chip 120 and the third chip 130 have a lower degree of deformation, a smaller connection spacing and less residual stress. Figure 6As shown, taking bonding based on a bonding layer as an example, the first chip 110 also includes a first interconnect structure (not shown) connected to the first peripheral circuit 111 and a second interconnect structure (not shown) connected to the second peripheral circuit 112, and a first bonding layer 141 is formed on the side of the first chip 110 facing the second chip 120 and the third chip 130, and a first bonding contact 142 and a second bonding contact 143 are formed in the first bonding layer 141 and penetrate the first bonding layer 141, the first bonding contact 142 is connected to the first interconnect structure, and the second bonding contact 143 is connected to the second interconnect structure. The second chip 120 also includes a third interconnect structure (not shown) connected to the first storage array 121, and the third chip 130 also includes a fourth interconnect structure (not shown) connected to the second storage array 131. A second bonding layer 144 is formed on the side of the second chip 120 and the third chip 130 facing the first chip 110, and a third bonding contact 145 and a fourth bonding contact 146 are formed in the second bonding layer 144 and penetrate the second bonding layer 144. The third bonding contact 145 is connected to the third interconnect structure, and the fourth bonding contact 146 is connected to the fourth interconnect structure. Among them, the materials of the first bonding layer 141 and the second bonding layer 144 may include but are not limited to insulating materials such as silicon oxide, silicon nitride and / or silicon oxynitride, the materials of the first bonding contact 142 to the fourth bonding contact 146 and the first interconnection structure to the fourth interconnection structure may include but are not limited to at least one of tungsten, cobalt, copper, aluminum and silicide, and the first interconnection structure to the fourth interconnection structure may include but are not limited to a vertical wire bonding structure and a TSV (Through Silicon Via, conductive through-silicon via) structure. In practical applications, the shape, material and preparation process of the first interconnection structure to the fourth interconnection structure can be determined according to the needs of the semiconductor structure 100. As an example, the first bonding layer 141 can be bonded to the second bonding layer 144 using an Xtacking bonding process. Among them, the Xtacking bonding process refers to the alignment bonding of the bonding structures between different devices in the same process step, thereby realizing the electrical connection of the two devices. After the first bonding layer 141 is bonded to the second bonding layer 144, the first bonding surface of the first bonding layer 141 overlaps with the second bonding surface of the second bonding layer 144, the first bonding contact 142 contacts the third bonding contact 145, and the second bonding contact 143 contacts the fourth bonding contact 146. The first bonding surface is the side of the first bonding layer 141 away from the first chip 110, and the second bonding surface is the side of the second bonding layer 144 away from the second chip 120 and the third chip 130.

[0056] For example, Figure 4As shown, if the area of ​​the second chip 120 is greater than the sum of the areas of the first chip 110 and the third chip 130, in other words, on a plane perpendicular to the first direction (z direction), the projections of the first chip 110 and the third chip 130 fall into the projection of the second chip 120, then the first chip 110 and the third chip 130 can be located on the same side of the second chip 120 and arranged in sequence along the second direction (x direction) perpendicular to the first direction, and the first chip 110 and the third chip 130 can be bonded to the second chip 120 respectively. Since the first chip 110 and the third chip 130 are arranged in parallel along the second direction, it is impossible to achieve the connection between the second storage array 131 and the second peripheral circuit 112 by direct bonding. Therefore, the second chip 120 may also include a wiring layer 122. The wiring layer 122 is located on the side of the first storage array 121 facing the first chip 110 and the third chip 130. The first chip 110 and the third chip 130 are bonded to the wiring layer 122 respectively, so that the first peripheral circuit 111 is connected to the first storage array 121 through the wiring layer 122, and the second peripheral circuit 112 is connected to the second storage array 131 through the wiring layer 122. In order to shorten the data transmission path between the second peripheral circuit 112 and the second storage array 131, the second peripheral circuit 112 is located between the first peripheral circuit 111 and the third chip 130 along the second direction (x direction). Among them, as Fig. 9 As shown, the wiring layer 122 may include a dielectric layer 123 and a solder resist layer 124 stacked in sequence along a first direction, the solder resist layer 124 is located on a side of the dielectric layer 123 away from the first storage array 121, at least one layer of metal wiring 125 is provided in the dielectric layer 123, the first peripheral circuit 111 and the first storage array 121 as well as the second peripheral circuit 112 and the second storage array 131 are connected via at least one layer of metal wiring 125, and the solder resist layer is provided with through holes penetrating the solder resist layer to expose the pad area of ​​the metal wiring.

[0057] It should be noted that the first storage array 121 can be a non-volatile storage array, for example, the first storage array 121 is a NAND storage array, a PROM (Programmable Read-Only memory) storage array or a NOR storage array, and the second storage array 131 can be a volatile storage array, for example, the second storage array 131 is a DRAM (Dynamic Random Access Memory) storage array or an SRAM (Static Random-Access Memory) storage array. Among them, the first peripheral circuit 111 and the second peripheral circuit 112 can include but are not limited to at least one of a high-voltage device, a low-voltage device and an ultra-low-voltage device. The high-voltage device can include but are not limited to at least one of a row decoder, a column decoder, a word line driver and a bit line driver, the low-voltage device can include but are not limited to a page buffer or a logic device, and the ultra-low-voltage device can include but are not limited to an I / O circuit. The operating voltage of a high-voltage device is generally greater than 3.3V, such as 5V to 30V. As an example, the operating voltage of a high-voltage device may be 5V, 10V, 15V, 20V, 25V or 30V; the operating voltage of a low-voltage device is generally between 1.3V and 3.3V. As an example, the operating voltage of a low-voltage device may be 1.3V, 1.8V, 2.3V, 2.8V or 3.3V; the operating voltage of an ultra-low-voltage device is generally lower than 1.3V, such as 0.9V to 1.2V; as an example, the operating voltage of an ultra-low-voltage device may be 0.9V, 0.95V, 1V, 1.05V, 1.1V, 1.15V or 1.2V. It should be noted that the operating voltage of a high-voltage device, a low-voltage device or an ultra-low-voltage device may also be any value between any two of the above voltage values. Those skilled in the art should understand that the description of the operating voltage ranges of high-voltage devices, low-voltage devices and ultra-low-voltage devices above is for a better understanding of the present solution and does not constitute a limitation on the present application.

[0058] As an example, the first storage array 121 may be a NAND storage array, the second storage array 131 may be a DRAM storage array, the first peripheral circuit 111 may be a NAND CMOS, and the second peripheral circuit 112 may be a DRAM CMOS. Since the NAND CMOS and the DRAM CMOS are integrated on the same chip, namely the first chip 110, the NAND CMOS and the DRAM CMOS may be directly connected, and data may be directly transmitted between the two. The second chip 120 may realize the connection between the NAND storage array and the NAND CMOS by bonding with the first chip 110, and the third chip 130 may also realize the connection between the DRAM storage array and the DRAM CMOS by bonding with the first chip 110. It can be seen that the embodiment of the present application splits the traditional NAND chip and DRAM chip, makes the NAND CMOS and DRAM CMOS with similar process on the same chip, namely the first chip 110, and makes the NAND storage array and DRAM storage array with greatly different process on the second chip 120 and the third chip 130 respectively. Not only can the connection between the NAND storage array and the NAND CMOS and the connection between the DRAM storage array and the DRAM CMOS be realized through the bonding of the first chip 110, the second chip 120 and the third chip 130, but also the direct communication of data between NAND and DRAM can be realized through the direct connection of NAND CMOS and DRAM CMOS, eliminating the transmission line between NAND and DRAM, shortening the data transmission path between NAND and DRAM, reducing data transmission delay, and reducing data transmission loss. In addition, compared with the prior art in which the DRAM chip and the NAND chip are packaged separately, the bonding of the first chip 110, the second chip 120 and the third chip 130 in the embodiment of the present application can also reduce the occupied area of ​​the entire semiconductor structure 100 and improve the integration.

[0059] In some embodiments, the first storage array 121 may include a stacked structure and a plurality of channel structures that penetrate the stacked structure along a first direction (z direction), the stacked structure including a connection area and a core area having a plurality of channel structures formed therein, the connection area being located on at least one side of the core area along a second direction. Among them, the connection area may be a stepped structure or a non-stepped structure. For example, under the SCT (Staircase Contact, step area contact) architecture, the connection area does not need to be stepped. The stacked structure includes gate layers and insulating layers that are alternately stacked along the stacking direction, i.e., the first direction. The gate layers and insulating layers may be arranged in pairs or may be arranged in non-pairs. As an example, the stacked structure may include, but is not limited to, 64 pairs, 128 pairs, or more than 128 pairs of gate layers and insulating layers, which is not limited in the present application. The higher the number of stacked layers of the gate layers and insulating layers, the higher the integration of the second chip 120. In other words, the higher the unit storage density of the second chip 120. The channel structure includes a functional layer and a channel layer, and both the functional layer and the channel layer can be formed by a thin film deposition process, and the thin film deposition process can be but not limited to a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or a combination of any of the above processes. Further, the functional layer may include a blocking layer, a charge capture layer, and a tunneling layer arranged in sequence along the second direction (x direction). Among them, the material of the blocking layer and the tunneling layer may be but not limited to silicon oxide, and the material of the charge capture layer may be but not limited to silicon nitride. In other words, the functional layer may have an ONO structure. Among them, the material of the channel layer may be but not limited to semiconductor materials such as amorphous silicon, polycrystalline silicon or single crystal silicon.

[0060] Among them, the functional layer of the channel structure and the portion of the channel layer corresponding to the gate layer of the stacked structure and a portion of the gate layer together constitute a storage unit, and multiple storage units are connected in series along the stacking direction of the stacked structure, that is, the first direction (z direction) to form a storage string, and the storage units located in the same row, that is, distributed along the second direction, can be connected to the same word line, and the remaining portion of the gate layer can be used as the word line of multiple storage units in the corresponding storage string, and each storage string, that is, the storage units in the same column, can be connected to the same bit line. Under the voltage control of the corresponding word line, the carriers in the channel layer of the storage unit enter the charge capture layer of the functional layer, or the carriers in the charge capture layer of the functional layer retreat to the channel layer, thereby realizing the programming or erasing of the storage unit. In the case where the first peripheral circuit 111 includes a page buffer, a word line driver, and an I / O circuit, the page buffer is connected to the bit line to apply a bit line voltage to the bit line, and the bit line voltage corresponds to the data DATA to be programmed, and the data DATA may include multi-bit data. In a read operation, the page buffer can sense the data DATA stored in the selected storage unit through the bit line, and output the sensed data DATA to the I / O circuit. The word line driver is connected to the word line through the word line contact to apply a word line voltage to the word line, thereby performing an erase operation on the memory cell corresponding to the word line.

[0061] In some embodiments, the second storage array 131 may include an insulating layer, a plurality of transistors penetrating the insulating layer, and capacitors corresponding to the transistors one by one, the transistors including a source, a channel, and a drain arranged in sequence along a first direction, and a gate located on one side of the channel along a second direction, the drains of the plurality of transistors in the same column are electrically connected to the same bit line (BL), the source of the transistor is electrically connected to one of the electrode plates of the corresponding capacitor, the other electrode plate of the capacitor may be grounded or connected to a reference voltage, and the gates of the plurality of transistors in the same row are electrically connected to the same word line (WL). The word line is used to apply a voltage to control the conduction or cutoff of the transistor, and the bit line is used to perform a read or write operation on the capacitor when the transistor is turned on.

[0062] In some embodiments, the first peripheral circuit 111 or the second peripheral circuit 112 includes at least one of a high voltage device, a low voltage device, and an ultra-low voltage device. Further, the high voltage device, the low voltage device, and the ultra-low voltage device may include, but are not limited to, at least one of a transistor, a diode, a resistor, an inductor, and a capacitor. As an example, the first peripheral circuit 111 or the second peripheral circuit 112 includes a substrate and a transistor and a trench isolation structure at least partially located in the substrate, the trench isolation structure surrounds the active area of ​​the transistor, and the trench isolation structure can achieve electrical isolation between the transistor and other devices. The transistor may include a source, a drain, and a gate structure, the source and the drain are formed in the substrate, the gate structure is located on one side of the substrate and is arranged between the drain and the source, the gate structure includes a gate insulating layer and a gate conductive layer, and the gate conductive layer is located on the side of the gate insulating layer away from the substrate. If the transistor is an N-type transistor, N-type dopants such as phosphorus (P), arsenic (As) and antimony (Sb) can be used to form a drain and a source in the substrate; if the transistor is a P-type transistor, P-type dopants such as boron (B) are used to form a drain and a source in the substrate. Wherein, the material of the gate insulating layer includes insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, zirconium oxide, aluminum oxide, magnesium oxide, and tantalum oxide, and the material of the gate conductive layer includes polysilicon, a conductive metal or a conductive alloy. As an example, the material of the gate conductive layer includes at least one of tungsten (W), titanium nitride (TiN), copper (Cu) and silver (Ag). Wherein, the gate insulating layer and the gate conductive layer can be formed on one side of the substrate by a thin film deposition process. In addition, the trench isolation structure can be formed in the substrate by an etching process and a filling process. For example, a dry etching process, a combination of dry and wet etching processes, or a patterning process can be used to form a trench on one side of the substrate, and then a thin film deposition process can be used to deposit an insulating material on one side of the substrate to fill the trench. Among them, the insulating material can be but not limited to silicon dioxide, silicon nitride or silicon oxynitride. Since the insulating material will cover one side of the substrate during the actual deposition process, after the deposition process is completed, the chemical mechanical polishing (CMP) process can be used to remove the insulating material covering other areas of the substrate outside the groove. Among them, the substrate can be a single-layer structure or a multi-layer structure. For example, the substrate is a single-layer structure prepared from semiconductor materials. Among them, the semiconductor material can be but not limited to single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon on insulator (SOI), germanium on insulator (GOI) or gallium arsenide and other III-V compounds. For another example, the substrate is a multi-layer structure and at least two layers are made of different materials, and the substrate can be prepared by a thin film deposition process.Among them, the above-mentioned thin film deposition process can be but is not limited to a physical vapor deposition (Physical Vapor Deposition, referred to as PVD) process, a chemical vapor deposition (Chemical Vapor Deposition, referred to as CVD) process, an atomic layer deposition (Atomic Layer Deposition, referred to as ALD) process or a combination of any of the above processes.

[0063] like Fig.10 As shown, the embodiment of the present application also provides a method 1000 for preparing a semiconductor structure, the method comprising:

[0064] S100, forming a first chip 110 including a first peripheral circuit 111 and a second peripheral circuit 112 connected to each other;

[0065] S200, forming a second chip 120 including a first storage array 121;

[0066] S300, forming a third chip 130 including a second storage array 131;

[0067] S400 , bonding the first chip 110 , the second chip 120 and the third chip 130 , so that the first peripheral circuit 111 is connected to the first memory array 121 , and the second peripheral circuit 112 is connected to the second memory array 131 .

[0068] It should be noted that steps S100 to S300 may be executed in parallel, sequentially, or in any other order, and this application does not limit this.

[0069] In some embodiments, step S100 may include: forming a plurality of transistors on a substrate, wherein at least a portion of the transistors is located in the substrate, wherein at least one of the plurality of transistors belongs to a first peripheral circuit 111, and at least another transistor belongs to a second peripheral circuit 112; forming a plurality of trench isolation structures surrounding active regions of the transistors on the substrate; forming a first interconnect layer on the substrate, wherein the first interconnect layer covers a side of the substrate on which the transistors are formed and a side of the transistors away from the substrate; forming a first interconnect structure and a second interconnect structure in the first interconnect layer that penetrate the first interconnect layer, wherein the first interconnect structure is connected to the transistor of the first peripheral circuit 111, and the second interconnect structure is connected to the transistor of the second peripheral circuit 112.

[0070] In some embodiments, the transistors of the first peripheral circuit 111 and / or the second peripheral circuit 112 may be formed by the following steps: forming a well region in the substrate; for example, if the transistor is an N-type transistor, an ion implantation or diffusion process may be used to form a P-type doped well, i.e., a P-well, in the substrate, and the dopant may be a P-type dopant with a relatively low concentration, such as boron (B); if the transistor is a P-type transistor, an ion implantation or diffusion process may be used to form an N-type doped well, i.e., an N-well, in the substrate, and the dopant may be a N-type dopant with a relatively low concentration, such as phosphorus (P), arsenic (As), and antimony (Sb). Forming a drain and a source in the well region, for example, if the transistor is an N-type transistor, an N-type dopant such as phosphorus (P), arsenic (As), and antimony (Sb) may be used to form the source and the drain in the substrate; if the transistor is a P-type transistor, an P-type dopant such as boron (B) may be used to form the source and the drain in the substrate. A gate structure including a gate insulating layer and a gate conductive layer is formed on one side of the substrate. For example, a gate insulating layer can be formed on one side of the substrate by a thin film deposition process, and a portion of the gate insulating layer is removed by an etching process so that the remaining gate insulating layer is located between the source and the drain; a gate conductive layer is formed on the side of the gate insulating layer facing away from the substrate by a thin film deposition process, and a portion of the gate conductive layer is removed by an etching process so that the remaining gate conductive layer is located between the source and the drain and covers the gate insulating layer. Wherein, the material of the gate insulating layer includes dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, zirconium oxide, aluminum oxide, magnesium oxide, and tantalum oxide, and the material of the gate conductive layer includes polysilicon, conductive metal or conductive alloy. As an example, the material of the gate conductive layer includes at least one of tungsten (W), titanium nitride (TiN), copper (Cu) and silver (Ag). It should be noted that the source and drain of the above-mentioned transistor can also be directly formed in the substrate. In other words, the above steps may not include the step of forming a well region.

[0071] In some embodiments, step S200 may include: forming a first memory array 121; forming a wiring layer 122 along a first direction and on one side of the first memory array 121. As an example, the first memory array 121 may be formed in the following manner: forming a stacked structure, the stacked structure including an insulating layer and a sacrificial layer stacked in sequence along the first direction; forming a channel structure penetrating the stacked structure in the stacked structure; replacing the sacrificial layer of the stacked structure with a gate layer to form a stacked structure; forming a second interconnection layer on one side of the stacked structure; forming a third interconnection structure penetrating the second interconnection layer in the second interconnection layer, the third interconnection structure being connected to the gate layer of the stacked structure.

[0072] As an example, the wiring layer 122 may be formed in the following manner: forming a seed layer (not shown) on one side of the first memory array 121 by physical sputtering, magnetron sputtering or evaporation process; patterning the seed layer to form a metal trace 125; forming a dielectric layer 123 covering the metal trace 125; forming a solder resist layer 124 on the side of the dielectric layer 123 away from the first memory array 121; performing a hole processing on the solder resist layer 124 to expose the pad area of ​​the metal trace 125, thereby forming the wiring layer 122. The seed layer may be one layer or multiple layers, and the material of the seed layer may be titanium, copper, silver, tin, nickel, etc. .

[0073] In some embodiments, the wiring layer 122 has a first region and a second region on a side away from the first memory array 121, and the first region and the second region are sequentially distributed along a second direction (x direction) perpendicular to the first direction. Thus, step S400 may include: bonding the first chip 110 to the first region of the wiring layer 122; bonding the second chip 120 to the second region of the wiring layer 122.

[0074] In some other embodiments, step S400 may include: bonding the second chip 120 to the first peripheral circuit 111 of the first chip 110 ; and bonding the third chip 130 to the second peripheral circuit 112 of the first chip 110 .

[0075] In some embodiments, step S300 may include: forming a second storage array 131; for example, forming a grid-shaped insulating layer inside the wafer from the first surface of the wafer to divide part of the wafer into a plurality of transistor columns distributed in an array; wherein the thickness of the insulating layer is less than the thickness of the wafer, in other words, the insulating layer does not penetrate the second surface of the wafer, and the first surface and the second surface are arranged back to back. A drain is formed based on the end of the transistor column away from the second surface; the second surface of the wafer is thinned to expose the other end of the transistor column; a source is formed based on the other end of the transistor column, and the remaining part of the transistor column constitutes a channel. A third interconnect layer is formed on one side of the second storage array 131; a fourth interconnect structure penetrating the third interconnect layer is formed in the third interconnect layer, and the fourth interconnect structure is connected to the transistors of the second storage array 131.

[0076] In addition, if Figure 7 and Figure 8 As shown, the embodiment of the present application further provides a storage device, which includes a plurality of the above-mentioned semiconductor structures 100, wherein the plurality of semiconductor structures 100 are stacked in sequence along a first direction (z direction), and the first chips 110 of two adjacent semiconductor structures 100 are connected to each other. By stacking the plurality of semiconductor structures 100 together along the first direction, the embodiment of the present application can reduce the footprint of the entire storage device, and can also reduce the subsequent packaging cost.

[0077] In some embodiments, the storage device may further include a packaging substrate 200 and a plastic package 300, wherein the plastic package 300 packages the plurality of semiconductor structures 100 on the packaging substrate 200, and the first chip 110 closest to the packaging substrate 200 is connected to the packaging substrate 200 via a second wire 420. The material of the plastic package 300 may include at least one of polyimide, silica gel, and EMC (Epoxy Molding Compound), and the material of the second wire 420 may include, but is not limited to, at least one of gold, silver, and copper.

[0078] In order to facilitate the connection of adjacent first chips 110, two adjacent semiconductor structures 100 are staggered in sequence along a second direction (x direction) perpendicular to the first direction. In other words, the projections of the two adjacent semiconductor structures 100 on a plane perpendicular to the first direction partially overlap to expose a portion of the first chip 110 of one of the semiconductor structures 100. The first chips 110 of the two adjacent semiconductor structures 100 are connected via the first wire 410. As an example, Figure 7 As shown, the first chip 110 of the semiconductor structure 100 is farther away from the packaging substrate 200 in the first direction than the second chip 120, and the two adjacent semiconductor structures 100 are staggered in sequence along the second direction so that a portion of the first chip 110 relatively close to the semiconductor structure 100 is exposed, and the exposed portions of the two adjacent first chips 110 are connected by a first wire 410, and the material of the first wire 410 can be but is not limited to at least one of gold, silver and copper.

[0079] In addition, an embodiment of the present application further provides a storage system, which includes a controller and the above-mentioned storage device, wherein the controller is coupled to the storage device and is used to control the storage device to store data.

[0080] In some embodiments, the storage system further includes a circuit board, the controller and the storage device electrical connection structure are connected to the circuit board, the controller and the storage device are placed on the circuit board, and the electrical connection structure is located between the circuit board and the controller and the storage device. The electrical connection structure may be, but is not limited to, at least one of a solder ball 500, a metal bump, and a conductive adhesive.

[0081] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. As an example, the steps recorded in the disclosure of the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution disclosed in the present application can be achieved, and this document does not limit this.

[0082] The above specific implementations do not constitute a limitation on the protection scope of this application. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of this application should be included in the protection scope of this application.

Claims

1. A semiconductor structure, characterized in that: include: A first chip includes a first peripheral circuit and a second peripheral circuit connected to each other; A second chip, located at one side of the first chip along a first direction, the second chip comprising a first storage array; as well as The third chip includes a second storage array, the first storage array and the second storage array are of different types, the first peripheral circuit is connected to the first storage array, and the second peripheral circuit is connected to the second storage array.

2. The semiconductor structure according to claim 1, wherein: The first storage array is a non-volatile storage array, and the second storage array is a volatile storage array.

3. The semiconductor structure according to claim 1 or 2, wherein: The first chip and the third chip are located on the same side of the second chip, and the first chip and the third chip are arranged in sequence along a second direction perpendicular to the first direction.

4. The semiconductor structure according to claim 3, wherein: The second peripheral circuit is located between the first peripheral circuit and the third chip.

5. The semiconductor structure according to claim 3, wherein: The second chip also includes a wiring layer, which is located on a side of the first storage array facing the first chip and the third chip. The first chip and the third chip are respectively bonded to the wiring layer so that the first peripheral circuit is connected to the first storage array through the wiring layer, and the second peripheral circuit is connected to the second storage array through the wiring layer.

6. The semiconductor structure according to claim 3, wherein: On a plane perpendicular to the first direction, projections of the first chip and the third chip fall within the projection of the second chip.

7. The semiconductor structure according to claim 1 or 2, wherein: The second chip and the third chip are located on the same side of the first chip, and the second chip and the third chip are arranged in sequence along a second direction perpendicular to the first direction.

8. The semiconductor structure according to claim 7, wherein: On a plane perpendicular to the first direction, a projection of the second chip at least partially overlaps with a projection of the first peripheral circuit, and a projection of the third chip at least partially overlaps with a projection of the second peripheral circuit.

9. The semiconductor structure according to claim 8, wherein: The second chip and the third chip are bonded to the first chip respectively.

10. The semiconductor structure according to claim 7, wherein: On a plane perpendicular to the first direction, projections of the second chip and the third chip fall within the projection of the first chip.

11. A storage device, characterized in that: It comprises a plurality of semiconductor structures according to any one of claims 1 to 10, wherein the plurality of semiconductor structures are stacked in sequence along a first direction, and the first chips of two adjacent semiconductor structures are connected to each other.

12. The storage device according to claim 11, wherein: Two adjacent semiconductor structures are staggered in sequence along a second direction perpendicular to the first direction to expose a portion of the first chip in one of the semiconductor structures, and the first chips of two adjacent semiconductor structures are connected via a first wire.

13. The storage device according to claim 11, wherein: The storage device also includes: Package substrate; A plastic package is used to package the plurality of semiconductor structures on the packaging substrate, and the first chip of the semiconductor structure closest to the packaging substrate is connected to the packaging substrate via a second wire.

14. A storage system, characterized in that: The invention comprises a controller and the storage device according to any one of claims 11 to 13, wherein the controller is coupled to the storage device and is used to control the storage device to store data.

15. A method for preparing a semiconductor structure, characterized in that: include: forming a first chip including a first peripheral circuit and a second peripheral circuit connected to each other; forming a second chip including the first memory array; forming a third chip including a second memory array; as well as The first chip, the second chip and the third chip are bonded together so that the first peripheral circuit is connected to the first storage array, and the second peripheral circuit is connected to the second storage array.

16. The method for preparing a semiconductor structure according to claim 15, wherein: Forming a second chip including a first memory array includes: forming a first memory array; and A wiring layer is formed along a first direction and on one side of the first memory array.

17. The method for preparing a semiconductor structure according to claim 16, wherein: The wiring layer has a first area and a second area on a side away from the first storage array, and the first area and the second area are sequentially distributed along a second direction perpendicular to the first direction; The step of bonding the first chip, the second chip and the third chip comprises: bonding the first chip to the first region of the wiring layer; and The second chip is bonded to the second region of the wiring layer.

18. The method for preparing a semiconductor structure according to claim 15, wherein: Bonding the first chip, the second chip, and the third chip comprises: bonding the second chip to the first peripheral circuit of the first chip; and The third chip is bonded to the second peripheral circuit of the first chip.

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