Preparation method of low-temperature-coefficient polycrystalline silicon resistor compatible with polycrystalline silicon emitter technology

Abstract

The invention relates to a method for preparing a low-temperature-coefficient polycrystalline silicon resistor compatible with a polycrystalline silicon emitter process, which comprises the following steps of: 1, injecting boron ions into an epitaxial base region on an epitaxial wafer (4), and depositing a polycrystalline silicon thin film; 2, depositing a dielectric layer (9) on the polycrystalline silicon thin film, and injecting arsenic impurities into the polycrystalline silicon thin film to form a polycrystalline silicon emitter region (11); 3, injecting phosphorus impurities and boron impurities to form a polycrystalline silicon resistor (13) and a polycrystalline silicon resistor (14); 4, photoetching a polycrystalline silicon layer to form a polycrystalline silicon emitter (12), the polycrystalline silicon resistor (13) and the polycrystalline silicon resistor (14); and 5, depositing a PSG dielectric layer (15), etching corresponding contact hole deposition metal, and etching to form a metal lead (16). According to the invention, the process integration of the polycrystalline silicon emitter NPN transistor, the N-type polycrystalline silicon resistor and the P-type polycrystalline silicon resistor with low temperature coefficient is realized, the temperature coefficient of resistivity of the P-type polycrystalline silicon resistor is 3.18 ppm / DEG C within the temperature range of-55 DEG C to 125 DEG C.

Description

Technical Field

[0001] The invention relates to the field of semiconductor integrated circuit technology, in particular to a method for preparing a low temperature coefficient polysilicon resistor compatible with a polysilicon emitter technology. Background Art

[0002] The polysilicon emitter junction has pseudo-heterojunction characteristics, which can obtain high injection efficiency and current gain. Its transistors have the characteristics of high characteristic frequency and high punch-through voltage. The polysilicon emitter process has become an important integrated process technology for the preparation of high-speed and high-precision analog integrated circuits. Compared with diffused resistors, polysilicon resistors have the advantages of high precision, low temperature coefficient, small area and small parasitic capacitance. With the development of analog integrated circuits, especially the performance improvement of high-precision operational amplifiers, it is necessary to realize polysilicon emitters, low temperature coefficient polysilicon resistors, and N-type polysilicon resistors in the same process.

[0003] After searching existing patents, the Chinese patent "Study on the Stability of Amplification Factor of Polysilicon Emitter Transistor" directly injects polysilicon after deposition and anneals the emitter area, which is only applicable to the preparation of polysilicon emitter junctions. On the one hand, there is no protective layer on the surface of polysilicon, and the doped ions on the surface of polysilicon diffuse outward and are lost during the annealing process, resulting in poor resistance uniformity. On the other hand, the annealing conditions of the emitter area are set according to the characteristics of the transistor, and the thermal process required for the subsequent annealing of polysilicon resistors is not considered, which is not compatible with the preparation of polysilicon resistors with low temperature coefficients. In addition, there is no other dielectric layer in front of the contact hole to further protect the polysilicon, the film stress is not eliminated, and the temperature coefficient of polysilicon resistance cannot be reduced. Summary of the invention

[0004] The purpose of the present invention is to solve the defects existing in the prior art and to provide a method for preparing a low temperature coefficient polysilicon resistor that is compatible with a polysilicon emitter process. In the case of a step-free process for preparing only one layer of polysilicon, while realizing the polysilicon emitter process, a P-type low temperature coefficient polysilicon resistor and an N-type polysilicon resistor can be formed simultaneously.

[0005] The technical solution adopted by the present invention is as follows: A method for preparing a low temperature coefficient polysilicon resistor compatible with a polysilicon emitter process, comprising forming an epitaxial wafer having a P+ isolation region, an N-type buried layer, an N-type epitaxial layer, and an N-type deep phosphorus region on a P-type substrate, characterized in that it comprises the following steps: 1) Perform base oxidation on the epitaxial wafers of the P+ isolation region, N-type epitaxial layer, and N-type deep phosphorus region to grow a silicon dioxide oxide layer; 2) In the epitaxial base region between the P+ isolation region and the N-type deep phosphorus region, the pattern of the P-type base region to be injected is formed by photolithography, and impurity boron ions are injected into the epitaxial base region pattern area (boron ions are injected through the oxide layer 6), with an energy of 90KeV and a dose of 4E14 / cm 2 , then debonding, and then annealing (debonding is required before annealing), the annealing process conditions are 1150℃, 90 minutes, N2 is introduced, and the N2 flow rate is 15L / min to form a P-type base region; 3) Use photolithography to form the emitter region pattern corresponding to the P-type base region, and perform etching and corrosion on the emitter region, and then remove the resist to form a gap; 4) Using LPCVD process, 4000A polysilicon film is deposited in the silicon dioxide layer and the gap; 5) Continue to use the LPCVD process to deposit a tetraethoxysilane dielectric layer with a thickness of 300A~500A on the polysilicon film, and then perform RTA rapid thermal annealing at 1080°C, with oxygen introduced, for 100 seconds; 6) Apply photoresist on the dielectric layer, use photolithography to form the pattern of the emitter area to be injected, and inject arsenic impurities into the emitter area of ​​the polysilicon film through the TEOS dielectric layer through the emitter area pattern, with an energy of 90KeV and a dose of 5E14 / cm 2 , followed by degumming; 7) Perform emitter annealing to form a polysilicon emitter region. The annealing process conditions are 1150°C, 90 minutes in N2; 8) Photolithography phosphorus impurity windows are formed on the photoresist layer, and phosphorus impurities are injected into the polysilicon layer to form low-value N-type polysilicon resistors. The phosphorus impurity injection dose is 2.0E16 / cm 2 , energy 100 KeV; 9) Photolithography of boron impurity windows on the photoresist layer, implantation of boron impurities to form low temperature coefficient P-type polysilicon resistors in the polysilicon layer, implantation of impurity dose 2.0E15 / cm 2 , energy 80 KeV; 10) Photolithography and etching of the polysilicon layer pattern to form a polysilicon emitter, an N-type polysilicon resistor (13), and a P-type polysilicon resistor with a low temperature coefficient; 11) Deposit a 6000A PSG dielectric layer on the oxide layer, the polysilicon emitter, the N-type polysilicon resistor, and the low temperature coefficient P-type polysilicon resistor, and anneal at 800°C with nitrogen N2 for 30 minutes. 12) Finally, corresponding contact holes are etched on the surface of the PSG dielectric layer, metal is deposited in the contact holes, and metal leads are formed by etching.

[0006] The technical solution of the present invention not only meets the characteristic requirements of polysilicon emitter NPN transistor, but also integrates N-type polysilicon resistor and P-type low temperature coefficient polysilicon resistor. The polysilicon layer undergoes a high temperature annealing process in the emitter region, the grains become larger, the grain boundaries are reduced, and the injection dose of the P-type low temperature coefficient polysilicon resistor is reduced. TEOS is deposited on the polysilicon layer and densified to prevent the impurity ions on the surface and edge of the polysilicon from diffusing outward and losing, thereby improving the consistency of the polysilicon resistor. By controlling the injection dose of impurities, and finally depositing a thick PSG dielectric layer and nitrogen densification, the polysilicon resistor is protected and stress matched. The P-type resistor is formed by photolithography and injection, which has a positive temperature coefficient. The nitrogen low-temperature densification process after the PSG dielectric layer allows the central P-type region to diffuse to the surroundings to form a low-concentration P-region with a negative temperature coefficient. The diffused P-region (negative TCR) of a certain width is reserved by photolithography and etching to parallel the central P-type (positive TCR) polysilicon resistor. Thus, a low temperature coefficient is obtained within the temperature range of -55℃~+125℃. In addition, this patent only deposits one layer of polysilicon, avoiding the steps caused by two layers of polysilicon, and does not require a planarization process, making the processing simpler. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic diagram of step 1 of the preparation method of the present invention; Figure 2 It is a schematic diagram of step 2 of the preparation method of the present invention; Figure 3 It is a schematic diagram of step 3 of the preparation method of the present invention; Figure 4 is a schematic diagram of step 4 of the preparation method of the present invention; Figure 5 is a schematic diagram of step 5 of the preparation method of the present invention; Figure 6 is a schematic diagram of step 6 of the preparation method of the present invention; Figure 7 is a schematic diagram of step 7 of the preparation method of the present invention; Figure 8 is a schematic diagram of step 8 of the preparation method of the present invention; Fig. 9 is a schematic diagram of step 9 of the preparation method of the present invention; Fig.10 is a schematic diagram of step 10 of the preparation method of the present invention; Fig.11 is a schematic diagram of step 11 of the preparation method of the present invention; Fig.12 is a schematic diagram of step 12 of the preparation method of the present invention; In the figure, 1 is the P-type silicon substrate; 2 is the P+ isolation; 3 is the N+ buried layer; 4 is the N-type epitaxy; 5 is the N+ deep phosphorus region; 6 is the oxide layer; 7 is the P-type base region; 8 is the polysilicon thin layer; 9 is the TEOS (tetraethoxysilane) dielectric layer; 10 is the photoresist; 11 is the N-type emitter region; 12 is the N-type polysilicon emitter; 13 is the N-type polysilicon resistor; 14 is the P-type polysilicon resistor with a low temperature coefficient; 15 is the PSG phosphorus silicon glass dielectric layer; and 16 is the metal lead. DETAILED DESCRIPTION

[0008] The present invention provides a method for preparing a low temperature coefficient polysilicon resistor compatible with a polysilicon emitter process, comprising the following steps: like Figure 1 As shown, on the basis of an epitaxial wafer having a P+ isolation region 2, an N-type buried layer 3, an N-type epitaxial layer 4, and an N-type deep phosphorus region 5 formed on a P-type substrate 1 (belonging to the prior art), base oxidation is performed on the epitaxial wafer having the P+ isolation region 2, the N-type epitaxial layer 4, and the N-type deep phosphorus region 5, and a silicon dioxide oxide layer 6 is grown; like Figure 2 As shown, in the base region epitaxially extended between the P+ isolation region 2 and the N-type deep phosphorus region 5, a pattern of the P-type base region 7 to be injected is formed by photolithography, and impurity boron ions are injected into the epitaxial base region pattern area (boron ions are injected through the oxide layer 6), with an energy of 90KeV and a dose of 4E14 / cm 2 Then, the resist is removed and the base region is annealed (overall annealing). The annealing process conditions are 1150°C for 90 minutes, and N2 is introduced at a flow rate of 15L / min to form a P-type base region 7; like Figure 3 As shown, a photolithography process is used to form an emitter region pattern corresponding to the P-type base region, and the emitter region is etched and corroded, and then the resin is removed to form a gap 6a to ensure that there is no residual silicon dioxide in the emitter region.

[0009] like Figure 4 As shown, a polysilicon film 8 with a thickness of 4000A is deposited in the silicon dioxide layer and the gap by using the LPCVD process; like Figure 5 As shown, the LPCVD process is continued to be used to deposit a TEOS (tetraethoxysilane) dielectric layer 9 with a thickness of 300A to 500A on the polysilicon film 8, and then RTA rapid thermal annealing is performed at 1080°C, oxygen, and 100 seconds; like Figure 6 As shown, a photoresist 10 is coated on the dielectric layer 9, and a pattern of the emitter region to be injected is formed by a photolithography process. Through the emitter region pattern, arsenic impurities are injected into the emitter region of the polysilicon film through the TEOS dielectric layer at an energy of 90 KeV and a dose of 5E14 / cm 2 , followed by degumming; like Figure 7 As shown, an emitter region annealing (overall annealing) is performed to form a polysilicon emitter region 11, and the annealing process conditions are 1150° C., 90 minutes N2; like Figure 8 As shown, a phosphorus impurity window is photolithographically formed on the photoresist layer 10, and phosphorus impurities are implanted to form a low-value N-type polysilicon resistor 13 in the polysilicon layer 8. The phosphorus impurity implantation dose is 2.0E16 / cm 2 , energy 100 KeV; A boron impurity window is photoetched on the photoresist layer 10, and boron impurities are implanted to form a low temperature coefficient P-type polysilicon resistor 14 in the polysilicon layer 8. The implanted impurity dose is 2.0E15 / cm 2 , energy 80 KeV, such as Fig. 9 As shown; Photolithography and etching of the polysilicon layer 8 pattern (to the oxide layer 6) to form a polysilicon emitter 12, an N-type polysilicon resistor 13, and a low temperature coefficient P-type polysilicon resistor 14, such as Fig.10 As shown; A PSG dielectric layer 15 with a thickness of 6000A is deposited on the oxide layer 6, the polysilicon emitter 12, the N-type polysilicon resistor 13, and the low temperature coefficient P-type polysilicon resistor 14, and annealed at 800°C for 30 minutes in nitrogen N2. Fig.11 As shown; Finally, corresponding contact holes are etched on the surface of the PSG dielectric layer 15, metal is deposited in the contact holes, and metal leads 16 are formed by etching. Fig.12 shown. Implementation Effect

[0010] After processing, testing and verification, an analog integrated circuit manufactured by the method of the present invention has a polysilicon emitter NPN device, an N-type polysilicon resistor, and a low temperature coefficient P-type polysilicon resistor integrated on the chip, and is tested according to the following method: (1) Polysilicon emitter NPN device At FAB room temperature (i.e. 23℃±1℃), use B1500A semiconductor device analyzer or similar instrument to test the amplification factor β and breakdown voltage BVceo, BVcbo, and BVebo of the NPN tube according to its electrode polarity (base B, collector C, emitter E).

[0011] (2) Polysilicon resistor In the temperature range of -55℃~+125℃, the resistivity is tested and the temperature coefficient is calculated. The specific data is shown in the following table. The calculation formula of the temperature coefficient of resistance is: TCR=(R2-R1) / (T2-T1) / R1*1E6.

[0012] (3) Test results The test data of NPN tube, N-type polysilicon resistor, and low temperature coefficient P-type polysilicon resistor are as follows:

[0013] As can be seen from the table above, the method is used to achieve the process integration of polysilicon emitter NPN transistors, N-type polysilicon resistors, and P-type low temperature coefficient polysilicon resistors. This shows that the polysilicon emitter NPN transistor integrated by the method of the present invention has good performance, and the P-type polysilicon resistor has a resistivity temperature coefficient of 3.18 ppm / ℃ in the temperature range of -55℃~+125℃.

Claims

1. A method for preparing a low temperature coefficient polysilicon resistor compatible with a polysilicon emitter process, comprising: forming an epitaxial wafer having a P+ isolation region (2), an N-type buried layer (3), an N-type epitaxial layer (4), and an N-type deep phosphorus region (5) on a P-type substrate (1), characterized in that The following steps are involved: 1) performing base oxidation on the epitaxial wafer of the P+ isolation region (2), the N-type epitaxial layer (4), and the N-type deep phosphorus region (5), and growing a silicon dioxide oxide layer (6); 2) In the epitaxial base region between the P+ isolation region (2) and the N-type deep phosphorus region (5), a pattern of the P-type base region (7) to be injected is formed by photolithography, and impurity boron ions are injected into the epitaxial base region pattern area with an energy of 90 KeV and a dose of 4E14 / cm 2 , followed by stripping and annealing. The annealing process conditions are 1150°C for 90 minutes, with N2 introduced at a flow rate of 15L / min to form a P-type base region (7); 3) Using a photolithography process to form an emitter region pattern corresponding to the P-type base region, and performing etching and corrosion on the emitter region, followed by stripping to form a notch (6a); 4) Using LPCVD process, a 4000A polysilicon film is deposited in the silicon dioxide layer and the gap (8); 5) Continue to use the LPCVD process to deposit a tetraethoxysilane dielectric layer (9) with a thickness of 300 Å to 500 Å on the polysilicon film (8), and then perform RTA rapid thermal annealing at 1080° C. with oxygen introduced for 100 seconds; 6) Coat a photoresist (10) on the dielectric layer (9), use a photolithography process to form a pattern of the emitter region to be injected, and inject arsenic impurities into the emitter region of the polysilicon film through the TEOS dielectric layer through the emitter region pattern, with an energy of 90 KeV and a dose of 5E14 / cm 2 , followed by degumming; 7) Performing emitter annealing to form a polysilicon emitter region (11), the annealing process conditions being 1150° C., N2 for 90 minutes; 8) Photolithography of a phosphorus impurity window on the photoresist layer (10) and implantation of phosphorus impurities to form a low-value N-type polysilicon resistor (13) in the polysilicon layer (8) with a phosphorus impurity implantation dose of 2.0E16 / cm 2 , energy 100 KeV; 9) Photolithography of a boron impurity window on the photoresist layer (10) and implantation of boron impurities to form a low temperature coefficient P-type polysilicon resistor (14) in the polysilicon layer (8) at an implantation impurity dose of 2.0E15 / cm 2 , energy 80 KeV; 10), photolithography and etching of the polysilicon layer (8) to form a polysilicon emitter (12), an N-type polysilicon resistor (13), and a P-type polysilicon resistor with a low temperature coefficient (14); 11) depositing a PSG dielectric layer (15) with a thickness of 6000A on the oxide layer (6) and the polysilicon emitter (12), the N-type polysilicon resistor (13), and the low temperature coefficient P-type polysilicon resistor (14), and annealing the layer at 800°C and introducing nitrogen gas N2 for 30 minutes; 12) Finally, corresponding contact holes are etched on the surface of the PSG dielectric layer (15), metal is deposited in the contact holes, and metal leads (16) are formed by etching.

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