A power device and a method of manufacturing the same

Abstract

The application discloses a power device and a preparation method thereof, and relates to the technical field of semiconductors. The power device comprises a semiconductor substrate, a first buffer layer, a second buffer layer, a third buffer layer, a barrier layer, a passivation layer, a first anode, a dielectric layer, a second anode, a cathode, a protective layer, anode conduction metal, cathode conduction metal and a field plate layer. The application solves the technical problem of large reverse leakage current of the power device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a power device and a preparation method thereof. BACKGROUND

[0002] The semiconductor device is a kind of semiconductor device made by using metal contact semiconductor layer. Compared with the semiconductor diode in the traditional sense, it has the characteristics of extremely short reverse recovery time, therefore, the semiconductor device is widely used in switching power supply, frequency converter, driver and other circuits. Gallium nitride material is the third generation of wide band gap semiconductor material, because it has large band gap, high electron saturation velocity, high breakdown field, high thermal conductivity, corrosion resistance and radiation resistance, etc., it becomes the best material for making short-wave optoelectronic devices and high-voltage high-frequency power devices. In summary, the semiconductor device prepared by using gallium nitride material combines the advantages of the above semiconductor device and gallium nitride material, has the advantages of fast switching speed, high field strength and good thermal performance, and has good development prospect in power rectifier market.

[0003] However, the reverse leakage of the traditional semiconductor device structure is large, and the place with the strongest electric field is concentrated in the anode edge, which leads to uneven distribution of electric field intensity, reduces the electric field intensity of the main schottky junction, reduces the voltage resistance of gallium nitride based (GaN based) semiconductor device, and affects the performance of gallium nitride based semiconductor device. In view of the problem that the reverse leakage of schottky structure is large, although many researches have proposed solutions at present, such as using schottky junction terminal, which can reduce the reverse current. However, it is difficult to manufacture semiconductor devices with low leakage by using COMS compatible process. SUMMARY

[0004] The purpose of the present application is to provide a power device and a preparation method thereof, which solves the technical problem that the reverse leakage of semiconductor device is large and it is difficult to manufacture semiconductor devices with low leakage by using COMS compatible process.

[0005] To solve the above technical problems, the present application is realized by the following technical scheme:

[0006] The present application provides a power device, which comprises:

[0007] A semiconductor substrate, the material of the semiconductor substrate is one of sapphire, silicon carbide, silicon, zinc oxide, lithium aluminate, aluminum nitride or gallium nitride;

[0008] A first buffer layer is arranged on the semiconductor substrate;

[0009] A second buffer layer is arranged on the side of the first buffer layer away from the semiconductor substrate;

[0010] a third buffer layer disposed on a side of the second buffer layer away from the first buffer layer;

[0011] a barrier layer disposed on a side of the third buffer layer away from the second buffer layer;

[0012] a passivation layer disposed on a side of the barrier layer away from the third buffer layer;

[0013] a first anode penetrating the passivation layer and extending into the barrier layer;

[0014] a dielectric layer disposed on a side of the passivation layer away from the barrier layer and between the first anode and the barrier layer;

[0015] a second anode penetrating the dielectric layer, the passivation layer and extending into the barrier layer;

[0016] a cathode disposed on the dielectric layer and penetrating the dielectric layer and the passivation layer;

[0017] a protection layer disposed on the first anode, the second anode, the cathode and the dielectric layer;

[0018] an anode conduction metal disposed on a side of the protection layer away from the dielectric layer, and the anode conduction metal is connected with the first anode and the second anode;

[0019] a cathode conduction metal disposed on a side of the protection layer away from the dielectric layer, and the cathode conduction metal is connected with the cathode;

[0020] a field plate layer disposed on the protection layer, the field plate layer is connected with the anode conduction metal, wherein the anode conduction metal, the cathode conduction metal and the field plate layer are synchronously formed.

[0021] The application also provides a gallium nitride epitaxial layer, comprising:

[0022] a semiconductor substrate, a material of the semiconductor substrate is one of sapphire, silicon carbide, silicon, zinc oxide, lithium aluminate, aluminum nitride or gallium nitride;

[0023] a first buffer layer disposed on the semiconductor substrate;

[0024] a second buffer layer disposed on a side of the first buffer layer away from the semiconductor substrate;

[0025] a third buffer layer disposed on a side of the second buffer layer away from the first buffer layer;

[0026] a barrier layer disposed on a side of the third buffer layer away from the second buffer layer.

[0027] In one embodiment of the present application, the power device further comprises a first anode contact hole, the first anode contact hole penetrating through the passivation layer and extending into the barrier layer, and the first anode is arranged in the first anode contact hole.

[0028] In one embodiment of the present application, the power device further comprises a second anode contact hole, the second anode contact hole penetrating through the dielectric layer, the passivation layer and extending into the barrier layer, and the second anode is arranged in the second anode contact hole.

[0029] In one embodiment of the present application, the first buffer layer is aluminum nitride.

[0030] In one embodiment of the present application, the first anode and the second anode comprise a first metal layer and a second metal layer, wherein the first metal layer is arranged on the side of the dielectric layer away from the passivation layer and extends into the first anode contact hole and the second anode contact hole to cover the dielectric layer at the bottom of the first anode contact hole and the dielectric layer at the bottom of the second anode contact hole, and the second metal layer is arranged on the first metal layer and fills the first anode contact hole and the second anode contact hole.

[0031] In one embodiment of the present application, the power device further comprises a cathode contact hole, the cathode contact hole penetrating through the dielectric layer and the passivation layer, and the cathode is arranged in the cathode contact hole.

[0032] The present application also provides a method for manufacturing a power device, which comprises at least the following steps:

[0033] forming a first buffer layer, a second buffer layer, a third buffer layer and a barrier layer on a substrate in sequence, wherein the material of the substrate is one of sapphire, silicon carbide, silicon, zinc oxide, lithium aluminate, aluminum nitride or gallium nitride;

[0034] forming a passivation layer on the barrier layer;

[0035] forming a first anode contact hole in the passivation layer and the barrier layer, wherein the first anode contact hole penetrates through the passivation layer and extends into the barrier layer;

[0036] forming a dielectric layer on the passivation layer and in the first anode contact hole, and patterning the dielectric layer, the passivation layer and the barrier layer to form a second anode contact hole penetrating through the dielectric layer, the passivation layer and extending into the barrier layer;

[0037] forming a first metal layer of an anode on the dielectric layer and in the second anode contact hole;

[0038] forming a cathode contact hole through the dielectric layer and the passivation layer on the dielectric layer and the first metal layer of the anode and in the cathode contact hole;

[0039] forming a second metal layer of the anode on the dielectric layer and the first metal layer of the anode and in the cathode contact hole, thereby obtaining a first anode and a second anode comprising the first metal layer and the second metal layer and a cathode comprising the second metal layer;

[0040] forming a protective layer on the dielectric layer, the first anode, the second anode and the cathode;

[0041] patterning the protective layer to form a field plate layer connected with the first anode and the second anode.

[0042] In an embodiment of the present application, the second metal layer is formed synchronously with the cathode, and each is a multi-layer metal structure.

[0043] In an embodiment of the present application, the first anode and the second anode are composed of a first number of stacked metal layers, the cathode is composed of a second number of stacked metal layers, and the first number is greater than the second number.

[0044] The present application reduces the lattice mismatch between the substrate and the barrier layer by setting a multi-layer buffer layer between the substrate and the barrier layer, increases the anode area by forming a dielectric layer before forming the first metal layer, greatly reduces the reverse leakage current, and the dielectric layer can be formed simultaneously with the gate dielectric layer of the GaN HEMT (High Electron Mobility Transistor), which is compatible with the CMOS process line; in addition, the anode conduction metal, the cathode conduction metal and the field plate structure are added to expand the depletion region of the gallium nitride-based semiconductor device, optimize the electric field distribution of the gallium nitride-based Schottky barrier diode, and improve the withstand voltage performance of the gallium nitride-based power semiconductor device.

[0045] Of course, implementing any product of the present application does not necessarily need to achieve all the advantages described above at the same time. BRIEF DESCRIPTION OF DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed for the embodiment description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0047] Figure 1-1 A schematic diagram of a gallium nitride epitaxial layer structure of the present application;

[0048] Figure 1-2 For Figure 1-1 Preparation method flow chart of gallium nitride epitaxial layer;

[0049] Figure 2-1 For another gallium nitride epitaxial layer structure diagram of the present application;

[0050] Figure 2-2 For Figure 2-1 Preparation method flow chart of gallium nitride epitaxial layer;

[0051] Figure 3-1 For another gallium nitride epitaxial layer structure diagram of the present application;

[0052] Figure 3-2 For Figure 3-1 Preparation method flow chart of gallium nitride epitaxial layer;

[0053] Figure 4-1 For another gallium nitride epitaxial layer structure diagram of the present application;

[0054] Figure 4-2 For Figure 4-1 Preparation method flow chart of gallium nitride epitaxial layer;

[0055] Figure 5-1 For another gallium nitride epitaxial layer structure diagram of the present application; Figure 1-1

[0056] For Figure 5-2 Preparation method flow chart of semiconductor device; Figure 5-1

[0057] For another gallium nitride epitaxial layer structure diagram of the present application; Figure 6-1 Figure 1-1 For

[0058] Preparation method flow chart of semiconductor device; Figure 6-2 Figure 6-1 For another gallium nitride epitaxial layer structure diagram of the present application;

[0059] Figure 7-1 Figure 2-1 For Preparation method flow chart of semiconductor device;

[0060] Figure 7-2 Figure 7-1 For another gallium nitride epitaxial layer structure diagram of the present application;

[0061] Figure 8-1 For Figure 2-1 Preparation method flow chart of semiconductor device;

[0062] Figure 8-2 For another gallium nitride epitaxial layer structure diagram of the present application;​​Figure 8-1 Flow chart of a method for manufacturing a semiconductor device;

[0063] Figure 9-1 For using Figure 3-1 Structure diagram of a semiconductor device obtained by using a gallium nitride epitaxial layer;

[0064] Figure 9-2 For using Figure 9-1 Flow chart of a method for manufacturing a semiconductor device;

[0065] Figure 10-1 For using Figure 3-1 Structure diagram of another semiconductor device obtained by using a gallium nitride epitaxial layer;

[0066] Figure 10-2 For using Figure 10-1 Flow chart of a method for manufacturing a semiconductor device;

[0067] Figure 11-1 For using Figure 4-1 Structure diagram of a semiconductor device obtained by using a gallium nitride epitaxial layer;

[0068] Figure 11-2 For using Figure 11-1 Flow chart of a method for manufacturing a semiconductor device. DETAILED DESCRIPTION

[0069] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the protection scope of the present application.

[0070] Gallium nitride material has low heat generation rate and high breakdown electric field, and is an important material for developing high-temperature and high-power electronic devices and high-frequency microwave devices. Gallium nitride material can be used to prepare metal field effect transistors (MESFET), heterojunction field effect transistors (HFET), modulation doped field effect transistors (MODFET) and other new devices. The modulation doped AlGaN / GaN structure has high electron mobility (2000 cm2 / v·s), high saturation velocity (1×107 cm / s) and low dielectric constant, and is a preferred material for manufacturing microwave devices. Gallium nitride has a wide band gap (3.4 eV), and is used as a substrate with sapphire, silicon carbide and other materials, which has good heat dissipation performance and is conducive to the operation of the device under high power conditions.

[0071] The gallium nitride epitaxial layer and the semiconductor device provided by the present application can be applied to power semiconductor devices and radio frequency semiconductor devices.

[0072] Referring to Figure 1-1 As shown in the figure, the present application provides a gallium nitride epitaxial layer, which comprises: a semiconductor substrate 1100, a buffer layer 1101, and a barrier layer 1102. The buffer layer 1101 is arranged on the semiconductor substrate 1100, and the barrier layer 1102 is arranged on the side of the buffer layer 1101 away from the semiconductor substrate 1100. The material of the semiconductor substrate 1100 is, for example, one of sapphire, silicon carbide, silicon, zinc oxide, lithium aluminate, aluminum nitride, or gallium nitride, and the material of the buffer layer 1101 can be one or more of aluminum oxide, hafnium oxide, titanium oxide, titanium nitride, aluminum nitride, aluminum gallium nitride, or gallium nitride. When the buffer layer 1101 is a multilayer structure, the lattice constants of different layers gradually change, the lattice constant near the surface of the semiconductor substrate 1100 is closest to the lattice constant of the semiconductor substrate 1100, and the lattice constant of the top layer is closest to the lattice constant of the subsequently formed barrier layer 1102, thereby reducing the lattice defects in the buffer layer caused by the lattice constant of the semiconductor substrate 1100, reducing the interface state on the interface between the buffer layer and the semiconductor substrate 1100, and reducing the interface leakage current on the interface. The material of the barrier layer 1102 can be, for example, one of aluminum gallium nitride or gallium nitride.

[0073] Referring to Figure 1-2 As shown in the figure, the preparation method of the gallium nitride epitaxial layer of the present embodiment comprises at least the following steps:

[0074] In step S1100, an epitaxial growth process is used to grow the buffer layer 1101 on the semiconductor substrate 1100, and in step S1101, an epitaxial growth process is then used to grow the barrier layer 1102 on the buffer layer 1101.

[0075] Referring to Figure 2-1 As shown in the figure, in other embodiments of the present application, a gallium nitride epitaxial layer can further comprise: a semiconductor substrate 1200, a first buffer layer 1201, a second buffer layer 1202, a third buffer layer 1203, and a barrier layer 1204.

[0076] The first buffer layer 1201 is arranged on the semiconductor substrate 1200. The second buffer layer 1202 is arranged on the side of the first buffer layer 1201 away from the semiconductor substrate 1200, and the third buffer layer 1203 is arranged on the side of the second buffer layer 1202 away from the first buffer layer 1201. The barrier layer 1204 is arranged on the side of the third buffer layer 1203 away from the second buffer layer 1202. In the above embodiment, the first buffer layer 1201 may, for example, be an aluminum nitride layer, the thickness of the first buffer layer 1201 may, for example, be 10-300 nm, the second buffer layer 1202 may, for example, be a gallium nitride or aluminum gallium nitride layer, and the third buffer layer 1203 may, for example, be a gallium nitride layer. The materials used in the first buffer layer 1201, the second buffer layer 1202, and the third buffer layer 1203 may, for example, be adaptively selected according to the material of the semiconductor substrate and the material used in the barrier layer.

[0077] Referring to Figure 2-2 The preparation method of the gallium nitride epitaxial layer of the embodiment includes at least the following steps:

[0078] In step S1200, an epitaxial growth process is used to grow the first buffer layer 1201, for example, an aluminum nitride buffer layer, on the semiconductor substrate 1200, for example, a silicon substrate or a silicon carbide substrate. In step S1201, an epitaxial growth process is used to grow the second buffer layer 1202, for example, a gallium nitride buffer layer, on the first buffer layer 1201. In step S1202, an epitaxial growth process is used to grow the third buffer layer 1203, for example, an aluminum gallium nitride buffer layer, on the second buffer layer 1202. In step S1203, an epitaxial growth process is used to grow the aluminum gallium nitride barrier layer 1204 on the third buffer layer 1203.

[0079] Referring to Figure 3-1 In other embodiments of the present application, a gallium nitride epitaxial layer may, for example, include a semiconductor substrate 1300, a first buffer layer 1301, a post-processing layer 1302, a second buffer layer 1303, and a barrier layer 1304.

[0080] The first buffer layer 1301 is arranged on the semiconductor substrate 1300, the post-processing layer 1302 is arranged on the side of the first buffer layer 1301 away from the semiconductor substrate 1300, the second buffer layer 1303 is arranged on the side of the post-processing layer 1302 away from the first buffer layer 1301, and the barrier layer 1304 is arranged on the side of the second buffer layer 1303 away from the post-processing layer 1302. The material of the semiconductor substrate 1300 is, for example, one of sapphire, silicon carbide, silicon, zinc oxide, lithium aluminate, aluminum nitride or gallium nitride. The first buffer layer 1301 can be, for example, an aluminum nitride layer, and the thickness of the first buffer layer 1301 is, for example, 10-300 nm. The post-processing layer 1302 can be, for example, an aluminum oxide (Al2O3) thin layer, and the thickness of the post-processing layer 1302 is 0.5-2 nm. The second buffer layer 1303 can be, for example, a gallium nitride layer or an aluminum gallium nitride layer. The material of the barrier layer 1304 is, for example, a gallium nitride layer or an aluminum gallium nitride layer. The first buffer layer 1301 and the post-processing layer 1302 are grown by PVD in the present application, so that the first buffer layer 1301 with good quality is obtained, and the preparation and application of the subsequent gallium nitride-based semiconductor device are facilitated.

[0081] For reference Figure 3-2 As shown in the drawings, the preparation method of the gallium nitride epitaxial wafer in the embodiment, for example, includes the following steps:

[0082] In step S1301, the material of the semiconductor substrate 1300 is one of sapphire, silicon carbide, silicon, zinc oxide, lithium aluminate, aluminum nitride or gallium nitride, the surface of the semiconductor substrate 1300 is treated by a hydrofluoric acid solution to remove the oxide layer, and then a first buffer layer 1301 such as a single-layer aluminum nitride buffer layer is deposited by a PVD process, for example, with a thickness in the range of 10-50 nm. Specifically, the epitaxial semiconductor substrate 1300 (for example, a Si substrate) is placed on a tray made of SiC, the tray is placed in a PVD sputtering machine, and the machine is transferred to a deposition chamber. After the semiconductor substrate 1300 is placed in the deposition chamber, the chamber is evacuated, and the semiconductor substrate 1300 is heated at the same time. When the base vacuum is less than, for example, 10-5-10-7 Torr, the heating temperature is stabilized at, for example, 400-600°C, the semiconductor substrate 1300 is baked, and the baking time is, for example, 1-10 minutes. After the semiconductor substrate 1300 is baked, Ar, N2 and O2 are introduced, the Ar:N2 flow ratio is, for example, 10:2-1:1, and the O2 flow is, for example, 0-5% of the total flow of Ar and N2. The total gas flow is preferably maintained at, for example, 2-8 mTorr in the PVD deposition chamber. At the same time, the heating temperature of the semiconductor substrate 1300 is set to the deposition temperature, and the preferred deposition temperature range is, for example, 400-600°C. After the reaction gas is introduced and the deposition temperature is stabilized for, for example, 10-60 seconds, the sputtering power is turned on, and the Al target is sputtered. At this time, an O-doped AlN crystal thin film is deposited on the semiconductor substrate 1300. The sputtering power can be set to, for example, 1-10 KW according to the deposition rate requirement, and the sputtering time can be set to, for example, 10 seconds-1000 seconds according to the thickness.

[0083] In step S1302, the post-treatment layer 1302, for example, an Al2O3 layer, is further prepared by an ALD process. The ALD chamber is evacuated to, for example, 0.05-0.5 MPa, the temperature is increased to, for example, 100°C, the precursors are trimethylaluminum and high-purity water, the deposition thickness is, for example, 0.5-2 nm, and the deposition time is, for example, 3-25 minutes.

[0084] In step S1303, the second buffer layer 1303, for example, a gallium nitride buffer layer, is further prepared on the post-treatment layer 1302. The gallium nitride buffer layer can be prepared by a two-step method. In the first step, the temperature is controlled to, for example, 450-600°C, and the pressure is controlled to, for example, 200-500 Torr to grow a gallium nitride nucleation layer. Then, the temperature is increased to 950-1200°C to grow a three-dimensional and two-dimensional gallium nitride cladding layer. The nucleation layer and the subsequent three-dimensional and two-dimensional gallium nitride layers are collectively referred to as the gallium nitride buffer layer.

[0085] In step S1304, the last step of growing the barrier layer 1304, for example, the gallium nitride barrier layer 1304, the temperature can be controlled, for example, at 950-1100℃, the pressure can be controlled, for example, at 70-200 torr, and the gallium nitride barrier layer 1304 is grown on the gallium nitride buffer layer, and the thickness of the gallium nitride barrier layer 1304 is, for example, 50-500 nm.

[0086] After epitaxy, the gallium nitride epitaxial layer is obtained by cooling.

[0087] The control of the temperature and the pressure refers to the control of the temperature and the pressure in the reaction chamber for growing the epitaxial wafer, and specifically refers to the reaction chamber of a metal organic chemical vapor deposition (MOCVD) device. In the implementation, trimethylgallium or triethylgallium is used as the gallium source, high-purity ammonia is used as the nitrogen source, trimethylindium is used as the indium source, trimethylaluminum is used as the aluminum source, silane is used as the silicon source, tetramethylgermanium is used as the germanium source, and dimethylmagnesium is used as the magnesium source.

[0088] Please refer to Figure 4-1 In other embodiments of the present application, the gallium nitride epitaxial layer can further include: a semiconductor substrate 1400, a first buffer layer 1401, a nano buffer layer 1402, a second buffer layer 1403, and a barrier layer 1404.

[0089] The first buffer layer 1401 is disposed on the semiconductor substrate 1400, and the first buffer layer 1401 can be, for example, an aluminum nitride layer, and the thickness of the first buffer layer 1401 is, for example, 10-300 nm. The nano buffer layer 1402 is disposed on the side of the first buffer layer 1401 away from the semiconductor substrate 1400. The second buffer layer 1403 is disposed on the side of the nano buffer layer 1402 away from the first buffer layer 1401, and the second buffer layer 1403 can be, for example, a gallium nitride or aluminum gallium nitride layer. The barrier layer 1400 is disposed on the side of the second buffer layer 1403 away from the nano buffer layer 1402. The nano buffer layer 1402 can be, for example, a gallium nitride nanocrystal or an aluminum gallium nitride nanocrystal.

[0090] Please refer to Figure 4-2As shown, the embodiment also provides a method for preparing a gallium nitride-based epitaxial wafer, which comprises the following steps: in step S1401, growing a first buffer layer 1401 on a semiconductor substrate; in step S1402, preparing a nano buffer layer 1402, such as a gallium nitride nano buffer layer 1402, on the first buffer layer by using a molecular beam epitaxy process, in an ultrahigh vacuum system, placing a substrate and several molecular beam source furnaces, and placing various elements, such as Ga, N and dopants, which constitute a compound, into different spraying furnaces for heating and cracking and ionization in different source furnaces, so that the molecules or atoms are sprayed onto the surface of the heated substrate at a certain thermal motion speed and a certain proportion of beam intensity, and the molecules or atoms interact on the surface and grow into a single crystal thin film. The growth rate of the single crystal thin film is, for example, 0.01-1 µm / h, and the growth temperature is, for example, 500-600°C. In step S1403, further, a second buffer layer 1403, such as a gallium nitride buffer layer, is prepared on the nano buffer layer 1402 by using a PVD process. The gallium nitride buffer layer can also be prepared by the two-step method of the above embodiment. In step S1404, a barrier layer 1404 is further grown on the second buffer layer 1403. After epitaxy, the gallium nitride epitaxial wafer layer is obtained by cooling.

[0091] Referring to Figure 5-1 As shown, the embodiment also provides a gallium nitride epitaxial layer-based semiconductor device, which comprises, for example: a semiconductor substrate 1100, a buffer layer 1101, a barrier layer 1102, a passivation layer 103, an anode 104, a cathode 107, a protective layer 108, a field plate layer 109, anode conduction metal 110 and cathode conduction metal 111.

[0092] Referring to Figure 5-1As shown in the figure, the buffer layer 1101 is arranged on the semiconductor substrate 1100, the barrier layer 1102 is arranged on the side of the buffer layer 1101 away from the semiconductor substrate 1100, and the passivation layer 103 is arranged on the side of the barrier layer 1102 away from the buffer layer 1101. The anode 104 penetrates the passivation layer 1103 and extends into the barrier layer 1102, and the cathode 107 penetrates the passivation layer 1103 and is connected with the barrier layer 1102. The protective layer 108 is arranged on the anode 104 and the cathode 107. The field plate layer 109 is arranged on the protective layer 108, and the field plate layer 109 is located between the anode 104 and the cathode 107. The anode conductive metal 110 is arranged on the field plate layer 109 and communicates with the anode 104, and the cathode conductive metal 111 is arranged on the field plate layer 109 and communicates with the cathode 107. The anode 104 and the cathode 107 can include a multi-layer metal layer structure, which includes but is not limited to a titanium metal layer, a metal aluminum layer, a metal titanium layer, and a metal titanium nitride layer. The protective layer 108 can be, for example, a tetraethyl orthosilicate (PETEOS) oxide layer, the anode conductive metal 110 and the cathode conductive metal 111 can be formed synchronously with the field plate layer 109, and the constituent material is, for example, copper aluminum silicon (AlSiCu). In this embodiment, by arranging the buffer layer 1101, the lattice defects of the barrier layer 1102 caused by the lattice constant of the semiconductor substrate 1100 are reduced, the interface state on the interface between the barrier layer 1102 and the semiconductor substrate 1100 is reduced, and the interface leakage current on the interface is reduced. The anode conductive metal 110, the cathode conductive metal 111, and the field plate layer 109 structure balance the electric field distribution, reduce the electric field strength of the main Schottky junction, and thus improve the voltage resistance of the semiconductor device.

[0093] Please refer to Figure 5-2 As shown in the figure, the present application also provides a preparation method of a semiconductor device, and the specific steps are as follows:

[0094] In step S101, an epitaxial growth process is used to grow, for example, an aluminum gallium nitride barrier layer 1102 on, for example, a silicon substrate or a silicon carbide substrate.

[0095] In step S102, a chemical vapor deposition process is used to deposit, for example, a silicon nitride passivation layer 103 on, for example, the aluminum gallium nitride barrier layer 1102.

[0096] In step S103, the patterned silicon nitride passivation layer 103 and the aluminum gallium nitride barrier layer 1102 are patterned to form the anode 104 and the cathode 107, the anode 104 and the cathode 107 penetrating through the silicon nitride passivation layer 103 and extending into the aluminum gallium nitride barrier layer 1102. More specifically, the step of patterning the silicon nitride passivation layer 103 and the aluminum gallium nitride barrier layer 1102 to obtain the anode 104 is, for example, as follows: applying photoresist on the silicon nitride passivation layer 103, exposing and developing the photoresist to obtain a patterned photoresist layer, and then etching the silicon nitride passivation layer 103 and the aluminum gallium nitride barrier layer 1102 using the patterned photoresist layer as a mask to determine the anode region AZ and the cathode region, and then depositing and patterning the first metal to obtain the first metal layer in the anode region AZ. More specifically, the specific steps of obtaining the first metal layer in the anode region AZ can be as follows: depositing the metal to form the first metal layer using, but not limited to, a magnetron sputtering deposition process, the material of the first metal layer can be one of titanium nitride and titanium, applying photoresist on the first metal layer, then exposing and developing the photoresist to obtain a patterned photoresist layer, and then etching the first metal layer using the patterned photoresist layer as a mask to remove the first metal layer outside the anode region AZ shown in the figure, to obtain the first metal layer in the anode region AZ.

[0097] In step S104, the first metal layer in the anode region AZ and the cathode region are deposited and patterned to obtain the second metal layer and the cathode 107. More specifically, the specific steps of obtaining the anode 104 and the cathode 107 can be as follows: depositing a titanium metal layer, an aluminum metal layer, a titanium metal layer and a titanium nitride metal layer in the passivation layer 103, the first metal layer in the anode region AZ and the cathode region using, but not limited to, an electron beam evaporation metal process, to form the second metal layer, i.e. the second metal layer is a laminated multi-layer metal structure, including but not limited to the titanium metal layer, the aluminum metal layer, the titanium metal layer and the titanium nitride metal layer; and then performing a photoetching and etching process on the second metal layer to form the second metal layer of the anode 104 and the cathode 107. More specifically, the anode 104 includes the first metal layer in the anode region AZ and the second metal layer.

[0098] In step S105, a protective layer 108 is formed on the passivation layer 103 and the anode 104 and the cathode 107, and more specifically, the protective layer 108 is, for example, a PETEOS (Plasma Enhanced Tetraethylorthosilicate) oxide layer, and a specific step of forming the protective layer 108, for example, a PETEOS oxide layer, can be: using tetraethyl orthosilicate as a raw material, a silicon dioxide film, i.e., the protective layer 108, is prepared on the passivation layer 103 and the anode 104 and the cathode 107 by a low-temperature microwave plasma chemical vapor deposition method. Photoresist is coated on the protective layer 108, and then the photoresist is exposed and developed to obtain a patterned photoresist layer, and then the protective layer 108 is etched with the patterned photoresist layer as a mask until the anode 104 and the cathode 107 are exposed, and the residual patterned photoresist layer is removed.

[0099] In steps S106 and S107, a third metal layer is formed on the protective layer 108 and the exposed anode 104 and cathode 107, and the third metal layer is patterned to form a field plate layer 109. An anode conduction metal 110 is formed on the exposed anode 104, and a cathode conduction metal 111 is formed on the exposed cathode 107. More specifically, the steps of forming the anode conduction metal 110, the cathode conduction metal 111, and the field plate layer 109 are as follows: a third metal layer is deposited on the protective layer 108 using, but not limited to, an electron beam evaporation metal process, and the third metal layer material is, for example, AlSiCu. Then, the third metal layer is subjected to a photoetching process (coating, exposure, and development) and an etching process to form the anode conduction metal 110, the cathode conduction metal 111, and the field plate layer 109. The field plate layer 109 is located in the region between the anode conduction metal 110 and the cathode conduction metal 111 and outside the anode region AZ and connected to the anode conduction metal 110.

[0100] Please refer to Figure 5-2 As shown, in summary, the present embodiment provides a preparation method of a semiconductor device, by setting the buffer layer 1101 to reduce the lattice defects of the barrier layer 1102 due to the lattice constant of the semiconductor substrate 1100, reduce the interface state on the interface between the barrier layer 1102 and the semiconductor substrate 1100, and reduce the interface leakage current on the interface. By setting the anode conduction metal 110, the cathode conduction metal 111, and the field plate, the depletion region of the semiconductor device is expanded, the electric field distribution is balanced, the electric field strength of the main Schottky junction is reduced, and thus the voltage resistance of the semiconductor device is improved.

[0101] Please refer to Figure 6-1As shown, the application also provides a semiconductor device based on a gallium nitride epitaxial layer, for example, comprising: a semiconductor substrate 1100, a buffer layer 1101, a barrier layer 1102, a passivation layer 203, a first anode 204, a dielectric layer 205, a second anode 206, a cathode 207, a protective layer 208, a field plate layer 209, anode conduction metal 210 and cathode conduction metal 211. The buffer layer 1101 is disposed on the semiconductor substrate 1100, the barrier layer 1102 is disposed on the side of the buffer layer 1101 away from the semiconductor substrate 1100, and the passivation layer 203 is disposed on the side of the barrier layer 1102 away from the semiconductor substrate 1100. The first anode 204 penetrates the passivation layer 203 and extends into the barrier layer 1102. The dielectric layer 205 is disposed on the side of the passivation layer 203 away from the barrier layer 1102 and between the first anode 204 and the barrier layer 1102. The second anode 206 penetrates the dielectric layer 205, the passivation layer 203 and extends into the barrier layer 1102. The cathode 207 is disposed on the dielectric layer 205 and penetrates the dielectric layer 205 and the passivation layer 203. The protective layer 208 is disposed on the first anode 204, the second anode 206, the cathode 207 and the dielectric layer 205. The field plate layer 209, the anode conduction metal 210 and the cathode conduction metal 211 are disposed on the protective layer 208, the field plate layer 209 is between the anode conduction metal 210 and the cathode conduction metal 211, and the field plate layer 209 is in communication with the anode conduction metal 210. On the basis of the above-mentioned embodiment, in this embodiment, the material of the dielectric layer 205 is, for example, one of silicon nitride, silicon oxide and tetraethyl orthosilicate, the first anode 204 and the second anode 206 are provided with a first metal layer and a second metal layer of a multi-layer structure, the material of the first metal layer can be a titanium metal layer or a titanium nitride metal layer, and the second metal layer can include, but is not limited to, a titanium metal layer, a metal aluminum layer, a metal titanium layer and a metal titanium nitride layer which are sequentially stacked. The cathode 207 includes a second metal layer, the second metal layer of the cathode 207 and the second metal layer of the anode can be synchronously formed and are both multi-layer metal structures. In other words, the first anode 204 and the second anode 206 are composed of a first number of metal layers which are stacked, the cathode 207 is composed of a second number of metal layers which are stacked, and the first number is greater than the second number.

[0102] Please refer to Figure 6-1 As shown, in this embodiment, the buffer layer 1101 is provided to reduce the lattice defects of the barrier layer 1102 caused by the lattice constant of the semiconductor substrate 1100, reduce the interface state on the interface between the barrier layer 1102 and the semiconductor substrate 1100, and reduce the interface leakage current on the interface. By forming the dielectric layer 205 on the passivation layer 203, the anode area is greatly increased, and the reverse leakage current is reduced. In addition, by providing the anode conduction metal 210, the cathode conduction metal 211 and the field plate layer 209 structure, the electric field distribution is balanced, the electric field strength of the main Schottky junction is reduced, and the withstand voltage of the semiconductor device is improved.

[0103] Please refer to Figure 6-2 As shown in the drawings, the present application also provides a preparation method of a semiconductor device, which comprises the following steps:

[0104] In step S201, a buffer layer 1101 and an aluminum gallium nitride barrier layer 1102 are grown on a silicon substrate or a silicon carbide substrate by epitaxial growth process.

[0105] In step S202, a silicon nitride passivation layer 203 is deposited on the aluminum gallium nitride barrier layer 1102 by chemical vapor deposition process, but not limited thereto.

[0106] In steps S203, S204 and S205, the silicon nitride passivation layer 203 and the aluminum gallium nitride barrier layer 1102 are patterned to form a first anode 204, a dielectric layer 205 is formed on the silicon nitride passivation layer 203 and in the first anode 204, and the dielectric layer 205, the silicon nitride passivation layer 203 and the aluminum gallium nitride barrier layer 1102 are patterned to form a second anode 206 penetrating through the dielectric layer 205, the silicon nitride passivation layer 203 and extending into the aluminum gallium nitride barrier layer 1102. More specifically, the material of the dielectric layer 205 is one of silicon nitride, silicon oxide and tetraethyl orthosilicate, and the steps of patterning the dielectric layer 205, the silicon nitride passivation layer 203 and the aluminum gallium nitride barrier layer 1102 to form the second anode 206 penetrating through the dielectric layer 205, the silicon nitride passivation layer 203 and extending into the aluminum gallium nitride barrier layer 1102 include, for example: coating a photoresist on the dielectric layer 205, exposing and developing the photoresist to obtain a patterned photoresist layer, and then etching the dielectric layer 205, the silicon nitride passivation layer 203 and the aluminum gallium nitride barrier layer 1102 with the patterned photoresist layer as a mask to form the second anode 206. A first metal layer is formed on the dielectric layer 205 and in the second anode 206, and the first metal layer is patterned to obtain a first metal layer located in the first anode 204 and the second anode 206. More specifically, the steps of obtaining the first metal layer located in the first anode 204 and the second anode 206 can be: depositing a metal to form the first metal layer in the region of the second anode 206 and on the dielectric layer 205 by, but not limited to, magnetron sputtering process, the material of the first metal layer can be one of titanium nitride and titanium, coating a photoresist on the first metal layer, then exposing and developing the photoresist to obtain a patterned photoresist layer, and then etching the first metal layer with the patterned photoresist layer as a mask to remove the first metal layer outside the first anode 204 and the second anode 206 to obtain the first metal layer located in the first anode 204 and the second anode 206.

[0107] In step S206, the medium layer 205 and the silicon nitride passivation layer 203 are patterned to form the cathode 207 region penetrating through the medium layer 205 and the silicon nitride passivation layer 203. More specifically, the step of patterning the medium layer 205 and the silicon nitride passivation layer 203 to form the cathode 207 region penetrating through the medium layer 205 and the silicon nitride passivation layer 203 can be specifically: coating a photoresist on the medium layer 205, then exposing and developing the photoresist to obtain a patterned photoresist layer, and then etching the medium layer 205 and the silicon nitride passivation layer 203 with the patterned photoresist layer as a mask until the surface of the aluminum gallium nitride barrier layer 1102 is exposed, forming the cathode 207 region, and removing the residual patterned photoresist layer. The second metal layer is formed on the medium layer 205 and the first metal layer located in the first anode 204 and the second anode 206, and in the cathode 207 region, and the second metal layer is patterned to obtain the second metal layer of the anode and the cathode 207. More specifically, the complete anode and the cathode 207 can be obtained by the following steps: sequentially depositing a titanium metal layer, an aluminum metal layer, a titanium metal layer, and a titanium nitride metal layer by, but not limited to, an electron beam evaporation metal process on the medium layer 205, the first metal layer located in the first anode 204 and the second anode 206, and the cathode 207 region to form the second metal layer, i.e., the second metal layer is a stacked multi-layer metal structure including, but not limited to, a titanium metal layer, an aluminum metal layer, a titanium metal layer, and a titanium nitride metal layer, and then performing a photoetching and etching process on the second metal layer to form the second metal layer of the anode and the cathode 207. More specifically, the anode includes the first metal layer and the second metal layer located in the first anode 204 and the second anode 206.

[0108] In step S207, a protective layer 208 is formed on the medium layer 205 and the anode and the cathode 207. More specifically, the protective layer 208 is, for example, a PETEOS (Plasma Enhanced Tetraethylorthosilicate) oxide layer, and the specific steps of forming the protective layer 208, for example, the PETEOS oxide layer, can be: using tetraethyl orthosilicate as a raw material to prepare a silicon dioxide film, i.e., the protective layer 208, on the medium layer 205, the first anode 204, the second anode 206, and the cathode 207 by, for example, a microwave plasma chemical vapor deposition method at low temperature.

[0109] In step 208, the protective layer 208 is patterned to expose the first anode 204, the second anode 206, and the cathode 207, respectively. More specifically, the step of exposing the first anode 204, the second anode 206, and the cathode 207 can be specifically: coating a photoresist on the protective layer 208, then exposing and developing the photoresist to obtain a patterned photoresist layer, and then etching the protective layer 208 with the patterned photoresist layer as a mask until the first anode 204, the second anode 206, and the cathode 207 are exposed, and removing the residual patterned photoresist layer.

[0110] In step S209, a third metal layer is formed on the protection layer 208 and the exposed first anode 204, second anode 206 and cathode 207, and the third metal layer is patterned to form a field plate layer 209, anode conduction metal 210 on the exposed first anode 204 and second anode 206, and cathode conduction metal 211 on the exposed cathode 207. More specifically, the steps of forming the anode conduction metal 210, cathode conduction metal 211 and field plate are as follows: a third metal layer is formed on the protection layer 208 by a process such as but not limited to electron beam evaporation of metal, and the third metal layer material is for example copper aluminum silicon (AlSiCu); then the third metal layer is subjected to photoetching (coating, exposure and development) and etching process to form the anode conduction metal 210, cathode conduction metal 211 and field plate layer 209. The field plate layer 209 is located in the region between the anode conduction metal 210 and the cathode conduction metal 211 and outside the anode region AZ and connected to the anode conduction metal 210.

[0111] Please refer to Figure 7-1As shown, the application also provides a semiconductor device based on a gallium nitride epitaxial layer, which comprises: a semiconductor substrate 1100, a buffer layer 1101, a barrier layer 1102, a passivation layer 303, a first anode contact hole 313, a dielectric layer 305, a second anode contact hole 314, a first anode 304, a second anode 306, a cathode contact hole 315, a cathode 307, a protective layer 308, an anode opening 316, a cathode opening 317, an anode conducting metal 310, a cathode conducting metal 311, a field plate layer 309. The buffer layer 312 is disposed on the semiconductor substrate 1100. The barrier layer 1102 is disposed on the side of the buffer layer 1101 away from the semiconductor substrate 1100. The passivation layer 303 is disposed on the side of the barrier layer 1102 away from the buffer layer 1101. The first anode contact hole 313 penetrates the passivation layer 303 and extends into the barrier layer 1102. The dielectric layer 305 is disposed on the side of the passivation layer 303 away from the barrier layer 1102 and inside the first anode contact hole 313. The second anode contact hole 314 penetrates the dielectric layer 305, the passivation layer 303 and extends into the barrier layer 1102. The first anode 304 and the second anode 306 are disposed inside the first anode contact hole 313 and the second anode contact hole 314, and the first anode 304 and the second anode 306 comprise a first metal layer and a second metal layer, wherein the first metal layer is disposed on the side of the dielectric layer 305 away from the passivation layer 303 and extends into the first anode contact hole 313 and the second anode contact hole 314 to cover the dielectric layer 305 at the bottom of the first anode contact hole 313 and the dielectric layer 305 at the bottom of the second anode contact hole 314, and the second metal layer is disposed on the first metal layer and fills the first anode contact hole 313 and the second anode contact hole 314. The cathode contact hole 315 penetrates the dielectric layer 305 and the passivation layer 303. The cathode 307 is disposed on the dielectric layer 305 and fills the cathode contact hole 315. The protective layer 308 is disposed on the first anode 304, the second anode 306, the cathode 307 and the dielectric layer 305. The anode opening 316 penetrates the protective layer 308 to expose the first anode 304 and the second anode 306. The cathode opening 317 penetrates the protective layer 308 to expose the cathode 307. The anode conducting metal 310 is disposed on the side of the protective layer 308 away from the dielectric layer 305, and the anode conducting metal 310 fills the anode opening 316. The cathode conducting metal 311 is disposed on the side of the protective layer 308 away from the dielectric layer 305, and the cathode conducting metal 311 fills the cathode opening 317. The field plate layer 309 is disposed on the protective layer 308 and in the region between the anode conducting metal 310 and the cathode conducting metal 311 and connected to the anode conducting metal 310, wherein the anode conducting metal 310, the cathode conducting metal 311 and the field plate layer 309 can be formed synchronously, for example, in the same photolithography and etching process.On the basis of the above-mentioned embodiments, the first anode contact hole 313 and the second anode contact hole 314 in the present embodiment are, for example, strip-shaped grooves, the material of the first metal layer contained in the first anode 304 and the second anode 306 can be a titanium metal layer or a titanium nitride metal layer, the second metal layer contained in the first anode 304 and the second anode 306 is a multi-layer structure, which can include, but is not limited to, a titanium metal layer, a metal aluminum layer, a metal titanium layer and a metal titanium nitride layer which are sequentially stacked. The cathode 307 is formed synchronously with the second metal layer, for example, in the same electron beam evaporation process, and is also a multi-layer metal structure. In other words, the first anode 304 and the second anode 306 are composed of a first number of stacked metal layers, the cathode 307 is composed of a second number of stacked metal layers, and the first number is greater than the second number.

[0112] In the present embodiment, the semiconductor device greatly increases the anode area and reduces the reverse leakage current by forming the dielectric layer 305 on the passivation layer 303. In addition, by providing the anode conduction metal 310, the cathode conduction metal 311 and the field plate structure, the electric field distribution is balanced, the electric field strength of the main Schottky junction is reduced, and thus the withstand voltage of the semiconductor device is improved.

[0113] Please refer to Figure 7-2 The present application also provides a manufacturing method of the semiconductor device, which comprises the following steps:

[0114] In step S301, an epitaxial growth process is used to grow, for example, a gallium nitride layer on a silicon substrate or a silicon carbide substrate, and then an epitaxial growth process is used to grow, for example, an aluminum gallium nitride layer on the gallium nitride layer.

[0115] In step S302, a chemical vapor deposition process is used to deposit a silicon nitride passivation layer 303 on the aluminum gallium nitride layer, but is not limited thereto.

[0116] In step S303, the silicon nitride passivation layer 303 and the aluminum gallium nitride layer are patterned to form the first anode contact hole 313, wherein the first anode contact hole 313 penetrates through the silicon nitride passivation layer 303 and extends into the aluminum gallium nitride layer. More specifically, the step of patterning the silicon nitride passivation layer 303 and the aluminum gallium nitride layer to form the first anode contact hole 313 is, for example, that a photoresist is coated on the silicon nitride passivation layer 303, the photoresist is exposed and developed to obtain a patterned photoresist layer, and then the silicon nitride passivation layer 303 and the aluminum gallium nitride layer are etched to form the first anode contact hole 313 with the patterned photoresist layer as a mask, wherein the first anode contact hole 313 is a strip-shaped groove.

[0117] In step S304, a dielectric layer 305 is formed on the silicon nitride passivation layer 303 and in the first anode contact hole 313, and the dielectric layer 305, the silicon nitride passivation layer 303 and the aluminum gallium nitride layer are patterned to form a second anode contact hole 314 penetrating the dielectric layer 305 and the silicon nitride passivation layer 303 and extending into the aluminum gallium nitride layer. More specifically, the material of the dielectric layer 305 is, for example, one of silicon nitride, silicon oxide and tetraethyl orthosilicate, and the step of patterning the dielectric layer 305, the silicon nitride passivation layer 303 and the aluminum gallium nitride layer to form the second anode contact hole 314 penetrating the dielectric layer 305 and the silicon nitride passivation layer 303 and extending into the aluminum gallium nitride layer includes, for example, coating a photoresist on the dielectric layer 305, exposing and developing the photoresist to obtain a patterned photoresist layer, and then etching the dielectric layer 305, the silicon nitride passivation layer 303 and the aluminum gallium nitride layer with the patterned photoresist layer as a mask to form the second anode contact hole 314. The regions where the first anode contact hole 313 and the second anode contact hole 314 are located constitute an anode region AZ, and the first anode 304 and the second anode 306 fill the first anode contact hole 313 and the second anode contact hole 314, respectively.

[0118] In step S305, a first metal layer is formed on the dielectric layer 305 and in the second anode contact hole 314, and the first metal layer is patterned to obtain a first metal layer located in the anode region AZ. More specifically, the specific steps of obtaining the first metal layer located in the anode region AZ can be: depositing a metal to form the first metal layer in the second anode contact hole 314 and on the dielectric layer 305 by, but not limited to, a magnetron sputtering process, the material of the first metal layer can be one of titanium nitride and titanium, coating a photoresist on the first metal layer, then exposing and developing the photoresist to obtain a patterned photoresist layer, and then etching the first metal layer with the patterned photoresist layer as a mask to remove the first metal layer outside the anode region AZ to obtain the first metal layer located in the anode region AZ.

[0119] In step S306, the dielectric layer 305 and the silicon nitride passivation layer 303 are patterned to form a cathode contact hole 315 penetrating the dielectric layer 305 and the silicon nitride passivation layer 303. More specifically, the step of patterning the dielectric layer 305 and the silicon nitride passivation layer 303 to form the cathode contact hole 315 penetrating the dielectric layer 305 and the silicon nitride passivation layer 303 can be: coating a photoresist on the dielectric layer 305, then exposing and developing the photoresist to obtain a patterned photoresist layer, and then etching the dielectric layer 305 and the silicon nitride passivation layer 303 with the patterned photoresist layer as a mask until the surface of the aluminum gallium nitride layer is exposed to form the cathode contact hole 315, and removing the residual patterned photoresist layer.

[0120] In step S307, a second metal layer is formed on the dielectric layer 305 and the first metal layer in the anode region AZ and in the cathode contact hole 315, and the second metal layer is patterned to obtain the second metal layer of the first anode 304 and the second anode 306 and the cathode 307, wherein the cathode 307 fills the cathode contact hole 315. More specifically, the specific steps to obtain the first anode 304, the second anode 306 and the cathode 307 can be: using but not limited to the process of electron beam evaporation metal, a titanium metal layer, a metal aluminum layer, a metal titanium layer and a metal titanium nitride layer are sequentially deposited in the dielectric layer 305, the first metal layer in the anode region AZ and the cathode contact hole 315 to form the second metal layer, that is, the second metal layer is a stacked multi-layer metal structure, including but not limited to a titanium metal layer, a metal aluminum layer, a metal titanium layer and a metal titanium nitride layer, and then the second metal layer is subjected to a photoetching and etching process to form the first anode 304, the second anode 306 and the cathode 307, and more specifically, the first anode 304 and the second anode 306 include the first metal layer and the second metal layer in the anode region AZ.

[0121] In step S308, a protective layer 308 is formed on the dielectric layer 305, the first anode 304, the second anode 306 and the cathode 307.

[0122] In step S309, the protective layer 308 is patterned to form an anode opening 316 and a cathode opening 317 through the protective layer 308 to respectively expose the first anode 304, the second anode 306 and the cathode 307. More specifically, the step of patterning the protective layer 308 to form the anode opening 316 and the cathode opening 317 through the protective layer 308 can be: coating a photoresist on the protective layer 308, then exposing and developing the photoresist to obtain a patterned photoresist layer, and then etching the protective layer 308 with the patterned photoresist layer as a mask until the first anode 304, the second anode 306 and the cathode 307 are exposed to form the anode opening 316 and the cathode opening 317, and the residual patterned photoresist layer is removed.

[0123] In step S310, a third metal layer is formed on the protective layer 308 and in the anode opening 316 and the cathode opening 317, and the third metal layer is patterned to form the field plate layer 309, the anode conductive metal 310 filling the anode opening 316, and the cathode conductive metal 311 filling the cathode opening 317. More specifically, the steps of forming the anode conductive metal 310, the cathode conductive metal 311, and the field plate are as follows: a third metal layer is deposited on the protective layer 308 by a process such as but not limited to electron beam evaporation of metal, and the third metal layer is made of a material such as copper aluminum silicon (AlSiCu), and then the third metal layer is subjected to a photolithography process (coating, exposure, and development) and an etching process to form the anode conductive metal 310, the cathode conductive metal 311, and the field plate. The field plate layer 309 is located in the region between the anode conductive metal 310 and the cathode conductive metal 311 and outside the anode region AZ and connected to the anode conductive metal 310.

[0124] In summary, the present embodiment provides a method for manufacturing a semiconductor device, in which a dielectric layer 305 is formed by depositing a layer of dielectric material on the surface of the silicon nitride passivation layer 303 and in the first anode contact hole 313, thereby increasing the area of the anode and greatly reducing the reverse leakage current. The dielectric layer can be formed simultaneously with the gate dielectric layer of the GaN HEMT and is compatible with the CMOS process line. Furthermore, by providing the anode conductive metal 310, the cathode conductive metal 311, and the field plate layer 309, the depletion region of the semiconductor device is expanded, the electric field distribution is balanced, the electric field strength of the main Schottky junction is reduced, and the voltage resistance of the semiconductor device is improved.

[0125] Referring to Figure 8-1 The present embodiment also provides a semiconductor device based on a gallium nitride epitaxial layer, which includes, for example: a semiconductor substrate 1200, a first buffer layer 1201, a second buffer layer 1202, a third buffer layer 1203, a barrier layer 1204, a passivation layer 503, a first anode contact hole 513, a first anode 504, a dielectric layer 505, a second anode contact hole 514, a second anode 506, a cathode contact hole 515, a cathode 507, a protective layer 508, a field plate layer 509, an anode opening 516, an anode conductive metal 510, a cathode opening 517, and a cathode conductive metal 511.

[0126] Referring to Figure 8-1 The semiconductor device in the present embodiment is based on a gallium nitride epitaxial layer as a substrate, on which the semiconductor device as described in the previous embodiments is manufactured. Figure 2-1 The semiconductor device in the present embodiment is based on a gallium nitride epitaxial layer as a substrate, on which the semiconductor device as described in the previous embodiments is manufactured.

[0127] Referring to Figure 8-2 The present embodiment also provides a method for manufacturing a semiconductor device, which includes the following specific steps:

[0128] In step S501, a gallium nitride epitaxial layer as shown in Figure 2-1 is prepared.

[0129] In steps S502-S510, a semiconductor device is prepared on the gallium nitride epitaxial layer as shown in Figure 2-1 according to steps S302-S310 in Figure 7-2 .

[0130] Referring to Figure 9-1 , the present application further provides a semiconductor device based on a gallium nitride epitaxial layer, which comprises: a semiconductor substrate 1300, a first buffer layer 1301, a post-processing layer 1302, a second buffer layer 1303, a barrier layer 1304, a passivation layer 603, a first anode contact hole 613, a first anode 604, a dielectric layer 605, a second anode contact hole 614, a second anode 606, a cathode contact hole 617, a cathode 607, a protective layer 608, a field plate layer 609, an anode opening 616, anode conducting metal 610, a cathode opening 617 and cathode conducting metal 611.

[0131] Referring to Figure 9-1 , the semiconductor device in the present embodiment is prepared on a gallium nitride epitaxial layer in Figure 3-1 as a substrate, and the semiconductor device as described in the foregoing embodiments is prepared thereon.

[0132] Referring to Figure 9-2 , the present embodiment further provides a preparation method of a semiconductor device, which comprises the following steps:

[0133] In steps S601-S604, a gallium nitride epitaxial layer as shown in Figure 3-1 is prepared on a semiconductor substrate 1300.

[0134] In steps S605-S613, a semiconductor device is prepared on the gallium nitride epitaxial layer as shown in Figure 3-1 according to steps S302-S310 in Figure 7-2 .

[0135] Referring to Figure 10-1 , the present application further provides a semiconductor device based on a gallium nitride epitaxial layer, which comprises: a semiconductor substrate 1300, a first buffer layer 1301, a post-processing layer 1302, a second buffer layer 1303, a barrier layer 1304, a dielectric layer 705, a source 704, a drain 706 and a gate 707.

[0136] Referring to Figure 10-1As shown in the figure, a first buffer layer 1301 is disposed on a semiconductor substrate 1300, a post-processing layer 1302 is disposed on a side of the first buffer layer 1301 away from the semiconductor substrate 1300, a second buffer layer 1303 is disposed on a side of the post-processing layer 1302 away from the first buffer layer 1301, a barrier layer 1304 is disposed on a side of the second buffer layer 1303 away from the post-processing layer 1302, the barrier layer 1304 has a wider band gap than the second buffer layer 1303 and causes a 2D electron gas (2DEG) in the channel. A dielectric layer 705 is disposed on a side of the barrier layer 1304 away from the second buffer layer 1303. A source electrode 704, a drain electrode 706 and a gate electrode 707 are disposed in the dielectric layer 705, the source electrode 704, the drain electrode 706 and the gate electrode 707 are connected with the barrier layer 1304 through the dielectric layer 705 respectively, and a part of the source electrode 704, the drain electrode 706 and the gate electrode 707 protrude from the top of the dielectric layer 705, wherein the gate electrode 707 extends into the barrier layer 1304 and reaches the bottom of the barrier layer 1304, and the gate electrode 707 has a tapered structure with a ratio of upper edge to lower edge of 1:2-1:4.

[0137] Please refer to Figure 10-1 As shown in the figure, on the basis of the above embodiment, in the present embodiment, the source electrode 704 and the drain electrode 706 are composed of a third metal layer, and the third metal layer comprises a first titanium metal layer, an aluminum metal layer, a second titanium metal layer and a titanium nitride layer in sequence. The gate electrode 707 is composed of a fourth metal layer, and the fourth metal layer is a nickel-gold alloy.

[0138] Please refer to Figure 10-2 As shown in the figure, the present embodiment further provides a preparation method of a semiconductor device, and the specific steps are as follows:

[0139] In step 701, on the semiconductor substrate 1300, a gallium nitride epitaxial layer is prepared as Figure 3-1 shown in the figure.

[0140] In step 702, a layer of hafnium oxide (HfO2) can be deposited on the surface of the gallium nitride-based epitaxial wafer by using a plasma-enhanced chemical vapor deposition method to form the dielectric layer 705. For example, the thickness of the hafnium oxide can be 2000 angstroms.

[0141] In step 703, dry etching is performed on the dielectric layer 705 to form a source electrode 704 contact hole and a drain electrode 706 contact hole arranged oppositely.

[0142] In step 704, a first metal is deposited in the contact holes of the source 704 and drain 706, and on the surface of the dielectric layer 705. Specifically, a magnetron sputtering deposition process can be used to sequentially deposit a first titanium metal layer, an aluminum metal layer, a second titanium metal layer, and a titanium nitride layer in the contact holes of the source 704 and drain 706, and on the surface of the dielectric layer 705 to form the first metal layer. The thickness of the first titanium metal layer can be, for example, 200 angstroms, the thickness of the aluminum metal layer can be, for example, 1200 angstroms, the thickness of the second titanium metal layer can be, for example, 200 angstroms, and the thickness of the titanium nitride layer can be, for example, 200 angstroms. The first metal is then photolithographically etched to expose a portion of the surface of the dielectric layer 705. The photolithography process includes resist coating, exposure, and development. Thus, the first metal layer on the contact hole of the source 704 constitutes the source 704 of the device, and the first metal layer on the contact hole of the drain 706 constitutes the drain 706 of the device.

[0143] In step 705, a portion of the exposed dielectric layer 705 and the gallium nitride layer are dry etched to form a gate 707 contact hole. The gate 707 contact hole completely penetrates the dielectric layer 705 and passes through the gallium nitride layer to the bottom of the gallium nitride layer. The gate 707 has a tapered structure with a top-to-bottom ratio of 1:2 to 1:4.

[0144] In step 706, a silicon nitride layer is deposited in the contact hole of the gate 707 using a magnetron sputtering deposition process. The silicon nitride layer is not higher than the contact hole of the gate 707. Then, Ni / Au is deposited as a second metal on the silicon nitride layer and at the outer edge of the contact hole of the gate 707. The Ni / Au metal thickness ratio is 0.01-0.04 μm / 0.08-0.4 μm, thereby forming the gate 707. Therefore, the gate 707 is a composite structure with multiple materials.

[0145] Please see Figure 11-1 As shown, the present invention also provides a semiconductor device based on a gallium nitride epitaxial layer, which includes, for example, a semiconductor substrate 1400, a first buffer layer 1401, a nano-buffer layer 1402, a second buffer layer 1403, a barrier layer 1404, a passivation layer 803, a first anode contact hole 813, a first anode 804, a dielectric layer 805, a second anode contact hole 814, a second anode 806, a cathode contact hole 815, a cathode 807, a protective layer 808, a field plate layer 809, an anode opening 816, an anode conductive metal 810, a cathode opening 817, and a cathode conductive metal 811.

[0146] Please see Figure 11-1 As shown, the semiconductor device in this embodiment is an application Figure 4-1 The gallium nitride epitaxial layer is used as a substrate, and the semiconductor device as described in the previous embodiment is fabricated on it.

[0147] Referring to Figure 11-1 In other embodiments, the nano buffer layer 1402 can also be disposed between the semiconductor substrate 1400 and the buffer layer, between the multi-layer buffer layer, and between the buffer layer and the barrier layer 1404, which provides nucleation points for the growth of the subsequent growth layer and is beneficial to improve the film quality of the subsequent growth layer.

[0148] Referring to Figure 11-2 The application also provides a preparation method of the semiconductor device, comprising the following steps:

[0149] In steps S801-S804, a gallium nitride epitaxial layer is prepared as shown in Figure 4-1 .

[0150] In steps S805-S813, a semiconductor device is prepared on the gallium nitride epitaxial layer as shown in Figure 4-1 according to steps S302-S310 in Figure 7-2 .

[0151] The preferred embodiments of the application disclosed above are only used to illustrate the application. The preferred embodiments do not describe all the details and limit the application to the specific embodiments. Obviously, many modifications and variations can be made according to the content of the present application. The present application is selected and described in detail in order to better explain the principles and practical application of the application, so that the skilled in the art can well understand and utilize the application. The application is limited by the claims and their full scope and equivalents.

Claims

1. A power device, characterized by, It comprises: a semiconductor substrate, the material of the semiconductor substrate is one of sapphire, silicon carbide, silicon, zinc oxide, lithium aluminate, aluminum nitride or gallium nitride; a buffer layer disposed on the semiconductor substrate; a barrier layer disposed on the side of the buffer layer away from the semiconductor substrate; a passivation layer disposed on the side of the barrier layer away from the buffer layer; a first anode penetrating through the passivation layer and extending into the barrier layer; a dielectric layer disposed on the side of the passivation layer away from the barrier layer and in a first anode contact hole penetrating through the passivation layer and extending into the barrier layer between the first anode and the barrier layer, the first anode being disposed in the first anode contact hole; a second anode penetrating through the dielectric layer, the passivation layer and extending into the barrier layer; a cathode disposed on the dielectric layer and penetrating through the dielectric layer and the passivation layer; a protection layer disposed on the first anode, the second anode, the cathode and the dielectric layer; anode conduction metal disposed on the side of the protection layer away from the dielectric layer, and the anode conduction metal is connected with the first anode and the second anode; cathode conduction metal disposed on the side of the protection layer away from the dielectric layer, and the cathode conduction metal is connected with the cathode; a field plate layer disposed on the protection layer, the field plate layer is connected with the anode conduction metal, wherein the anode conduction metal, the cathode conduction metal and the field plate layer are formed synchronously.

2. The power device of claim 1, wherein, The power device further comprises a second anode contact hole penetrating through the dielectric layer, the passivation layer and extending into the barrier layer, and the second anode is disposed in the second anode contact hole.

3. The power device of claim 1, wherein, The buffer layer is one or more of aluminum oxide, hafnium oxide, titanium oxide, titanium nitride, aluminum nitride, aluminum gallium nitride or gallium nitride.

4. The power device of claim 2, wherein, The first anode and the second anode comprise a first metal layer and a second metal layer, wherein the first metal layer is disposed on the side of the dielectric layer away from the passivation layer and extends into the first anode contact hole and the second anode contact hole to cover the dielectric layer at the bottom of the first anode contact hole and the second anode contact hole, and the second metal layer is disposed on the first metal layer and fills the first anode contact hole and the second anode contact hole.

5. The power device of claim 1, wherein, The power device further comprises a cathode contact hole penetrating through the dielectric layer and the passivation layer, and the cathode is disposed in the cathode contact hole.

6. A method of manufacturing a power device, characterized by, It at least comprises the following steps: forming a buffer layer and a barrier layer on a substrate in sequence, the material of the substrate is one of sapphire, silicon carbide, silicon, zinc oxide, lithium aluminate, aluminum nitride or gallium nitride; forming a passivation layer on the barrier layer; forming a first anode contact hole on the passivation layer and the barrier layer, wherein the first anode contact hole penetrates through the passivation layer and extends into the barrier layer; forming a dielectric layer on the passivation layer and in the first anode contact hole, and patterning the dielectric layer, the passivation layer and the barrier layer to form a second anode contact hole through the dielectric layer, the passivation layer and into the barrier layer; forming a first metal layer of an anode on the dielectric layer and in the second anode contact hole; forming a cathode contact hole through the dielectric layer and the passivation layer; forming a second metal layer of an anode on the dielectric layer and the first metal layer of the anode and in the cathode contact hole, thereby obtaining a first anode and a second anode comprising the first metal layer and the second metal layer and a cathode comprising the second metal layer; forming a protective layer on the dielectric layer, the first anode, the second anode and the cathode; patterning the protective layer to form a field plate layer connected to the first anode and the second anode.

7. The method of claim 6, wherein the step of forming the gate electrode is performed by forming a gate electrode layer on the substrate, and patterning the gate electrode layer. The second metal layer is formed synchronously with the cathode and is a multi-layer metal structure respectively.

8. The method for fabricating a power device according to claim 6, characterized in that, The first anode and the second anode are composed of a first number of stacked metal layers, and the cathode is composed of a second number of stacked metal layers, and the first number is greater than the second number. The second metal layer is formed synchronously with the cathode and is a multi-layer metal structure respectively. The first anode and the second anode are composed of a first number of stacked metal layers, and the cathode is composed of a second number of stacked metal layers, and the first number is greater than the second number.

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