Groove Schottky barrier diode and manufacturing method thereof

Abstract

The invention discloses a trench Schottky barrier diode and a manufacturing method, a trench of the diode located in an epitaxial layer is in a step shape formed by a small upper cylindrical opening and a large lower cylindrical opening, conductive polycrystalline silicon is arranged in the trench, a dielectric layer isolates the conductive polycrystalline silicon from the epitaxial layer on the inner wall of the trench, and the dielectric layer is connected with the trench. The thickness of the dielectric layer on the inner wall of the upper cylindrical opening is smaller than that of the dielectric layer on the inner wall of the lower cylindrical opening. According to the trench and the upper cylindrical small opening, the conductive area during forward conduction is increased, and forward conduction voltage drop is reduced; the lower cylindrical opening is large, so that the point discharge effect during reverse bias of the device is avoided; furthermore, the dielectric layer covered on the inner wall of the lower cylindrical opening of the groove is thicker, and the pressure drop borne by the dielectric layer is increased during reverse bias; and the thin dielectric layer on the side wall of the upper cylindrical opening is beneficial to forming depletion pinch-off in the mesa structure epitaxial layer during reverse bias, so that the reverse blocking performance of the device is further improved, the reliability of the device is improved, and the service life of the device is prolonged.

Description

Technical Field

[0001] The invention relates to a semiconductor device, and in particular to a Schottky barrier diode of a discrete semiconductor device and a manufacturing method thereof. Background Art

[0002] As a conversion device from AC to DC, the rectifier device requires unidirectional conduction characteristics, that is, low turn-on voltage and small on-resistance when forward-biased, and high blocking voltage and small reverse leakage when reverse-biased. Schottky barrier diodes have been used in power supply applications as rectifier devices for decades. Due to their advantages of low forward turn-on voltage and fast switching speed, they are very suitable for use in switching power supplies and high-frequency applications.

[0003] Schottky barrier diodes are made using the principle of metal-semiconductor junction formed by the contact between metal and semiconductor. Traditional planar Schottky barrier diode devices are usually composed of a low-doping concentration N-epitaxial layer and a metal layer deposited on the top surface to form a Schottky barrier contact. The work function difference between the metal and N-type single crystal silicon forms a barrier. The height of the barrier determines the characteristics of the Schottky barrier diode. A lower barrier can reduce the forward conduction turn-on voltage, but it will increase the reverse leakage and reduce the reverse blocking voltage; conversely, a higher barrier will increase the forward conduction turn-on voltage, while reducing the reverse leakage and enhancing the reverse blocking ability. However, the traditional planar Schottky barrier diode generally has large reverse leakage and low reverse blocking voltage. In response to the above problems, the trench Schottky barrier diode was invented, which has a low forward conduction turn-on voltage while overcoming the shortcomings of the above-mentioned planar Schottky diode.

[0004] The notable features of the trench Schottky barrier diode are that there are a number of trenches extending into the N-epitaxial layer, an oxide layer covering the surface of the trenches, and a conductive material filled therein. For example, U.S. Pat. No. 5,365,102 discloses a trench Schottky barrier diode, in which the device structure of one embodiment is shown in the attached figure. Figure 1As shown, it is a trench Schottky barrier diode structure commonly used in the prior art. As can be seen from the figure, the silicon wafer used to make the diode is composed of a highly doped N+ substrate 301 and a relatively low-doped N- epitaxial layer 302, a series of trenches 303 are prepared in the N- epitaxial layer 302, and between the trenches 303 is an N-type single crystal silicon mesa structure 304, a silicon dioxide layer 305 is grown on the sidewall of the trench 303, a metal layer 306 covers the upper surface of the entire structure, and contacts the top surface of the single crystal silicon mesa structure 304 to form a Schottky barrier contact; a cathode metal layer 307 is deposited on the bottom surface of the N+ substrate 301. Due to the presence of the composite structure consisting of the groove 303, the silicon dioxide layer 305, and the conductive material 306 in the groove, the electric field distribution of the device changes when it is reverse biased, the electric field strength in the bottom area of ​​the groove reaches a peak, the free carriers in the mesa structure 304 are completely exhausted, and the electric field strength reaching the Schottky barrier is reduced, thereby enhancing the reverse voltage blocking capability of the device and reducing reverse leakage.

[0005] However, there are still some problems with the trench Schottky barrier diode structure in the prior art, the main problems exposed include: 1) when forward conduction occurs, the area occupied by the trench structure cannot conduct current, causing the current to be crowded in the semiconductor of the table, making the forward conduction voltage drop of the trench Schottky diode larger; 2) when reverse biased, the electric field strength in the bottom area of ​​the trench is the largest, the curvature radius of the bottom structure is small, or the thickness of the oxide layer at the bottom of the trench is thin or uneven due to the limitation of the step coverage ability, which can lead to uneven distribution of the electric field strength and excessive local electric field strength, resulting in a decrease in the reverse voltage drop blocking ability of the device, and a decrease in the reliability and life of the device; 3) when reverse biased, it is necessary to achieve complete depletion in the table to obtain reverse leakage and device reliability and life that meet the requirements.

[0006] In summary, the existing trench Schottky barrier diode structure still has certain defects, and its performance needs to be further optimized to improve device reliability and simplify the device manufacturing method to reduce costs. Summary of the invention

[0007] In view of the above-mentioned defects of the prior art, the object of the present invention is to provide a trench Schottky barrier diode and a manufacturing method thereof, so as to improve the above-mentioned deficiencies of the existing trench Schottky barrier diode, while further improving the performance and reliability of the device and optimizing the manufacturing cost.

[0008] To achieve the above object, the present invention adopts the following technical solution.

[0009] The present invention first provides a trench Schottky barrier diode, comprising:

[0010] A semiconductor substrate heavily doped with a first conductivity type;

[0011] A semiconductor epitaxial layer lightly doped with a first conductivity type located on the upper surface of the substrate;

[0012] A series of periodically arranged grooves located in the epitaxial layer, opening at the upper surface of the epitaxial layer and extending into the epitaxial layer; wherein the epitaxial layer between adjacent grooves forms a mesa structure;

[0013] Conductive polysilicon heavily doped with a first conductivity type filled in the trench;

[0014] A first isolation dielectric layer located on the inner wall of the trench and used to isolate the conductive polysilicon from the epitaxial layer;

[0015] A Schottky barrier metal layer covering the upper surface of the epitaxial layer in the mesa structure region;

[0016] an ohmic contact metal layer covering the upper surface of the conductive polysilicon;

[0017] A second isolation dielectric layer formed by extending upward from the first isolation dielectric layer and isolating the Schottky barrier metal layer and the ohmic contact metal layer;

[0018] an anode metal layer covering the upper surface of the Schottky barrier diode;

[0019] and a cathode metal layer located on the lower surface of the substrate, wherein the lower surface of the substrate forms an ohmic contact with the cathode metal layer;

[0020] The groove is composed of two cylindrical openings connected up and down, and the lateral opening size of the upper cylindrical opening is smaller than the lateral opening size of the lower cylindrical opening, and the connection between the two forms a step shape;

[0021] The first isolation dielectric layer is composed of a first upper isolation dielectric layer and a first lower isolation dielectric layer; the first upper isolation dielectric layer is located on the inner wall of the upper columnar opening of the groove, and is used to isolate the epitaxial layer constituting the inner wall of the upper columnar opening from the conductive polysilicon; the first lower isolation dielectric layer is located on the inner wall of the lower columnar opening of the groove, and is used to isolate the epitaxial layer constituting the inner wall of the lower columnar opening from the conductive polysilicon. The thickness of the first upper isolation dielectric layer is less than that of the first lower isolation dielectric layer.

[0022] As a preferred solution, the thickness of the first upper isolation dielectric layer is 0.05 micrometers to 0.15 micrometers, the thickness of the first lower isolation dielectric layer is 0.1 micrometers to 0.6 micrometers, and the difference between the two is greater than or equal to 0.01 micron.

[0023] Furthermore, there is a second conductivity type ion implantation region in the epitaxial layer region at the bottom of the trench.

[0024] The cross sections of the upper cylindrical opening and the lower cylindrical opening of the groove are both circular. The upper small cylindrical opening structure maximizes the Schottky barrier area of ​​the above-mentioned mesa structure; at the same time, in order to improve the tip discharge enhancement that may be formed by the reduction of the upper opening, the lower cylindrical lateral opening of the groove is widened to form a structure with an enlarged curvature radius at the bottom of the groove, thereby avoiding the tip discharge enhancement.

[0025] Furthermore, the lateral opening size of the upper cylindrical opening is 0.1 micron to 0.5 micron; the lateral opening size of the lower cylindrical opening is 0.2 micron to 2 micron, and the difference between the lateral opening size of the lower cylindrical opening and the lateral opening size of the upper cylindrical opening is greater than or equal to 0.1 micron.

[0026] Furthermore, the first upper isolation dielectric layer and the second isolation dielectric layer are grown and formed synchronously, and have the same thickness.

[0027] The Schottky barrier metal layer and the ohmic contact metal layer are formed by alloying the same metal deposited simultaneously.

[0028] Furthermore, the first conductivity type is N-type, and the second conductivity type is P-type.

[0029] The present invention also provides a method for manufacturing the trench Schottky barrier diode, which comprises the following steps.

[0030] S1. Growing a semiconductor epitaxial layer lightly doped with a first conductivity type on a semiconductor substrate heavily doped with a first conductivity type.

[0031] S2. Form a first dielectric layer on the upper surface of the epitaxial layer, perform photolithography on the first dielectric layer, define an upper columnar opening pattern, selectively remove the first dielectric layer not protected by the photoresist, expose the epitaxial layer corresponding to the upper columnar opening pattern, and then remove the photoresist on the first dielectric layer; use the first dielectric layer retained after removing the photoresist as a first dielectric hard mask.

[0032] S3. Using the first dielectric hard mask as protection, the exposed epitaxial layer is selectively etched by dry etching to form an upper columnar opening in the groove in the epitaxial layer. Thus, the mesa structure with a certain width is formed between the upper columnar openings, and the upper surface of the mesa structure is still covered by the first dielectric hard mask.

[0033] S4. Form a second dielectric layer on the entire surface of the structure.

[0034] S5. The second dielectric layer is selectively etched by dry etching to expose the epitaxial layer at the bottom of the upper cylindrical opening, and the second dielectric layer located above the first dielectric layer is also removed synchronously; at this time, the upper surface of the mesa structure is still covered with the first dielectric layer, i.e., the first dielectric hard mask, and the second dielectric layer covering the side wall of the upper cylindrical opening is used as the second dielectric hard mask.

[0035] S6. Using the first dielectric hard mask and the second dielectric hard mask as protection, selectively etch the exposed epitaxial layer using a dry etching method.

[0036] S7. Continue to use the first dielectric hard mask and the second dielectric hard mask as protection, and adopt the xenon difluoride dry etching method to selectively etch the exposed epitaxial layer to form a lower columnar opening of the groove; and make the lower columnar opening larger in lateral size than the upper columnar opening formed in S3.

[0037] S8. Continue to use the first dielectric hard mask and the second dielectric hard mask as protection, and use an ion implantation method to implant second conductive type doping impurities into the exposed epitaxial layer.

[0038] S9. Continue to form an oxide layer on the exposed epitaxial layer with the first dielectric hard mask and the second dielectric hard mask as protection. At this time, the oxide layer formed on the inner wall of the lower columnar opening constitutes a preliminary first lower isolation dielectric layer; at the same time, the thermal process during the formation of the oxide layer promotes the diffusion of the second conductive type doped impurities to form a preliminary ion implantation area.

[0039] S10. Remove the second dielectric layer and the first dielectric layer using a wet etching method.

[0040] S11. An oxide layer is formed on the surface of the entire structure formed after step S10 is completed. The oxide layer formed on the side wall of the upper columnar opening in this step constitutes the first upper isolation dielectric layer. At this time, the final formation of the first lower isolation dielectric layer is also completed. At the same time, the second conductive type doped impurities are further diffused during the thermal process of the oxide layer growth to complete the formation of the ion implantation area.

[0041] S12. Conductive polysilicon is deposited on the surface of the entire structure formed after step S11 is completed; the conductive polysilicon outside the groove is selectively removed by dry etching, and the upper surface of the conductive polysilicon filled in the groove is flush with the upper surface of the epitaxial layer of the mesa structure. Since the oxide layer on the inner wall of the lower columnar opening, i.e., the first lower isolation dielectric layer, is thick, no voids are left inside the conductive polysilicon during the process of polysilicon filling the lower columnar opening.

[0042] S13. Use dry etching or wet etching to selectively remove the oxide layer on the surface of the mesa structure, and retain the oxide layer that extends upward from the first upper isolation dielectric layer and surrounds the upper surface opening of the groove. The retained oxide layer constitutes the second isolation dielectric layer, which is used to isolate the Schottky barrier metal layer and the ohmic contact metal layer to be formed.

[0043] S14. After step S13 is completed, a first metal layer is deposited on the surface of the entire structure. After the alloying process, the first metal layer forms a Schottky barrier contact with the upper surface of the epitaxial layer of the mesa structure, that is, the Schottky barrier metal layer is formed, and forms an ohmic contact with the upper surface of the conductive polysilicon filled in the groove, that is, the ohmic contact metal layer is formed.

[0044] S15. Depositing an anode metal layer on the entire surface of the structure after step S14 is completed.

[0045] S16. Thinning the substrate by grinding and etching the lower surface of the substrate, and then depositing a cathode metal layer on the lower surface of the substrate.

[0046] Furthermore, the lateral opening size of the upper columnar opening formed in step S3 is 0.1 micron to 0.5 micron; the lateral opening size of the lower columnar opening formed in step S7 is 0.2 micron to 2 micron, and the difference between the lateral opening size of the lower columnar opening and the lateral opening size of the upper columnar opening is greater than or equal to 0.1 micron.

[0047] Furthermore, the final thickness of the first lower isolation dielectric layer formed in step S11 is 0.1 micrometer to 0.6 micrometer.

[0048] Further, the thickness of the first lower isolation dielectric layer formed in step S11 is 0.05 micrometers to 0.15 micrometers, and the difference between the final thickness of the first lower isolation dielectric layer formed in step S11 and the thickness of the first lower isolation dielectric layer formed in step S11 is greater than or equal to 0.01 micrometers.

[0049] Furthermore, the upper cylindrical opening formed in S3 and the lower cylindrical opening formed in S7 are both cylindrical openings.

[0050] The beneficial effects of the present invention are as follows.

[0051] Due to the application of the above technical solution, the present invention has the following advantages and effects compared with the prior art:

[0052] 1). The periodically arranged grooves present a stepped structure design with a small upper opening and a large lower opening. The lateral size of the upper cylindrical opening of the groove is small, which reduces the chip area occupied by the non-conductive structure, increases the conductive semiconductor area during forward conduction, reduces the current density during forward conduction, reduces the forward conduction voltage drop, and also reduces the junction temperature during forward conduction, thereby improving the forward conduction performance, device reliability and life of the device.

[0053] 2) The upper cylindrical opening of the groove has a small lateral dimension, while the lower cylindrical opening has a large lateral dimension, which avoids the tip discharge effect that may be deteriorated by the small curvature radius of the groove bottom when the device is reverse biased, thereby improving the reverse blocking performance, device reliability and life of the device.

[0054] 3). The isolation dielectric layer covering the inner wall of the lower cylindrical opening of the trench is relatively thick. When reverse biased, the voltage drop borne by this part of the dielectric layer increases, thereby improving the reverse blocking capability of the device.

[0055] 4) The isolation dielectric layer covering the sidewalls of the upper cylindrical opening of the trench is relatively thin, which is conducive to the formation of depletion pinch-off in the epitaxial layer of the mesa structure when reverse biased, thereby improving the reverse blocking performance, device reliability and life of the device.

[0056] 5). A second conductive type injection region is set in the epitaxial layer at the bottom of the trench, and the first conductive type doping concentration in the local area is reduced through compensation, which helps to broaden the electric field strength distribution in the bottom epitaxial layer when the device is reverse biased, and reduce the electric field strength in the local area, thereby improving the reverse blocking performance of the device, device reliability and life. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 It is a trench Schottky barrier diode disclosed in US Pat. No. 5,365,102 and is also a schematic structural diagram of a trench Schottky barrier diode commonly used in the current prior art.

[0058] in, Figure 1 In the above example, 301 is N. + Substrate, 302 for N － Epitaxial layer, 303 is a trench, 304 is an N-type single crystal silicon mesa structure, 305 is a silicon dioxide layer, 306 is a metal layer, and 307 is a cathode metal layer.

[0059] Figure 2 It is a schematic diagram of a top view structure of a Schottky barrier diode manufactured according to various embodiments of the present invention.

[0060] Figure 3 The Schottky barrier diode of each embodiment of the present invention is Figure 2 Schematic diagram of the cross-sectional structure at position A1-A2.

[0061] Figure 4It is a cross-sectional schematic diagram of the device structure formed after step S4 in embodiment 1 of the present invention is completed.

[0062] Figure 5 It is a cross-sectional schematic diagram of the device structure formed after step S8 in embodiment 1 of the present invention is completed.

[0063] Figure 6 It is a cross-sectional schematic diagram of the device structure formed after step S9 in embodiment 1 of the present invention is completed.

[0064] Figure 7 It is a cross-sectional schematic diagram of the device structure formed after step S11 in embodiment 1 of the present invention is completed.

[0065] Figure 8 It is a cross-sectional schematic diagram of the device structure formed after step S12 in embodiment 1 of the present invention is completed.

[0066] Fig. 9 It is a cross-sectional schematic diagram of the device structure formed after step S14 in embodiment 1 of the present invention is completed.

[0067] in, Figure 2-Figure 8 In the figure: 10 is a cathode metal layer, 20 is a first conductive type heavily doped substrate, 30 is a first conductive type lightly doped epitaxial layer, 30a is a table structure, 31 is a stepped trench, 31a is an upper cylindrical opening, 31b is a lower cylindrical opening, 32 is conductive polysilicon, 33a is a first upper isolation dielectric layer, 34 is a first lower isolation dielectric layer, 33b is a second isolation dielectric layer, 35 is an ion implantation region, 35a is a second conductive type doped impurity, 40 is a functional metal layer, 40a is a Schottky barrier metal layer, 40b is an ohmic contact metal layer, 50 is an anode metal layer; 61 is a first dielectric layer, and 62 is a second dielectric layer. DETAILED DESCRIPTION

[0068] In order to more clearly illustrate the technical solution and purpose of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0069] like Figure 2 A schematic diagram of a top view of a Schottky barrier diode manufactured according to various embodiments of the present invention is shown in FIG. Figure 3 The Schottky barrier diode of each embodiment is Figure 2 Schematic diagram of the cross-sectional structure at the A1-A2 position. Figure 2-3It can be seen that the Schottky barrier diode of the present invention comprises, from bottom to top, a cathode metal layer 10, a semiconductor first conductivity type heavily doped substrate 20, a semiconductor first conductivity type lightly doped epitaxial layer 30, a functional metal layer 40, and an anode metal layer 50 covering the top layer of the entire Schottky barrier diode structure; and further comprises a series of step-shaped grooves 31 located in the epitaxial layer 30, the step-shaped grooves 31 opening on the upper surface of the epitaxial layer 30 and extending into the epitaxial layer 30; Figure 2 , Figure 3 It can be seen that the step-shaped groove in the figure is composed of two upper and lower cylindrical openings connected, and the inner diameter of the upper cylindrical opening 31a (i.e., the lateral opening size) is smaller than the inner diameter of the lower cylindrical opening 31b (i.e., the lateral opening size); the first conductive type heavily doped conductive polysilicon 32 is filled in the groove; the inner wall of the step-shaped groove 31 is covered with an isolation oxide layer as the first isolation dielectric layer, and the first isolation dielectric layer is composed of a first upper isolation dielectric layer 33a covering the inner wall of the upper cylindrical opening and a first lower isolation dielectric layer 34 covering the inner wall of the lower cylindrical opening, and the first isolation dielectric layer is used to isolate the conductive polysilicon 32 and the epitaxial layer constituting the inner wall of the groove; in the epitaxial layer near the bottom of the step-shaped groove 31, a second conductive type ion implantation area 35 is contained. Among them, the epitaxial layer between adjacent grooves forms a mesa structure 30a, and the functional metal layer 40 covering the upper surface of the epitaxial layer of the mesa structure 30a forms a Schottky barrier metal layer 40a in contact with the epitaxial layer; and the functional metal layer 40 covering the upper surface of the conductive polysilicon 32 is an ohmic contact metal layer 40b that forms an ohmic contact with the heavily doped conductive polysilicon; the isolation oxide layer extending upward from the first upper isolation dielectric layer 33a to between the Schottky barrier metal layer 40a and the ohmic contact metal layer 40b constitutes a second isolation dielectric layer 33b for isolating the Schottky barrier metal layer and the ohmic contact metal layer.

[0070] The Schottky barrier diode of the present invention and its specific manufacturing process are described in more detail below through specific embodiments.

[0071] Example 1

[0072] In this embodiment, the heavily doped substrate is an N+ single crystal silicon wafer, the epitaxial layer is a lightly doped N- silicon epitaxial layer grown on the N+ single crystal silicon wafer, the ion implantation region is a P-type ion implantation region, and the silicon oxide layer serves as an isolation oxide layer. The inner diameter (lateral opening size) of the upper cylindrical opening 31a in the step-shaped groove 31 is 0.25 microns, and the inner diameter (lateral opening size) of the lower cylindrical opening 31b is 0.5 microns. The thickness of the first upper isolation dielectric layer 33a covering the inner wall of the upper cylindrical opening is 0.1 microns, and the thickness of the first lower isolation dielectric layer 34 covering the inner wall of the lower cylindrical opening is 0.11 microns.

[0073] The specific process flow for manufacturing the trench Schottky barrier diode of this embodiment is as follows:

[0074] S1. Prepare a semiconductor first conductivity type heavily doped substrate N+ single crystal silicon wafer, and grow a first conductivity type lightly doped epitaxial layer N− silicon epitaxial layer 30 on the substrate 20 .

[0075] S2. A first dielectric layer 61 is formed on the upper surface of the epitaxial layer, and photolithography is performed on the first dielectric layer to define an upper cylindrical opening 31a pattern, and the first dielectric layer not protected by the photoresist is selectively removed to expose the epitaxial layer corresponding to the upper cylindrical opening pattern, and then the photoresist on the first dielectric layer is removed; the first dielectric layer retained after removing the photoresist is used as a first dielectric hard mask.

[0076] S3. With the first dielectric hard mask as protection, the exposed epitaxial layer 30 is selectively etched by dry etching method to form an upper cylindrical opening 31a in the step-shaped groove 31 in the epitaxial layer, so that a mesa structure 30a is formed in the epitaxial layer between the upper cylindrical openings. At this time, the upper surface of the mesa structure 30a is still covered by the first dielectric hard mask.

[0077] S4. After completing step S3, a second dielectric layer 62 is formed on the entire surface of the structure. At this time, a schematic diagram of the cross-section of the structure is obtained as shown in FIG. Figure 4 shown.

[0078] S5. The second dielectric layer 62 is selectively etched by dry etching to expose the epitaxial layer on the bottom surface of the upper cylindrical opening 31a, and the second dielectric layer 62 located on the first dielectric layer 61 is also removed synchronously; at this time, the upper surface of the mesa structure 30a is still covered with the first dielectric layer 61, that is, the first dielectric hard mask, and the second dielectric layer 62 covering the side wall of the upper cylindrical opening 31a is used as the second dielectric hard mask.

[0079] S6. Using the first dielectric hard mask and the second dielectric hard mask as protection, selectively etch the exposed epitaxial layer using a dry etching method.

[0080] S7 . Continue to use the first dielectric hard mask and the second dielectric hard mask as protection, and adopt the xenon difluoride dry etching method to selectively etch the exposed epitaxial layer to form the lower cylindrical opening 31 b of the stepped trench 31 .

[0081] S8. Continue to use the first dielectric hard mask and the second dielectric hard mask as protection, and use the ion implantation method to implant the second conductive type doping impurities 35a into the exposed epitaxial layer, and then obtain a schematic diagram of the cross-section of the structure as shown in FIG. Figure 5 shown.

[0082] S9. Continue to form an oxide layer on the exposed epitaxial layer with the first dielectric hard mask and the second dielectric hard mask as protection. At this time, the oxide layer formed on the inner wall of the lower cylindrical opening 31b constitutes the preliminary first lower isolation dielectric layer 34; at the same time, the thermal process of the oxide layer formation promotes the diffusion of the second conductive type doping impurities to form a preliminary ion implantation area. At this time, the device structure cross-sectional diagram is obtained as shown in FIG. Figure 6 shown.

[0083] S10. Selectively remove the second dielectric layer 62 and the first dielectric layer 61 by wet etching.

[0084] S11. After step S10 is completed, an oxide layer is deposited on the surface of the entire structure. At this time, the oxide layer deposited on the inner wall of the upper cylindrical opening 31a constitutes the first upper isolation dielectric layer 33a; at this time, the final formation of the first lower isolation dielectric layer 34 is also completed synchronously; at the same time, the second conductive type doping impurities 35a are further diffused during the thermal process of the oxide layer deposition to complete the formation of the ion implantation area 35. At this time, the device structure cross-sectional diagram is obtained as shown in FIG. Figure 7 shown.

[0085] S12. After step S11 is completed, conductive polysilicon 32 is deposited on the surface of the entire structure formed; the conductive polysilicon outside the groove is selectively removed by dry etching, and the upper surface of the conductive polysilicon 32 filled in the groove is flush with the upper surface of the epitaxial layer of the mesa structure 30a; since the thickness of the oxide layer on the inner wall of the lower cylindrical opening, i.e., the first lower isolation dielectric layer, is large, no void is left inside the conductive polysilicon during the process of polysilicon filling the lower cylindrical opening. At this time, the cross-sectional schematic diagram of the structure is obtained as shown in FIG. Figure 8 shown.

[0086] S13. Dry etching is used to selectively remove the isolation oxide layer on the surface of the mesa structure 30a, and the oxide layer extending upward from the first isolation dielectric layer and surrounding the upper surface opening of the groove is retained. The retained oxide layer constitutes the second isolation dielectric layer 33b, which is used to isolate the Schottky barrier metal layer and the ohmic contact metal layer to be formed in the subsequent steps.

[0087] S14. After step S13 is completed, a metal layer is deposited on the entire surface of the structure. After the metal layer undergoes an alloying process, the functional metal layer 40 is formed. The portion of the functional metal layer in contact with the upper surface of the epitaxial layer of the mesa structure 30a forms a Schottky barrier contact, i.e., the Schottky barrier metal layer 40a. The portion of the functional metal layer in contact with the upper surface of the conductive polysilicon filled in the trench forms an ohmic contact, i.e., an ohmic contact metal layer 40b. The cross-sectional view of the structure obtained at this time is as follows: Fig. 9 shown.

[0088] S15. After step S13 is completed, an anode metal layer 50 is deposited on the entire surface of the structure.

[0089] S16. The substrate is thinned by grinding and etching the lower surface of the substrate, and then a cathode metal layer 10 is deposited on the lower surface of the substrate. The trench Schottky barrier diode of this embodiment is fabricated. The overall structure of the diode is as follows: Figure 3 Schematic diagram of the middle section.

[0090] Example 2

[0091] The difference from Example 1 is that the inner diameter (lateral opening size) of the upper cylindrical opening 31a in the stepped groove 31 is 0.5 microns, and the inner diameter (lateral opening size) of the lower cylindrical opening 31b is 1.0 microns. The thickness of the first upper isolation dielectric layer 33a covering the inner wall of the upper cylindrical opening is 0.1 microns, and the thickness of the first lower isolation dielectric layer 34 covering the inner wall of the lower cylindrical opening is 0.4 microns.

[0092] Other process steps, parameters, etc. are the same as those in Example 1.

[0093] Example 3

[0094] The difference from Example 1 is that the inner diameter (lateral opening size) of the upper cylindrical opening 31a in the stepped groove 31 is 0.15 microns, and the inner diameter (lateral opening size) of the lower cylindrical opening 31b is 0.25 microns. The thickness of the first upper isolation dielectric layer 33a covering the inner wall of the upper cylindrical opening is 0.05 microns, and the thickness of the first lower isolation dielectric layer 34 covering the inner wall of the lower cylindrical opening is 0.1 microns.

[0095] Other process steps, parameters, etc. are the same as those in Example 1.

[0096] Example 4

[0097] The difference from Example 1 is that the inner diameter (lateral opening size) of the upper cylindrical opening 31a in the stepped groove 31 is 0.5 microns, and the inner diameter (lateral opening size) of the lower cylindrical opening 31b is 2.0 microns. The thickness of the first upper isolation dielectric layer 33a covering the inner wall of the upper cylindrical opening is 0.15 microns, and the thickness of the first lower isolation dielectric layer 34 covering the inner wall of the lower cylindrical opening is 0.6 microns.

[0098] Other process steps, parameters, etc. are the same as those in Example 1.

[0099] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Any technician familiar with the art can make many possible changes and modifications to the technical solution of the present invention by using the above disclosed methods and technical contents without departing from the scope of the technical solution of the present invention, or modify it into an equivalent embodiment of equivalent changes to achieve the above invention effects. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A trench Schottky barrier diode, characterized in that: include: A semiconductor substrate heavily doped with a first conductivity type; A semiconductor epitaxial layer lightly doped with a first conductivity type located on the upper surface of the substrate; A series of periodically arranged grooves located in the epitaxial layer, opening at the upper surface of the epitaxial layer and extending into the epitaxial layer; wherein the epitaxial layer between adjacent grooves forms a mesa structure; Conductive polysilicon heavily doped with a first conductivity type filled in the trench; A first isolation dielectric layer located on the inner wall of the trench and used to isolate the conductive polysilicon from the epitaxial layer; A Schottky barrier metal layer covering the upper surface of the epitaxial layer in the mesa structure region; an ohmic contact metal layer covering the upper surface of the conductive polysilicon; A second isolation dielectric layer formed by extending upward from the first isolation dielectric layer and isolating the Schottky barrier metal layer and the ohmic contact metal layer; an anode metal layer covering the upper surface of the Schottky barrier diode; and a cathode metal layer located on the lower surface of the substrate, wherein the lower surface of the substrate forms an ohmic contact with the cathode metal layer; The groove is composed of two cylindrical openings connected up and down, and the lateral opening size of the upper cylindrical opening is smaller than the lateral opening size of the lower cylindrical opening, and the connection between the two forms a step shape; Among them, the first isolation dielectric layer consists of a first upper isolation dielectric layer and a first lower isolation dielectric layer; the first upper isolation dielectric layer is located on the inner wall of the upper columnar opening of the groove, and is used to isolate the epitaxial layer constituting the inner wall of the upper columnar opening from the conductive polysilicon; the first lower isolation dielectric layer is located on the inner wall of the lower columnar opening of the groove, and is used to isolate the epitaxial layer constituting the inner wall of the lower columnar opening from the conductive polysilicon; and the thickness of the first upper isolation dielectric layer is less than the thickness of the first lower isolation dielectric layer.

2. A trench Schottky barrier diode according to claim 1, characterized in that: The lateral opening size of the upper columnar opening is 0.1 micron to 0.5 micron; the lateral opening size of the lower columnar opening is 0.2 micron to 2 micron, and the difference between the lateral opening size of the lower columnar opening and the lateral opening size of the upper columnar opening is greater than or equal to 0.1 micron.

3. A trench Schottky barrier diode according to claim 2, characterized in that: The thickness of the first upper isolation dielectric layer is 0.05 micrometer to 0.15 micrometer, the thickness of the first lower isolation dielectric layer is 0.1 micrometer to 0.6 micrometer, and the difference between the two is greater than or equal to 0.01 micrometer.

4. A trench Schottky barrier diode according to claim 1, characterized in that: The first upper isolation dielectric layer and the second isolation dielectric layer are grown synchronously and have the same thickness.

5. The trench Schottky barrier diode according to claim 1, characterized in that: A second conductive type ion implantation region is provided in the epitaxial layer region at the bottom of the trench.

6. The trench Schottky barrier diode according to claim 1, characterized in that: The upper cylindrical opening and the lower cylindrical opening of the groove are both cylindrical openings.

7. The trench Schottky barrier diode according to claim 1, characterized in that: The Schottky barrier metal layer and the ohmic contact metal layer are formed by alloying the same metal deposited simultaneously.

8. The method for manufacturing a trench Schottky barrier diode according to any one of claims 1 to 7, characterized in that: The steps include: S1, growing a semiconductor epitaxial layer lightly doped with a first conductivity type on a semiconductor substrate heavily doped with a first conductivity type; S2, forming a first dielectric layer on the upper surface of the epitaxial layer, performing photolithography on the first dielectric layer to define an upper columnar opening pattern, selectively removing the first dielectric layer not protected by the photoresist to expose the epitaxial layer corresponding to the upper columnar opening pattern, and then removing the photoresist on the first dielectric layer; The first dielectric layer retained after removing the photoresist is used as a first dielectric hard mask; S3, using the first dielectric hard mask as protection, selectively etching the exposed epitaxial layer by dry etching to form an upper columnar opening in the trench in the epitaxial layer; the epitaxial layer between the upper columnar openings constitutes the mesa structure, and the upper surface of the mesa structure is still covered by the first dielectric hard mask; S4, forming a second dielectric layer on the entire structure surface; S5, selectively etching the second dielectric layer by dry etching to expose the epitaxial layer on the bottom surface of the upper cylindrical opening, and simultaneously removing the second dielectric layer located on the first dielectric layer; at this time, the upper surface of the mesa structure is still covered with the first dielectric layer, i.e., the first dielectric hard mask, and the second dielectric layer covered by the side wall of the upper cylindrical opening is used as the second dielectric hard mask; S6, using the first dielectric hard mask and the second dielectric hard mask as protection, selectively etching the exposed epitaxial layer by dry etching; S7, continuing to use the first dielectric hard mask and the second dielectric hard mask as protection, selectively etching the exposed epitaxial layer by a xenon difluoride dry etching method to form a lower columnar opening of the trench; and making the lower columnar opening larger in lateral dimension than the upper columnar opening formed in S3; S8, continuing to use the first dielectric hard mask and the second dielectric hard mask as protection, using an ion implantation method to implant second conductive type doping impurities into the exposed epitaxial layer at the bottom of the lower columnar opening; S9, continuing to form an oxide layer on the exposed epitaxial layer with the first dielectric hard mask and the second dielectric hard mask as protection, wherein the oxide layer formed on the inner wall of the lower columnar opening constitutes a preliminary first lower isolation dielectric layer; and simultaneously, the thermal process of oxide layer formation promotes the diffusion of the second conductive type doping impurities to form a preliminary ion implantation region; S10, removing the second dielectric layer and the first dielectric layer by wet etching; S11, forming an oxide layer on the surface of the entire structure formed after step S10 is completed. The oxide layer formed on the sidewall of the upper columnar opening in this step constitutes the first upper isolation dielectric layer; at this time, the final formation of the first lower isolation dielectric layer is also completed; at the same time, the second conductive type doping impurities are further diffused during the thermal process of the oxide layer growth to complete the formation of the ion implantation region; S12, depositing conductive polysilicon on the surface of the entire structure formed after step S11; Then, selectively removing the conductive polysilicon outside the trench by dry etching, and making the upper surface of the conductive polysilicon filled in the trench flush with the upper surface of the epitaxial layer of the mesa structure; S13, selectively removing the oxide layer on the surface of the mesa structure by dry etching or wet etching, and retaining the oxide layer extending upward from the first upper isolation dielectric layer and surrounding the upper surface opening of the trench, wherein the retained oxide layer constitutes the second isolation dielectric layer for isolating the Schottky barrier metal layer and the ohmic contact metal layer to be formed; S14, depositing a first metal layer on the surface of the entire structure after step S13 is completed, and after the alloying process, the first metal layer forms a Schottky barrier contact with the upper surface of the epitaxial layer of the mesa structure, that is, the Schottky barrier metal layer is formed, and forms an ohmic contact with the upper surface of the conductive polysilicon filled in the trench, that is, the ohmic contact metal layer is formed; S15. Depositing an anode metal layer on the entire surface of the structure after step S14 is completed; S16. Thinning the substrate by grinding and etching the lower surface of the substrate, and then depositing a cathode metal layer on the lower surface of the substrate.

9. The method for manufacturing a trench Schottky barrier diode according to claim 8, characterized in that: In each step, the first conductivity type is N type, and the second conductivity type is P type.

10. The method for manufacturing a trench Schottky barrier diode according to claim 8, characterized in that: The lateral opening size of the upper columnar opening formed by S3 is 0.1 micron to 0.5 micron; the lateral opening size of the lower columnar opening formed by S7 is 0.2 micron to 2 micron, and the difference between the lateral opening size of the lower columnar opening and the lateral opening size of the upper columnar opening is greater than or equal to 0.1 micron.

11. The method for manufacturing a trench Schottky barrier diode according to claim 10, characterized in that: The final thickness of the first lower isolation dielectric layer formed in step S11 is 0.1 micrometer to 0.6 micrometer.

12. The method for manufacturing a trench Schottky barrier diode according to claim 11, characterized in that: The thickness of the first lower isolation dielectric layer formed in step S11 is 0.05 micrometers to 0.15 micrometers, and the difference between the final thickness of the first lower isolation dielectric layer formed in step S11 and the thickness of the first lower isolation dielectric layer formed in step S11 is greater than or equal to 0.01 micrometers.

13. The method for manufacturing a trench Schottky barrier diode according to claim 8, characterized in that: The upper cylindrical opening formed in S3 and the lower cylindrical opening formed in S7 are both cylindrical openings.

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