High electron mobility transistor and preparation method thereof

Abstract

The invention provides a preparation method of a high electron mobility transistor, which comprises the following steps of: providing a substrate on which a semiconductor layer is formed, and a source electrode and a drain electrode are formed on the semiconductor layer; forming a passivation layer on the source electrode and the drain electrode; the passivation layer is etched to form a through hole between the source electrode and the drain electrode, and the through hole exposes a region of the semiconductor layer; a photoresist layer is formed on the passivation layer, a first sub-region of the region of the semiconductor layer is covered by the photoresist layer, and a second sub-region of the region of the semiconductor layer is not covered by the photoresist layer; forming a metal layer on the second sub-region to form a gate electrode; and removing the passivation layer. The invention also provides the high electron mobility transistor prepared by the method.

Description

Technical Field

[0001] The present invention relates to a high electron mobility transistor and a preparation method thereof, in particular to an I-type gate high electron mobility transistor and a preparation method thereof. Background Art

[0002] High electron mobility transistors have the advantages of fast switching speed, high electron mobility, high breakdown power and wide bandgap, and can be used in high voltage electronic components or high frequency electronic components. It is currently known that electron beam lithography can be used to prepare high electron mobility transistors with small line width gates.

[0003] Electron beam lithography has been widely used in various graphic structures, which has unique advantages such as high resolution of size, high process reliability, high accuracy of positioning or alignment, and high flexibility of graphic replication. However, electron beam lithography still has great disadvantages, the main ones being long operation time and high cost.

[0004] In view of this, a novel process still needs to be developed to improve the shortcomings of the aforementioned electron beam lithography process. Summary of the invention

[0005] The main purpose of the present invention is to provide a method for preparing a high electron mobility transistor, which can effectively improve the efficiency of component manufacturing and reduce the process cost.

[0006] The preparation method of the high electron mobility transistor provided by the present invention comprises the following steps: providing a substrate, wherein a semiconductor layer is formed on the substrate, and a source and a drain are formed on the semiconductor layer; forming a passivation layer on the source and the drain; etching the passivation layer to form a through hole between the source and the drain, and the through hole exposes an area of ​​the semiconductor layer; forming a photoresist layer on the passivation layer, wherein a first sub-area of ​​the area of ​​the semiconductor layer is covered by the photoresist layer, and a second sub-area of ​​the area of ​​the semiconductor layer is not covered by the photoresist layer; forming a metal layer on the second sub-area to form a gate; and removing the passivation layer.

[0007] In the preparation method of the present invention, the gate region of the device is defined by shielding the passivation layer and matching the photoresist layer to produce a high electron mobility transistor with a small line width gate. In particular, the preparation method of the present invention can improve the shortcomings of the electron beam lithography process, improve the efficiency of device production and reduce the process cost.

[0008] In the preparation method of the present invention, between the steps of forming the passivation layer and the source and drain electrodes and etching the passivation layer, a step of forming an etching photoresist layer on the passivation layer can be further included. By forming the etching photoresist layer, a through hole exposing the semiconductor layer can be defined, and the through hole is located between the source and drain electrodes.

[0009] In the manufacturing method of the present invention, the photoresist layer for etching and the photoresist layer for defining the metal layer deposition area can be formed by using the same photomask.

[0010] In the preparation method of the present invention, in the step of forming a photoresist layer on the passivation layer, a portion of the passivation layer adjacent to the second sub-region of the semiconductor layer (the region not covered by the photoresist layer) is not covered by the photoresist layer. In the preparation method of the present invention, in the step of forming a metal layer and the second sub-region of the semiconductor layer (the region not covered by the photoresist layer), the metal layer is also formed on the portion of the passivation layer not covered by the photoresist layer.

[0011] In the preparation method of the present invention, the gate position can be defined by two-stage exposure and development at different positions in combination with passivation layer shielding. In more detail, the exposure and development process at the first position can form an etching photoresist layer to define a through hole between the source and the drain to expose the semiconductor layer, which is the first lithography process; and the exposure and development process at the second position can form another photoresist layer to define the deposition area of ​​the metal layer, which is the second lithography process. The exposure and development processes at the first position and the second position can be performed using a stepper exposure machine. In addition, the second position is offset toward the source or drain compared to the first position; therefore, during the second lithography process, the first sub-region of the semiconductor layer exposed by the through hole can be covered by the photoresist layer, and the second sub-region of the semiconductor layer exposed by the through hole is not covered by the photoresist layer. Therefore, when the metal layer is formed, the metal layer can be deposited in the second sub-region of the semiconductor layer not covered by the photoresist layer through the shielding of the photoresist layer and the passivation layer formed by the second lithography process to form a gate.

[0012] Furthermore, when the photomask used in the exposure and development process of the first position and the second position is the same photomask, by shifting the second position toward the source or drain compared to the first position, a portion of the passivation layer in the second sub-region (region not covered by the photoresist layer) adjacent to the semiconductor layer is not covered by the photoresist layer, and the subsequently deposited metal layer will also be formed on the portion of the passivation layer not covered by the photoresist layer. When the passivation layer is subsequently removed, the metal layer deposited on the passivation layer will also be removed at the same time, leaving only the gate metal layer located on the semiconductor layer.

[0013] In the preparation method of the present invention, the thickness of the metal layer can be less than the thickness of the passivation layer; therefore, when the subsequently deposited metal layer is simultaneously formed on the portion of the passivation layer not covered by the photoresist layer, the metal layer formed on the portion of the passivation layer and the metal layer serving as the gate will not be connected to each other, and when the passivation layer is subsequently removed, the formed gate will not be affected.

[0014] In one embodiment of the present invention, the difference between the thickness of the metal layer and the thickness of the passivation layer may be between 0.01μm and 0.7μm, for example, between 0.01μm and 0.6μm, 0.01μm and 0.5μm, 0.01μm and 0.3μm, 0.01μm and 0.2μm, 0.01μm and 0.1μm or 0.03μm and 0.1μm.

[0015] In the preparation method of the present invention, the passivation layer can be etched by dry etching or wet etching to form a through hole between the source and the drain. In one embodiment of the present invention, the passivation layer can be etched by inductively coupled plasma (ICP) etching; but the present invention is not limited to this. In one embodiment of the present invention, lateral etching occurs when etching the passivation layer. At this time, the side wall of the through hole and the surface of the exposed semiconductor layer area may have an angle less than 90 degrees, for example, between 40 degrees and 85 degrees, 50 degrees to 85 degrees, 60 degrees to 85 degrees, but the present invention is not limited to this. The angle formed depends on the process or material (for example, the passivation layer material).

[0016] In the preparation method of the present invention, after the step of removing the passivation layer, a step may be further included: forming a protective layer, and the protective layer covers the gate, source, drain and semiconductor layer to prevent moisture from penetrating into the interior of the device.

[0017] The present invention further provides a high electron mobility transistor prepared by the above-mentioned preparation method, comprising: a substrate; a semiconductor layer, arranged on the substrate; a source, arranged on the semiconductor layer; a drain, arranged on the semiconductor layer; and a gate, arranged on the semiconductor layer and located between the source and the drain, wherein the gate has a bottom surface and a top surface opposite to the bottom surface, the bottom surface is the surface of the gate in contact with the semiconductor layer, and the width of the top surface is less than or equal to the width of the bottom surface.

[0018] In the high electron mobility transistor of the present invention, the width of the gate top surface is less than or equal to the width of the bottom surface, preferably the width of the gate top surface is substantially equal to the width of the bottom surface, and the high electron mobility transistor is an I-type gate. In one embodiment of the present invention, the difference between the width of the gate top surface and the width of the bottom surface can be less than or equal to 10nm.

[0019] In the high electron mobility transistor of the present invention, the line width of the gate may be between 0.05 μm and 0.5 μm, for example, between 0.05 μm and 0.4 μm, 0.1 μm and 0.4 μm, 0.1 μm and 0.3 μm. In one embodiment of the present invention, the line width of the gate may be about 0.2 μm. In the present invention, the line width of the gate refers to the gate width measured from the bottom surface of the gate in the cross-sectional view of the high electron mobility transistor.

[0020] The high electron mobility transistor of the present invention may further include: a protective layer covering the gate, source, drain and semiconductor layer. The high electron mobility transistor of the present invention may further include: a buffer layer disposed between the substrate and the semiconductor layer.

[0021] In the present invention, the substrate may be a hard substrate or a soft substrate, and its material may include quartz, glass, wafer, sapphire, resin, epoxy resin, polycarbonate (PC), polyimide (PI), polypropylene (PP), polyethylene terephthalate (PET), polymethylmethacrylate (PMMA), other plastic materials or combinations thereof, but the present invention is not limited thereto.

[0022] In the present invention, the semiconductor layer may include a gallium nitride layer and an aluminum gallium nitride layer. However, the present invention is not limited thereto, and other materials that can be used for high electron mobility transistors are also included in the present invention.

[0023] In the present invention, the etching photoresist layer formed by the first lithography process and the photoresist layer formed by the second lithography process can be positive type or negative type photoresist, respectively.

[0024] In the present invention, the materials of the passivation layer, the protective layer and the buffer layer may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, aluminum oxide, or a combination thereof, and may have a single layer or a multilayer structure. In one embodiment of the present invention, the passivation layer is a silicon nitride layer. In one embodiment of the present invention, the protective layer is a silicon nitride layer. However, the present invention is not limited thereto.

[0025] In the present invention, the materials of the gate (metal layer), source and drain may include indium (In), tin (Sn), aluminum (Al), gold (Au), platinum (Pt), indium (In), zinc (Zn), germanium (Ge), silver (Ag), lead (Pb), palladium (Pd), copper (Cu), gold beryllium (AuBe), germanium beryllium (BeGe), nickel (Ni), lead tin (PbSn), chromium (Cr), gold zinc (AuZn), titanium (Ti), tungsten (W), titanium tungsten (TiW), their alloys or combinations thereof, and may have a single-layer or multi-layer structure respectively.

[0026] In the present invention, the passivation layer, the protective layer, the buffer layer, the photoresist layer, the gate (metal layer), the source and the drain can be prepared by appropriate methods. The appropriate methods include electroplating, chemical plating, chemical vapor deposition, sputtering, coating, yellow light processing or a combination thereof, but the present invention is not limited thereto. The coating method can be, for example, dip coating, spin coating, roller coating, blade coating, spray coating, or a combination thereof, but the present invention is not limited thereto.

[0027] The following detailed description will be given in conjunction with the accompanying drawings to make other objects, advantages, and novel features of the present invention more apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1A to 1H is a cross-sectional schematic diagram of a method for preparing a high electron mobility transistor according to an embodiment of the present invention;

[0029] Figure 2 is a DC characteristic of a high electron mobility transistor according to an embodiment of the present invention;

[0030] Figure 3 is a high frequency characteristic of a high electron mobility transistor according to an embodiment of the present invention;

[0031] Figure 4 This is the load-pull measurement result of a high electron mobility transistor according to an embodiment of the present invention. In the above figures, the meanings of the reference numerals are as follows:

[0032] 11-Substrate;

[0033] 12- buffer layer;

[0034] 13- semiconductor layer;

[0035] 13a-surface;

[0036] 131-gallium nitride layer;

[0037] 132-aluminum gallium nitride layer;

[0038] 14- source;

[0039] 15-Drainage pole;

[0040] 151-through hole;

[0041] 151a-side wall;

[0042] 16- passivation layer;

[0043] 17-photoresist layer for etching;

[0044] 18- photoresist layer;

[0045] 19-metal layer;

[0046] 191-gate;

[0047] 191a - bottom surface;

[0048] 191b - top surface;

[0049] 192-partial;

[0050] 20-protective layer;

[0051] R1-region;

[0052] R11 - first sub-region;

[0053] R12 - second sub-region;

[0054] R2-section;

[0055] T1, T2-thickness;

[0056] W1, W2 – width. DETAILED DESCRIPTION

[0057] The following describes the implementation of the present invention through specific embodiments, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed in various ways according to different viewpoints and applications without departing from the present invention.

[0058] It should be noted that, in this document, unless otherwise specified, "having an element" is not limited to having a single element, but may have one or more elements. Furthermore, the ordinal numbers used in the specification and claims, such as "first" and "second", to modify the elements of the claims, do not themselves imply or represent any previous ordinal numbers of the claimed elements, nor do they represent the order of one claimed element and another claimed element, or the order of the manufacturing method. The use of these ordinals is only used to make a claimed element with a certain name clearly distinguishable from another claimed element with the same name.

[0059] Certain words are used throughout the specification and the claims that follow to refer to specific components. It will be understood by those skilled in the art that electronic equipment manufacturers may refer to the same components by different names. It is not intended herein to distinguish between components that have the same function but different names. In the following specification and claims, the words "comprises", "contains", "has", etc. are open-ended words, and therefore should be interpreted as "including but not limited to..." Therefore, when the terms "comprises", "contains" and / or "has" are used in the description of the present invention, they specify the presence of corresponding features, regions, steps, operations and / or components, but do not exclude the presence of one or more corresponding features, regions, steps, operations and / or components.

[0060] In the text, the terms "about", "approximately", "substantially", and "roughly" generally mean within 10%, within 5%, within 3%, within 2%, within 1%, or within 0.5% of a given value or range. The numbers given here are approximate numbers, that is, in the absence of specific instructions for "about", "approximately", "substantially", and "roughly", the meanings of "about", "approximately", "substantially", and "roughly" can still be implied. In addition, the terms "range is from a first value to a second value", "range is between a first value and a second value" mean that the range includes the first value, the second value, and other values ​​therebetween.

[0061] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with the background or context of the relevant technology and the present invention, and should not be interpreted in an idealized or overly formal manner unless specifically defined herein.

[0062] In addition, relative terms such as "below" or "bottom" and "above" or "top" may be used in the embodiments to describe the relative relationship of one element of the diagram to another element. It is understood that if the device of the diagram is turned upside down, the element described on the "below" side will become the element on the "above" side. When a corresponding component (such as a film layer or area) is referred to as "on another component", it can be directly on the other component, or there can be other components between the two. On the other hand, when a component is referred to as "directly on another component", there is no component between the two. In addition, when a component is referred to as "on another component", the two have an up-and-down relationship in the top-view direction, and this component can be above or below the other component, and this up-and-down relationship depends on the orientation of the device.

[0063] In the present invention, the distance and thickness can be measured by an optical microscope, and the distance and thickness can be measured by a cross-sectional image in an electron microscope, but the present invention is not limited thereto. In addition, any two values ​​or directions used for comparison may have a certain error. If the first value is equal to the second value, it implies that there may be an error of about 10% between the first value and the second value.

[0064] Figures 1A to 1H It is a cross-sectional schematic diagram of a method for preparing a high electron mobility transistor according to an embodiment of the present invention.

[0065] like Figure 1A As shown, first, a substrate 11 is provided, wherein a semiconductor layer 13 is formed on the substrate 11, and a source 14 and a drain 15 are formed on the semiconductor layer 13. In this embodiment, a buffer layer 12 is further disposed between the substrate 11 and the semiconductor layer 13. In addition, the semiconductor layer 13 includes a gallium nitride layer 131 and an aluminum gallium nitride layer 132, wherein the aluminum gallium nitride layer 132 is disposed on the gallium nitride layer 131. Furthermore, the source 14 and the drain 15 are Ti / Al / Ni / Au metal layers, respectively, and the thicknesses of the Ti layer, the Al layer, the Ni layer and the Au layer are 20nm, 120nm, 25nm and 100nm, respectively; however, the present invention is not limited thereto. In this way, the ohmic contact of the device is completed and the active region is defined.

[0066] Next, a passivation layer 16 is formed on the source electrode 14 and the drain electrode 15. Here, a plasma-assisted chemical vapor deposition system (PECVD) can be used to form the passivation layer 16, wherein the passivation layer 16 is a silicon nitride layer and has a thickness between 250 nm and 800 nm. In the present embodiment, the thickness of the passivation layer 16 is about 250 nm.

[0067] like Figure 1B As shown, an etching photoresist layer 17 is formed on the passivation layer 16. Here, a stepper exposure machine can be used to perform a first lithography process to define a gate region.

[0068] like Figure 1C As shown, the passivation layer 16 is etched to form a through hole 151 between the source 14 and the drain 15, and the through hole 151 exposes a region R1 of the semiconductor layer 13. Here, inductively coupled plasma (ICP) dry etching can be used to etch the passivation layer 16 to produce a region R1 where the gate metal can contact the semiconductor layer 13. The sidewall 151a of the through hole 151 and the surface 13a of the region R1 of the semiconductor layer 13 have an angle less than 90 degrees. Then, the etching photoresist layer 17 is removed, as shown in FIG. Figure 1D shown.

[0069] like Figure 1EAs shown, the pattern of the mask is shifted toward the drain 15, and a second lithography process is performed to form a photoresist layer 18 on the passivation layer 16. Here, the etching photoresist layer 17 (such as Figure 1C The photoresist layer 18 formed in the first and second photolithography processes can be formed by using the same photomask. After the second photolithography process, a first sub-region R11 of the region R1 of the semiconductor layer 13 is covered by the photoresist layer 18, while a second sub-region R12 of the region R1 of the semiconductor layer 13 is not covered by the photoresist layer 18. In addition, a portion R2 of the passivation layer 16 adjacent to the second sub-region R12 is not covered by the photoresist layer 18.

[0070] like Figure 1F As shown, a metal layer 19 is formed on the second sub-region R12 to form a gate 191. In addition, another portion 192 of the metal layer 19 is further formed on the portion R2 (eg, Figure 1E In this embodiment, the metal layer 19 is a Ni / Au metal layer, and the thicknesses of the Ni layer and the Au layer are 50 nm and 150 nm respectively; however, the present invention is not limited thereto.

[0071] In this embodiment, a stepper is used to perform the first lithography process and the second lithography process. By shifting the pattern of the mask toward the drain 15 (in other embodiments of the present invention, the pattern of the mask may be shifted toward the source 14), the portion where the second lithography area overlaps the first etched area is the gate 191 area.

[0072] like Figure 1F and Figure 1G As shown, the passivation layer 16 is removed. In the present embodiment, the passivation layer 16 is used as a mask, and the other portion 192 of the metal layer 19 deposited on the passivation layer 16 is removed together with the passivation layer 16 using an HF solution. In addition, the thickness T1 of the metal layer 19 needs to be smaller than the thickness T2 of the passivation layer 16, so that the metal layer 19 can be divided into two unconnected pieces (i.e., the gate 191 and the portion 192) when deposited, so as to facilitate the removal of the other redundant portion 192 of the metal layer 19 on the passivation layer 16. The difference between the thickness T1 of the metal layer 19 and the thickness T2 of the passivation layer 16 can be adjusted according to the needs, for example, it can be between 0.01μm and 0.7μm.

[0073] like Figure 1H As shown, a protective layer 20 is formed, and the protective layer 20 covers the gate 191, the source 14, the drain 15 and the semiconductor layer 13. In this embodiment, silicon nitride with a thickness of 100 nm can be deposited as the protective layer 20 to cover the surfaces of the gate 191, the source 14, the drain 15 and the semiconductor layer 13; however, the present invention is not limited thereto.

[0074] like Figure 1H As shown, after the above-mentioned process, the high electron mobility transistor of the present embodiment can be obtained, including: a substrate 11; a semiconductor layer 13, disposed on the substrate 11; a source 14, disposed on the semiconductor layer 13; a drain 15, disposed on the semiconductor layer 13; and a gate 191, disposed on the semiconductor layer 13 and located between the source 14 and the drain 15. In addition, the high electron mobility transistor of the present embodiment further includes: a protective layer 20, covering the gate 191, the source 14, the drain 15 and the semiconductor layer 13.

[0075] The semiconductor layer 13 includes a gallium nitride layer 131 and an aluminum gallium nitride layer 132, and the aluminum gallium nitride layer 132 is disposed on the gallium nitride layer 131. In addition, the gate 191 has a bottom surface 191a and a top surface 191b opposite to the bottom surface 191a, the bottom surface 191a is the surface where the gate 191 contacts the semiconductor layer 13, and the width W1 of the top surface 191b is less than or equal to the width W2 of the bottom surface 191a, for example, the difference between the width W1 of the top surface 191b and the width W2 of the bottom surface 191a is less than or equal to 10nm. In this embodiment, the width W1 of the top surface 191b is substantially the same as the width W2 of the bottom surface 191a. Furthermore, the line width of the gate 191 may be between 0.05μm and 0.5μm; wherein the line width of the gate 191 is the width W2 of the bottom surface 191a. In this embodiment, the line width of the gate 191 is 0.2 μm.

[0076] Here, the electrical properties of the high electron mobility transistors prepared in the above-mentioned embodiments are measured.

[0077] Figure 2 , which is the DC characteristic of the high electron mobility transistor prepared in the above embodiment of the present invention. As can be seen from the figure, the steady-state current density (I dss ) can reach 1050mA / mm, and the maximum transconductance (g m，max ) can reach 365mS / mm.

[0078] Figure 3 It is the high frequency characteristic of the high electron mobility transistor prepared in the above embodiment of the present invention. As can be seen from the figure, the cut-off frequency (f T ) can reach 27GHz, and the maximum oscillation frequency (f max ) can reach 106GHz.

[0079] Figure 4 The load-pull measurement results of the high electron mobility transistor prepared in the above embodiment of the present invention are shown in the figure. As can be seen from the figure, the maximum power conversion efficiency (PAE) of the high electron mobility transistor of the present invention can reach 34.23%, and the maximum output power density (P out，max ) can reach 2.39W / mm.

[0080] Although the traditional electron beam lithography process can expose a smaller line width with higher precision, it has the disadvantages of being time-consuming and costly. As mentioned above, the present invention uses a low-cost stepper exposure machine to perform two-stage exposure by offsetting the exposure position, and uses the overlapping area of ​​the two exposures as the area of ​​the gate area to further reduce the line width. At the same time, the present invention increases the thickness of the passivation layer so that when the gate metal is deposited, it can be divided into two unconnected blocks of the passivation layer above and below, thereby improving the success rate of forming the gate structure, and the height allowable value of the gate metal can be increased by this thickness. In addition, with the gate structure produced by the present invention, it is not necessary to use silicon nitride under the gate to improve mechanical stability, which can further reduce parasitic capacitance.

Claims

1. A method for preparing a high electron mobility transistor, comprising the following steps: Providing a substrate, wherein a semiconductor layer is formed on the substrate, and a source and a drain are formed on the semiconductor layer; forming a passivation layer on the source and the drain; Etching the passivation layer to form a through hole between the source and the drain, wherein the through hole exposes a region of the semiconductor layer; forming a photoresist layer on the passivation layer, wherein a first sub-region of the region of the semiconductor layer is covered by the photoresist layer, and a second sub-region of the region of the semiconductor layer is not covered by the photoresist layer; forming a metal layer on the second sub-region to form a gate; as well as The passivation layer is removed. 2 . The preparation method according to claim 1 , wherein the semiconductor layer comprises a gallium nitride layer and an aluminum gallium nitride layer. The preparation method according to claim 1 , wherein the passivation layer is a silicon nitride layer. The preparation method according to claim 1 , wherein the thickness of the metal layer is less than the thickness of the passivation layer. 5 . The preparation method according to claim 4 , wherein a difference between a thickness of the metal layer and a thickness of the passivation layer is between 0.01 μm and 0.7 μm. 6 . The method according to claim 1 , wherein the line width of the gate is between 0.05 μm and 0.5 μm.

7. The preparation method according to claim 1, wherein the gate has a bottom surface and a top surface opposite to the bottom surface, the bottom surface is a surface of the gate in contact with the semiconductor layer, and a width of the top surface is less than or equal to a width of the bottom surface. 8 . The preparation method according to claim 7 , wherein a difference between a width of the top surface and a width of the bottom surface is less than or equal to 10 nm. 9 . The manufacturing method according to claim 1 , wherein an angle smaller than 90 degrees is formed between a sidewall of the through hole and a surface of the region of the semiconductor layer. 10 . The preparation method according to claim 1 , further comprising a step of forming a protection layer after removing the passivation layer, wherein the protection layer covers the gate, the source, the drain and the semiconductor layer. 11 . The method according to claim 1 , further comprising a step of forming an etching photoresist layer on the passivation layer between the steps of forming the passivation layer on the source and the drain and etching the passivation layer. 12 . The manufacturing method according to claim 11 , wherein the etching photoresist layer and the photoresist layer are formed using the same photomask. 13 . The manufacturing method according to claim 1 , wherein in the step of forming the photoresist layer and the passivation layer, a portion of the passivation layer adjacent to the second sub-region is not covered by the photoresist layer. 14 . The preparation method according to claim 13 , wherein in the step of forming the metal layer and the second sub-region, the metal layer is also formed on the portion of the passivation layer not covered by the photoresist layer.

15. A high electron mobility transistor, comprising: a substrate; a semiconductor layer disposed on the substrate; a source electrode disposed on the semiconductor layer; A drain electrode is disposed on the semiconductor layer; as well as A gate is arranged on the semiconductor layer and located between the source and the drain, wherein the gate has a bottom surface and a top surface opposite to the bottom surface, the bottom surface is the surface of the gate in contact with the semiconductor layer, and the width of the top surface is less than or equal to the width of the bottom surface. 16 . The high electron mobility transistor according to claim 15 , wherein the semiconductor layer comprises a gallium nitride layer and an aluminum gallium nitride layer. 17 . The high electron mobility transistor according to claim 15 , wherein a line width of the gate is between 0.05 μm and 0.5 μm. 18 . The high electron mobility transistor of claim 15 , wherein a difference between a width of the top surface and a width of the bottom surface is less than or equal to 10 nm.

19. The high electron mobility transistor according to claim 15, further comprising: A protective layer, Covering the gate, the source, the drain and the semiconductor layer.

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