VDMOS device of integrated capacitor and preparation method of VDMOS device

Abstract

The invention discloses a VDMOS device of an integrated capacitor and a preparation method thereof, and relates to the technical field of microelectronics, and the VDMOS device comprises a drain electrode, a substrate and a drift region which are stacked in sequence; the first gate oxide layer is located on the upper surface of the drift region, and the orthographic projection of the first gate oxide layer is located in the orthographic projection range of the substrate in the direction perpendicular to the substrate; the grid electrode is located on the upper surface of the first gate oxide layer, and the orthographic projection of the grid electrode is located in the range of the orthographic projection of the first gate oxide layer; the second gate oxide layer covers the upper surface and the side surface of the gate electrode, and the orthographic projection of the second gate oxide layer is overlapped with the orthographic projection of the first gate oxide layer; the source electrode is located on the side face of a gate oxide layer composed of the first gate oxide layer and the second gate oxide layer, and the height of the source electrode is larger than that of the gate oxide layer; the insulating layer is positioned on the upper surface of the source electrode; the metal layer is located on the upper surface of the insulating layer, and the metal layer is connected with the grid electrode through the conductive hole. According to the invention, the switching rate of the VDMOS device can be reduced.

Description

Technical Field

[0001] The invention belongs to the field of microelectronic technology, and in particular relates to a VDMOS device with integrated capacitance and a preparation method thereof. Background Art

[0002] Electromagnetic interference (EMI) refers to the phenomenon of mutual interference between electromagnetic fields and circuits, or between different circuits. This interference can be generated by electromagnetic radiation, electromagnetic induction, or electromagnetic coupling, and its negative effects include device performance degradation, signal distortion, and communication interruption. In severe cases, it may even cause device damage or safety accidents.

[0003] Electromagnetic interference propagates mainly in two forms: conducted interference and radiated interference. Power devices, as commonly used switches in circuit systems, are one of the main sources of electromagnetic interference. The noise interference generated by their constant opening and closing usually propagates to the back end of the circuit in the form of conducted interference. At present, the response to electromagnetic interference mainly starts from three aspects: interference source, propagation path and sensitive equipment. Generally, from the circuit level, by adding LC filters, optimizing circuit design and layout, using decoupling capacitors and protection circuits to optimize the propagation path; and by reducing the frequency of signal generation and selecting low-noise components to suppress the interference source; but these measures are likely to increase the size and cost of the system, and the high-frequency attenuation effect is not obvious. In particular, circuit design and capacitor selection require rich knowledge and experience and the best layout plan, otherwise the expected effect cannot be achieved.

[0004] Therefore, how to improve electromagnetic interference from the device structure level has become a problem that needs to be solved urgently. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a VDMOS device with integrated capacitor and a method for manufacturing the same. The technical problem to be solved by the present invention is achieved by the following technical solution: In a first aspect, the present invention provides a VDMOS device with integrated capacitor, comprising: A drain electrode, a substrate and a drift region are stacked in sequence; A first gate oxide layer is located on the upper surface of the drift region, and along a direction perpendicular to the substrate, an orthographic projection of the first gate oxide layer is located within the range of an orthographic projection of the substrate; A gate is located on an upper surface of the first gate oxide layer, and along a direction perpendicular to the substrate, an orthographic projection of the gate is located within the range of an orthographic projection of the first gate oxide layer; A second gate oxide layer covers the upper surface and side surfaces of the gate, and an orthographic projection of the second gate oxide layer overlaps with an orthographic projection of the first gate oxide layer in a direction perpendicular to the substrate; A source electrode is located on a side of a gate oxide layer composed of the first gate oxide layer and the second gate oxide layer, and along a direction perpendicular to the substrate, a height of the source electrode is greater than a height of the gate oxide layer; an insulating layer, located on the upper surface of the source; The metal layer is located on the upper surface of the insulating layer, and the metal layer is connected to the gate through a conductive hole.

[0006] In a second aspect, the present invention further provides a method for preparing a VDMOS device with an integrated capacitor, which is used to prepare the VDMOS device with an integrated capacitor provided by the present invention, comprising: providing a substrate; epitaxially growing a drift region on a substrate; Depositing a first gate oxide layer on the drift region, depositing a gate on the first gate oxide layer, depositing a second gate oxide layer on the upper surface and side surfaces of the gate, wherein the first gate oxide layer and the second gate oxide layer form a gate oxide layer; Depositing a source electrode around the gate oxide layer and on the drift region; depositing an insulating layer on the source electrode; A metal layer is deposited on the insulating layer, and the metal layer is connected to the gate through a conductive hole.

[0007] Beneficial effects of the present invention: The invention provides a VDMOS device with integrated capacitance and a preparation method thereof. The device comprises a drain electrode, a substrate and a drift region which are stacked in sequence. The device is a vertical structure device. A first gate oxide layer and a source electrode are arranged on the upper surface of the drift region. The source electrode is located at the periphery of the first gate oxide layer. A gate electrode is arranged on the upper surface of the first gate oxide layer. The upper surface and the side surface of the gate electrode are covered with a second gate oxide layer. The first gate oxide layer and the second gate oxide layer jointly form a gate oxide layer. In a direction perpendicular to the substrate, the source electrode has a height greater than the gate oxide layer height. The source electrode surrounds the gate oxide layer to form a groove. An insulating layer is arranged on the upper surface of the source electrode. A metal layer is arranged on the upper surface of the insulating layer. On the one hand, the source electrode and the gate electrode form a capacitor. On the other hand, the metal layer and the source electrode form another capacitor. The metal layer is electrically connected to the gate electrode through a conductive hole, which is equivalent to two capacitors being connected in parallel. The parasitic capacitance between the gate electrode and the source electrode is further increased, so as to reduce the switching rate of the VDMOS device, thereby optimizing the electromagnetic interference performance of the VDMOS device, and improving the performance of the VDMOS device.

[0008] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic diagram of a VDMOS device with integrated capacitor provided in an embodiment of the present invention; Figure 2 is a top view of a VDMOS device with integrated capacitor provided in an embodiment of the present invention; Figure 3 It is a flow chart of a method for preparing a VDMOS device with integrated capacitor provided in an embodiment of the present invention; Figure 4a~4k It is a schematic diagram of a method for preparing a VDMOS device with integrated capacitor provided in an embodiment of the present invention; Figure 5 It is a schematic diagram comparing the turn-off current characteristics of the device provided by the embodiment of the present invention and the existing device; Figure 6 It is a schematic diagram comparing the turn-off voltage characteristics of the device provided by the embodiment of the present invention and the existing device; Figure 7 It is a schematic diagram comparing the static characteristics of the device provided by the embodiment of the present invention with those of the existing device. DETAILED DESCRIPTION

[0010] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0011] At present, the main approaches to deal with electromagnetic interference are from three aspects: interference source, propagation path and sensitive equipment. Generally, from the circuit level, the propagation path is optimized by adding LC filters, optimizing circuit design and layout, using decoupling capacitors and protection circuits, etc.; the interference source is suppressed by reducing the signal generation frequency and selecting low-noise components; in addition, there is also optimization at the device level, generally by increasing the doping concentration of the JFET area, changing the gate length and gate oxide thickness to reduce the switching rate of the device.

[0012] These existing circuit optimization measures will increase the size and cost of the system, and have little effect on high-frequency attenuation. In particular, they require rich knowledge and experience in circuit design and capacitor selection, as well as the best layout plan, otherwise the expected effect cannot be achieved. These device optimization measures will also increase process manufacturing costs, and will have an adverse effect on the originally desired static characteristics of the device, and may even make it substandard.

[0013] In view of this, the present invention provides a VDMOS device with integrated capacitor and a preparation method thereof, which further optimizes the electromagnetic interference problem by integrating capacitors inside the VDMOS device; and when optimizing the electromagnetic interference problem, the static characteristics of the VDMOS device itself are not affected.

[0014] See also Figure 1 , Figure 1 is a schematic diagram of a VDMOS device with integrated capacitor provided in an embodiment of the present invention, Figure 21 is a top view of a VDMOS device with integrated capacitor provided by an embodiment of the present invention. The VDMOS device with integrated capacitor provided by the present invention includes: A drain electrode 10, a substrate 20 and a drift region 30 are stacked in sequence; A first gate oxide layer 41 is located on the upper surface of the drift region 30 , and along a direction D1 perpendicular to the substrate, an orthographic projection of the first gate oxide layer 41 is located within the range of an orthographic projection of the substrate 20 ; The gate 50 is located on the upper surface of the first gate oxide layer 41, and along a direction D1 perpendicular to the substrate, the orthographic projection of the gate 50 is located within the range of the orthographic projection of the first gate oxide layer 41; A second gate oxide layer 42 covers the upper surface and side surfaces of the gate 50 , and along a direction D1 perpendicular to the substrate, an orthographic projection of the second gate oxide layer 42 overlaps with an orthographic projection of the first gate oxide layer 41 ; The source electrode 60 is located on the side of the gate oxide layer composed of the first gate oxide layer 41 and the second gate oxide layer 42, and along the direction D1 perpendicular to the substrate, the height of the source electrode 60 is greater than the height of the gate oxide layer; An insulating layer 70 , located on the upper surface of the source electrode 60 ; The metal layer 80 is located on the upper surface of the insulating layer 70 , and the metal layer 80 is connected to the gate 50 through a conductive hole.

[0015] For more details, please see Figure 1 and Figure 2 The present invention provides a VDMOS device with integrated capacitor, comprising a drain 10, a substrate 20 and a drift region 30 stacked in sequence, and is a vertical structure device. A first gate oxide layer 41 and a source 60 are arranged on the upper surface of the drift region 30. The source 60 is located around the first gate oxide layer 41. A gate 50 is arranged on the upper surface of the first gate oxide layer 41. The upper surface and the side of the gate 50 are covered with a second gate oxide layer 42. The first gate oxide layer 41 and the second gate oxide layer 42 jointly form a gate oxide layer. Along a direction D1 perpendicular to the substrate, the height of the source 60 is greater than the height of the gate oxide layer. Figure 1 As shown, combined with Figure 2 The source electrode 60 surrounds the gate oxide layer to form a groove, an insulating layer 70 is provided on the upper surface of the source electrode 60, and a metal layer 80 is provided on the upper surface of the insulating layer 70; on the one hand, the source electrode 60 and the gate electrode 50 form a capacitor, and on the other hand, the metal layer 80 and the source electrode 60 form another capacitor, and the metal layer 80 is electrically connected to the gate electrode 50 through a conductive hole, which is equivalent to two capacitors in parallel, further increasing the parasitic capacitance between the gate electrode 50 and the source electrode 60, reducing the switching rate of the VDMOS device, thereby optimizing the electromagnetic interference performance of the VDMOS device and improving the performance of the VDMOS device.

[0016] In an optional embodiment of the present invention, a capacitor is formed between the source electrode 60 and the metal layer 80. , a capacitor is formed between the source 60 and the gate 50 , the metal layer 80 is connected to the gate 50 through a conductive hole, so that the capacitor With capacitor Connect in parallel to form parallel capacitors; The relationship between the shunt capacitance and the switching voltage slope of the VDMOS device is: ; The relationship between the shunt capacitance and the switching current slope of the VDMOS device is: ; in, represents the switching voltage of the VDMOS device, represents the switching current of the VDMOS device, Indicates the maximum value of drain 10 current during the switching process, With capacitor Inversely proportional, represents the gate 50 voltage, represents the capacitance formed between the gate 50 and the source 60, represents the voltage between the drain 10 and the source 60 of the MOSFET device, represents the drain 10 continuous current, represents the capacitance formed between the source 60 and the metal layer 80, represents the flat-band voltage of the VDMOS device, Indicates the threshold voltage at which the VDMOS device turns on.

[0017] In an optional embodiment of the present invention, the switching voltage slope of the VDMOS device is related to the capacitance The switching current slope of the VDMOS device is inversely proportional to the capacitance. Inversely proportional.

[0018] In this embodiment, the switch current slope of the VDMOS device and the switch voltage slope of the VDMOS device increase with the capacitance. The smaller the switching current slope of the VDMOS device and the switching voltage slope of the VDMOS device, the smaller the switching rate of the VDMOS device, thereby optimizing the electromagnetic interference performance of the VDMOS device and improving the performance of the VDMOS device; it can also be understood that the capacitor The larger the capacitance value, the more advantages it has.

[0019] In an optional embodiment of the present invention, the capacitor The expression is: ; in, represents the relative dielectric constant of the insulating layer 70, represents the thickness of the insulating layer 70, It represents the overlapping area between the source 60 and the metal layer 80 .

[0020] It should be noted that, in this embodiment, it can be obtained from the above formula that the capacitance value required to be increased by the VDMOS device can be adjusted according to the type and thickness of the insulating layer 70 .

[0021] In an optional embodiment of the present invention, the material of the insulating layer 70 is silicon dioxide or silicon nitride.

[0022] Optionally, the material of the insulating layer 70 is silicon dioxide (SiO2), the relative dielectric constant is 3.9, the thickness of the insulating layer 70 along the direction D1 perpendicular to the substrate is 0.1 μm, and the value of the integrated capacitance is about 600 pf.

[0023] In an optional embodiment of the present invention, along a direction D1 perpendicular to the substrate, the thickness of the insulating layer 70 is 0.1-0.3 μm.

[0024] It should be noted that the thickness of the insulating layer 70 is not fixed and can be adjusted based on the capacitance to be implanted. The thickness of the insulating layer 70 is calculated based on the dielectric constant of the insulating layer 70 .

[0025] In an optional embodiment of the present invention, along a direction D1 perpendicular to the substrate, the thickness of the metal layer 80 is 4-5 μm.

[0026] Optionally, the material of the metal layer 80 may be Al.

[0027] In an optional embodiment of the present invention, the metal layer 80 is connected to the gate 50 via a conductive via, wherein the conductive via penetrates the gate oxide layer along a direction D1 perpendicular to the substrate.

[0028] Specifically, in this embodiment, a conductive hole is opened in the gate oxide layer, and the gate 50 is electrically connected to the metal layer 80 through the conductive hole.

[0029] It should be noted that if Figure 1 As shown, the source 60 is located around the gate oxide layer, and along the direction D1 perpendicular to the substrate, the source 60 and the gate oxide layer do not overlap, the insulating layer 70 is located on the upper surface of the source 60, and the metal layer 80 is located on the upper surface of the insulating layer 70, that is, the orthographic projections of the insulating layer 70 and the metal layer 80 do not overlap with the orthographic projections of the gate oxide layer. It can also be understood that the gate oxide layer is directly exposed on the top of the device, and a conductive hole is opened in the gate oxide layer to realize the electrical connection between the gate 50 and the metal layer 80.

[0030] Based on the same inventive concept, see Figure 3 , Figure 3 1 is a flow chart of a method for preparing a VDMOS device with integrated capacitors provided in an embodiment of the present invention. The present invention also provides a method for preparing a VDMOS device with integrated capacitors, which is used to prepare the VDMOS device with integrated capacitors provided in the above embodiment of the present invention. The embodiments of the device are referred to above and will not be described in detail herein. The preparation method comprises: S101, providing a substrate 20; S102, epitaxially growing a drift region 30 on the substrate 20; S103, depositing a first gate oxide layer 41 on the drift region 30, depositing a gate 50 on the first gate oxide layer 41, and depositing a second gate oxide layer 42 on the upper surface and side surfaces of the gate 50, so that the first gate oxide layer 41 and the second gate oxide layer 42 form a gate oxide layer; S104, depositing a source electrode 60 around the gate oxide layer and on the drift region 30; S105, depositing an insulating layer 70 on the source electrode 60; S106, depositing a metal layer 80 on the insulating layer 70, and connecting the metal layer 80 to the gate 50 through a conductive hole; S107 , depositing the drain 10 on the side of the substrate 20 away from the drift region 30 .

[0031] In an optional embodiment of the present invention, before depositing the first gate oxide layer 41 on the drift region 30, the method further includes: A P-type well region 90 is formed on both sides of the drift region 30 by ion implantation; An N-type source region 100 is formed in the P-type well region 90 by ion implantation.

[0032] In an optional embodiment of the present invention, a VDMOS device with integrated capacitor is prepared by the following process, specifically: S1, provide an N+ type substrate 20, such as Figure 4a shown.

[0033] Specifically, the N+ type substrate 20 is heavily doped, with a doping concentration of 1×10 18 ~6×10 20 cm 2 .

[0034] S2, epitaxially growing an N-drift region 30 on an N+ type substrate 20, such as Figure 4b shown.

[0035] Specifically, the N-drift region 30 is lightly doped, with a doping concentration of 1×10 14 ~1×10 16 cm 2 .

[0036] S3, ion implantation is performed on both sides of the N-drift region 30 to form a P-type well region 90, such as Figure 4c shown.

[0037] Specifically, a mask is used to perform ion implantation on both sides of the N-drift region 30 , and B ions are implanted to form a P-type well region 90 on each side of the N-drift region 30 .

[0038] The P-type well region 90 is lightly doped, with a doping concentration of 8×10 15 ~1×10 18 cm 2 .

[0039] S4, ion implantation is performed in the P-type well region 90 to form an N-type source region 100, such as Figure 4d shown.

[0040] Specifically, ion implantation is performed in the P-type well region 90 by using a mask, and As ions are implanted to form the N-type source region 100 . One N-type source region 100 is formed in each of the two P-type well regions 90 .

[0041] Among them, the N+ type source region 100 is heavily doped, and the doping concentration is 1×10 18 ~1×10 20 cm 2 .

[0042] S5, depositing oxide on the upper surface of the N-drift region 30 to form a first gate oxide layer 41, such as Figure 4e shown.

[0043] Specifically, on the surface of silicon carbide, oxide is grown by adopting a thermal oxidation process to form a first gate oxide layer 41 . The thickness of the first gate oxide layer 41 is about 0.1 μm.

[0044] S6, depositing a gate 50 on the upper surface of the first gate oxide layer 41, such as Figure 4f shown.

[0045] Specifically, a deposition process is adopted to deposit polysilicon on the upper surface of the first gate oxide layer 41 to form the gate 50 .

[0046] S7, depositing a second gate oxide layer 42 on the upper surface and side surfaces of the gate 50, such as Figure 4g shown.

[0047] Specifically, a second gate oxide layer 42 is deposited on the upper surface and side surfaces of the gate 50 by a deposition process, and a conductive hole (not shown) is formed by an etching process and a deposition process. The first gate oxide layer 41 and the second gate oxide layer 42 form a gate oxide layer.

[0048] The thickness of the second gate oxide layer 42 is about 1 μm.

[0049] S8, depositing the source electrode 60 on the upper surface of part of the N-type source region 100 and part of the P-type well region 90, and around the gate oxide layer, as shown in FIG. Figure 4h shown.

[0050] Specifically, a deposition process is adopted to deposit metal on the upper surface of a portion of the N-type source region 100 and a portion of the P-type well region 90 to form the source 60 .

[0051] S9, using a deposition process, deposit an insulating layer 70 on the upper surface of the source 60, such as Figure 4i shown.

[0052] Specifically, the insulating layer 70 is made of silicon dioxide and has a thickness of about 0.1 μm, which can be based on the required implanted capacitance. And the dielectric constant of the insulating layer 70 is adjusted by the thickness.

[0053] S10, using a deposition process, depositing a metal layer 80 on the upper surface of the insulating layer 70, such as Figure 4j shown.

[0054] Specifically, the material of the metal layer 80 is Al, and the thickness is 4-5 μm.

[0055] S11, using a deposition process, depositing the drain 10 on the side of the substrate 20 away from the drift region 30, such as Figure 4k shown.

[0056] In an optional embodiment of the present invention, the structure of the VDMOS device with integrated capacitor provided in the above embodiment is verified by simulation experiments, specifically: 1. Simulation content and result analysis See also Figure 5 and Figure 6 , Figure 5 is a schematic diagram comparing the turn-off current characteristics of the device provided by the embodiment of the present invention and the existing device, Figure 6 is a schematic diagram comparing the turn-off voltage characteristics of the device provided by the embodiment of the present invention and the existing device, Figure 5 and Figure 6 In the figure, Origin represents an existing device without integrated capacitor, and New represents the device provided by the present invention. It can be seen from the figure that after the VDMOS device provided by the present invention integrates a capacitor of about 600pf between the gate and the source, the turn-off current voltage rate is significantly reduced. Through calculation, the turn-off current slope is reduced by about 43%, and the turn-off voltage slope is reduced by about 39%, and the slope reduction amplitude will increase with the increase of the integrated capacitance value.

[0057] See also Figure 7 , Figure 7 is a schematic diagram comparing the static characteristics of the device provided by the embodiment of the present invention with those of the existing device. Figure 7 In FIG. 1 , Origin represents an existing device without integrated capacitor, and New represents the device provided by the present invention. The threshold voltage, breakdown voltage and on-resistance of the existing device and the VDMOS device provided by the present invention are simulated. As can be seen from the figure, there is no significant difference in the threshold voltage, breakdown voltage and on-resistance between the two, indicating that integrating a capacitor inside the VDMOS device has no effect on the static characteristics of the device.

[0058] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant is intended to cover non-exclusive inclusion, so that the article or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed. In the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the article or device including the elements. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The orientation or position relationship indicated by "up", "down", "left", "right", etc. is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention.

[0059] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0060] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A VDMOS device with integrated capacitor, characterized in that: include: A drain electrode, a substrate and a drift region are stacked in sequence; A first gate oxide layer is located on an upper surface of the drift region, and along a direction perpendicular to the substrate, an orthographic projection of the first gate oxide layer is located within a range of an orthographic projection of the substrate; A gate is located on an upper surface of the first gate oxide layer, and along a direction perpendicular to the substrate, an orthographic projection of the gate is located within a range of an orthographic projection of the first gate oxide layer; A second gate oxide layer covers the upper surface and side surfaces of the gate, and an orthographic projection of the second gate oxide layer overlaps with an orthographic projection of the first gate oxide layer in a direction perpendicular to the substrate; A source electrode is located on a side of a gate oxide layer composed of the first gate oxide layer and the second gate oxide layer, and along a direction perpendicular to the substrate, a height of the source electrode is greater than a height of the gate oxide layer; an insulating layer, located on an upper surface of the source electrode; The metal layer is located on the upper surface of the insulating layer, and the metal layer is connected to the gate through a conductive hole.

2. The VDMOS device with integrated capacitor according to claim 1, characterized in that: A capacitor is formed between the source electrode and the metal layer , a capacitor is formed between the source and the gate The metal layer is connected to the gate through a conductive hole so that the capacitor With the capacitor Connect in parallel to form parallel capacitors; The relationship between the parallel capacitance and the switching voltage slope of the VDMOS device is: ； The relationship between the parallel capacitance and the switching current slope of the VDMOS device is: ； in, represents the switching voltage of the VDMOS device, represents the switching current of the VDMOS device, Indicates the maximum value of drain current during the switching process, represents the gate resistance, represents the capacitance formed between the gate and the source, represents the voltage between the drain and source of the MOSFET device, represents the continuous drain current, Represents the capacitance formed between the source and the metal layer, represents the flat-band voltage of the VDMOS device, Indicates the threshold voltage at which the VDMOS device turns on.

3. The VDMOS device with integrated capacitor according to claim 2, characterized in that: The switching voltage slope of the VDMOS device is related to the capacitance The switching current slope of the VDMOS device is inversely proportional to the capacitance Inversely proportional.

4. The VDMOS device with integrated capacitor according to claim 2, characterized in that: The capacitor The expression is: ； in, represents the relative dielectric constant of the insulating layer, Indicates the thickness of the insulation layer, Represents the overlapping area between the source and the metal layer.

5. The VDMOS device with integrated capacitor according to claim 1, characterized in that: The insulating layer is made of silicon dioxide or silicon nitride.

6. The VDMOS device with integrated capacitor according to claim 1, characterized in that: Along the direction perpendicular to the substrate, the thickness of the insulating layer is 0.1-0.3 μm.

7. The VDMOS device with integrated capacitor according to claim 1, characterized in that: Along the direction perpendicular to the substrate, the thickness of the metal layer is 4-5 μm.

8. The VDMOS device with integrated capacitor according to claim 1, characterized in that: The metal layer is connected to the gate via a conductive hole, wherein the conductive hole penetrates the gate oxide layer along a direction perpendicular to the substrate.

9. A method for preparing a VDMOS device with integrated capacitor, for preparing the VDMOS device with integrated capacitor as claimed in any one of claims 1 to 8, characterized in that: include: providing a substrate; epitaxially growing a drift region on the substrate; Depositing a first gate oxide layer on the drift region, depositing a gate on the first gate oxide layer, and depositing a second gate oxide layer on the upper surface and side surfaces of the gate, wherein the first gate oxide layer and the second gate oxide layer form a gate oxide layer; Depositing a source electrode around the gate oxide layer and on the drift region; depositing an insulating layer on the source electrode; Depositing a metal layer on the insulating layer, wherein the metal layer is connected to the gate via a conductive hole; A drain is deposited on a side of the substrate facing away from the drift region.

10. The method for preparing a VDMOS device with integrated capacitor according to claim 9, characterized in that: Before depositing the first gate oxide layer on the drift region, the method further comprises: forming a P-type well region on both sides of the drift region by ion implantation; An N-type source region is formed in the P-type well region by ion implantation.

Images